2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * - fix mask for depth control & cull for query
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_upload_mgr.h>
43 #include <util/u_index_modify.h>
44 #include <pipebuffer/pb_buffer.h>
51 #include "r600_resource.h"
52 #include "r600_shader.h"
53 #include "r600_pipe.h"
54 #include "r600_state_inlines.h"
57 static void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
59 struct r600_pipe_state
*rstate
= &shader
->rstate
;
60 struct r600_shader
*rshader
= &shader
->shader
;
61 unsigned spi_vs_out_id
[10];
64 /* clear previous register */
67 /* so far never got proper semantic id from tgsi */
68 for (i
= 0; i
< 10; i
++) {
71 for (i
= 0; i
< 32; i
++) {
72 tmp
= i
<< ((i
& 3) * 8);
73 spi_vs_out_id
[i
/ 4] |= tmp
;
75 for (i
= 0; i
< 10; i
++) {
76 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
77 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
78 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
81 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
82 R_0286C4_SPI_VS_OUT_CONFIG
,
83 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
85 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
86 R_028868_SQ_PGM_RESOURCES_VS
,
87 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
88 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
90 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
91 R_0288A4_SQ_PGM_RESOURCES_FS
,
92 0x00000000, 0xFFFFFFFF, NULL
);
93 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
94 R_0288D0_SQ_PGM_CF_OFFSET_VS
,
95 0x00000000, 0xFFFFFFFF, NULL
);
96 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
97 R_0288DC_SQ_PGM_CF_OFFSET_FS
,
98 0x00000000, 0xFFFFFFFF, NULL
);
99 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
100 R_028858_SQ_PGM_START_VS
,
101 0x00000000, 0xFFFFFFFF, shader
->bo
);
102 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
103 R_028894_SQ_PGM_START_FS
,
104 0x00000000, 0xFFFFFFFF, shader
->bo
);
107 static void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
109 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
110 struct r600_pipe_state
*rstate
= &shader
->rstate
;
111 struct r600_shader
*rshader
= &shader
->shader
;
112 unsigned i
, tmp
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
;
113 boolean have_pos
= FALSE
, have_face
= FALSE
;
115 /* clear previous register */
118 for (i
= 0; i
< rshader
->ninput
; i
++) {
119 tmp
= S_028644_SEMANTIC(i
);
120 tmp
|= S_028644_SEL_CENTROID(1);
121 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
123 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
124 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
||
125 rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
) {
126 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
128 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
130 if (rctx
->sprite_coord_enable
& (1 << i
)) {
131 tmp
|= S_028644_PT_SPRITE_TEX(1);
133 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4, tmp
, 0xFFFFFFFF, NULL
);
138 for (i
= 0; i
< rshader
->noutput
; i
++) {
139 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
141 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
145 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
147 /* always at least export 1 component per pixel */
151 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
152 S_0286CC_PERSP_GRADIENT_ENA(1);
155 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
156 S_0286CC_BARYC_SAMPLE_CNTL(1);
159 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
160 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286D0_SPI_PS_IN_CONTROL_1
, S_0286D0_FRONT_FACE_ENA(have_face
), 0xFFFFFFFF, NULL
);
161 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
162 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
163 R_028840_SQ_PGM_START_PS
,
164 0x00000000, 0xFFFFFFFF, shader
->bo
);
165 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
166 R_028850_SQ_PGM_RESOURCES_PS
,
167 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
168 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
170 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
171 R_028854_SQ_PGM_EXPORTS_PS
,
172 exports_ps
, 0xFFFFFFFF, NULL
);
173 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
174 R_0288CC_SQ_PGM_CF_OFFSET_PS
,
175 0x00000000, 0xFFFFFFFF, NULL
);
177 if (rshader
->uses_kill
) {
178 /* only set some bits here, the other bits are set in the dsa state */
179 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
180 R_02880C_DB_SHADER_CONTROL
,
181 S_02880C_KILL_ENABLE(1),
182 S_02880C_KILL_ENABLE(1), NULL
);
186 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
188 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
189 struct r600_shader
*rshader
= &shader
->shader
;
192 /* copy new shader */
193 if (shader
->bo
== NULL
) {
194 shader
->bo
= radeon_ws_bo(rctx
->radeon
, rshader
->bc
.ndw
* 4, 4096, 0);
195 if (shader
->bo
== NULL
) {
198 ptr
= radeon_ws_bo_map(rctx
->radeon
, shader
->bo
, 0, NULL
);
199 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
200 radeon_ws_bo_unmap(rctx
->radeon
, shader
->bo
);
203 rshader
->flat_shade
= rctx
->flatshade
;
204 switch (rshader
->processor_type
) {
205 case TGSI_PROCESSOR_VERTEX
:
206 if (rshader
->family
>= CHIP_CEDAR
) {
207 evergreen_pipe_shader_vs(ctx
, shader
);
209 r600_pipe_shader_vs(ctx
, shader
);
212 case TGSI_PROCESSOR_FRAGMENT
:
213 if (rshader
->family
>= CHIP_CEDAR
) {
214 evergreen_pipe_shader_ps(ctx
, shader
);
216 r600_pipe_shader_ps(ctx
, shader
);
222 r600_context_pipe_state_set(&rctx
->ctx
, &shader
->rstate
);
226 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_pipe_shader
*rshader
)
228 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
229 struct r600_shader
*shader
= &rshader
->shader
;
230 const struct util_format_description
*desc
;
231 enum pipe_format resource_format
[160];
232 unsigned i
, nresources
= 0;
233 struct r600_bc
*bc
= &shader
->bc
;
234 struct r600_bc_cf
*cf
;
235 struct r600_bc_vtx
*vtx
;
237 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
239 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
240 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
242 radeon_ws_bo_reference(rctx
->radeon
, &rshader
->bo
, NULL
);
243 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
245 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
246 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
247 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
248 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
250 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
253 vtx
->dst_sel_x
= desc
->swizzle
[0];
254 vtx
->dst_sel_y
= desc
->swizzle
[1];
255 vtx
->dst_sel_z
= desc
->swizzle
[2];
256 vtx
->dst_sel_w
= desc
->swizzle
[3];
263 return r600_bc_build(&shader
->bc
);
266 int r600_pipe_shader_update2(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
268 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
273 /* there should be enough input */
274 if (rctx
->vertex_elements
->count
< shader
->shader
.bc
.nresource
) {
275 R600_ERR("%d resources provided, expecting %d\n",
276 rctx
->vertex_elements
->count
, shader
->shader
.bc
.nresource
);
279 r
= r600_shader_update(ctx
, shader
);
282 return r600_pipe_shader(ctx
, shader
);
285 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
286 int r600_pipe_shader_create2(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
, const struct tgsi_token
*tokens
)
288 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
291 //fprintf(stderr, "--------------------------------------------------------------\n");
292 //tgsi_dump(tokens, 0);
293 shader
->shader
.family
= r600_get_family(rctx
->radeon
);
294 r
= r600_shader_from_tgsi(tokens
, &shader
->shader
);
296 R600_ERR("translation from TGSI failed !\n");
299 r
= r600_bc_build(&shader
->shader
.bc
);
301 R600_ERR("building bytecode failed !\n");
304 //fprintf(stderr, "______________________________________________________________\n");
307 /* r600_shader.c END */
309 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
314 static const char* r600_get_name(struct pipe_screen
* pscreen
)
316 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
317 enum radeon_family family
= r600_get_family(rscreen
->radeon
);
319 if (family
>= CHIP_R600
&& family
< CHIP_RV770
)
320 return "R600 (HD2XXX,HD3XXX)";
322 return "R700 (HD4XXX)";
325 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
328 /* Supported features (boolean caps). */
329 case PIPE_CAP_NPOT_TEXTURES
:
330 case PIPE_CAP_TWO_SIDED_STENCIL
:
332 case PIPE_CAP_DUAL_SOURCE_BLEND
:
333 case PIPE_CAP_ANISOTROPIC_FILTER
:
334 case PIPE_CAP_POINT_SPRITE
:
335 case PIPE_CAP_OCCLUSION_QUERY
:
336 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
337 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
338 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
339 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
341 case PIPE_CAP_TEXTURE_SWIZZLE
:
342 case PIPE_CAP_INDEP_BLEND_ENABLE
:
343 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
344 case PIPE_CAP_DEPTH_CLAMP
:
347 /* Unsupported features (boolean caps). */
348 case PIPE_CAP_TIMER_QUERY
:
349 case PIPE_CAP_STREAM_OUTPUT
:
350 case PIPE_CAP_INDEP_BLEND_FUNC
: /* FIXME allow this */
354 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
355 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
356 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
358 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
359 /* FIXME allow this once infrastructure is there */
361 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
362 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
365 /* Render targets. */
366 case PIPE_CAP_MAX_RENDER_TARGETS
:
367 /* FIXME some r6xx are buggy and can only do 4 */
370 /* Fragment coordinate conventions. */
371 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
372 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
374 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
375 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
379 R600_ERR("r600: unknown param %d\n", param
);
384 static float r600_get_paramf(struct pipe_screen
* pscreen
, enum pipe_cap param
)
387 case PIPE_CAP_MAX_LINE_WIDTH
:
388 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
389 case PIPE_CAP_MAX_POINT_WIDTH
:
390 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
392 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
394 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
397 R600_ERR("r600: unsupported paramf %d\n", param
);
402 static boolean
r600_is_format_supported(struct pipe_screen
* screen
,
403 enum pipe_format format
,
404 enum pipe_texture_target target
,
405 unsigned sample_count
,
410 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
411 R600_ERR("r600: unsupported texture type %d\n", target
);
416 if (sample_count
> 1)
419 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
420 r600_is_sampler_format_supported(format
)) {
421 retval
|= PIPE_BIND_SAMPLER_VIEW
;
424 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
425 PIPE_BIND_DISPLAY_TARGET
|
427 PIPE_BIND_SHARED
)) &&
428 r600_is_colorbuffer_format_supported(format
)) {
430 (PIPE_BIND_RENDER_TARGET
|
431 PIPE_BIND_DISPLAY_TARGET
|
436 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
437 r600_is_zs_format_supported(format
)) {
438 retval
|= PIPE_BIND_DEPTH_STENCIL
;
441 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
442 r600_is_vertex_format_supported(format
))
443 retval
|= PIPE_BIND_VERTEX_BUFFER
;
445 if (usage
& PIPE_BIND_TRANSFER_READ
)
446 retval
|= PIPE_BIND_TRANSFER_READ
;
447 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
448 retval
|= PIPE_BIND_TRANSFER_WRITE
;
450 return retval
== usage
;
453 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
455 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
462 int r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
);
463 static void r600_draw_common(struct r600_drawl
*draw
)
465 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)draw
->ctx
;
466 struct r600_pipe_state
*rstate
;
467 struct r600_resource
*rbuffer
;
468 unsigned i
, j
, offset
, format
, prim
;
469 u32 vgt_dma_index_type
, vgt_draw_initiator
, mask
;
470 struct pipe_vertex_buffer
*vertex_buffer
;
471 struct r600_draw rdraw
;
472 struct r600_pipe_state vgt
;
474 switch (draw
->index_size
) {
476 vgt_draw_initiator
= 0;
477 vgt_dma_index_type
= 0;
480 vgt_draw_initiator
= 0;
481 vgt_dma_index_type
= 1;
484 vgt_draw_initiator
= 2;
485 vgt_dma_index_type
= 0;
488 R600_ERR("unsupported index size %d\n", draw
->index_size
);
491 if (r600_conv_pipe_prim(draw
->mode
, &prim
))
495 /* rebuild vertex shader if input format changed */
496 if (r600_pipe_shader_update2(&rctx
->context
, rctx
->vs_shader
))
498 if (r600_pipe_shader_update2(&rctx
->context
, rctx
->ps_shader
))
501 for (i
= 0 ; i
< rctx
->vertex_elements
->count
; i
++) {
502 unsigned num_format
= 0, format_comp
= 0;
504 rstate
= &rctx
->vs_resource
[i
];
505 j
= rctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
506 vertex_buffer
= &rctx
->vertex_buffer
[j
];
507 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
508 offset
= rctx
->vertex_elements
->elements
[i
].src_offset
+ vertex_buffer
->buffer_offset
;
509 format
= r600_translate_colorformat(rctx
->vertex_elements
->elements
[i
].src_format
);
510 rstate
->id
= R600_PIPE_STATE_RESOURCE
;
513 r600_translate_vertex_num_format(rctx
->vertex_elements
->elements
[i
].src_format
, &num_format
, &format_comp
);
514 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038000_RESOURCE0_WORD0
, offset
, 0xFFFFFFFF, rbuffer
->bo
);
515 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038004_RESOURCE0_WORD1
, rbuffer
->size
- offset
- 1, 0xFFFFFFFF, NULL
);
516 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
,
517 R_038008_RESOURCE0_WORD2
,
518 S_038008_STRIDE(vertex_buffer
->stride
) |
519 S_038008_DATA_FORMAT(format
) |
520 S_038008_NUM_FORMAT_ALL(num_format
) |
521 S_038008_FORMAT_COMP_ALL(format_comp
),
523 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_03800C_RESOURCE0_WORD3
, 0x00000000, 0xFFFFFFFF, NULL
);
524 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038010_RESOURCE0_WORD4
, 0x00000000, 0xFFFFFFFF, NULL
);
525 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038014_RESOURCE0_WORD5
, 0x00000000, 0xFFFFFFFF, NULL
);
526 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038018_RESOURCE0_WORD6
, 0xC0000000, 0xFFFFFFFF, NULL
);
527 r600_context_pipe_state_set_vs_resource(&rctx
->ctx
, rstate
, i
);
531 for (int i
= 0; i
< rctx
->framebuffer
.nr_cbufs
; i
++) {
532 mask
|= (0xF << (i
* 4));
535 vgt
.id
= R600_PIPE_STATE_VGT
;
537 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONFIG
, R_008958_VGT_PRIMITIVE_TYPE
, prim
, 0xFFFFFFFF, NULL
);
538 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
, R_028408_VGT_INDX_OFFSET
, draw
->index_bias
, 0xFFFFFFFF, NULL
);
539 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
, R_028400_VGT_MAX_VTX_INDX
, draw
->max_index
, 0xFFFFFFFF, NULL
);
540 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
, R_028404_VGT_MIN_VTX_INDX
, draw
->min_index
, 0xFFFFFFFF, NULL
);
541 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
, R_028238_CB_TARGET_MASK
, rctx
->cb_target_mask
& mask
, 0xFFFFFFFF, NULL
);
542 /* build late state */
543 if (rctx
->rasterizer
&& rctx
->framebuffer
.zsbuf
) {
544 float offset_units
= rctx
->rasterizer
->offset_units
;
545 unsigned offset_db_fmt_cntl
= 0, depth
;
547 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
548 case PIPE_FORMAT_Z24X8_UNORM
:
549 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
551 offset_units
*= 2.0f
;
553 case PIPE_FORMAT_Z32_FLOAT
:
555 offset_units
*= 1.0f
;
556 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
558 case PIPE_FORMAT_Z16_UNORM
:
560 offset_units
*= 4.0f
;
565 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
566 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
,
567 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
,
568 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
569 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
,
570 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
571 fui(offset_units
), 0xFFFFFFFF, NULL
);
572 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
,
573 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
,
574 fui(rctx
->rasterizer
->offset_scale
), 0xFFFFFFFF, NULL
);
575 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
,
576 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
577 fui(offset_units
), 0xFFFFFFFF, NULL
);
578 r600_pipe_state_add_reg(&vgt
, R600_GROUP_CONTEXT
,
579 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
580 offset_db_fmt_cntl
, 0xFFFFFFFF, NULL
);
582 r600_context_pipe_state_set(&rctx
->ctx
, &vgt
);
584 rdraw
.vgt_num_indices
= draw
->count
;
585 rdraw
.vgt_num_instances
= 1;
586 rdraw
.vgt_index_type
= vgt_dma_index_type
;
587 rdraw
.vgt_draw_initiator
= vgt_draw_initiator
;
588 rdraw
.indices
= NULL
;
589 if (draw
->index_buffer
) {
590 rbuffer
= (struct r600_resource
*)draw
->index_buffer
;
591 rdraw
.indices
= rbuffer
->bo
;
592 rdraw
.indices_bo_offset
= 0;
594 r600_context_draw(&rctx
->ctx
, &rdraw
);
597 void r600_translate_index_buffer2(struct r600_pipe_context
*r600
,
598 struct pipe_resource
**index_buffer
,
599 unsigned *index_size
,
600 unsigned *start
, unsigned count
)
602 switch (*index_size
) {
604 util_shorten_ubyte_elts(&r600
->context
, index_buffer
, 0, *start
, count
);
610 if (*start
% 2 != 0) {
611 util_rebuild_ushort_elts(&r600
->context
, index_buffer
, 0, *start
, count
);
621 static void r600_draw_vbo2(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
623 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
624 struct r600_drawl draw
;
626 assert(info
->index_bias
== 0);
628 if (rctx
->any_user_vbs
) {
629 r600_upload_user_buffers2(rctx
);
630 rctx
->any_user_vbs
= FALSE
;
633 memset(&draw
, 0, sizeof(struct r600_drawl
));
635 draw
.mode
= info
->mode
;
636 draw
.start
= info
->start
;
637 draw
.count
= info
->count
;
638 if (info
->indexed
&& rctx
->index_buffer
.buffer
) {
639 draw
.min_index
= info
->min_index
;
640 draw
.max_index
= info
->max_index
;
641 draw
.index_bias
= info
->index_bias
;
643 r600_translate_index_buffer2(rctx
, &rctx
->index_buffer
.buffer
,
644 &rctx
->index_buffer
.index_size
,
648 draw
.index_size
= rctx
->index_buffer
.index_size
;
649 draw
.index_buffer
= rctx
->index_buffer
.buffer
;
650 draw
.index_buffer_offset
= draw
.start
* draw
.index_size
;
652 r600_upload_index_buffer2(rctx
, &draw
);
655 draw
.index_buffer
= NULL
;
656 draw
.min_index
= info
->min_index
;
657 draw
.max_index
= info
->max_index
;
658 draw
.index_bias
= info
->start
;
660 r600_draw_common(&draw
);
663 static void r600_flush2(struct pipe_context
*ctx
, unsigned flags
,
664 struct pipe_fence_handle
**fence
)
666 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
672 if (!rctx
->ctx
.pm4_cdwords
)
675 u_upload_flush(rctx
->upload_vb
);
676 u_upload_flush(rctx
->upload_ib
);
679 sprintf(dname
, "gallium-%08d.bof", dc
);
681 r600_context_dump_bof(&rctx
->ctx
, dname
);
682 R600_ERR("dumped %s\n", dname
);
686 r600_context_flush(&rctx
->ctx
);
689 static void r600_destroy_context(struct pipe_context
*context
)
691 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)context
;
693 r600_context_fini(&rctx
->ctx
);
694 for (int i
= 0; i
< R600_PIPE_NSTATES
; i
++) {
695 free(rctx
->states
[i
]);
698 u_upload_destroy(rctx
->upload_vb
);
699 u_upload_destroy(rctx
->upload_ib
);
704 static void r600_blitter_save_states(struct pipe_context
*ctx
)
706 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
708 util_blitter_save_blend(rctx
->blitter
, rctx
->states
[R600_PIPE_STATE_BLEND
]);
709 util_blitter_save_depth_stencil_alpha(rctx
->blitter
, rctx
->states
[R600_PIPE_STATE_DSA
]);
710 if (rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]) {
711 util_blitter_save_stencil_ref(rctx
->blitter
, &rctx
->stencil_ref
);
713 util_blitter_save_rasterizer(rctx
->blitter
, rctx
->states
[R600_PIPE_STATE_RASTERIZER
]);
714 util_blitter_save_fragment_shader(rctx
->blitter
, rctx
->ps_shader
);
715 util_blitter_save_vertex_shader(rctx
->blitter
, rctx
->vs_shader
);
716 util_blitter_save_vertex_elements(rctx
->blitter
, rctx
->vertex_elements
);
717 if (rctx
->states
[R600_PIPE_STATE_VIEWPORT
]) {
718 util_blitter_save_viewport(rctx
->blitter
, &rctx
->viewport
);
720 if (rctx
->states
[R600_PIPE_STATE_CLIP
]) {
721 util_blitter_save_clip(rctx
->blitter
, &rctx
->clip
);
723 util_blitter_save_vertex_buffers(rctx
->blitter
, rctx
->nvertex_buffer
, rctx
->vertex_buffer
);
725 rctx
->vertex_elements
= NULL
;
730 static void r600_clear(struct pipe_context
*ctx
, unsigned buffers
,
731 const float *rgba
, double depth
, unsigned stencil
)
733 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
734 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
;
736 r600_blitter_save_states(ctx
);
737 util_blitter_clear(rctx
->blitter
, fb
->width
, fb
->height
,
738 fb
->nr_cbufs
, buffers
, rgba
, depth
,
742 static void r600_clear_render_target(struct pipe_context
*ctx
,
743 struct pipe_surface
*dst
,
745 unsigned dstx
, unsigned dsty
,
746 unsigned width
, unsigned height
)
748 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
749 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
;
751 util_blitter_save_framebuffer(rctx
->blitter
, fb
);
752 util_blitter_clear_render_target(rctx
->blitter
, dst
, rgba
,
753 dstx
, dsty
, width
, height
);
756 static void r600_clear_depth_stencil(struct pipe_context
*ctx
,
757 struct pipe_surface
*dst
,
758 unsigned clear_flags
,
761 unsigned dstx
, unsigned dsty
,
762 unsigned width
, unsigned height
)
764 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
765 struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
;
767 util_blitter_save_framebuffer(rctx
->blitter
, fb
);
768 util_blitter_clear_depth_stencil(rctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
769 dstx
, dsty
, width
, height
);
773 static void r600_resource_copy_region(struct pipe_context
*ctx
,
774 struct pipe_resource
*dst
,
775 struct pipe_subresource subdst
,
776 unsigned dstx
, unsigned dsty
, unsigned dstz
,
777 struct pipe_resource
*src
,
778 struct pipe_subresource subsrc
,
779 unsigned srcx
, unsigned srcy
, unsigned srcz
,
780 unsigned width
, unsigned height
)
782 util_resource_copy_region(ctx
, dst
, subdst
, dstx
, dsty
, dstz
,
783 src
, subsrc
, srcx
, srcy
, srcz
, width
, height
);
786 static void r600_init_blit_functions2(struct r600_pipe_context
*rctx
)
788 rctx
->context
.clear
= r600_clear
;
789 rctx
->context
.clear_render_target
= r600_clear_render_target
;
790 rctx
->context
.clear_depth_stencil
= r600_clear_depth_stencil
;
791 rctx
->context
.resource_copy_region
= r600_resource_copy_region
;
794 static void r600_init_context_resource_functions2(struct r600_pipe_context
*r600
)
796 r600
->context
.get_transfer
= u_get_transfer_vtbl
;
797 r600
->context
.transfer_map
= u_transfer_map_vtbl
;
798 r600
->context
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
799 r600
->context
.transfer_unmap
= u_transfer_unmap_vtbl
;
800 r600
->context
.transfer_destroy
= u_transfer_destroy_vtbl
;
801 r600
->context
.transfer_inline_write
= u_transfer_inline_write_vtbl
;
802 r600
->context
.is_resource_referenced
= u_is_resource_referenced_vtbl
;
805 static void r600_set_blend_color(struct pipe_context
*ctx
,
806 const struct pipe_blend_color
*state
)
808 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
809 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
814 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
815 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), 0xFFFFFFFF, NULL
);
816 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), 0xFFFFFFFF, NULL
);
817 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), 0xFFFFFFFF, NULL
);
818 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), 0xFFFFFFFF, NULL
);
819 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
820 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
821 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
824 static void *r600_create_blend_state(struct pipe_context
*ctx
,
825 const struct pipe_blend_state
*state
)
827 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
828 struct r600_pipe_state
*rstate
;
829 u32 color_control
, target_mask
;
834 rstate
= &blend
->rstate
;
836 rstate
->id
= R600_PIPE_STATE_BLEND
;
839 color_control
= S_028808_PER_MRT_BLEND(1);
840 if (state
->logicop_enable
) {
841 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
843 color_control
|= (0xcc << 16);
845 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
846 if (state
->independent_blend_enable
) {
847 for (int i
= 0; i
< 8; i
++) {
848 if (state
->rt
[i
].blend_enable
) {
849 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
851 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
854 for (int i
= 0; i
< 8; i
++) {
855 if (state
->rt
[0].blend_enable
) {
856 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
858 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
861 blend
->cb_target_mask
= target_mask
;
862 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028808_CB_COLOR_CONTROL
,
863 color_control
, 0xFFFFFFFF, NULL
);
865 for (int i
= 0; i
< 8; i
++) {
866 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
867 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
868 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
870 unsigned eqA
= state
->rt
[i
].alpha_func
;
871 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
872 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
875 if (!state
->rt
[i
].blend_enable
)
878 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
879 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
880 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
882 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
883 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
884 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
885 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
886 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
889 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, bc
, 0xFFFFFFFF, NULL
);
891 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028804_CB_BLEND_CONTROL
, bc
, 0xFFFFFFFF, NULL
);
897 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
899 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
900 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
901 struct r600_pipe_state
*rstate
;
905 rstate
= &blend
->rstate
;
906 rctx
->states
[rstate
->id
] = rstate
;
907 rctx
->cb_target_mask
= blend
->cb_target_mask
;
908 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
911 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
912 const struct pipe_depth_stencil_alpha_state
*state
)
914 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
915 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
916 unsigned stencil_ref_mask
, stencil_ref_mask_bf
, db_render_override
, db_render_control
;
918 if (rstate
== NULL
) {
922 rstate
->id
= R600_PIPE_STATE_DSA
;
923 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
924 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
925 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
926 * be set if shader use texkill instruction
928 db_shader_control
= 0x210;
929 stencil_ref_mask
= 0;
930 stencil_ref_mask_bf
= 0;
931 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
932 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
933 S_028800_ZFUNC(state
->depth
.func
);
936 if (state
->stencil
[0].enabled
) {
937 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
938 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
939 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
940 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
941 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
944 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
945 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
946 if (state
->stencil
[1].enabled
) {
947 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
948 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
949 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
950 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
951 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
952 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
953 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
958 alpha_test_control
= 0;
960 if (state
->alpha
.enabled
) {
961 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
962 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
963 alpha_ref
= fui(state
->alpha
.ref_value
);
967 db_render_control
= 0;
968 db_render_override
= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
969 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
970 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
971 /* TODO db_render_override depends on query */
972 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028028_DB_STENCIL_CLEAR
, 0x00000000, 0xFFFFFFFF, NULL
);
973 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000, 0xFFFFFFFF, NULL
);
974 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028410_SX_ALPHA_TEST_CONTROL
, alpha_test_control
, 0xFFFFFFFF, NULL
);
975 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
976 R_028430_DB_STENCILREFMASK
, stencil_ref_mask
,
977 0xFFFFFFFF & C_028430_STENCILREF
, NULL
);
978 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
979 R_028434_DB_STENCILREFMASK_BF
, stencil_ref_mask_bf
,
980 0xFFFFFFFF & C_028434_STENCILREF_BF
, NULL
);
981 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028438_SX_ALPHA_REF
, alpha_ref
, 0xFFFFFFFF, NULL
);
982 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286E0_SPI_FOG_FUNC_SCALE
, 0x00000000, 0xFFFFFFFF, NULL
);
983 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286E4_SPI_FOG_FUNC_BIAS
, 0x00000000, 0xFFFFFFFF, NULL
);
984 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286DC_SPI_FOG_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
985 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
, 0xFFFFFFFF, NULL
);
986 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
, 0xFFFFFFBE, NULL
);
987 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028D0C_DB_RENDER_CONTROL
, db_render_control
, 0xFFFFFFFF, NULL
);
988 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028D10_DB_RENDER_OVERRIDE
, db_render_override
, 0xFFFFFFFF, NULL
);
989 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 0x00000000, 0xFFFFFFFF, NULL
);
990 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028D30_DB_PRELOAD_CONTROL
, 0x00000000, 0xFFFFFFFF, NULL
);
991 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028D44_DB_ALPHA_TO_MASK
, 0x0000AA00, 0xFFFFFFFF, NULL
);
996 static void *r600_create_rs_state(struct pipe_context
*ctx
,
997 const struct pipe_rasterizer_state
*state
)
999 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
1000 struct r600_pipe_state
*rstate
;
1002 unsigned prov_vtx
= 1;
1008 rstate
= &rs
->rstate
;
1009 rs
->flatshade
= state
->flatshade
;
1010 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
1013 rs
->offset_units
= state
->offset_units
;
1014 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
1016 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
1017 if (state
->flatshade_first
)
1020 if (state
->sprite_coord_enable
) {
1021 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
1022 S_0286D4_PNT_SPRITE_OVRD_X(2) |
1023 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
1024 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
1025 S_0286D4_PNT_SPRITE_OVRD_W(1);
1026 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
1027 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
1030 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
, 0xFFFFFFFF, NULL
);
1032 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028814_PA_SU_SC_MODE_CNTL
,
1033 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
1034 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
1035 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
1036 S_028814_FACE(!state
->front_ccw
) |
1037 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
1038 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
1039 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
), 0xFFFFFFFF, NULL
);
1040 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02881C_PA_CL_VS_OUT_CNTL
,
1041 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
1042 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
), 0xFFFFFFFF, NULL
);
1043 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1044 /* point size 12.4 fixed point */
1045 tmp
= (unsigned)(state
->point_size
* 8.0);
1046 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
), 0xFFFFFFFF, NULL
);
1047 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A04_PA_SU_POINT_MINMAX
, 0x80000000, 0xFFFFFFFF, NULL
);
1048 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A08_PA_SU_LINE_CNTL
, 0x00000008, 0xFFFFFFFF, NULL
);
1049 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A0C_PA_SC_LINE_STIPPLE
, 0x00000005, 0xFFFFFFFF, NULL
);
1050 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
1051 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C00_PA_SC_LINE_CNTL
, 0x00000400, 0xFFFFFFFF, NULL
);
1052 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
1053 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C10_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
1054 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
1055 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C18_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000, 0xFFFFFFFF, NULL
);
1056 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, 0x00000000, 0xFFFFFFFF, NULL
);
1060 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1062 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
1063 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1068 rctx
->flatshade
= rs
->flatshade
;
1069 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
1070 rctx
->rasterizer
= rs
;
1072 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
1073 r600_context_pipe_state_set(&rctx
->ctx
, &rs
->rstate
);
1076 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1078 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1079 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
1081 if (rctx
->rasterizer
== rs
) {
1082 rctx
->rasterizer
= NULL
;
1084 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
1085 rctx
->states
[rs
->rstate
.id
] = NULL
;
1090 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
1091 const struct pipe_sampler_state
*state
)
1093 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1094 union util_color uc
;
1096 if (rstate
== NULL
) {
1100 rstate
->id
= R600_PIPE_STATE_SAMPLER
;
1101 util_pack_color(state
->border_color
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
1102 r600_pipe_state_add_reg(rstate
, R600_GROUP_SAMPLER
, R_03C000_SQ_TEX_SAMPLER_WORD0_0
,
1103 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
1104 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
1105 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
1106 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
1107 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
1108 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
1109 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
1110 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0), 0xFFFFFFFF, NULL
);
1111 /* FIXME LOD it depends on texture base level ... */
1112 r600_pipe_state_add_reg(rstate
, R600_GROUP_SAMPLER
, R_03C004_SQ_TEX_SAMPLER_WORD1_0
,
1113 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
1114 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
1115 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6)), 0xFFFFFFFF, NULL
);
1116 r600_pipe_state_add_reg(rstate
, R600_GROUP_SAMPLER
, R_03C008_SQ_TEX_SAMPLER_WORD2_0
, S_03C008_TYPE(1), 0xFFFFFFFF, NULL
);
1118 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_00A400_TD_PS_SAMPLER0_BORDER_RED
, fui(state
->border_color
[0]), 0xFFFFFFFF, NULL
);
1119 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN
, fui(state
->border_color
[1]), 0xFFFFFFFF, NULL
);
1120 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE
, fui(state
->border_color
[2]), 0xFFFFFFFF, NULL
);
1121 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA
, fui(state
->border_color
[3]), 0xFFFFFFFF, NULL
);
1126 static void *r600_create_vertex_elements(struct pipe_context
*ctx
,
1128 const struct pipe_vertex_element
*elements
)
1130 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
1135 memcpy(v
->elements
, elements
, count
* sizeof(struct pipe_vertex_element
));
1139 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
1140 struct pipe_sampler_view
*state
)
1142 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
1144 pipe_resource_reference(&state
->texture
, NULL
);
1148 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
1149 struct pipe_resource
*texture
,
1150 const struct pipe_sampler_view
*state
)
1152 struct r600_pipe_sampler_view
*resource
= CALLOC_STRUCT(r600_pipe_sampler_view
);
1153 struct r600_pipe_state
*rstate
;
1154 const struct util_format_description
*desc
;
1155 struct r600_resource_texture
*tmp
;
1156 struct r600_resource
*rbuffer
;
1158 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1159 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
1160 struct radeon_ws_bo
*bo
[2];
1162 if (resource
== NULL
)
1164 rstate
= &resource
->state
;
1166 /* initialize base object */
1167 resource
->base
= *state
;
1168 resource
->base
.texture
= NULL
;
1169 pipe_reference(NULL
, &texture
->reference
);
1170 resource
->base
.texture
= texture
;
1171 resource
->base
.reference
.count
= 1;
1172 resource
->base
.context
= ctx
;
1174 swizzle
[0] = state
->swizzle_r
;
1175 swizzle
[1] = state
->swizzle_g
;
1176 swizzle
[2] = state
->swizzle_b
;
1177 swizzle
[3] = state
->swizzle_a
;
1178 format
= r600_translate_texformat(texture
->format
,
1180 &word4
, &yuv_format
);
1184 desc
= util_format_description(texture
->format
);
1186 R600_ERR("unknow format %d\n", texture
->format
);
1188 tmp
= (struct r600_resource_texture
*)texture
;
1189 rbuffer
= &tmp
->resource
;
1190 bo
[0] = rbuffer
->bo
;
1191 bo
[1] = rbuffer
->bo
;
1192 /* FIXME depth texture decompression */
1195 r
= r600_texture_from_depth(ctx
, tmp
, view
->first_level
);
1199 bo
[0] = radeon_ws_bo_incref(rscreen
->rw
, tmp
->uncompressed
);
1200 bo
[1] = radeon_ws_bo_incref(rscreen
->rw
, tmp
->uncompressed
);
1203 pitch
= align(tmp
->pitch
[0] / tmp
->bpt
, 8);
1205 /* FIXME properly handle first level != 0 */
1206 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038000_RESOURCE0_WORD0
,
1207 S_038000_DIM(r600_tex_dim(texture
->target
)) |
1208 S_038000_TILE_MODE(array_mode
) |
1209 S_038000_TILE_TYPE(tile_type
) |
1210 S_038000_PITCH((pitch
/ 8) - 1) |
1211 S_038000_TEX_WIDTH(texture
->width0
- 1), 0xFFFFFFFF, NULL
);
1212 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038004_RESOURCE0_WORD1
,
1213 S_038004_TEX_HEIGHT(texture
->height0
- 1) |
1214 S_038004_TEX_DEPTH(texture
->depth0
- 1) |
1215 S_038004_DATA_FORMAT(format
), 0xFFFFFFFF, NULL
);
1216 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038008_RESOURCE0_WORD2
,
1217 tmp
->offset
[0] >> 8, 0xFFFFFFFF, bo
[0]);
1218 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_03800C_RESOURCE0_WORD3
,
1219 tmp
->offset
[1] >> 8, 0xFFFFFFFF, bo
[1]);
1220 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038010_RESOURCE0_WORD4
,
1221 word4
| S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM
) |
1222 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO
) |
1223 S_038010_REQUEST_SIZE(1) |
1224 S_038010_BASE_LEVEL(state
->first_level
), 0xFFFFFFFF, NULL
);
1225 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038014_RESOURCE0_WORD5
,
1226 S_038014_LAST_LEVEL(state
->last_level
) |
1227 S_038014_BASE_ARRAY(0) |
1228 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL
);
1229 r600_pipe_state_add_reg(rstate
, R600_GROUP_RESOURCE
, R_038018_RESOURCE0_WORD6
,
1230 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
), 0xFFFFFFFF, NULL
);
1232 return &resource
->base
;
1235 static void r600_set_vs_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1236 struct pipe_sampler_view
**views
)
1242 static void r600_set_ps_sampler_view(struct pipe_context
*ctx
, unsigned count
,
1243 struct pipe_sampler_view
**views
)
1245 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1246 struct r600_pipe_sampler_view
**resource
= (struct r600_pipe_sampler_view
**)views
;
1248 for (int i
= 0; i
< count
; i
++) {
1250 r600_context_pipe_state_set_ps_resource(&rctx
->ctx
, &resource
[i
]->state
, i
);
1255 static void r600_bind_state(struct pipe_context
*ctx
, void *state
)
1257 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1258 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
1262 rctx
->states
[rstate
->id
] = rstate
;
1263 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1266 static void r600_bind_ps_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1268 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1269 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1271 for (int i
= 0; i
< count
; i
++) {
1272 r600_context_pipe_state_set_ps_sampler(&rctx
->ctx
, rstates
[i
], i
);
1276 static void r600_bind_vs_sampler(struct pipe_context
*ctx
, unsigned count
, void **states
)
1278 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1279 struct r600_pipe_state
**rstates
= (struct r600_pipe_state
**)states
;
1281 /* TODO implement */
1282 for (int i
= 0; i
< count
; i
++) {
1283 r600_context_pipe_state_set_vs_sampler(&rctx
->ctx
, rstates
[i
], i
);
1287 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
1289 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1290 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
1292 if (rctx
->states
[rstate
->id
] == rstate
) {
1293 rctx
->states
[rstate
->id
] = NULL
;
1295 for (int i
= 0; i
< rstate
->nregs
; i
++) {
1296 radeon_ws_bo_reference(rctx
->radeon
, &rstate
->regs
[i
].bo
, NULL
);
1301 static void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
1303 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
1312 static void r600_set_clip_state(struct pipe_context
*ctx
,
1313 const struct pipe_clip_state
*state
)
1315 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1316 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1321 rctx
->clip
= *state
;
1322 rstate
->id
= R600_PIPE_STATE_CLIP
;
1323 for (int i
= 0; i
< state
->nr
; i
++) {
1324 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1325 R_028E20_PA_CL_UCP0_X
+ i
* 4,
1326 fui(state
->ucp
[i
][0]), 0xFFFFFFFF, NULL
);
1327 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1328 R_028E24_PA_CL_UCP0_Y
+ i
* 4,
1329 fui(state
->ucp
[i
][1]) , 0xFFFFFFFF, NULL
);
1330 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1331 R_028E28_PA_CL_UCP0_Z
+ i
* 4,
1332 fui(state
->ucp
[i
][2]), 0xFFFFFFFF, NULL
);
1333 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1334 R_028E2C_PA_CL_UCP0_W
+ i
* 4,
1335 fui(state
->ucp
[i
][3]), 0xFFFFFFFF, NULL
);
1337 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028810_PA_CL_CLIP_CNTL
,
1338 S_028810_PS_UCP_MODE(3) | ((1 << state
->nr
) - 1) |
1339 S_028810_ZCLIP_NEAR_DISABLE(state
->depth_clamp
) |
1340 S_028810_ZCLIP_FAR_DISABLE(state
->depth_clamp
), 0xFFFFFFFF, NULL
);
1342 free(rctx
->states
[R600_PIPE_STATE_CLIP
]);
1343 rctx
->states
[R600_PIPE_STATE_CLIP
] = rstate
;
1344 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1347 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
1349 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1350 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
1352 r600_delete_vertex_element(ctx
, rctx
->vertex_elements
);
1353 rctx
->vertex_elements
= v
;
1356 // rctx->vs_rebuild = TRUE;
1360 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
1361 const struct pipe_poly_stipple
*state
)
1365 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1369 static void r600_set_scissor_state(struct pipe_context
*ctx
,
1370 const struct pipe_scissor_state
*state
)
1372 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1373 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1379 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1380 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
1381 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
1382 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1383 R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
,
1385 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1386 R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
,
1388 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1389 R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
,
1391 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1392 R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
,
1394 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1395 R_028210_PA_SC_CLIPRECT_0_TL
, tl
,
1397 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1398 R_028214_PA_SC_CLIPRECT_0_BR
, br
,
1400 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1401 R_028218_PA_SC_CLIPRECT_1_TL
, tl
,
1403 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1404 R_02821C_PA_SC_CLIPRECT_1_BR
, br
,
1406 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1407 R_028220_PA_SC_CLIPRECT_2_TL
, tl
,
1409 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1410 R_028224_PA_SC_CLIPRECT_2_BR
, br
,
1412 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1413 R_028228_PA_SC_CLIPRECT_3_TL
, tl
,
1415 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1416 R_02822C_PA_SC_CLIPRECT_3_BR
, br
,
1418 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1419 R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000,
1421 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1422 R_02820C_PA_SC_CLIPRECT_RULE
, 0x0000FFFF,
1424 if (rctx
->family
>= CHIP_RV770
) {
1425 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1426 R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA,
1430 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1431 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1432 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1435 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
1436 const struct pipe_stencil_ref
*state
)
1438 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1439 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1445 rctx
->stencil_ref
= *state
;
1446 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
1447 tmp
= S_028430_STENCILREF(state
->ref_value
[0]);
1448 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1449 R_028430_DB_STENCILREFMASK
, tmp
,
1450 ~C_028430_STENCILREF
, NULL
);
1451 tmp
= S_028434_STENCILREF_BF(state
->ref_value
[1]);
1452 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1453 R_028434_DB_STENCILREFMASK_BF
, tmp
,
1454 ~C_028434_STENCILREF_BF
, NULL
);
1456 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
1457 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
1458 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1461 static void r600_set_viewport_state(struct pipe_context
*ctx
,
1462 const struct pipe_viewport_state
*state
)
1464 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1465 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1470 rctx
->viewport
= *state
;
1471 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
1472 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000, 0xFFFFFFFF, NULL
);
1473 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000, 0xFFFFFFFF, NULL
);
1474 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]), 0xFFFFFFFF, NULL
);
1475 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]), 0xFFFFFFFF, NULL
);
1476 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]), 0xFFFFFFFF, NULL
);
1477 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]), 0xFFFFFFFF, NULL
);
1478 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]), 0xFFFFFFFF, NULL
);
1479 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]), 0xFFFFFFFF, NULL
);
1480 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F, 0xFFFFFFFF, NULL
);
1482 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
1483 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
1484 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1487 static void r600_cb(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
1488 const struct pipe_framebuffer_state
*state
, int cb
)
1490 struct r600_resource_texture
*rtex
;
1491 struct r600_resource
*rbuffer
;
1492 unsigned level
= state
->cbufs
[cb
]->level
;
1493 unsigned pitch
, slice
;
1494 unsigned color_info
;
1495 unsigned format
, swap
, ntype
;
1496 const struct util_format_description
*desc
;
1497 struct radeon_ws_bo
*bo
[3];
1499 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
1500 rbuffer
= &rtex
->resource
;
1501 bo
[0] = rbuffer
->bo
;
1502 bo
[1] = rbuffer
->bo
;
1503 bo
[2] = rbuffer
->bo
;
1505 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
1506 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->cbufs
[cb
]->height
/ 64 - 1;
1508 desc
= util_format_description(rtex
->resource
.base
.b
.format
);
1509 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1510 ntype
= V_0280A0_NUMBER_SRGB
;
1512 format
= r600_translate_colorformat(rtex
->resource
.base
.b
.format
);
1513 swap
= r600_translate_colorswap(rtex
->resource
.base
.b
.format
);
1514 color_info
= S_0280A0_FORMAT(format
) |
1515 S_0280A0_COMP_SWAP(swap
) |
1516 S_0280A0_BLEND_CLAMP(1) |
1517 S_0280A0_SOURCE_FORMAT(1) |
1518 S_0280A0_NUMBER_TYPE(ntype
);
1520 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1521 R_028040_CB_COLOR0_BASE
+ cb
* 4,
1522 state
->cbufs
[cb
]->offset
>> 8, 0xFFFFFFFF, bo
[0]);
1523 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1524 R_0280A0_CB_COLOR0_INFO
+ cb
* 4,
1525 color_info
, 0xFFFFFFFF, bo
[0]);
1526 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1527 R_028060_CB_COLOR0_SIZE
+ cb
* 4,
1528 S_028060_PITCH_TILE_MAX(pitch
) |
1529 S_028060_SLICE_TILE_MAX(slice
),
1531 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1532 R_028080_CB_COLOR0_VIEW
+ cb
* 4,
1533 0x00000000, 0xFFFFFFFF, NULL
);
1534 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1535 R_0280E0_CB_COLOR0_FRAG
+ cb
* 4,
1536 0x00000000, 0xFFFFFFFF, bo
[1]);
1537 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1538 R_0280C0_CB_COLOR0_TILE
+ cb
* 4,
1539 0x00000000, 0xFFFFFFFF, bo
[2]);
1540 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1541 R_028100_CB_COLOR0_MASK
+ cb
* 4,
1542 0x00000000, 0xFFFFFFFF, NULL
);
1545 static void r600_db(struct r600_pipe_context
*rctx
, struct r600_pipe_state
*rstate
,
1546 const struct pipe_framebuffer_state
*state
)
1548 struct r600_resource_texture
*rtex
;
1549 struct r600_resource
*rbuffer
;
1551 unsigned pitch
, slice
, format
;
1553 if (state
->zsbuf
== NULL
)
1556 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
1558 rtex
->array_mode
= 2;
1559 rtex
->tile_type
= 1;
1561 rbuffer
= &rtex
->resource
;
1563 level
= state
->zsbuf
->level
;
1564 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
1565 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->zsbuf
->height
/ 64 - 1;
1566 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
1568 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02800C_DB_DEPTH_BASE
,
1569 state
->zsbuf
->offset
>> 8, 0xFFFFFFFF, rbuffer
->bo
);
1570 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028000_DB_DEPTH_SIZE
,
1571 S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
),
1573 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028004_DB_DEPTH_VIEW
, 0x00000000, 0xFFFFFFFF, NULL
);
1574 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028010_DB_DEPTH_INFO
,
1575 S_028010_ARRAY_MODE(rtex
->array_mode
) | S_028010_FORMAT(format
),
1576 0xFFFFFFFF, rbuffer
->bo
);
1577 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028D34_DB_PREFETCH_LIMIT
,
1578 (state
->zsbuf
->height
/ 8) - 1, 0xFFFFFFFF, NULL
);
1581 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1582 const struct pipe_framebuffer_state
*state
)
1584 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1585 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1586 u32 shader_mask
, tl
, br
, shader_control
, target_mask
;
1591 /* unreference old buffer and reference new one */
1592 rstate
->id
= R600_PIPE_STATE_FRAMEBUFFER
;
1593 for (int i
= 0; i
< rctx
->framebuffer
.nr_cbufs
; i
++) {
1594 pipe_surface_reference(&rctx
->framebuffer
.cbufs
[i
], NULL
);
1596 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1597 pipe_surface_reference(&rctx
->framebuffer
.cbufs
[i
], state
->cbufs
[i
]);
1599 pipe_surface_reference(&rctx
->framebuffer
.zsbuf
, state
->zsbuf
);
1600 rctx
->framebuffer
= *state
;
1603 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1604 r600_cb(rctx
, rstate
, state
, i
);
1607 r600_db(rctx
, rstate
, state
);
1610 target_mask
= 0x00000000;
1611 target_mask
= 0xFFFFFFFF;
1614 for (int i
= 0; i
< state
->nr_cbufs
; i
++) {
1615 target_mask
^= 0xf << (i
* 4);
1616 shader_mask
|= 0xf << (i
* 4);
1617 shader_control
|= 1 << i
;
1619 tl
= S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1620 br
= S_028244_BR_X(state
->width
) | S_028244_BR_Y(state
->height
);
1622 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1623 R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
,
1625 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1626 R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
,
1628 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1629 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
,
1631 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
,
1632 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
,
1635 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0287A0_CB_SHADER_CONTROL
,
1636 shader_control
, 0xFFFFFFFF, NULL
);
1637 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028238_CB_TARGET_MASK
,
1638 0x00000000, target_mask
, NULL
);
1639 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02823C_CB_SHADER_MASK
,
1640 shader_mask
, 0xFFFFFFFF, NULL
);
1641 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C04_PA_SC_AA_CONFIG
,
1642 0x00000000, 0xFFFFFFFF, NULL
);
1643 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
,
1644 0x00000000, 0xFFFFFFFF, NULL
);
1645 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
,
1646 0x00000000, 0xFFFFFFFF, NULL
);
1647 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C30_CB_CLRCMP_CONTROL
,
1648 0x01000000, 0xFFFFFFFF, NULL
);
1649 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C34_CB_CLRCMP_SRC
,
1650 0x00000000, 0xFFFFFFFF, NULL
);
1651 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C38_CB_CLRCMP_DST
,
1652 0x000000FF, 0xFFFFFFFF, NULL
);
1653 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C3C_CB_CLRCMP_MSK
,
1654 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
1655 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028C48_PA_SC_AA_MASK
,
1656 0xFFFFFFFF, 0xFFFFFFFF, NULL
);
1658 free(rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
]);
1659 rctx
->states
[R600_PIPE_STATE_FRAMEBUFFER
] = rstate
;
1660 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
1663 static void r600_set_index_buffer(struct pipe_context
*ctx
,
1664 const struct pipe_index_buffer
*ib
)
1666 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1669 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
1670 memcpy(&rctx
->index_buffer
, ib
, sizeof(rctx
->index_buffer
));
1672 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
1673 memset(&rctx
->index_buffer
, 0, sizeof(rctx
->index_buffer
));
1676 /* TODO make this more like a state */
1679 static void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
1680 const struct pipe_vertex_buffer
*buffers
)
1682 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1684 for (int i
= 0; i
< rctx
->nvertex_buffer
; i
++) {
1685 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, NULL
);
1687 memcpy(rctx
->vertex_buffer
, buffers
, sizeof(struct pipe_vertex_buffer
) * count
);
1688 for (int i
= 0; i
< count
; i
++) {
1689 rctx
->vertex_buffer
[i
].buffer
= NULL
;
1690 if (r600_buffer_is_user_buffer(buffers
[i
].buffer
))
1691 rctx
->any_user_vbs
= TRUE
;
1692 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, buffers
[i
].buffer
);
1694 rctx
->nvertex_buffer
= count
;
1697 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
1698 struct pipe_resource
*buffer
)
1700 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1701 struct r600_pipe_state
*rstate
;
1702 struct pipe_transfer
*transfer
;
1703 unsigned *nconst
= NULL
;
1707 case PIPE_SHADER_VERTEX
:
1708 rstate
= rctx
->vs_const
;
1709 nconst
= &rctx
->vs_nconst
;
1710 offset
= R_030000_SQ_ALU_CONSTANT0_0
+ 0x1000;
1712 case PIPE_SHADER_FRAGMENT
:
1713 rstate
= rctx
->ps_const
;
1714 nconst
= &rctx
->ps_nconst
;
1715 offset
= R_030000_SQ_ALU_CONSTANT0_0
;
1718 R600_ERR("unsupported %d\n", shader
);
1721 if (buffer
&& buffer
->width0
> 0) {
1722 *nconst
= buffer
->width0
/ 16;
1723 ptr
= pipe_buffer_map(ctx
, buffer
, PIPE_TRANSFER_READ
, &transfer
);
1726 for (int i
= 0; i
< *nconst
; i
++, offset
+= 0x10) {
1727 rstate
[i
].nregs
= 0;
1728 r600_pipe_state_add_reg(&rstate
[i
], R600_GROUP_ALU_CONST
, offset
+ 0x0, ptr
[i
* 4 + 0], 0xFFFFFFFF, NULL
);
1729 r600_pipe_state_add_reg(&rstate
[i
], R600_GROUP_ALU_CONST
, offset
+ 0x4, ptr
[i
* 4 + 1], 0xFFFFFFFF, NULL
);
1730 r600_pipe_state_add_reg(&rstate
[i
], R600_GROUP_ALU_CONST
, offset
+ 0x8, ptr
[i
* 4 + 2], 0xFFFFFFFF, NULL
);
1731 r600_pipe_state_add_reg(&rstate
[i
], R600_GROUP_ALU_CONST
, offset
+ 0xC, ptr
[i
* 4 + 3], 0xFFFFFFFF, NULL
);
1732 r600_context_pipe_state_set(&rctx
->ctx
, &rstate
[i
]);
1734 pipe_buffer_unmap(ctx
, buffer
, transfer
);
1738 static void *r600_create_shader_state(struct pipe_context
*ctx
,
1739 const struct pipe_shader_state
*state
)
1741 struct r600_pipe_shader
*shader
= CALLOC_STRUCT(r600_pipe_shader
);
1744 r
= r600_pipe_shader_create2(ctx
, shader
, state
->tokens
);
1751 static void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
1753 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1755 /* TODO delete old shader */
1756 rctx
->ps_shader
= (struct r600_pipe_shader
*)state
;
1759 static void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
1761 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1763 /* TODO delete old shader */
1764 rctx
->vs_shader
= (struct r600_pipe_shader
*)state
;
1767 static void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
1769 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1770 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
1772 if (rctx
->ps_shader
== shader
) {
1773 rctx
->ps_shader
= NULL
;
1775 /* TODO proper delete */
1779 static void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
1781 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
1782 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
1784 if (rctx
->vs_shader
== shader
) {
1785 rctx
->vs_shader
= NULL
;
1787 /* TODO proper delete */
1791 static void r600_init_state_functions2(struct r600_pipe_context
*rctx
)
1793 rctx
->context
.create_blend_state
= r600_create_blend_state
;
1794 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
1795 rctx
->context
.create_fs_state
= r600_create_shader_state
;
1796 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
1797 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
1798 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
1799 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1800 rctx
->context
.create_vs_state
= r600_create_shader_state
;
1801 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1802 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_state
;
1803 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler
;
1804 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
1805 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1806 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1807 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler
;
1808 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
1809 rctx
->context
.delete_blend_state
= r600_delete_state
;
1810 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1811 rctx
->context
.delete_fs_state
= r600_delete_ps_shader
;
1812 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1813 rctx
->context
.delete_sampler_state
= r600_delete_state
;
1814 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
1815 rctx
->context
.delete_vs_state
= r600_delete_vs_shader
;
1816 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1817 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1818 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1819 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_view
;
1820 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
1821 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
1822 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1823 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
1824 rctx
->context
.set_stencil_ref
= r600_set_stencil_ref
;
1825 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1826 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1827 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_view
;
1828 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1829 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1832 static void r600_init_config2(struct r600_pipe_context
*rctx
)
1847 int num_ps_stack_entries
;
1848 int num_vs_stack_entries
;
1849 int num_gs_stack_entries
;
1850 int num_es_stack_entries
;
1851 enum radeon_family family
;
1852 struct r600_pipe_state
*rstate
= &rctx
->config
;
1855 family
= r600_get_family(rctx
->radeon
);
1867 num_ps_threads
= 136;
1868 num_vs_threads
= 48;
1871 num_ps_stack_entries
= 128;
1872 num_vs_stack_entries
= 128;
1873 num_gs_stack_entries
= 0;
1874 num_es_stack_entries
= 0;
1883 num_ps_threads
= 144;
1884 num_vs_threads
= 40;
1887 num_ps_stack_entries
= 40;
1888 num_vs_stack_entries
= 40;
1889 num_gs_stack_entries
= 32;
1890 num_es_stack_entries
= 16;
1902 num_ps_threads
= 136;
1903 num_vs_threads
= 48;
1906 num_ps_stack_entries
= 40;
1907 num_vs_stack_entries
= 40;
1908 num_gs_stack_entries
= 32;
1909 num_es_stack_entries
= 16;
1917 num_ps_threads
= 136;
1918 num_vs_threads
= 48;
1921 num_ps_stack_entries
= 40;
1922 num_vs_stack_entries
= 40;
1923 num_gs_stack_entries
= 32;
1924 num_es_stack_entries
= 16;
1932 num_ps_threads
= 188;
1933 num_vs_threads
= 60;
1936 num_ps_stack_entries
= 256;
1937 num_vs_stack_entries
= 256;
1938 num_gs_stack_entries
= 0;
1939 num_es_stack_entries
= 0;
1948 num_ps_threads
= 188;
1949 num_vs_threads
= 60;
1952 num_ps_stack_entries
= 128;
1953 num_vs_stack_entries
= 128;
1954 num_gs_stack_entries
= 0;
1955 num_es_stack_entries
= 0;
1963 num_ps_threads
= 144;
1964 num_vs_threads
= 48;
1967 num_ps_stack_entries
= 128;
1968 num_vs_stack_entries
= 128;
1969 num_gs_stack_entries
= 0;
1970 num_es_stack_entries
= 0;
1974 rstate
->id
= R600_PIPE_STATE_CONFIG
;
1986 tmp
|= S_008C00_VC_ENABLE(1);
1989 tmp
|= S_008C00_DX9_CONSTS(1);
1990 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
1991 tmp
|= S_008C00_PS_PRIO(ps_prio
);
1992 tmp
|= S_008C00_VS_PRIO(vs_prio
);
1993 tmp
|= S_008C00_GS_PRIO(gs_prio
);
1994 tmp
|= S_008C00_ES_PRIO(es_prio
);
1995 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_008C00_SQ_CONFIG
, tmp
, 0xFFFFFFFF, NULL
);
1997 /* SQ_GPR_RESOURCE_MGMT_1 */
1999 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2000 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2001 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs
);
2002 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
2004 /* SQ_GPR_RESOURCE_MGMT_2 */
2006 tmp
|= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2007 tmp
|= S_008C08_NUM_GS_GPRS(num_es_gprs
);
2008 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
2010 /* SQ_THREAD_RESOURCE_MGMT */
2012 tmp
|= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2013 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2014 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2015 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2016 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_008C0C_SQ_THREAD_RESOURCE_MGMT
, tmp
, 0xFFFFFFFF, NULL
);
2018 /* SQ_STACK_RESOURCE_MGMT_1 */
2020 tmp
|= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2021 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2022 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_008C10_SQ_STACK_RESOURCE_MGMT_1
, tmp
, 0xFFFFFFFF, NULL
);
2024 /* SQ_STACK_RESOURCE_MGMT_2 */
2026 tmp
|= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2027 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2028 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_008C14_SQ_STACK_RESOURCE_MGMT_2
, tmp
, 0xFFFFFFFF, NULL
);
2030 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_009714_VC_ENHANCE
, 0x00000000, 0xFFFFFFFF, NULL
);
2031 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028350_SX_MISC
, 0x00000000, 0xFFFFFFFF, NULL
);
2033 if (family
>= CHIP_RV770
) {
2034 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000, 0xFFFFFFFF, NULL
);
2035 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_009508_TA_CNTL_AUX
, 0x07000002, 0xFFFFFFFF, NULL
);
2036 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_009830_DB_DEBUG
, 0x00000000, 0xFFFFFFFF, NULL
);
2037 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_009838_DB_WATERMARKS
, 0x00420204, 0xFFFFFFFF, NULL
);
2038 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286C8_SPI_THREAD_GROUPING
, 0x00000000, 0xFFFFFFFF, NULL
);
2039 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A4C_PA_SC_MODE_CNTL
, 0x00514000, 0xFFFFFFFF, NULL
);
2041 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00000000, 0xFFFFFFFF, NULL
);
2042 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_009508_TA_CNTL_AUX
, 0x07000003, 0xFFFFFFFF, NULL
);
2043 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_009830_DB_DEBUG
, 0x82000000, 0xFFFFFFFF, NULL
);
2044 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONFIG
, R_009838_DB_WATERMARKS
, 0x01020204, 0xFFFFFFFF, NULL
);
2045 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0286C8_SPI_THREAD_GROUPING
, 0x00000001, 0xFFFFFFFF, NULL
);
2046 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A4C_PA_SC_MODE_CNTL
, 0x00004010, 0xFFFFFFFF, NULL
);
2048 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2049 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2050 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2051 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2052 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2053 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2054 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288C0_SQ_FBUF_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2055 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288C4_SQ_REDUC_RING_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2056 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_0288C8_SQ_GS_VERT_ITEMSIZE
, 0x00000000, 0xFFFFFFFF, NULL
);
2057 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
2058 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A14_VGT_HOS_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
2059 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x00000000, 0xFFFFFFFF, NULL
);
2060 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x00000000, 0xFFFFFFFF, NULL
);
2061 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x00000000, 0xFFFFFFFF, NULL
);
2062 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x00000000, 0xFFFFFFFF, NULL
);
2063 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x00000000, 0xFFFFFFFF, NULL
);
2064 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A2C_VGT_GROUP_DECR
, 0x00000000, 0xFFFFFFFF, NULL
);
2065 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
2066 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
2067 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
2068 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x00000000, 0xFFFFFFFF, NULL
);
2069 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A40_VGT_GS_MODE
, 0x00000000, 0xFFFFFFFF, NULL
);
2070 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028AB0_VGT_STRMOUT_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
2071 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028AB4_VGT_REUSE_OFF
, 0x00000001, 0xFFFFFFFF, NULL
);
2072 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028AB8_VGT_VTX_CNT_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
2073 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
2075 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, 0x00000000, 0xFFFFFFFF, NULL
);
2076 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A84_VGT_PRIMITIVEID_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
2077 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, 0x00000000, 0xFFFFFFFF, NULL
);
2078 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0x00000000, 0xFFFFFFFF, NULL
);
2079 r600_pipe_state_add_reg(rstate
, R600_GROUP_CONTEXT
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0x00000000, 0xFFFFFFFF, NULL
);
2080 r600_context_pipe_state_set(&rctx
->ctx
, rstate
);
2083 static struct pipe_query
*r600_create_query(struct pipe_context
*ctx
, unsigned query_type
)
2085 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2087 return (struct pipe_query
*)r600_context_query_create(&rctx
->ctx
, query_type
);
2090 static void r600_destroy_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
2092 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2094 r600_context_query_destroy(&rctx
->ctx
, (struct r600_query
*)query
);
2097 static void r600_begin_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
2099 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2100 struct r600_query
*rquery
= (struct r600_query
*)query
;
2103 rquery
->num_results
= 0;
2104 r600_query_begin(&rctx
->ctx
, (struct r600_query
*)query
);
2107 static void r600_end_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
2109 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2111 r600_query_end(&rctx
->ctx
, (struct r600_query
*)query
);
2114 static boolean
r600_get_query_result(struct pipe_context
*ctx
,
2115 struct pipe_query
*query
,
2116 boolean wait
, void *vresult
)
2118 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
2119 struct r600_query
*rquery
= (struct r600_query
*)query
;
2121 if (rquery
->num_results
) {
2122 ctx
->flush(ctx
, 0, NULL
);
2124 return r600_context_query_result(&rctx
->ctx
, (struct r600_query
*)query
, wait
, vresult
);
2127 static void r600_init_query_functions2(struct r600_pipe_context
*rctx
)
2129 rctx
->context
.create_query
= r600_create_query
;
2130 rctx
->context
.destroy_query
= r600_destroy_query
;
2131 rctx
->context
.begin_query
= r600_begin_query
;
2132 rctx
->context
.end_query
= r600_end_query
;
2133 rctx
->context
.get_query_result
= r600_get_query_result
;
2136 static struct pipe_context
*r600_create_context2(struct pipe_screen
*screen
, void *priv
)
2138 struct r600_pipe_context
*rctx
= CALLOC_STRUCT(r600_pipe_context
);
2139 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
2143 rctx
->context
.winsys
= rscreen
->screen
.winsys
;
2144 rctx
->context
.screen
= screen
;
2145 rctx
->context
.priv
= priv
;
2146 rctx
->context
.destroy
= r600_destroy_context
;
2147 rctx
->context
.flush
= r600_flush2
;
2149 /* Easy accessing of screen/winsys. */
2150 rctx
->screen
= rscreen
;
2151 rctx
->radeon
= rscreen
->radeon
;
2152 rctx
->family
= r600_get_family(rctx
->radeon
);
2154 r600_init_blit_functions2(rctx
);
2155 r600_init_query_functions2(rctx
);
2156 r600_init_context_resource_functions2(rctx
);
2158 switch (r600_get_family(rctx
->radeon
)) {
2171 rctx
->context
.draw_vbo
= r600_draw_vbo2
;
2172 r600_init_state_functions2(rctx
);
2173 if (r600_context_init(&rctx
->ctx
, rctx
->radeon
)) {
2174 r600_destroy_context(&rctx
->context
);
2177 r600_init_config2(rctx
);
2184 rctx
->context
.draw_vbo
= evergreen_draw
;
2185 evergreen_init_state_functions2(rctx
);
2186 if (evergreen_context_init(&rctx
->ctx
, rctx
->radeon
)) {
2187 r600_destroy_context(&rctx
->context
);
2190 evergreen_init_config2(rctx
);
2193 R600_ERR("unsupported family %d\n", r600_get_family(rctx
->radeon
));
2194 r600_destroy_context(&rctx
->context
);
2198 rctx
->upload_ib
= u_upload_create(&rctx
->context
, 32 * 1024, 16,
2199 PIPE_BIND_INDEX_BUFFER
);
2200 if (rctx
->upload_ib
== NULL
) {
2201 r600_destroy_context(&rctx
->context
);
2205 rctx
->upload_vb
= u_upload_create(&rctx
->context
, 128 * 1024, 16,
2206 PIPE_BIND_VERTEX_BUFFER
);
2207 if (rctx
->upload_vb
== NULL
) {
2208 r600_destroy_context(&rctx
->context
);
2212 rctx
->blitter
= util_blitter_create(&rctx
->context
);
2213 if (rctx
->blitter
== NULL
) {
2218 return &rctx
->context
;
2221 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
2225 case PIPE_SHADER_FRAGMENT
:
2226 case PIPE_SHADER_VERTEX
:
2228 case PIPE_SHADER_GEOMETRY
:
2229 /* TODO: support and enable geometry programs */
2232 /* TODO: support tessellation on Evergreen */
2236 /* TODO: all these should be fixed, since r600 surely supports much more! */
2238 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
2239 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
2240 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
2241 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
2243 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
2244 return 8; /* FIXME */
2245 case PIPE_SHADER_CAP_MAX_INPUTS
:
2246 if(shader
== PIPE_SHADER_FRAGMENT
)
2250 case PIPE_SHADER_CAP_MAX_TEMPS
:
2251 return 256; //max native temporaries
2252 case PIPE_SHADER_CAP_MAX_ADDRS
:
2253 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
2254 case PIPE_SHADER_CAP_MAX_CONSTS
:
2255 return 256; //max native parameters
2256 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
2258 case PIPE_SHADER_CAP_MAX_PREDS
:
2259 return 0; /* FIXME */
2260 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
2267 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
2268 const struct pipe_resource
*templ
);
2269 struct pipe_resource
*r600_user_buffer_create2(struct pipe_screen
*screen
,
2270 void *ptr
, unsigned bytes
,
2273 struct pipe_resource
*resource
;
2274 struct r600_resource
*rresource
;
2275 struct pipe_resource desc
;
2276 struct radeon
*radeon
= (struct radeon
*)screen
->winsys
;
2279 desc
.screen
= screen
;
2280 desc
.target
= PIPE_BUFFER
;
2281 desc
.format
= PIPE_FORMAT_R8_UNORM
;
2282 desc
.usage
= PIPE_USAGE_IMMUTABLE
;
2284 desc
.width0
= bytes
;
2288 resource
= r600_buffer_create(screen
, &desc
);
2289 if (resource
== NULL
) {
2293 rresource
= (struct r600_resource
*)resource
;
2294 rptr
= radeon_ws_bo_map(radeon
, rresource
->bo
, 0, NULL
);
2295 memcpy(rptr
, ptr
, bytes
);
2296 radeon_ws_bo_unmap(radeon
, rresource
->bo
);
2301 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
2302 struct pipe_screen
*r600_screen_create2(struct radeon
*radeon
)
2304 struct r600_screen
*rscreen
;
2306 rscreen
= CALLOC_STRUCT(r600_screen
);
2307 if (rscreen
== NULL
) {
2311 rscreen
->radeon
= radeon
;
2312 rscreen
->screen
.winsys
= (struct pipe_winsys
*)radeon
;
2313 rscreen
->screen
.destroy
= r600_destroy_screen
;
2314 rscreen
->screen
.get_name
= r600_get_name
;
2315 rscreen
->screen
.get_vendor
= r600_get_vendor
;
2316 rscreen
->screen
.get_param
= r600_get_param
;
2317 rscreen
->screen
.get_shader_param
= r600_get_shader_param
;
2318 rscreen
->screen
.get_paramf
= r600_get_paramf
;
2319 rscreen
->screen
.is_format_supported
= r600_is_format_supported
;
2320 rscreen
->screen
.context_create
= r600_create_context2
;
2321 r600_init_screen_texture_functions(&rscreen
->screen
);
2322 r600_init_screen_resource_functions(&rscreen
->screen
);
2323 // rscreen->screen.user_buffer_create = r600_user_buffer_create2;
2325 return &rscreen
->screen
;
2328 int r600_upload_index_buffer2(struct r600_pipe_context
*rctx
, struct r600_drawl
*draw
)
2330 struct pipe_resource
*upload_buffer
= NULL
;
2331 unsigned index_offset
= draw
->index_buffer_offset
;
2334 if (r600_buffer_is_user_buffer(draw
->index_buffer
)) {
2335 ret
= u_upload_buffer(rctx
->upload_ib
,
2337 draw
->count
* draw
->index_size
,
2344 draw
->index_buffer_offset
= index_offset
;
2345 draw
->index_buffer
= upload_buffer
;
2352 int r600_upload_user_buffers2(struct r600_pipe_context
*rctx
)
2354 enum pipe_error ret
= PIPE_OK
;
2357 nr
= rctx
->vertex_elements
->count
;
2359 for (i
= 0; i
< nr
; i
++) {
2360 struct pipe_vertex_buffer
*vb
=
2361 &rctx
->vertex_buffer
[rctx
->vertex_elements
->elements
[i
].vertex_buffer_index
];
2363 if (r600_buffer_is_user_buffer(vb
->buffer
)) {
2364 struct pipe_resource
*upload_buffer
= NULL
;
2365 unsigned offset
= 0; /*vb->buffer_offset * 4;*/
2366 unsigned size
= vb
->buffer
->width0
;
2367 unsigned upload_offset
;
2368 ret
= u_upload_buffer(rctx
->upload_vb
,
2371 &upload_offset
, &upload_buffer
);
2375 pipe_resource_reference(&vb
->buffer
, NULL
);
2376 vb
->buffer
= upload_buffer
;
2377 vb
->buffer_offset
= upload_offset
;