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0a159113d391cfad2575e152fba669b8becfc04a
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_blitter.h"
31 #include "tgsi/tgsi_parse.h"
32
33 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
34 {
35 struct radeon_winsys_cs *cs = rctx->cs;
36 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
37
38 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
39 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
40 cs->cdw += cb->atom.num_dw;
41 }
42
43 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
44 {
45 cb->atom.emit = r600_emit_command_buffer;
46 cb->atom.num_dw = 0;
47 cb->atom.flags = flags;
48 cb->buf = CALLOC(1, 4 * num_dw);
49 cb->max_num_dw = num_dw;
50 }
51
52 void r600_release_command_buffer(struct r600_command_buffer *cb)
53 {
54 FREE(cb->buf);
55 }
56
57 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
58 {
59 struct radeon_winsys_cs *cs = rctx->cs;
60 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
61
62 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
63 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
64 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
65 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
66 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
67
68 a->flush_flags = 0;
69 }
70
71 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
72 {
73 struct radeon_winsys_cs *cs = rctx->cs;
74 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
75 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
76 }
77
78 void r600_init_atom(struct r600_atom *atom,
79 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
80 unsigned num_dw, enum r600_atom_flags flags)
81 {
82 atom->emit = emit;
83 atom->num_dw = num_dw;
84 atom->flags = flags;
85 }
86
87 void r600_init_common_atoms(struct r600_context *rctx)
88 {
89 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
90 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
91 }
92
93 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
94 {
95 unsigned flags = 0;
96
97 if (rctx->framebuffer.nr_cbufs) {
98 flags |= S_0085F0_CB_ACTION_ENA(1) |
99 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
100 }
101
102 /* Workaround for broken flushing on some R6xx chipsets. */
103 if (rctx->family == CHIP_RV670 ||
104 rctx->family == CHIP_RS780 ||
105 rctx->family == CHIP_RS880) {
106 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
107 S_0085F0_DEST_BASE_0_ENA(1);
108 }
109 return flags;
110 }
111
112 void r600_texture_barrier(struct pipe_context *ctx)
113 {
114 struct r600_context *rctx = (struct r600_context *)ctx;
115
116 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
117 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
118 }
119
120 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
121 {
122 static const int prim_conv[] = {
123 V_008958_DI_PT_POINTLIST,
124 V_008958_DI_PT_LINELIST,
125 V_008958_DI_PT_LINELOOP,
126 V_008958_DI_PT_LINESTRIP,
127 V_008958_DI_PT_TRILIST,
128 V_008958_DI_PT_TRISTRIP,
129 V_008958_DI_PT_TRIFAN,
130 V_008958_DI_PT_QUADLIST,
131 V_008958_DI_PT_QUADSTRIP,
132 V_008958_DI_PT_POLYGON,
133 -1,
134 -1,
135 -1,
136 -1
137 };
138
139 *prim = prim_conv[pprim];
140 if (*prim == -1) {
141 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
142 return false;
143 }
144 return true;
145 }
146
147 /* common state between evergreen and r600 */
148 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
149 {
150 struct r600_context *rctx = (struct r600_context *)ctx;
151 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
152 struct r600_pipe_state *rstate;
153
154 if (state == NULL)
155 return;
156 rstate = &blend->rstate;
157 rctx->states[rstate->id] = rstate;
158 rctx->cb_target_mask = blend->cb_target_mask;
159
160 /* Replace every bit except MULTIWRITE_ENABLE. */
161 rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
162 rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
163
164 r600_context_pipe_state_set(rctx, rstate);
165 }
166
167 void r600_set_blend_color(struct pipe_context *ctx,
168 const struct pipe_blend_color *state)
169 {
170 struct r600_context *rctx = (struct r600_context *)ctx;
171 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
172
173 if (rstate == NULL)
174 return;
175
176 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
177 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
178 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
179 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
180 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
181
182 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
183 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
184 r600_context_pipe_state_set(rctx, rstate);
185 }
186
187 static void r600_set_stencil_ref(struct pipe_context *ctx,
188 const struct r600_stencil_ref *state)
189 {
190 struct r600_context *rctx = (struct r600_context *)ctx;
191 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
192
193 if (rstate == NULL)
194 return;
195
196 rstate->id = R600_PIPE_STATE_STENCIL_REF;
197 r600_pipe_state_add_reg(rstate,
198 R_028430_DB_STENCILREFMASK,
199 S_028430_STENCILREF(state->ref_value[0]) |
200 S_028430_STENCILMASK(state->valuemask[0]) |
201 S_028430_STENCILWRITEMASK(state->writemask[0]),
202 NULL, 0);
203 r600_pipe_state_add_reg(rstate,
204 R_028434_DB_STENCILREFMASK_BF,
205 S_028434_STENCILREF_BF(state->ref_value[1]) |
206 S_028434_STENCILMASK_BF(state->valuemask[1]) |
207 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
208 NULL, 0);
209
210 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
211 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
212 r600_context_pipe_state_set(rctx, rstate);
213 }
214
215 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
216 const struct pipe_stencil_ref *state)
217 {
218 struct r600_context *rctx = (struct r600_context *)ctx;
219 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
220 struct r600_stencil_ref ref;
221
222 rctx->stencil_ref = *state;
223
224 if (!dsa)
225 return;
226
227 ref.ref_value[0] = state->ref_value[0];
228 ref.ref_value[1] = state->ref_value[1];
229 ref.valuemask[0] = dsa->valuemask[0];
230 ref.valuemask[1] = dsa->valuemask[1];
231 ref.writemask[0] = dsa->writemask[0];
232 ref.writemask[1] = dsa->writemask[1];
233
234 r600_set_stencil_ref(ctx, &ref);
235 }
236
237 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
238 {
239 struct r600_context *rctx = (struct r600_context *)ctx;
240 struct r600_pipe_dsa *dsa = state;
241 struct r600_pipe_state *rstate;
242 struct r600_stencil_ref ref;
243
244 if (state == NULL)
245 return;
246 rstate = &dsa->rstate;
247 rctx->states[rstate->id] = rstate;
248 rctx->alpha_ref = dsa->alpha_ref;
249 rctx->alpha_ref_dirty = true;
250 r600_context_pipe_state_set(rctx, rstate);
251
252 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
253 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
254 ref.valuemask[0] = dsa->valuemask[0];
255 ref.valuemask[1] = dsa->valuemask[1];
256 ref.writemask[0] = dsa->writemask[0];
257 ref.writemask[1] = dsa->writemask[1];
258
259 r600_set_stencil_ref(ctx, &ref);
260
261 if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
262 rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
263 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
264 }
265 }
266
267 void r600_set_max_scissor(struct r600_context *rctx)
268 {
269 /* Set a scissor state such that it doesn't do anything. */
270 struct pipe_scissor_state scissor;
271 scissor.minx = 0;
272 scissor.miny = 0;
273 scissor.maxx = 8192;
274 scissor.maxy = 8192;
275
276 r600_set_scissor_state(rctx, &scissor);
277 }
278
279 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
280 {
281 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
282 struct r600_context *rctx = (struct r600_context *)ctx;
283
284 if (state == NULL)
285 return;
286
287 rctx->sprite_coord_enable = rs->sprite_coord_enable;
288 rctx->two_side = rs->two_side;
289 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
290 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
291
292 rctx->rasterizer = rs;
293
294 rctx->states[rs->rstate.id] = &rs->rstate;
295 r600_context_pipe_state_set(rctx, &rs->rstate);
296
297 if (rctx->chip_class >= EVERGREEN) {
298 evergreen_polygon_offset_update(rctx);
299 evergreen_set_rasterizer_discard(ctx, rs->rasterizer_discard);
300 } else {
301 r600_polygon_offset_update(rctx);
302 }
303
304 /* Workaround for a missing scissor enable on r600. */
305 if (rctx->chip_class == R600) {
306 if (rs->scissor_enable != rctx->scissor_enable) {
307 rctx->scissor_enable = rs->scissor_enable;
308
309 if (rs->scissor_enable) {
310 r600_set_scissor_state(rctx, &rctx->scissor_state);
311 } else {
312 r600_set_max_scissor(rctx);
313 }
314 }
315 }
316 }
317
318 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
319 {
320 struct r600_context *rctx = (struct r600_context *)ctx;
321 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
322
323 if (rctx->rasterizer == rs) {
324 rctx->rasterizer = NULL;
325 }
326 if (rctx->states[rs->rstate.id] == &rs->rstate) {
327 rctx->states[rs->rstate.id] = NULL;
328 }
329 free(rs);
330 }
331
332 void r600_sampler_view_destroy(struct pipe_context *ctx,
333 struct pipe_sampler_view *state)
334 {
335 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
336
337 pipe_resource_reference(&state->texture, NULL);
338 FREE(resource);
339 }
340
341 void r600_delete_state(struct pipe_context *ctx, void *state)
342 {
343 struct r600_context *rctx = (struct r600_context *)ctx;
344 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
345
346 if (rctx->states[rstate->id] == rstate) {
347 rctx->states[rstate->id] = NULL;
348 }
349 for (int i = 0; i < rstate->nregs; i++) {
350 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
351 }
352 free(rstate);
353 }
354
355 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
356 {
357 struct r600_context *rctx = (struct r600_context *)ctx;
358 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
359
360 rctx->vertex_elements = v;
361 if (v) {
362 r600_inval_shader_cache(rctx);
363 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
364 v->vmgr_elements);
365
366 rctx->states[v->rstate.id] = &v->rstate;
367 r600_context_pipe_state_set(rctx, &v->rstate);
368 }
369 }
370
371 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
372 {
373 struct r600_context *rctx = (struct r600_context *)ctx;
374 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
375
376 if (rctx->states[v->rstate.id] == &v->rstate) {
377 rctx->states[v->rstate.id] = NULL;
378 }
379 if (rctx->vertex_elements == state)
380 rctx->vertex_elements = NULL;
381
382 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
383 u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
384 FREE(state);
385 }
386
387
388 void r600_set_index_buffer(struct pipe_context *ctx,
389 const struct pipe_index_buffer *ib)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392
393 u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
394 }
395
396 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
397 const struct pipe_vertex_buffer *buffers)
398 {
399 struct r600_context *rctx = (struct r600_context *)ctx;
400 int i;
401
402 /* Zero states. */
403 for (i = 0; i < count; i++) {
404 if (!buffers[i].buffer) {
405 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
406 }
407 }
408 for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
409 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
410 }
411
412 u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
413 }
414
415 void *r600_create_vertex_elements(struct pipe_context *ctx,
416 unsigned count,
417 const struct pipe_vertex_element *elements)
418 {
419 struct r600_context *rctx = (struct r600_context *)ctx;
420 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
421
422 assert(count < 32);
423 if (!v)
424 return NULL;
425
426 v->count = count;
427 v->vmgr_elements =
428 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
429 elements, v->elements);
430
431 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
432 FREE(v);
433 return NULL;
434 }
435
436 return v;
437 }
438
439 void *r600_create_shader_state(struct pipe_context *ctx,
440 const struct pipe_shader_state *state)
441 {
442 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
443 int r;
444
445 shader->tokens = tgsi_dup_tokens(state->tokens);
446 shader->so = state->stream_output;
447
448 r = r600_pipe_shader_create(ctx, shader);
449 if (r) {
450 return NULL;
451 }
452 return shader;
453 }
454
455 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
456 {
457 struct r600_context *rctx = (struct r600_context *)ctx;
458
459 if (!state) {
460 state = rctx->dummy_pixel_shader;
461 }
462
463 rctx->ps_shader = (struct r600_pipe_shader *)state;
464
465 r600_inval_shader_cache(rctx);
466 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
467
468 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
469 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
470
471 if (rctx->ps_shader && rctx->vs_shader) {
472 r600_adjust_gprs(rctx);
473 }
474 }
475
476 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
477 {
478 struct r600_context *rctx = (struct r600_context *)ctx;
479
480 rctx->vs_shader = (struct r600_pipe_shader *)state;
481 if (state) {
482 r600_inval_shader_cache(rctx);
483 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
484 }
485 if (rctx->ps_shader && rctx->vs_shader) {
486 r600_adjust_gprs(rctx);
487 }
488 }
489
490 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
491 {
492 struct r600_context *rctx = (struct r600_context *)ctx;
493 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
494
495 if (rctx->ps_shader == shader) {
496 rctx->ps_shader = NULL;
497 }
498
499 free(shader->tokens);
500 r600_pipe_shader_destroy(ctx, shader);
501 free(shader);
502 }
503
504 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
505 {
506 struct r600_context *rctx = (struct r600_context *)ctx;
507 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
508
509 if (rctx->vs_shader == shader) {
510 rctx->vs_shader = NULL;
511 }
512
513 free(shader->tokens);
514 r600_pipe_shader_destroy(ctx, shader);
515 free(shader);
516 }
517
518 static void r600_update_alpha_ref(struct r600_context *rctx)
519 {
520 unsigned alpha_ref;
521 struct r600_pipe_state rstate;
522
523 alpha_ref = rctx->alpha_ref;
524 rstate.nregs = 0;
525 if (rctx->export_16bpc)
526 alpha_ref &= ~0x1FFF;
527 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
528
529 r600_context_pipe_state_set(rctx, &rstate);
530 rctx->alpha_ref_dirty = false;
531 }
532
533 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
534 struct pipe_resource *buffer)
535 {
536 struct r600_context *rctx = (struct r600_context *)ctx;
537 struct r600_resource *rbuffer = r600_resource(buffer);
538 struct r600_pipe_resource_state *rstate;
539 uint64_t va_offset;
540 uint32_t offset;
541
542 /* Note that the state tracker can unbind constant buffers by
543 * passing NULL here.
544 */
545 if (buffer == NULL) {
546 return;
547 }
548
549 r600_inval_shader_cache(rctx);
550
551 r600_upload_const_buffer(rctx, &rbuffer, &offset);
552 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
553 va_offset += offset;
554 va_offset >>= 8;
555
556 switch (shader) {
557 case PIPE_SHADER_VERTEX:
558 rctx->vs_const_buffer.nregs = 0;
559 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
560 R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
561 ALIGN_DIVUP(buffer->width0 >> 4, 16),
562 NULL, 0);
563 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
564 R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
565 va_offset, rbuffer, RADEON_USAGE_READ);
566 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
567
568 rstate = &rctx->vs_const_buffer_resource[index];
569 if (!rstate->id) {
570 if (rctx->chip_class >= EVERGREEN) {
571 evergreen_pipe_init_buffer_resource(rctx, rstate);
572 } else {
573 r600_pipe_init_buffer_resource(rctx, rstate);
574 }
575 }
576
577 if (rctx->chip_class >= EVERGREEN) {
578 evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
579 } else {
580 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
581 }
582 r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
583 break;
584 case PIPE_SHADER_FRAGMENT:
585 rctx->ps_const_buffer.nregs = 0;
586 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
587 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
588 ALIGN_DIVUP(buffer->width0 >> 4, 16),
589 NULL, 0);
590 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
591 R_028940_ALU_CONST_CACHE_PS_0,
592 va_offset, rbuffer, RADEON_USAGE_READ);
593 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
594
595 rstate = &rctx->ps_const_buffer_resource[index];
596 if (!rstate->id) {
597 if (rctx->chip_class >= EVERGREEN) {
598 evergreen_pipe_init_buffer_resource(rctx, rstate);
599 } else {
600 r600_pipe_init_buffer_resource(rctx, rstate);
601 }
602 }
603 if (rctx->chip_class >= EVERGREEN) {
604 evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
605 } else {
606 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
607 }
608 r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
609 break;
610 default:
611 R600_ERR("unsupported %d\n", shader);
612 return;
613 }
614
615 if (buffer != &rbuffer->b.b.b)
616 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
617 }
618
619 struct pipe_stream_output_target *
620 r600_create_so_target(struct pipe_context *ctx,
621 struct pipe_resource *buffer,
622 unsigned buffer_offset,
623 unsigned buffer_size)
624 {
625 struct r600_context *rctx = (struct r600_context *)ctx;
626 struct r600_so_target *t;
627 void *ptr;
628
629 t = CALLOC_STRUCT(r600_so_target);
630 if (!t) {
631 return NULL;
632 }
633
634 t->b.reference.count = 1;
635 t->b.context = ctx;
636 pipe_resource_reference(&t->b.buffer, buffer);
637 t->b.buffer_offset = buffer_offset;
638 t->b.buffer_size = buffer_size;
639
640 t->filled_size = (struct r600_resource*)
641 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
642 ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
643 memset(ptr, 0, t->filled_size->buf->size);
644 rctx->ws->buffer_unmap(t->filled_size->buf);
645
646 return &t->b;
647 }
648
649 void r600_so_target_destroy(struct pipe_context *ctx,
650 struct pipe_stream_output_target *target)
651 {
652 struct r600_so_target *t = (struct r600_so_target*)target;
653 pipe_resource_reference(&t->b.buffer, NULL);
654 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
655 FREE(t);
656 }
657
658 void r600_set_so_targets(struct pipe_context *ctx,
659 unsigned num_targets,
660 struct pipe_stream_output_target **targets,
661 unsigned append_bitmask)
662 {
663 struct r600_context *rctx = (struct r600_context *)ctx;
664 unsigned i;
665
666 /* Stop streamout. */
667 if (rctx->num_so_targets) {
668 r600_context_streamout_end(rctx);
669 }
670
671 /* Set the new targets. */
672 for (i = 0; i < num_targets; i++) {
673 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
674 }
675 for (; i < rctx->num_so_targets; i++) {
676 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
677 }
678
679 rctx->num_so_targets = num_targets;
680 rctx->streamout_start = num_targets != 0;
681 rctx->streamout_append_bitmask = append_bitmask;
682 }
683
684 static void r600_vertex_buffer_update(struct r600_context *rctx)
685 {
686 struct r600_pipe_resource_state *rstate;
687 struct r600_resource *rbuffer;
688 struct pipe_vertex_buffer *vertex_buffer;
689 unsigned i, count, offset;
690
691 r600_inval_vertex_cache(rctx);
692
693 if (rctx->vertex_elements->vbuffer_need_offset) {
694 /* one resource per vertex elements */
695 count = rctx->vertex_elements->count;
696 } else {
697 /* bind vertex buffer once */
698 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
699 }
700
701 for (i = 0 ; i < count; i++) {
702 rstate = &rctx->fs_resource[i];
703
704 if (rctx->vertex_elements->vbuffer_need_offset) {
705 /* one resource per vertex elements */
706 unsigned vbuffer_index;
707 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
708 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
709 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
710 offset = rctx->vertex_elements->vbuffer_offset[i];
711 } else {
712 /* bind vertex buffer once */
713 vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
714 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
715 offset = 0;
716 }
717 if (vertex_buffer == NULL || rbuffer == NULL)
718 continue;
719 offset += vertex_buffer->buffer_offset;
720
721 if (!rstate->id) {
722 if (rctx->chip_class >= EVERGREEN) {
723 evergreen_pipe_init_buffer_resource(rctx, rstate);
724 } else {
725 r600_pipe_init_buffer_resource(rctx, rstate);
726 }
727 }
728
729 if (rctx->chip_class >= EVERGREEN) {
730 evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
731 } else {
732 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
733 }
734 r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
735 }
736 }
737
738 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
739 {
740 struct r600_context *rctx = (struct r600_context *)ctx;
741 int r;
742
743 r600_pipe_shader_destroy(ctx, shader);
744 r = r600_pipe_shader_create(ctx, shader);
745 if (r) {
746 return r;
747 }
748 r600_context_pipe_state_set(rctx, &shader->rstate);
749
750 return 0;
751 }
752
753 static void r600_update_derived_state(struct r600_context *rctx)
754 {
755 struct pipe_context * ctx = (struct pipe_context*)rctx;
756 struct r600_pipe_state rstate;
757
758 rstate.nregs = 0;
759
760 if (rstate.nregs)
761 r600_context_pipe_state_set(rctx, &rstate);
762
763 if (!rctx->blitter->running) {
764 if (rctx->have_depth_fb || rctx->have_depth_texture)
765 r600_flush_depth_textures(rctx);
766 }
767
768 if (rctx->chip_class < EVERGREEN) {
769 r600_update_sampler_states(rctx);
770 }
771
772 if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
773 ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
774 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
775 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
776 }
777
778 if (rctx->alpha_ref_dirty) {
779 r600_update_alpha_ref(rctx);
780 }
781
782 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
783 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
784 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
785
786 if (rctx->chip_class >= EVERGREEN)
787 evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
788 else
789 r600_pipe_shader_ps(ctx, rctx->ps_shader);
790
791 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
792 }
793
794 }
795
796 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
797 {
798 static const int prim_conv[] = {
799 V_028A6C_OUTPRIM_TYPE_POINTLIST,
800 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
801 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
802 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
803 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
804 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
805 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
806 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
807 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
808 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
809 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
810 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
811 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
812 V_028A6C_OUTPRIM_TYPE_TRISTRIP
813 };
814 assert(mode < Elements(prim_conv));
815
816 return prim_conv[mode];
817 }
818
819 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
820 {
821 struct r600_context *rctx = (struct r600_context *)ctx;
822 struct pipe_draw_info info = *dinfo;
823 struct pipe_index_buffer ib = {};
824 unsigned prim, mask, ls_mask = 0;
825 struct r600_block *dirty_block = NULL, *next_block = NULL;
826 struct r600_atom *state = NULL, *next_state = NULL;
827 struct radeon_winsys_cs *cs = rctx->cs;
828 uint64_t va;
829
830 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
831 (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
832 !r600_conv_pipe_prim(info.mode, &prim)) {
833 assert(0);
834 return;
835 }
836
837 if (!rctx->vs_shader) {
838 assert(0);
839 return;
840 }
841
842 r600_update_derived_state(rctx);
843
844 u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
845 r600_vertex_buffer_update(rctx);
846
847 if (info.indexed) {
848 /* Initialize the index buffer struct. */
849 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
850 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
851 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
852
853 /* Translate or upload, if needed. */
854 r600_translate_index_buffer(rctx, &ib, info.count);
855
856 if (u_vbuf_resource(ib.buffer)->user_ptr) {
857 r600_upload_index_buffer(rctx, &ib, info.count);
858 }
859 } else {
860 info.index_bias = info.start;
861 if (info.count_from_stream_output) {
862 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
863 }
864 }
865
866 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
867
868 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
869 rctx->vgt.id = R600_PIPE_STATE_VGT;
870 rctx->vgt.nregs = 0;
871 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
872 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, NULL, 0);
873 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
874 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
875 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
876 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
877 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
878 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
879 if (rctx->chip_class <= R700)
880 r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
881 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
882 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
883 }
884
885 rctx->vgt.nregs = 0;
886 r600_pipe_state_mod_reg(&rctx->vgt, prim);
887 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
888 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
889 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
890 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
891 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
892 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
893
894 if (prim == V_008958_DI_PT_LINELIST)
895 ls_mask = 1;
896 else if (prim == V_008958_DI_PT_LINESTRIP)
897 ls_mask = 2;
898 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
899 if (rctx->chip_class <= R700)
900 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
901 r600_pipe_state_mod_reg(&rctx->vgt,
902 rctx->vs_shader->pa_cl_vs_out_cntl |
903 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
904 r600_pipe_state_mod_reg(&rctx->vgt,
905 rctx->pa_cl_clip_cntl |
906 (rctx->vs_shader->shader.clip_dist_write ||
907 rctx->vs_shader->shader.vs_prohibit_ucps ?
908 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
909
910 r600_context_pipe_state_set(rctx, &rctx->vgt);
911
912 /* Emit states (the function expects that we emit at most 17 dwords here). */
913 r600_need_cs_space(rctx, 0, TRUE);
914
915 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
916 r600_emit_atom(rctx, state);
917 }
918 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
919 r600_context_block_emit_dirty(rctx, dirty_block);
920 }
921 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
922 r600_context_block_resource_emit_dirty(rctx, dirty_block);
923 }
924 rctx->pm4_dirty_cdwords = 0;
925
926 /* Enable stream out if needed. */
927 if (rctx->streamout_start) {
928 r600_context_streamout_begin(rctx);
929 rctx->streamout_start = FALSE;
930 }
931
932 /* draw packet */
933 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
934 cs->buf[cs->cdw++] = ib.index_size == 4 ?
935 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
936 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
937 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
938 cs->buf[cs->cdw++] = info.instance_count;
939 if (info.indexed) {
940 va = r600_resource_va(ctx->screen, ib.buffer);
941 va += ib.offset;
942 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
943 cs->buf[cs->cdw++] = va;
944 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
945 cs->buf[cs->cdw++] = info.count;
946 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
947 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
948 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
949 } else {
950 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
951 cs->buf[cs->cdw++] = info.count;
952 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
953 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
954 }
955
956 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
957
958 if (rctx->framebuffer.zsbuf)
959 {
960 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
961 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
962 }
963
964 pipe_resource_reference(&ib.buffer, NULL);
965 u_vbuf_draw_end(rctx->vbuf_mgr);
966 }
967
968 void _r600_pipe_state_add_reg(struct r600_context *ctx,
969 struct r600_pipe_state *state,
970 uint32_t offset, uint32_t value,
971 uint32_t range_id, uint32_t block_id,
972 struct r600_resource *bo,
973 enum radeon_bo_usage usage)
974 {
975 struct r600_range *range;
976 struct r600_block *block;
977
978 if (bo) assert(usage);
979
980 range = &ctx->range[range_id];
981 block = range->blocks[block_id];
982 state->regs[state->nregs].block = block;
983 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
984
985 state->regs[state->nregs].value = value;
986 state->regs[state->nregs].bo = bo;
987 state->regs[state->nregs].bo_usage = usage;
988
989 state->nregs++;
990 assert(state->nregs < R600_BLOCK_MAX_REG);
991 }
992
993 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
994 uint32_t offset, uint32_t value,
995 struct r600_resource *bo,
996 enum radeon_bo_usage usage)
997 {
998 if (bo) assert(usage);
999
1000 state->regs[state->nregs].id = offset;
1001 state->regs[state->nregs].block = NULL;
1002 state->regs[state->nregs].value = value;
1003 state->regs[state->nregs].bo = bo;
1004 state->regs[state->nregs].bo_usage = usage;
1005
1006 state->nregs++;
1007 assert(state->nregs < R600_BLOCK_MAX_REG);
1008 }
1009
1010 uint32_t r600_translate_stencil_op(int s_op)
1011 {
1012 switch (s_op) {
1013 case PIPE_STENCIL_OP_KEEP:
1014 return V_028800_STENCIL_KEEP;
1015 case PIPE_STENCIL_OP_ZERO:
1016 return V_028800_STENCIL_ZERO;
1017 case PIPE_STENCIL_OP_REPLACE:
1018 return V_028800_STENCIL_REPLACE;
1019 case PIPE_STENCIL_OP_INCR:
1020 return V_028800_STENCIL_INCR;
1021 case PIPE_STENCIL_OP_DECR:
1022 return V_028800_STENCIL_DECR;
1023 case PIPE_STENCIL_OP_INCR_WRAP:
1024 return V_028800_STENCIL_INCR_WRAP;
1025 case PIPE_STENCIL_OP_DECR_WRAP:
1026 return V_028800_STENCIL_DECR_WRAP;
1027 case PIPE_STENCIL_OP_INVERT:
1028 return V_028800_STENCIL_INVERT;
1029 default:
1030 R600_ERR("Unknown stencil op %d", s_op);
1031 assert(0);
1032 break;
1033 }
1034 return 0;
1035 }
1036
1037 uint32_t r600_translate_fill(uint32_t func)
1038 {
1039 switch(func) {
1040 case PIPE_POLYGON_MODE_FILL:
1041 return 2;
1042 case PIPE_POLYGON_MODE_LINE:
1043 return 1;
1044 case PIPE_POLYGON_MODE_POINT:
1045 return 0;
1046 default:
1047 assert(0);
1048 return 0;
1049 }
1050 }
1051
1052 unsigned r600_tex_wrap(unsigned wrap)
1053 {
1054 switch (wrap) {
1055 default:
1056 case PIPE_TEX_WRAP_REPEAT:
1057 return V_03C000_SQ_TEX_WRAP;
1058 case PIPE_TEX_WRAP_CLAMP:
1059 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1060 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1061 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1062 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1063 return V_03C000_SQ_TEX_CLAMP_BORDER;
1064 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1065 return V_03C000_SQ_TEX_MIRROR;
1066 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1067 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1068 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1069 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1070 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1071 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1072 }
1073 }
1074
1075 unsigned r600_tex_filter(unsigned filter)
1076 {
1077 switch (filter) {
1078 default:
1079 case PIPE_TEX_FILTER_NEAREST:
1080 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1081 case PIPE_TEX_FILTER_LINEAR:
1082 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1083 }
1084 }
1085
1086 unsigned r600_tex_mipfilter(unsigned filter)
1087 {
1088 switch (filter) {
1089 case PIPE_TEX_MIPFILTER_NEAREST:
1090 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1091 case PIPE_TEX_MIPFILTER_LINEAR:
1092 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1093 default:
1094 case PIPE_TEX_MIPFILTER_NONE:
1095 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1096 }
1097 }
1098
1099 unsigned r600_tex_compare(unsigned compare)
1100 {
1101 switch (compare) {
1102 default:
1103 case PIPE_FUNC_NEVER:
1104 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1105 case PIPE_FUNC_LESS:
1106 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1107 case PIPE_FUNC_EQUAL:
1108 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1109 case PIPE_FUNC_LEQUAL:
1110 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1111 case PIPE_FUNC_GREATER:
1112 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1113 case PIPE_FUNC_NOTEQUAL:
1114 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1115 case PIPE_FUNC_GEQUAL:
1116 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1117 case PIPE_FUNC_ALWAYS:
1118 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1119 }
1120 }