projects / mesa.git / blob
? search:


0e071d0f9dae6cfe0ad23eb89f647dfee9c4eba4
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
36 {
37 struct radeon_winsys_cs *cs = rctx->cs;
38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
39
40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
42 cs->cdw += cb->atom.num_dw;
43 }
44
45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
46 {
47 cb->atom.emit = r600_emit_command_buffer;
48 cb->atom.num_dw = 0;
49 cb->atom.flags = flags;
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
60 {
61 struct radeon_winsys_cs *cs = rctx->cs;
62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
63
64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
69
70 a->flush_flags = 0;
71 }
72
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 struct radeon_winsys_cs *cs = rctx->cs;
76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
78 }
79
80 void r600_init_atom(struct r600_atom *atom,
81 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
82 unsigned num_dw, enum r600_atom_flags flags)
83 {
84 atom->emit = emit;
85 atom->num_dw = num_dw;
86 atom->flags = flags;
87 }
88
89 void r600_init_common_atoms(struct r600_context *rctx)
90 {
91 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
92 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
93 }
94
95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
96 {
97 unsigned flags = 0;
98
99 if (rctx->framebuffer.nr_cbufs) {
100 flags |= S_0085F0_CB_ACTION_ENA(1) |
101 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
102 }
103
104 /* Workaround for broken flushing on some R6xx chipsets. */
105 if (rctx->family == CHIP_RV670 ||
106 rctx->family == CHIP_RS780 ||
107 rctx->family == CHIP_RS880) {
108 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
109 S_0085F0_DEST_BASE_0_ENA(1);
110 }
111 return flags;
112 }
113
114 void r600_texture_barrier(struct pipe_context *ctx)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117
118 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
119 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
120 }
121
122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
123 {
124 static const int prim_conv[] = {
125 V_008958_DI_PT_POINTLIST,
126 V_008958_DI_PT_LINELIST,
127 V_008958_DI_PT_LINELOOP,
128 V_008958_DI_PT_LINESTRIP,
129 V_008958_DI_PT_TRILIST,
130 V_008958_DI_PT_TRISTRIP,
131 V_008958_DI_PT_TRIFAN,
132 V_008958_DI_PT_QUADLIST,
133 V_008958_DI_PT_QUADSTRIP,
134 V_008958_DI_PT_POLYGON,
135 -1,
136 -1,
137 -1,
138 -1
139 };
140
141 *prim = prim_conv[pprim];
142 if (*prim == -1) {
143 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
144 return false;
145 }
146 return true;
147 }
148
149 /* common state between evergreen and r600 */
150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
151 {
152 struct r600_context *rctx = (struct r600_context *)ctx;
153 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
154 struct r600_pipe_state *rstate;
155
156 if (state == NULL)
157 return;
158 rstate = &blend->rstate;
159 rctx->states[rstate->id] = rstate;
160 /* Replace every bit except MULTIWRITE_ENABLE. */
161 rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
162 rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
163 rctx->dual_src_blend = blend->dual_src_blend;
164 r600_context_pipe_state_set(rctx, rstate);
165
166 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
167 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
168 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
169 }
170 }
171
172 void r600_set_blend_color(struct pipe_context *ctx,
173 const struct pipe_blend_color *state)
174 {
175 struct r600_context *rctx = (struct r600_context *)ctx;
176 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
177
178 if (rstate == NULL)
179 return;
180
181 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
182 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
183 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
184 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
185 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
186
187 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
188 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
189 r600_context_pipe_state_set(rctx, rstate);
190 }
191
192 static void r600_set_stencil_ref(struct pipe_context *ctx,
193 const struct r600_stencil_ref *state)
194 {
195 struct r600_context *rctx = (struct r600_context *)ctx;
196 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
197
198 if (rstate == NULL)
199 return;
200
201 rstate->id = R600_PIPE_STATE_STENCIL_REF;
202 r600_pipe_state_add_reg(rstate,
203 R_028430_DB_STENCILREFMASK,
204 S_028430_STENCILREF(state->ref_value[0]) |
205 S_028430_STENCILMASK(state->valuemask[0]) |
206 S_028430_STENCILWRITEMASK(state->writemask[0]));
207 r600_pipe_state_add_reg(rstate,
208 R_028434_DB_STENCILREFMASK_BF,
209 S_028434_STENCILREF_BF(state->ref_value[1]) |
210 S_028434_STENCILMASK_BF(state->valuemask[1]) |
211 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
212
213 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
214 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
215 r600_context_pipe_state_set(rctx, rstate);
216 }
217
218 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
219 const struct pipe_stencil_ref *state)
220 {
221 struct r600_context *rctx = (struct r600_context *)ctx;
222 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
223 struct r600_stencil_ref ref;
224
225 rctx->stencil_ref = *state;
226
227 if (!dsa)
228 return;
229
230 ref.ref_value[0] = state->ref_value[0];
231 ref.ref_value[1] = state->ref_value[1];
232 ref.valuemask[0] = dsa->valuemask[0];
233 ref.valuemask[1] = dsa->valuemask[1];
234 ref.writemask[0] = dsa->writemask[0];
235 ref.writemask[1] = dsa->writemask[1];
236
237 r600_set_stencil_ref(ctx, &ref);
238 }
239
240 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
241 {
242 struct r600_context *rctx = (struct r600_context *)ctx;
243 struct r600_pipe_dsa *dsa = state;
244 struct r600_pipe_state *rstate;
245 struct r600_stencil_ref ref;
246
247 if (state == NULL)
248 return;
249 rstate = &dsa->rstate;
250 rctx->states[rstate->id] = rstate;
251 rctx->sx_alpha_test_control &= ~0xff;
252 rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
253 rctx->alpha_ref = dsa->alpha_ref;
254 rctx->alpha_ref_dirty = true;
255 r600_context_pipe_state_set(rctx, rstate);
256
257 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
258 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
259 ref.valuemask[0] = dsa->valuemask[0];
260 ref.valuemask[1] = dsa->valuemask[1];
261 ref.writemask[0] = dsa->writemask[0];
262 ref.writemask[1] = dsa->writemask[1];
263
264 r600_set_stencil_ref(ctx, &ref);
265
266 if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
267 rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
268 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
269 }
270 }
271
272 void r600_set_max_scissor(struct r600_context *rctx)
273 {
274 /* Set a scissor state such that it doesn't do anything. */
275 struct pipe_scissor_state scissor;
276 scissor.minx = 0;
277 scissor.miny = 0;
278 scissor.maxx = 8192;
279 scissor.maxy = 8192;
280
281 r600_set_scissor_state(rctx, &scissor);
282 }
283
284 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
285 {
286 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
287 struct r600_context *rctx = (struct r600_context *)ctx;
288
289 if (state == NULL)
290 return;
291
292 rctx->sprite_coord_enable = rs->sprite_coord_enable;
293 rctx->two_side = rs->two_side;
294 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
295 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
296
297 rctx->rasterizer = rs;
298
299 rctx->states[rs->rstate.id] = &rs->rstate;
300 r600_context_pipe_state_set(rctx, &rs->rstate);
301
302 if (rctx->chip_class >= EVERGREEN) {
303 evergreen_polygon_offset_update(rctx);
304 } else {
305 r600_polygon_offset_update(rctx);
306 }
307
308 /* Workaround for a missing scissor enable on r600. */
309 if (rctx->chip_class == R600) {
310 if (rs->scissor_enable != rctx->scissor_enable) {
311 rctx->scissor_enable = rs->scissor_enable;
312
313 if (rs->scissor_enable) {
314 r600_set_scissor_state(rctx, &rctx->scissor_state);
315 } else {
316 r600_set_max_scissor(rctx);
317 }
318 }
319 }
320 }
321
322 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
323 {
324 struct r600_context *rctx = (struct r600_context *)ctx;
325 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
326
327 if (rctx->rasterizer == rs) {
328 rctx->rasterizer = NULL;
329 }
330 if (rctx->states[rs->rstate.id] == &rs->rstate) {
331 rctx->states[rs->rstate.id] = NULL;
332 }
333 free(rs);
334 }
335
336 void r600_sampler_view_destroy(struct pipe_context *ctx,
337 struct pipe_sampler_view *state)
338 {
339 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
340
341 pipe_resource_reference(&state->texture, NULL);
342 FREE(resource);
343 }
344
345 void r600_delete_state(struct pipe_context *ctx, void *state)
346 {
347 struct r600_context *rctx = (struct r600_context *)ctx;
348 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
349
350 if (rctx->states[rstate->id] == rstate) {
351 rctx->states[rstate->id] = NULL;
352 }
353 for (int i = 0; i < rstate->nregs; i++) {
354 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
355 }
356 free(rstate);
357 }
358
359 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
360 {
361 struct r600_context *rctx = (struct r600_context *)ctx;
362 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
363
364 rctx->vertex_elements = v;
365 if (v) {
366 r600_inval_shader_cache(rctx);
367
368 rctx->states[v->rstate.id] = &v->rstate;
369 r600_context_pipe_state_set(rctx, &v->rstate);
370 }
371 }
372
373 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
374 {
375 struct r600_context *rctx = (struct r600_context *)ctx;
376 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
377
378 if (rctx->states[v->rstate.id] == &v->rstate) {
379 rctx->states[v->rstate.id] = NULL;
380 }
381 if (rctx->vertex_elements == state)
382 rctx->vertex_elements = NULL;
383
384 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
385 FREE(state);
386 }
387
388 void r600_set_index_buffer(struct pipe_context *ctx,
389 const struct pipe_index_buffer *ib)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392
393 if (ib) {
394 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
395 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
396 } else {
397 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
398 }
399 }
400
401 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
402 const struct pipe_vertex_buffer *buffers)
403 {
404 struct r600_context *rctx = (struct r600_context *)ctx;
405
406 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
407
408 r600_inval_vertex_cache(rctx);
409 rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
410 rctx->nr_vertex_buffers;
411 r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
412 }
413
414 void *r600_create_vertex_elements(struct pipe_context *ctx,
415 unsigned count,
416 const struct pipe_vertex_element *elements)
417 {
418 struct r600_context *rctx = (struct r600_context *)ctx;
419 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
420
421 assert(count < 32);
422 if (!v)
423 return NULL;
424
425 v->count = count;
426 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
427
428 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
429 FREE(v);
430 return NULL;
431 }
432
433 return v;
434 }
435
436 /* Compute the key for the hw shader variant */
437 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
438 struct r600_pipe_shader_selector * sel)
439 {
440 struct r600_context *rctx = (struct r600_context *)ctx;
441 unsigned key;
442
443 if (sel->type == PIPE_SHADER_FRAGMENT) {
444 key = rctx->two_side |
445 MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 1;
446 } else
447 key = 0;
448
449 return key;
450 }
451
452 /* Select the hw shader variant depending on the current state.
453 * (*dirty) is set to 1 if current variant was changed */
454 static int r600_shader_select(struct pipe_context *ctx,
455 struct r600_pipe_shader_selector* sel,
456 unsigned *dirty)
457 {
458 unsigned key;
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 struct r600_pipe_shader * shader = NULL;
461 int r;
462
463 key = r600_shader_selector_key(ctx, sel);
464
465 /* Check if we don't need to change anything.
466 * This path is also used for most shaders that don't need multiple
467 * variants, it will cost just a computation of the key and this
468 * test. */
469 if (likely(sel->current && sel->current->key == key)) {
470 return 0;
471 }
472
473 /* lookup if we have other variants in the list */
474 if (sel->num_shaders > 1) {
475 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
476
477 while (c && c->key != key) {
478 p = c;
479 c = c->next_variant;
480 }
481
482 if (c) {
483 p->next_variant = c->next_variant;
484 shader = c;
485 }
486 }
487
488 if (unlikely(!shader)) {
489 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
490 shader->selector = sel;
491
492 r = r600_pipe_shader_create(ctx, shader);
493 if (unlikely(r)) {
494 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
495 sel->type, key, r);
496 sel->current = NULL;
497 return r;
498 }
499
500 /* We don't know the value of nr_ps_max_color_exports until we built
501 * at least one variant, so we may need to recompute the key after
502 * building first variant. */
503 if (sel->type == PIPE_SHADER_FRAGMENT &&
504 sel->num_shaders == 0) {
505 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
506 key = r600_shader_selector_key(ctx, sel);
507 }
508
509 shader->key = key;
510 sel->num_shaders++;
511 }
512
513 if (dirty)
514 *dirty = 1;
515
516 shader->next_variant = sel->current;
517 sel->current = shader;
518
519 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
520 r600_adjust_gprs(rctx);
521 }
522
523 return 0;
524 }
525
526 static void *r600_create_shader_state(struct pipe_context *ctx,
527 const struct pipe_shader_state *state,
528 unsigned pipe_shader_type)
529 {
530 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
531 int r;
532
533 sel->type = pipe_shader_type;
534 sel->tokens = tgsi_dup_tokens(state->tokens);
535 sel->so = state->stream_output;
536
537 r = r600_shader_select(ctx, sel, NULL);
538 if (r)
539 return NULL;
540
541 return sel;
542 }
543
544 void *r600_create_shader_state_ps(struct pipe_context *ctx,
545 const struct pipe_shader_state *state)
546 {
547 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
548 }
549
550 void *r600_create_shader_state_vs(struct pipe_context *ctx,
551 const struct pipe_shader_state *state)
552 {
553 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
554 }
555
556 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
557 {
558 struct r600_context *rctx = (struct r600_context *)ctx;
559
560 if (!state)
561 state = rctx->dummy_pixel_shader;
562
563 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
564 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
565
566
567 if (rctx->chip_class < EVERGREEN && rctx->vs_shader) {
568 r600_adjust_gprs(rctx);
569 }
570 }
571
572 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
573 {
574 struct r600_context *rctx = (struct r600_context *)ctx;
575
576 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
577 if (state) {
578 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
579
580 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
581 r600_adjust_gprs(rctx);
582 }
583 }
584
585 static void r600_delete_shader_selector(struct pipe_context *ctx,
586 struct r600_pipe_shader_selector *sel)
587 {
588 struct r600_pipe_shader *p = sel->current, *c;
589 while (p) {
590 c = p->next_variant;
591 r600_pipe_shader_destroy(ctx, p);
592 free(p);
593 p = c;
594 }
595
596 free(sel->tokens);
597 free(sel);
598 }
599
600
601 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
602 {
603 struct r600_context *rctx = (struct r600_context *)ctx;
604 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
605
606 if (rctx->ps_shader == sel) {
607 rctx->ps_shader = NULL;
608 }
609
610 r600_delete_shader_selector(ctx, sel);
611 }
612
613 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
614 {
615 struct r600_context *rctx = (struct r600_context *)ctx;
616 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
617
618 if (rctx->vs_shader == sel) {
619 rctx->vs_shader = NULL;
620 }
621
622 r600_delete_shader_selector(ctx, sel);
623 }
624
625 static void r600_update_alpha_ref(struct r600_context *rctx)
626 {
627 unsigned alpha_ref;
628 struct r600_pipe_state rstate;
629
630 alpha_ref = rctx->alpha_ref;
631 rstate.nregs = 0;
632 if (rctx->export_16bpc && rctx->chip_class >= EVERGREEN) {
633 alpha_ref &= ~0x1FFF;
634 }
635 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
636
637 r600_context_pipe_state_set(rctx, &rstate);
638 rctx->alpha_ref_dirty = false;
639 }
640
641 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
642 {
643 r600_inval_shader_cache(rctx);
644 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
645 : util_bitcount(state->dirty_mask)*19;
646 r600_atom_dirty(rctx, &state->atom);
647 }
648
649 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
650 struct pipe_constant_buffer *input)
651 {
652 struct r600_context *rctx = (struct r600_context *)ctx;
653 struct r600_constbuf_state *state;
654 struct pipe_constant_buffer *cb;
655 const uint8_t *ptr;
656
657 switch (shader) {
658 case PIPE_SHADER_VERTEX:
659 state = &rctx->vs_constbuf_state;
660 break;
661 case PIPE_SHADER_FRAGMENT:
662 state = &rctx->ps_constbuf_state;
663 break;
664 default:
665 return;
666 }
667
668 /* Note that the state tracker can unbind constant buffers by
669 * passing NULL here.
670 */
671 if (unlikely(!input)) {
672 state->enabled_mask &= ~(1 << index);
673 state->dirty_mask &= ~(1 << index);
674 pipe_resource_reference(&state->cb[index].buffer, NULL);
675 return;
676 }
677
678 cb = &state->cb[index];
679 cb->buffer_size = input->buffer_size;
680
681 ptr = input->user_buffer;
682
683 if (ptr) {
684 /* Upload the user buffer. */
685 if (R600_BIG_ENDIAN) {
686 uint32_t *tmpPtr;
687 unsigned i, size = input->buffer_size;
688
689 if (!(tmpPtr = malloc(size))) {
690 R600_ERR("Failed to allocate BE swap buffer.\n");
691 return;
692 }
693
694 for (i = 0; i < size / 4; ++i) {
695 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
696 }
697
698 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
699 free(tmpPtr);
700 } else {
701 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
702 }
703 } else {
704 /* Setup the hw buffer. */
705 cb->buffer_offset = input->buffer_offset;
706 pipe_resource_reference(&cb->buffer, input->buffer);
707 }
708
709 state->enabled_mask |= 1 << index;
710 state->dirty_mask |= 1 << index;
711 r600_constant_buffers_dirty(rctx, state);
712 }
713
714 struct pipe_stream_output_target *
715 r600_create_so_target(struct pipe_context *ctx,
716 struct pipe_resource *buffer,
717 unsigned buffer_offset,
718 unsigned buffer_size)
719 {
720 struct r600_context *rctx = (struct r600_context *)ctx;
721 struct r600_so_target *t;
722 void *ptr;
723
724 t = CALLOC_STRUCT(r600_so_target);
725 if (!t) {
726 return NULL;
727 }
728
729 t->b.reference.count = 1;
730 t->b.context = ctx;
731 pipe_resource_reference(&t->b.buffer, buffer);
732 t->b.buffer_offset = buffer_offset;
733 t->b.buffer_size = buffer_size;
734
735 t->filled_size = (struct r600_resource*)
736 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
737 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
738 memset(ptr, 0, t->filled_size->buf->size);
739 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
740
741 return &t->b;
742 }
743
744 void r600_so_target_destroy(struct pipe_context *ctx,
745 struct pipe_stream_output_target *target)
746 {
747 struct r600_so_target *t = (struct r600_so_target*)target;
748 pipe_resource_reference(&t->b.buffer, NULL);
749 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
750 FREE(t);
751 }
752
753 void r600_set_so_targets(struct pipe_context *ctx,
754 unsigned num_targets,
755 struct pipe_stream_output_target **targets,
756 unsigned append_bitmask)
757 {
758 struct r600_context *rctx = (struct r600_context *)ctx;
759 unsigned i;
760
761 /* Stop streamout. */
762 if (rctx->num_so_targets && !rctx->streamout_start) {
763 r600_context_streamout_end(rctx);
764 }
765
766 /* Set the new targets. */
767 for (i = 0; i < num_targets; i++) {
768 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
769 }
770 for (; i < rctx->num_so_targets; i++) {
771 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
772 }
773
774 rctx->num_so_targets = num_targets;
775 rctx->streamout_start = num_targets != 0;
776 rctx->streamout_append_bitmask = append_bitmask;
777 }
778
779 static void r600_update_derived_state(struct r600_context *rctx)
780 {
781 struct pipe_context * ctx = (struct pipe_context*)rctx;
782 unsigned ps_dirty = 0;
783
784 if (!rctx->blitter->running) {
785 if (rctx->have_depth_fb || rctx->have_depth_texture)
786 r600_flush_depth_textures(rctx);
787 }
788
789 if (rctx->chip_class < EVERGREEN) {
790 r600_update_sampler_states(rctx);
791 }
792
793 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
794
795 if (rctx->alpha_ref_dirty) {
796 r600_update_alpha_ref(rctx);
797 }
798
799 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
800 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
801 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
802
803 if (rctx->chip_class >= EVERGREEN)
804 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
805 else
806 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
807
808 ps_dirty = 1;
809 }
810
811 if (ps_dirty)
812 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
813
814 if (rctx->chip_class >= EVERGREEN) {
815 evergreen_update_dual_export_state(rctx);
816 } else {
817 r600_update_dual_export_state(rctx);
818 }
819
820 if (rctx->dual_src_blend) {
821 rctx->cb_shader_mask = rctx->ps_shader->current->ps_cb_shader_mask | rctx->fb_cb_shader_mask;
822 } else {
823 rctx->cb_shader_mask = rctx->fb_cb_shader_mask;
824 }
825 }
826
827 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
828 {
829 static const int prim_conv[] = {
830 V_028A6C_OUTPRIM_TYPE_POINTLIST,
831 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
832 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
833 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
834 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
835 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
836 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
837 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
838 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
839 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
840 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
841 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
842 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
843 V_028A6C_OUTPRIM_TYPE_TRISTRIP
844 };
845 assert(mode < Elements(prim_conv));
846
847 return prim_conv[mode];
848 }
849
850 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
851 {
852 struct r600_context *rctx = (struct r600_context *)ctx;
853 struct pipe_draw_info info = *dinfo;
854 struct pipe_index_buffer ib = {};
855 unsigned prim, ls_mask = 0;
856 struct r600_block *dirty_block = NULL, *next_block = NULL;
857 struct r600_atom *state = NULL, *next_state = NULL;
858 struct radeon_winsys_cs *cs = rctx->cs;
859 uint64_t va;
860 uint8_t *ptr;
861
862 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
863 !r600_conv_pipe_prim(info.mode, &prim)) {
864 assert(0);
865 return;
866 }
867
868 if (!rctx->vs_shader) {
869 assert(0);
870 return;
871 }
872
873 r600_update_derived_state(rctx);
874
875 if (info.indexed) {
876 /* Initialize the index buffer struct. */
877 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
878 ib.user_buffer = rctx->index_buffer.user_buffer;
879 ib.index_size = rctx->index_buffer.index_size;
880 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
881
882 /* Translate or upload, if needed. */
883 r600_translate_index_buffer(rctx, &ib, info.count);
884
885 ptr = (uint8_t*)ib.user_buffer;
886 if (!ib.buffer && ptr) {
887 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
888 ptr, &ib.offset, &ib.buffer);
889 }
890 } else {
891 info.index_bias = info.start;
892 if (info.count_from_stream_output) {
893 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
894 }
895 }
896
897 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
898 rctx->vgt.id = R600_PIPE_STATE_VGT;
899 rctx->vgt.nregs = 0;
900 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
901 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
902 r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0);
903 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
904 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
905 r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
906 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
907 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
908 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
909 if (rctx->chip_class <= R700) {
910 unsigned multi_write = !!rctx->ps_shader->current->shader.fs_write_all &&
911 (rctx->nr_cbufs > 1);
912 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
913 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(multi_write);
914 r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
915 }
916 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
917 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
918 }
919
920 rctx->vgt.nregs = 0;
921 r600_pipe_state_mod_reg(&rctx->vgt, prim);
922 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
923 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
924 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
925 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
926 r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
927 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
928 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
929
930 if (prim == V_008958_DI_PT_LINELIST)
931 ls_mask = 1;
932 else if (prim == V_008958_DI_PT_LINESTRIP)
933 ls_mask = 2;
934 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
935 if (rctx->chip_class <= R700) {
936 unsigned multi_write = !!rctx->ps_shader->current->shader.fs_write_all &&
937 (rctx->nr_cbufs > 1);
938 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
939 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(multi_write);
940 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
941 }
942 r600_pipe_state_mod_reg(&rctx->vgt,
943 rctx->vs_shader->current->pa_cl_vs_out_cntl |
944 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
945 r600_pipe_state_mod_reg(&rctx->vgt,
946 rctx->pa_cl_clip_cntl |
947 (rctx->vs_shader->current->shader.clip_dist_write ||
948 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
949 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
950
951 r600_context_pipe_state_set(rctx, &rctx->vgt);
952
953 /* Emit states (the function expects that we emit at most 17 dwords here). */
954 r600_need_cs_space(rctx, 0, TRUE);
955
956 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
957 r600_emit_atom(rctx, state);
958 }
959 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
960 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
961 }
962 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
963 r600_context_block_resource_emit_dirty(rctx, dirty_block);
964 }
965 rctx->pm4_dirty_cdwords = 0;
966
967 /* Enable stream out if needed. */
968 if (rctx->streamout_start) {
969 r600_context_streamout_begin(rctx);
970 rctx->streamout_start = FALSE;
971 }
972
973 /* draw packet */
974 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
975 cs->buf[cs->cdw++] = ib.index_size == 4 ?
976 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
977 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
978 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
979 cs->buf[cs->cdw++] = info.instance_count;
980 if (info.indexed) {
981 va = r600_resource_va(ctx->screen, ib.buffer);
982 va += ib.offset;
983 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
984 cs->buf[cs->cdw++] = va;
985 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
986 cs->buf[cs->cdw++] = info.count;
987 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
988 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
989 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
990 } else {
991 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
992 cs->buf[cs->cdw++] = info.count;
993 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
994 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
995 }
996
997 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
998
999 if (rctx->framebuffer.zsbuf)
1000 {
1001 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
1002 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
1003 }
1004
1005 pipe_resource_reference(&ib.buffer, NULL);
1006 }
1007
1008 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1009 struct r600_pipe_state *state,
1010 uint32_t offset, uint32_t value,
1011 uint32_t range_id, uint32_t block_id,
1012 struct r600_resource *bo,
1013 enum radeon_bo_usage usage)
1014
1015 {
1016 struct r600_range *range;
1017 struct r600_block *block;
1018
1019 if (bo) assert(usage);
1020
1021 range = &ctx->range[range_id];
1022 block = range->blocks[block_id];
1023 state->regs[state->nregs].block = block;
1024 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1025
1026 state->regs[state->nregs].value = value;
1027 state->regs[state->nregs].bo = bo;
1028 state->regs[state->nregs].bo_usage = usage;
1029
1030 state->nregs++;
1031 assert(state->nregs < R600_BLOCK_MAX_REG);
1032 }
1033
1034 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1035 struct r600_pipe_state *state,
1036 uint32_t offset, uint32_t value,
1037 uint32_t range_id, uint32_t block_id)
1038 {
1039 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1040 range_id, block_id, NULL, 0);
1041 }
1042
1043 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
1044 uint32_t offset, uint32_t value,
1045 struct r600_resource *bo,
1046 enum radeon_bo_usage usage)
1047 {
1048 if (bo) assert(usage);
1049
1050 state->regs[state->nregs].id = offset;
1051 state->regs[state->nregs].block = NULL;
1052 state->regs[state->nregs].value = value;
1053 state->regs[state->nregs].bo = bo;
1054 state->regs[state->nregs].bo_usage = usage;
1055
1056 state->nregs++;
1057 assert(state->nregs < R600_BLOCK_MAX_REG);
1058 }
1059
1060 uint32_t r600_translate_stencil_op(int s_op)
1061 {
1062 switch (s_op) {
1063 case PIPE_STENCIL_OP_KEEP:
1064 return V_028800_STENCIL_KEEP;
1065 case PIPE_STENCIL_OP_ZERO:
1066 return V_028800_STENCIL_ZERO;
1067 case PIPE_STENCIL_OP_REPLACE:
1068 return V_028800_STENCIL_REPLACE;
1069 case PIPE_STENCIL_OP_INCR:
1070 return V_028800_STENCIL_INCR;
1071 case PIPE_STENCIL_OP_DECR:
1072 return V_028800_STENCIL_DECR;
1073 case PIPE_STENCIL_OP_INCR_WRAP:
1074 return V_028800_STENCIL_INCR_WRAP;
1075 case PIPE_STENCIL_OP_DECR_WRAP:
1076 return V_028800_STENCIL_DECR_WRAP;
1077 case PIPE_STENCIL_OP_INVERT:
1078 return V_028800_STENCIL_INVERT;
1079 default:
1080 R600_ERR("Unknown stencil op %d", s_op);
1081 assert(0);
1082 break;
1083 }
1084 return 0;
1085 }
1086
1087 uint32_t r600_translate_fill(uint32_t func)
1088 {
1089 switch(func) {
1090 case PIPE_POLYGON_MODE_FILL:
1091 return 2;
1092 case PIPE_POLYGON_MODE_LINE:
1093 return 1;
1094 case PIPE_POLYGON_MODE_POINT:
1095 return 0;
1096 default:
1097 assert(0);
1098 return 0;
1099 }
1100 }
1101
1102 unsigned r600_tex_wrap(unsigned wrap)
1103 {
1104 switch (wrap) {
1105 default:
1106 case PIPE_TEX_WRAP_REPEAT:
1107 return V_03C000_SQ_TEX_WRAP;
1108 case PIPE_TEX_WRAP_CLAMP:
1109 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1110 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1111 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1112 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1113 return V_03C000_SQ_TEX_CLAMP_BORDER;
1114 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1115 return V_03C000_SQ_TEX_MIRROR;
1116 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1117 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1118 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1119 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1120 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1121 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1122 }
1123 }
1124
1125 unsigned r600_tex_filter(unsigned filter)
1126 {
1127 switch (filter) {
1128 default:
1129 case PIPE_TEX_FILTER_NEAREST:
1130 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1131 case PIPE_TEX_FILTER_LINEAR:
1132 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1133 }
1134 }
1135
1136 unsigned r600_tex_mipfilter(unsigned filter)
1137 {
1138 switch (filter) {
1139 case PIPE_TEX_MIPFILTER_NEAREST:
1140 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1141 case PIPE_TEX_MIPFILTER_LINEAR:
1142 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1143 default:
1144 case PIPE_TEX_MIPFILTER_NONE:
1145 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1146 }
1147 }
1148
1149 unsigned r600_tex_compare(unsigned compare)
1150 {
1151 switch (compare) {
1152 default:
1153 case PIPE_FUNC_NEVER:
1154 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1155 case PIPE_FUNC_LESS:
1156 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1157 case PIPE_FUNC_EQUAL:
1158 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1159 case PIPE_FUNC_LEQUAL:
1160 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1161 case PIPE_FUNC_GREATER:
1162 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1163 case PIPE_FUNC_NOTEQUAL:
1164 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1165 case PIPE_FUNC_GEQUAL:
1166 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1167 case PIPE_FUNC_ALWAYS:
1168 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1169 }
1170 }