2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
98 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
99 R600_CONTEXT_FLUSH_AND_INV_CB
|
100 R600_CONTEXT_FLUSH_AND_INV
|
101 R600_CONTEXT_WAIT_3D_IDLE
;
102 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
105 static unsigned r600_conv_pipe_prim(unsigned prim
)
107 static const unsigned prim_conv
[] = {
108 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
109 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
110 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
111 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
112 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
113 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
114 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
115 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
116 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
117 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
118 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
119 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
120 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
121 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
122 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
123 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
125 assert(prim
< ARRAY_SIZE(prim_conv
));
126 return prim_conv
[prim
];
129 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
131 static const int prim_conv
[] = {
132 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
133 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
134 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
135 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
136 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
138 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
139 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
140 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
141 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
142 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
143 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
144 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
145 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
146 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
147 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
149 assert(mode
< ARRAY_SIZE(prim_conv
));
151 return prim_conv
[mode
];
154 /* common state between evergreen and r600 */
156 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
157 struct r600_blend_state
*blend
, bool blend_disable
)
159 unsigned color_control
;
160 bool update_cb
= false;
162 rctx
->alpha_to_one
= blend
->alpha_to_one
;
163 rctx
->dual_src_blend
= blend
->dual_src_blend
;
165 if (!blend_disable
) {
166 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
167 color_control
= blend
->cb_color_control
;
169 /* Blending is disabled. */
170 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
171 color_control
= blend
->cb_color_control_no_blend
;
174 /* Update derived states. */
175 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
176 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
179 if (rctx
->b
.chip_class
<= R700
&&
180 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
181 rctx
->cb_misc_state
.cb_color_control
= color_control
;
184 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
185 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
189 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
191 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
192 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
193 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
197 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
199 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
200 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
203 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
207 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
210 static void r600_set_blend_color(struct pipe_context
*ctx
,
211 const struct pipe_blend_color
*state
)
213 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
215 rctx
->blend_color
.state
= *state
;
216 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
219 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
221 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
222 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
224 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
225 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
226 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
227 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
228 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
231 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
233 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
234 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
236 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
237 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
238 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
239 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
240 if (a
->last_draw_was_indirect
) {
241 a
->last_draw_was_indirect
= false;
242 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
246 static void r600_set_clip_state(struct pipe_context
*ctx
,
247 const struct pipe_clip_state
*state
)
249 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
251 rctx
->clip_state
.state
= *state
;
252 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
253 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
256 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
257 const struct r600_stencil_ref
*state
)
259 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
261 rctx
->stencil_ref
.state
= *state
;
262 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
265 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
267 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
268 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
270 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
271 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
272 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
273 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
274 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
275 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
276 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
277 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
278 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
281 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
282 const struct pipe_stencil_ref
*state
)
284 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
285 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
286 struct r600_stencil_ref ref
;
288 rctx
->stencil_ref
.pipe_state
= *state
;
293 ref
.ref_value
[0] = state
->ref_value
[0];
294 ref
.ref_value
[1] = state
->ref_value
[1];
295 ref
.valuemask
[0] = dsa
->valuemask
[0];
296 ref
.valuemask
[1] = dsa
->valuemask
[1];
297 ref
.writemask
[0] = dsa
->writemask
[0];
298 ref
.writemask
[1] = dsa
->writemask
[1];
300 r600_set_stencil_ref(ctx
, &ref
);
303 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
305 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
306 struct r600_dsa_state
*dsa
= state
;
307 struct r600_stencil_ref ref
;
310 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
314 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
316 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
317 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
318 ref
.valuemask
[0] = dsa
->valuemask
[0];
319 ref
.valuemask
[1] = dsa
->valuemask
[1];
320 ref
.writemask
[0] = dsa
->writemask
[0];
321 ref
.writemask
[1] = dsa
->writemask
[1];
322 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
323 rctx
->zwritemask
= dsa
->zwritemask
;
324 if (rctx
->b
.chip_class
>= EVERGREEN
) {
325 /* work around some issue when not writing to zbuffer
326 * we are having lockup on evergreen so do not enable
327 * hyperz when not writing zbuffer
329 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
333 r600_set_stencil_ref(ctx
, &ref
);
335 /* Update alphatest state. */
336 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
337 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
338 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
339 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
340 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
344 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
346 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
347 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
352 rctx
->rasterizer
= rs
;
354 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
356 if (rs
->offset_enable
&&
357 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
358 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
359 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
360 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
361 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
362 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
363 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
366 /* Update clip_misc_state. */
367 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
368 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
369 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
370 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
371 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
374 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
376 /* Re-emit PA_SC_LINE_STIPPLE. */
377 rctx
->last_primitive_type
= -1;
380 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
382 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
384 r600_release_command_buffer(&rs
->buffer
);
388 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
389 struct pipe_sampler_view
*state
)
391 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
393 if (view
->tex_resource
->gpu_address
&&
394 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
395 LIST_DELINIT(&view
->list
);
397 pipe_resource_reference(&state
->texture
, NULL
);
401 void r600_sampler_states_dirty(struct r600_context
*rctx
,
402 struct r600_sampler_states
*state
)
404 if (state
->dirty_mask
) {
405 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
406 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
409 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
410 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
411 r600_mark_atom_dirty(rctx
, &state
->atom
);
415 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
416 enum pipe_shader_type shader
,
418 unsigned count
, void **states
)
420 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
421 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
422 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
423 int seamless_cube_map
= -1;
425 /* This sets 1-bit for states with index >= count. */
426 uint32_t disable_mask
= ~((1ull << count
) - 1);
427 /* These are the new states set by this function. */
428 uint32_t new_mask
= 0;
430 assert(start
== 0); /* XXX fix below */
437 for (i
= 0; i
< count
; i
++) {
438 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
440 if (rstate
== dst
->states
.states
[i
]) {
445 if (rstate
->border_color_use
) {
446 dst
->states
.has_bordercolor_mask
|= 1 << i
;
448 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
450 seamless_cube_map
= rstate
->seamless_cube_map
;
454 disable_mask
|= 1 << i
;
458 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
459 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
461 dst
->states
.enabled_mask
&= ~disable_mask
;
462 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
463 dst
->states
.enabled_mask
|= new_mask
;
464 dst
->states
.dirty_mask
|= new_mask
;
465 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
467 r600_sampler_states_dirty(rctx
, &dst
->states
);
469 /* Seamless cubemap state. */
470 if (rctx
->b
.chip_class
<= R700
&&
471 seamless_cube_map
!= -1 &&
472 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
473 /* change in TA_CNTL_AUX need a pipeline flush */
474 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
475 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
476 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
480 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
485 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
487 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
488 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
490 if (rctx
->blend_state
.cso
== state
) {
491 ctx
->bind_blend_state(ctx
, NULL
);
494 r600_release_command_buffer(&blend
->buffer
);
495 r600_release_command_buffer(&blend
->buffer_no_blend
);
499 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
501 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
502 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
504 if (rctx
->dsa_state
.cso
== state
) {
505 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
508 r600_release_command_buffer(&dsa
->buffer
);
512 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
514 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
516 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
519 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
521 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
522 r600_resource_reference(&shader
->buffer
, NULL
);
526 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
528 if (rctx
->vertex_buffer_state
.dirty_mask
) {
529 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
530 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
531 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
535 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
536 unsigned start_slot
, unsigned count
,
537 const struct pipe_vertex_buffer
*input
)
539 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
540 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
541 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
543 uint32_t disable_mask
= 0;
544 /* These are the new buffers set by this function. */
545 uint32_t new_buffer_mask
= 0;
547 /* Set vertex buffers. */
549 for (i
= 0; i
< count
; i
++) {
550 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
551 if (input
[i
].buffer
.resource
) {
552 vb
[i
].stride
= input
[i
].stride
;
553 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
554 pipe_resource_reference(&vb
[i
].buffer
.resource
, input
[i
].buffer
.resource
);
555 new_buffer_mask
|= 1 << i
;
556 r600_context_add_resource_size(ctx
, input
[i
].buffer
.resource
);
558 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
559 disable_mask
|= 1 << i
;
564 for (i
= 0; i
< count
; i
++) {
565 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
567 disable_mask
= ((1ull << count
) - 1);
570 disable_mask
<<= start_slot
;
571 new_buffer_mask
<<= start_slot
;
573 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
574 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
575 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
576 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
578 r600_vertex_buffers_dirty(rctx
);
581 void r600_sampler_views_dirty(struct r600_context
*rctx
,
582 struct r600_samplerview_state
*state
)
584 if (state
->dirty_mask
) {
585 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
586 util_bitcount(state
->dirty_mask
);
587 r600_mark_atom_dirty(rctx
, &state
->atom
);
591 static void r600_set_sampler_views(struct pipe_context
*pipe
,
592 enum pipe_shader_type shader
,
593 unsigned start
, unsigned count
,
594 struct pipe_sampler_view
**views
)
596 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
597 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
598 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
599 uint32_t dirty_sampler_states_mask
= 0;
601 /* This sets 1-bit for textures with index >= count. */
602 uint32_t disable_mask
= ~((1ull << count
) - 1);
603 /* These are the new textures set by this function. */
604 uint32_t new_mask
= 0;
606 /* Set textures with index >= count to NULL. */
607 uint32_t remaining_mask
;
609 assert(start
== 0); /* XXX fix below */
616 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
618 while (remaining_mask
) {
619 i
= u_bit_scan(&remaining_mask
);
620 assert(dst
->views
.views
[i
]);
622 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
625 for (i
= 0; i
< count
; i
++) {
626 if (rviews
[i
] == dst
->views
.views
[i
]) {
631 struct r600_texture
*rtex
=
632 (struct r600_texture
*)rviews
[i
]->base
.texture
;
633 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
635 if (!is_buffer
&& rtex
->db_compatible
) {
636 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
638 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
641 /* Track compressed colorbuffers. */
642 if (!is_buffer
&& rtex
->cmask
.size
) {
643 dst
->views
.compressed_colortex_mask
|= 1 << i
;
645 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
648 /* Changing from array to non-arrays textures and vice versa requires
649 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
650 if (rctx
->b
.chip_class
<= R700
&&
651 (dst
->states
.enabled_mask
& (1 << i
)) &&
652 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
653 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
654 dirty_sampler_states_mask
|= 1 << i
;
657 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
659 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
661 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
662 disable_mask
|= 1 << i
;
666 dst
->views
.enabled_mask
&= ~disable_mask
;
667 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
668 dst
->views
.enabled_mask
|= new_mask
;
669 dst
->views
.dirty_mask
|= new_mask
;
670 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
671 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
672 dst
->views
.dirty_buffer_constants
= TRUE
;
673 r600_sampler_views_dirty(rctx
, &dst
->views
);
675 if (dirty_sampler_states_mask
) {
676 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
677 r600_sampler_states_dirty(rctx
, &dst
->states
);
681 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
683 uint32_t mask
= views
->enabled_mask
;
686 unsigned i
= u_bit_scan(&mask
);
687 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
689 if (res
&& res
->target
!= PIPE_BUFFER
) {
690 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
692 if (rtex
->cmask
.size
) {
693 views
->compressed_colortex_mask
|= 1 << i
;
695 views
->compressed_colortex_mask
&= ~(1 << i
);
701 /* Compute the key for the hw shader variant */
702 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
703 const struct r600_pipe_shader_selector
*sel
,
704 union r600_shader_key
*key
)
706 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
707 memset(key
, 0, sizeof(*key
));
710 case PIPE_SHADER_VERTEX
: {
711 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
713 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
715 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
716 key
->vs
.as_gs_a
= true;
717 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
721 case PIPE_SHADER_GEOMETRY
:
723 case PIPE_SHADER_FRAGMENT
: {
724 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
725 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
726 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
727 !rctx
->framebuffer
.cb0_is_integer
;
728 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
729 /* Dual-source blending only makes sense with nr_cbufs == 1. */
730 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
731 key
->ps
.nr_cbufs
= 2;
734 case PIPE_SHADER_TESS_EVAL
:
735 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
737 case PIPE_SHADER_TESS_CTRL
:
738 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
745 /* Select the hw shader variant depending on the current state.
746 * (*dirty) is set to 1 if current variant was changed */
747 static int r600_shader_select(struct pipe_context
*ctx
,
748 struct r600_pipe_shader_selector
* sel
,
751 union r600_shader_key key
;
752 struct r600_pipe_shader
* shader
= NULL
;
755 r600_shader_selector_key(ctx
, sel
, &key
);
757 /* Check if we don't need to change anything.
758 * This path is also used for most shaders that don't need multiple
759 * variants, it will cost just a computation of the key and this
761 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
765 /* lookup if we have other variants in the list */
766 if (sel
->num_shaders
> 1) {
767 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
769 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
775 p
->next_variant
= c
->next_variant
;
780 if (unlikely(!shader
)) {
781 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
782 shader
->selector
= sel
;
784 r
= r600_pipe_shader_create(ctx
, shader
, key
);
786 R600_ERR("Failed to build shader variant (type=%u) %d\n",
793 /* We don't know the value of nr_ps_max_color_exports until we built
794 * at least one variant, so we may need to recompute the key after
795 * building first variant. */
796 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
797 sel
->num_shaders
== 0) {
798 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
799 r600_shader_selector_key(ctx
, sel
, &key
);
802 memcpy(&shader
->key
, &key
, sizeof(key
));
809 shader
->next_variant
= sel
->current
;
810 sel
->current
= shader
;
815 static void *r600_create_shader_state(struct pipe_context
*ctx
,
816 const struct pipe_shader_state
*state
,
817 unsigned pipe_shader_type
)
819 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
822 sel
->type
= pipe_shader_type
;
823 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
824 sel
->so
= state
->stream_output
;
825 tgsi_scan_shader(state
->tokens
, &sel
->info
);
827 switch (pipe_shader_type
) {
828 case PIPE_SHADER_GEOMETRY
:
829 sel
->gs_output_prim
=
830 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
831 sel
->gs_max_out_vertices
=
832 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
833 sel
->gs_num_invocations
=
834 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
836 case PIPE_SHADER_VERTEX
:
837 case PIPE_SHADER_TESS_CTRL
:
838 sel
->lds_patch_outputs_written_mask
= 0;
839 sel
->lds_outputs_written_mask
= 0;
841 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
842 unsigned name
= sel
->info
.output_semantic_name
[i
];
843 unsigned index
= sel
->info
.output_semantic_index
[i
];
846 case TGSI_SEMANTIC_TESSINNER
:
847 case TGSI_SEMANTIC_TESSOUTER
:
848 case TGSI_SEMANTIC_PATCH
:
849 sel
->lds_patch_outputs_written_mask
|=
850 1ull << r600_get_lds_unique_index(name
, index
);
853 sel
->lds_outputs_written_mask
|=
854 1ull << r600_get_lds_unique_index(name
, index
);
865 static void *r600_create_ps_state(struct pipe_context
*ctx
,
866 const struct pipe_shader_state
*state
)
868 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
871 static void *r600_create_vs_state(struct pipe_context
*ctx
,
872 const struct pipe_shader_state
*state
)
874 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
877 static void *r600_create_gs_state(struct pipe_context
*ctx
,
878 const struct pipe_shader_state
*state
)
880 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
883 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
884 const struct pipe_shader_state
*state
)
886 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
889 static void *r600_create_tes_state(struct pipe_context
*ctx
,
890 const struct pipe_shader_state
*state
)
892 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
895 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
897 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
900 state
= rctx
->dummy_pixel_shader
;
902 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
905 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
908 return &rctx
->gs_shader
->info
;
909 else if (rctx
->tes_shader
)
910 return &rctx
->tes_shader
->info
;
911 else if (rctx
->vs_shader
)
912 return &rctx
->vs_shader
->info
;
917 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
919 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
921 if (!state
|| rctx
->vs_shader
== state
)
924 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
925 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
926 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
929 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
931 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
933 if (state
== rctx
->gs_shader
)
936 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
937 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
941 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
944 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
946 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
948 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
951 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
953 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
955 if (state
== rctx
->tes_shader
)
958 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
959 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
963 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
966 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
967 struct r600_pipe_shader_selector
*sel
)
969 struct r600_pipe_shader
*p
= sel
->current
, *c
;
972 r600_pipe_shader_destroy(ctx
, p
);
982 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
984 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
985 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
987 if (rctx
->ps_shader
== sel
) {
988 rctx
->ps_shader
= NULL
;
991 r600_delete_shader_selector(ctx
, sel
);
994 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
996 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
997 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
999 if (rctx
->vs_shader
== sel
) {
1000 rctx
->vs_shader
= NULL
;
1003 r600_delete_shader_selector(ctx
, sel
);
1007 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1009 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1010 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1012 if (rctx
->gs_shader
== sel
) {
1013 rctx
->gs_shader
= NULL
;
1016 r600_delete_shader_selector(ctx
, sel
);
1019 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1021 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1022 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1024 if (rctx
->tcs_shader
== sel
) {
1025 rctx
->tcs_shader
= NULL
;
1028 r600_delete_shader_selector(ctx
, sel
);
1031 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1033 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1034 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1036 if (rctx
->tes_shader
== sel
) {
1037 rctx
->tes_shader
= NULL
;
1040 r600_delete_shader_selector(ctx
, sel
);
1043 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1045 if (state
->dirty_mask
) {
1046 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1047 : util_bitcount(state
->dirty_mask
)*19;
1048 r600_mark_atom_dirty(rctx
, &state
->atom
);
1052 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1053 enum pipe_shader_type shader
, uint index
,
1054 const struct pipe_constant_buffer
*input
)
1056 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1057 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1058 struct pipe_constant_buffer
*cb
;
1061 /* Note that the state tracker can unbind constant buffers by
1062 * passing NULL here.
1064 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1065 state
->enabled_mask
&= ~(1 << index
);
1066 state
->dirty_mask
&= ~(1 << index
);
1067 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1071 cb
= &state
->cb
[index
];
1072 cb
->buffer_size
= input
->buffer_size
;
1074 ptr
= input
->user_buffer
;
1077 /* Upload the user buffer. */
1078 if (R600_BIG_ENDIAN
) {
1080 unsigned i
, size
= input
->buffer_size
;
1082 if (!(tmpPtr
= malloc(size
))) {
1083 R600_ERR("Failed to allocate BE swap buffer.\n");
1087 for (i
= 0; i
< size
/ 4; ++i
) {
1088 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1091 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1092 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1095 u_upload_data(ctx
->stream_uploader
, 0,
1096 input
->buffer_size
, 256, ptr
,
1097 &cb
->buffer_offset
, &cb
->buffer
);
1099 /* account it in gtt */
1100 rctx
->b
.gtt
+= input
->buffer_size
;
1102 /* Setup the hw buffer. */
1103 cb
->buffer_offset
= input
->buffer_offset
;
1104 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1105 r600_context_add_resource_size(ctx
, input
->buffer
);
1108 state
->enabled_mask
|= 1 << index
;
1109 state
->dirty_mask
|= 1 << index
;
1110 r600_constant_buffers_dirty(rctx
, state
);
1113 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1115 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1117 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1120 rctx
->sample_mask
.sample_mask
= sample_mask
;
1121 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1124 static void r600_update_driver_const_buffers(struct r600_context
*rctx
)
1128 struct pipe_constant_buffer cb
;
1129 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
1130 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1131 if (!info
->vs_ucp_dirty
&&
1132 !info
->texture_const_dirty
&&
1133 !info
->ps_sample_pos_dirty
)
1136 ptr
= info
->constants
;
1137 size
= info
->alloc_size
;
1138 if (info
->vs_ucp_dirty
) {
1139 assert(sh
== PIPE_SHADER_VERTEX
);
1141 ptr
= rctx
->clip_state
.state
.ucp
;
1142 size
= R600_UCP_SIZE
;
1144 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1146 info
->vs_ucp_dirty
= false;
1149 if (info
->ps_sample_pos_dirty
) {
1150 assert(sh
== PIPE_SHADER_FRAGMENT
);
1152 ptr
= rctx
->sample_positions
;
1153 size
= R600_UCP_SIZE
;
1155 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1157 info
->ps_sample_pos_dirty
= false;
1160 if (info
->texture_const_dirty
) {
1163 if (sh
== PIPE_SHADER_VERTEX
)
1164 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1165 if (sh
== PIPE_SHADER_FRAGMENT
)
1166 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1168 info
->texture_const_dirty
= false;
1171 cb
.user_buffer
= ptr
;
1172 cb
.buffer_offset
= 0;
1173 cb
.buffer_size
= size
;
1174 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1175 pipe_resource_reference(&cb
.buffer
, NULL
);
1179 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1180 int array_size
, uint32_t *base_offset
)
1182 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1183 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1184 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1185 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1187 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1188 info
->texture_const_dirty
= true;
1189 *base_offset
= R600_UCP_SIZE
;
1190 return info
->constants
;
1193 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1194 * doesn't require full swizzles it does need masking and setting alpha
1195 * to one, so we setup a set of 5 constants with the masks + alpha value
1196 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1197 * then OR the alpha with the value given here.
1198 * We use a 6th constant to store the txq buffer size in
1199 * we use 7th slot for number of cube layers in a cube map array.
1201 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1203 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1205 uint32_t array_size
;
1207 uint32_t *constants
;
1208 uint32_t base_offset
;
1209 if (!samplers
->views
.dirty_buffer_constants
)
1212 samplers
->views
.dirty_buffer_constants
= FALSE
;
1214 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1215 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1217 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1219 for (i
= 0; i
< bits
; i
++) {
1220 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1221 int offset
= (base_offset
/ 4) + i
* 8;
1222 const struct util_format_description
*desc
;
1223 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1225 for (j
= 0; j
< 4; j
++)
1226 if (j
< desc
->nr_channels
)
1227 constants
[offset
+j
] = 0xffffffff;
1229 constants
[offset
+j
] = 0x0;
1230 if (desc
->nr_channels
< 4) {
1231 if (desc
->channel
[0].pure_integer
)
1232 constants
[offset
+4] = 1;
1234 constants
[offset
+4] = fui(1.0);
1236 constants
[offset
+ 4] = 0;
1238 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1239 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1245 /* On evergreen we store two values
1246 * 1. buffer size for TXQ
1247 * 2. number of cube layers in a cube map array.
1249 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1251 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1253 uint32_t array_size
;
1255 uint32_t *constants
;
1256 uint32_t base_offset
;
1257 if (!samplers
->views
.dirty_buffer_constants
)
1260 samplers
->views
.dirty_buffer_constants
= FALSE
;
1262 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1263 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1265 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1268 for (i
= 0; i
< bits
; i
++) {
1269 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1270 uint32_t offset
= (base_offset
/ 4) + i
* 2;
1271 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1272 constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1277 /* set sample xy locations as array of fragment shader constants */
1278 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1281 struct pipe_context
*ctx
= &rctx
->b
.b
;
1283 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1284 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1286 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1287 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1288 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1289 /* Also fill in center-zeroed positions used for interpolateAtSample */
1290 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1291 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1294 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1297 static void update_shader_atom(struct pipe_context
*ctx
,
1298 struct r600_shader_state
*state
,
1299 struct r600_pipe_shader
*shader
)
1301 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1303 state
->shader
= shader
;
1305 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1306 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1308 state
->atom
.num_dw
= 0;
1310 r600_mark_atom_dirty(rctx
, &state
->atom
);
1313 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1315 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1316 rctx
->shader_stages
.geom_enable
= enable
;
1317 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1320 if (rctx
->gs_rings
.enable
!= enable
) {
1321 rctx
->gs_rings
.enable
= enable
;
1322 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1324 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1325 unsigned size
= 0x1C000;
1326 rctx
->gs_rings
.esgs_ring
.buffer
=
1327 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1328 PIPE_USAGE_DEFAULT
, size
);
1329 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1333 rctx
->gs_rings
.gsvs_ring
.buffer
=
1334 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1335 PIPE_USAGE_DEFAULT
, size
);
1336 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1340 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1341 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1342 if (rctx
->tes_shader
) {
1343 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1344 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1346 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1347 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1350 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1351 R600_GS_RING_CONST_BUFFER
, NULL
);
1352 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1353 R600_GS_RING_CONST_BUFFER
, NULL
);
1354 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1355 R600_GS_RING_CONST_BUFFER
, NULL
);
1360 static void r600_update_clip_state(struct r600_context
*rctx
,
1361 struct r600_pipe_shader
*current
)
1363 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1364 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1365 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1366 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1367 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1368 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1369 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1370 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1371 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1375 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1377 struct ureg_src const0
, const1
;
1378 struct ureg_dst tessouter
, tessinner
;
1379 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1382 return; /* if we get here, we're screwed */
1384 assert(!rctx
->fixed_func_tcs_shader
);
1386 ureg_DECL_constant2D(ureg
, 0, 3, R600_LDS_INFO_CONST_BUFFER
);
1387 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 2),
1388 R600_LDS_INFO_CONST_BUFFER
);
1389 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 3),
1390 R600_LDS_INFO_CONST_BUFFER
);
1392 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1393 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1395 ureg_MOV(ureg
, tessouter
, const0
);
1396 ureg_MOV(ureg
, tessinner
, const1
);
1399 rctx
->fixed_func_tcs_shader
=
1400 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1403 static void r600_update_compressed_resource_state(struct r600_context
*rctx
)
1408 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1409 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1410 rctx
->b
.last_compressed_colortex_counter
= counter
;
1412 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1413 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1417 /* Decompress textures if needed. */
1418 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1419 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1420 if (views
->compressed_depthtex_mask
) {
1421 r600_decompress_depth_textures(rctx
, views
);
1423 if (views
->compressed_colortex_mask
) {
1424 r600_decompress_color_textures(rctx
, views
);
1429 #define SELECT_SHADER_OR_FAIL(x) do { \
1430 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1431 if (unlikely(!rctx->x##_shader->current)) \
1435 #define UPDATE_SHADER(hw, sw) do { \
1436 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1437 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1440 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1441 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1442 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1443 clip_so_current = rctx->sw##_shader->current; \
1447 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1448 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1449 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1450 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1451 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1455 #define SET_NULL_SHADER(hw) do { \
1456 if (rctx->hw_shader_stages[(hw)].shader) \
1457 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1460 static bool r600_update_derived_state(struct r600_context
*rctx
)
1462 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1463 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1464 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1466 bool need_buf_const
;
1467 struct r600_pipe_shader
*clip_so_current
= NULL
;
1469 if (!rctx
->blitter
->running
)
1470 r600_update_compressed_resource_state(rctx
);
1472 SELECT_SHADER_OR_FAIL(ps
);
1474 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1476 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1478 if (rctx
->gs_shader
)
1479 SELECT_SHADER_OR_FAIL(gs
);
1482 if (rctx
->tcs_shader
) {
1483 SELECT_SHADER_OR_FAIL(tcs
);
1485 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1486 } else if (rctx
->tes_shader
) {
1487 if (!rctx
->fixed_func_tcs_shader
) {
1488 r600_generate_fixed_func_tcs(rctx
);
1489 if (!rctx
->fixed_func_tcs_shader
)
1493 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1495 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1497 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1499 if (rctx
->tes_shader
) {
1500 SELECT_SHADER_OR_FAIL(tes
);
1503 SELECT_SHADER_OR_FAIL(vs
);
1505 if (rctx
->gs_shader
) {
1506 if (!rctx
->shader_stages
.geom_enable
) {
1507 rctx
->shader_stages
.geom_enable
= true;
1508 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1511 /* gs_shader provides GS and VS (copy shader) */
1512 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1514 /* vs_shader is used as ES */
1516 if (rctx
->tes_shader
) {
1517 /* VS goes to LS, TES goes to ES */
1518 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1519 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1521 /* vs_shader is used as ES */
1522 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1523 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1526 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1527 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1528 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1529 rctx
->shader_stages
.geom_enable
= false;
1530 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1533 if (rctx
->tes_shader
) {
1534 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1535 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1536 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1538 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1539 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1543 /* Update clip misc state. */
1544 if (clip_so_current
) {
1545 r600_update_clip_state(rctx
, clip_so_current
);
1546 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1549 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1550 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1551 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1553 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1554 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1555 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1558 if (rctx
->b
.chip_class
<= R700
) {
1559 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1561 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1562 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1563 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1567 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1568 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1569 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1571 if (rctx
->b
.chip_class
>= EVERGREEN
)
1572 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1574 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1577 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1579 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1581 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1582 evergreen_update_db_shader_control(rctx
);
1584 r600_update_db_shader_control(rctx
);
1587 /* on R600 we stuff masks + txq info into one constant buffer */
1588 /* on evergreen we only need a txq info one */
1589 if (rctx
->ps_shader
) {
1590 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1591 if (need_buf_const
) {
1592 if (rctx
->b
.chip_class
< EVERGREEN
)
1593 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1595 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1599 if (rctx
->vs_shader
) {
1600 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1601 if (need_buf_const
) {
1602 if (rctx
->b
.chip_class
< EVERGREEN
)
1603 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1605 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1609 if (rctx
->gs_shader
) {
1610 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1611 if (need_buf_const
) {
1612 if (rctx
->b
.chip_class
< EVERGREEN
)
1613 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1615 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1619 r600_update_driver_const_buffers(rctx
);
1621 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1622 if (!r600_adjust_gprs(rctx
)) {
1623 /* discard rendering */
1628 if (rctx
->b
.chip_class
== EVERGREEN
) {
1629 if (!evergreen_adjust_gprs(rctx
)) {
1630 /* discard rendering */
1635 blend_disable
= (rctx
->dual_src_blend
&&
1636 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1638 if (blend_disable
!= rctx
->force_blend_disable
) {
1639 rctx
->force_blend_disable
= blend_disable
;
1640 r600_bind_blend_state_internal(rctx
,
1641 rctx
->blend_state
.cso
,
1648 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1650 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1651 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1653 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1654 state
->pa_cl_clip_cntl
|
1655 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1656 S_028810_CLIP_DISABLE(state
->clip_disable
));
1657 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1658 state
->pa_cl_vs_out_cntl
|
1659 (state
->clip_plane_enable
& state
->clip_dist_write
));
1660 /* reuse needs to be set off if we write oViewport */
1661 if (rctx
->b
.chip_class
>= EVERGREEN
)
1662 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1663 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1666 /* rast_prim is the primitive type after GS. */
1667 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
1669 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1670 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
1672 /* Skip this if not rendering lines. */
1673 if (rast_prim
!= PIPE_PRIM_LINES
&&
1674 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
1675 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
1676 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
1677 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
1680 if (rast_prim
== rctx
->last_rast_prim
)
1683 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1684 * reset the stipple pattern at each packet (line strips, line loops).
1686 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1687 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
1688 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1689 rctx
->last_rast_prim
= rast_prim
;
1692 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1694 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1695 struct pipe_resource
*indexbuf
= info
->has_user_indices
? NULL
: info
->index
.resource
;
1696 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1697 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
1698 bool has_user_indices
= info
->has_user_indices
;
1700 unsigned num_patches
, dirty_tex_counter
, index_offset
= 0;
1701 unsigned index_size
= info
->index_size
;
1704 if (!info
->indirect
&& !info
->count
&& (index_size
|| !info
->count_from_stream_output
)) {
1708 if (unlikely(!rctx
->vs_shader
)) {
1712 if (unlikely(!rctx
->ps_shader
&&
1713 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
1718 /* make sure that the gfx ring is only one active */
1719 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
1720 rctx
->b
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1723 /* Re-emit the framebuffer state if needed. */
1724 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
1725 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
1726 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1727 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1728 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
1731 if (!r600_update_derived_state(rctx
)) {
1732 /* useless to render because current rendering command
1738 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
1739 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
1743 index_offset
+= info
->start
* index_size
;
1745 /* Translate 8-bit indices to 16-bit. */
1746 if (unlikely(index_size
== 1)) {
1747 struct pipe_resource
*out_buffer
= NULL
;
1748 unsigned out_offset
;
1750 unsigned start
, count
;
1752 if (likely(!info
->indirect
)) {
1754 count
= info
->count
;
1757 /* Have to get start/count from indirect buffer, slow path ahead... */
1758 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
->buffer
;
1759 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1760 PIPE_TRANSFER_READ
);
1762 data
+= info
->indirect
->offset
/ sizeof(unsigned);
1763 start
= data
[2] * index_size
;
1772 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
1773 256, &out_offset
, &out_buffer
, &ptr
);
1777 util_shorten_ubyte_elts_to_userptr(
1778 &rctx
->b
.b
, info
, 0, 0, index_offset
, count
, ptr
);
1780 indexbuf
= out_buffer
;
1781 index_offset
= out_offset
;
1783 has_user_indices
= false;
1786 /* Upload the index buffer.
1787 * The upload is skipped for small index counts on little-endian machines
1788 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1789 * Indirect draws never use immediate indices.
1790 * Note: Instanced rendering in combination with immediate indices hangs. */
1791 if (has_user_indices
&& (R600_BIG_ENDIAN
|| info
->indirect
||
1792 info
->instance_count
> 1 ||
1793 info
->count
*index_size
> 20)) {
1795 u_upload_data(ctx
->stream_uploader
, 0,
1796 info
->count
* index_size
, 256,
1797 info
->index
.user
, &index_offset
, &indexbuf
);
1798 has_user_indices
= false;
1800 index_bias
= info
->index_bias
;
1802 index_bias
= info
->start
;
1805 /* Set the index offset and primitive restart. */
1806 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
1807 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
1808 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
1809 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
1810 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
1811 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
1812 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
1813 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1816 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1817 if (rctx
->b
.chip_class
== R600
) {
1818 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1819 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1822 if (rctx
->b
.chip_class
>= EVERGREEN
)
1823 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
1826 r600_need_cs_space(rctx
, has_user_indices
? 5 : 0, TRUE
);
1827 r600_flush_emit(rctx
);
1829 mask
= rctx
->dirty_atoms
;
1831 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
1834 if (rctx
->b
.chip_class
== CAYMAN
) {
1835 /* Copied from radeonsi. */
1836 unsigned primgroup_size
= 128; /* recommended without a GS */
1837 bool ia_switch_on_eop
= false;
1838 bool partial_vs_wave
= false;
1840 if (rctx
->gs_shader
)
1841 primgroup_size
= 64; /* recommended with a GS */
1843 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1844 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1845 ia_switch_on_eop
= true;
1848 if (r600_get_strmout_en(&rctx
->b
))
1849 partial_vs_wave
= true;
1851 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1852 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1853 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1854 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1857 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1858 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
1861 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
1862 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
1865 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1866 * even though it should have no effect on those. */
1867 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1868 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1869 unsigned prim
= info
->mode
;
1871 if (rctx
->gs_shader
) {
1872 prim
= rctx
->gs_shader
->gs_output_prim
;
1874 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1876 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1877 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1878 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
1879 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1881 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1884 /* Update start instance. */
1885 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
1886 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
1887 rctx
->last_start_instance
= info
->start_instance
;
1890 /* Update the primitive type. */
1891 if (rctx
->last_primitive_type
!= info
->mode
) {
1892 r600_emit_rasterizer_prim_state(rctx
);
1893 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1894 r600_conv_pipe_prim(info
->mode
));
1896 rctx
->last_primitive_type
= info
->mode
;
1900 if (likely(!info
->indirect
)) {
1901 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
1902 radeon_emit(cs
, info
->instance_count
);
1904 uint64_t va
= r600_resource(info
->indirect
->buffer
)->gpu_address
;
1905 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1907 // Invalidate so non-indirect draw calls reset this state
1908 rctx
->vgt_state
.last_draw_was_indirect
= true;
1909 rctx
->last_start_instance
= -1;
1911 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
1912 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
1913 radeon_emit(cs
, va
);
1914 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1916 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1917 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1918 (struct r600_resource
*)info
->indirect
->buffer
,
1920 RADEON_PRIO_DRAW_INDIRECT
));
1924 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1925 radeon_emit(cs
, index_size
== 4 ?
1926 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1927 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
1929 if (has_user_indices
) {
1930 unsigned size_bytes
= info
->count
*index_size
;
1931 unsigned size_dw
= align(size_bytes
, 4) / 4;
1932 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
1933 radeon_emit(cs
, info
->count
);
1934 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
1935 radeon_emit_array(cs
, info
->index
.user
, size_dw
);
1937 uint64_t va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
1939 if (likely(!info
->indirect
)) {
1940 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
1941 radeon_emit(cs
, va
);
1942 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1943 radeon_emit(cs
, info
->count
);
1944 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1945 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1946 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1947 (struct r600_resource
*)indexbuf
,
1949 RADEON_PRIO_INDEX_BUFFER
));
1952 uint32_t max_size
= (indexbuf
->width0
- index_offset
) / index_size
;
1954 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
1955 radeon_emit(cs
, va
);
1956 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1958 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1959 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1960 (struct r600_resource
*)indexbuf
,
1962 RADEON_PRIO_INDEX_BUFFER
));
1964 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1965 radeon_emit(cs
, max_size
);
1967 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
1968 radeon_emit(cs
, info
->indirect
->offset
);
1969 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1973 if (unlikely(info
->count_from_stream_output
)) {
1974 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
1975 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1977 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1979 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
1980 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
1981 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
1982 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
1983 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
1984 radeon_emit(cs
, 0); /* unused */
1986 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1987 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1988 t
->buf_filled_size
, RADEON_USAGE_READ
,
1989 RADEON_PRIO_SO_FILLED_SIZE
));
1992 if (likely(!info
->indirect
)) {
1993 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
1994 radeon_emit(cs
, info
->count
);
1997 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
1998 radeon_emit(cs
, info
->indirect
->offset
);
2000 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2001 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2004 /* SMX returns CONTEXT_DONE too early workaround */
2005 if (rctx
->b
.family
== CHIP_R600
||
2006 rctx
->b
.family
== CHIP_RV610
||
2007 rctx
->b
.family
== CHIP_RV630
||
2008 rctx
->b
.family
== CHIP_RV635
) {
2009 /* if we have gs shader or streamout
2010 we need to do a wait idle after every draw */
2011 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2012 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2016 /* ES ring rolling over at EOP - workaround */
2017 if (rctx
->b
.chip_class
== R600
) {
2018 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2019 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2022 if (rctx
->trace_buf
)
2023 eg_trace_emit(rctx
);
2025 if (rctx
->framebuffer
.do_update_surf_dirtiness
) {
2026 /* Set the depth buffer as dirty. */
2027 if (rctx
->framebuffer
.state
.zsbuf
) {
2028 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2029 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2031 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2033 if (rtex
->surface
.has_stencil
)
2034 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2036 if (rctx
->framebuffer
.compressed_cb_mask
) {
2037 struct pipe_surface
*surf
;
2038 struct r600_texture
*rtex
;
2039 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2042 unsigned i
= u_bit_scan(&mask
);
2043 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2044 rtex
= (struct r600_texture
*)surf
->texture
;
2046 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2050 rctx
->framebuffer
.do_update_surf_dirtiness
= false;
2053 if (index_size
&& indexbuf
!= info
->index
.resource
)
2054 pipe_resource_reference(&indexbuf
, NULL
);
2055 rctx
->b
.num_draw_calls
++;
2058 uint32_t r600_translate_stencil_op(int s_op
)
2061 case PIPE_STENCIL_OP_KEEP
:
2062 return V_028800_STENCIL_KEEP
;
2063 case PIPE_STENCIL_OP_ZERO
:
2064 return V_028800_STENCIL_ZERO
;
2065 case PIPE_STENCIL_OP_REPLACE
:
2066 return V_028800_STENCIL_REPLACE
;
2067 case PIPE_STENCIL_OP_INCR
:
2068 return V_028800_STENCIL_INCR
;
2069 case PIPE_STENCIL_OP_DECR
:
2070 return V_028800_STENCIL_DECR
;
2071 case PIPE_STENCIL_OP_INCR_WRAP
:
2072 return V_028800_STENCIL_INCR_WRAP
;
2073 case PIPE_STENCIL_OP_DECR_WRAP
:
2074 return V_028800_STENCIL_DECR_WRAP
;
2075 case PIPE_STENCIL_OP_INVERT
:
2076 return V_028800_STENCIL_INVERT
;
2078 R600_ERR("Unknown stencil op %d", s_op
);
2085 uint32_t r600_translate_fill(uint32_t func
)
2088 case PIPE_POLYGON_MODE_FILL
:
2090 case PIPE_POLYGON_MODE_LINE
:
2092 case PIPE_POLYGON_MODE_POINT
:
2100 unsigned r600_tex_wrap(unsigned wrap
)
2104 case PIPE_TEX_WRAP_REPEAT
:
2105 return V_03C000_SQ_TEX_WRAP
;
2106 case PIPE_TEX_WRAP_CLAMP
:
2107 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2108 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2109 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2110 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2111 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2112 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2113 return V_03C000_SQ_TEX_MIRROR
;
2114 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2115 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2116 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2117 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2118 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2119 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2123 unsigned r600_tex_mipfilter(unsigned filter
)
2126 case PIPE_TEX_MIPFILTER_NEAREST
:
2127 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2128 case PIPE_TEX_MIPFILTER_LINEAR
:
2129 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2131 case PIPE_TEX_MIPFILTER_NONE
:
2132 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2136 unsigned r600_tex_compare(unsigned compare
)
2140 case PIPE_FUNC_NEVER
:
2141 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2142 case PIPE_FUNC_LESS
:
2143 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2144 case PIPE_FUNC_EQUAL
:
2145 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2146 case PIPE_FUNC_LEQUAL
:
2147 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2148 case PIPE_FUNC_GREATER
:
2149 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2150 case PIPE_FUNC_NOTEQUAL
:
2151 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2152 case PIPE_FUNC_GEQUAL
:
2153 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2154 case PIPE_FUNC_ALWAYS
:
2155 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2159 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2161 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2162 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2164 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2165 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2168 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2170 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2171 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2173 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2174 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2175 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2176 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2177 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2180 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2183 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2184 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2189 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2190 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2191 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2192 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2195 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2196 const unsigned char *swizzle_view
,
2200 unsigned char swizzle
[4];
2201 unsigned result
= 0;
2202 const uint32_t tex_swizzle_shift
[4] = {
2205 const uint32_t vtx_swizzle_shift
[4] = {
2208 const uint32_t swizzle_bit
[4] = {
2211 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2214 swizzle_shift
= vtx_swizzle_shift
;
2217 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2219 memcpy(swizzle
, swizzle_format
, 4);
2223 for (i
= 0; i
< 4; i
++) {
2224 switch (swizzle
[i
]) {
2225 case PIPE_SWIZZLE_Y
:
2226 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2228 case PIPE_SWIZZLE_Z
:
2229 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2231 case PIPE_SWIZZLE_W
:
2232 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2234 case PIPE_SWIZZLE_0
:
2235 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2237 case PIPE_SWIZZLE_1
:
2238 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2240 default: /* PIPE_SWIZZLE_X */
2241 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2247 /* texture format translate */
2248 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2249 enum pipe_format format
,
2250 const unsigned char *swizzle_view
,
2251 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2252 bool do_endian_swap
)
2254 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2255 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2256 const struct util_format_description
*desc
;
2257 boolean uniform
= TRUE
;
2258 bool is_srgb_valid
= FALSE
;
2259 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2260 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2261 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2262 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2263 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2266 const uint32_t sign_bit
[4] = {
2267 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2268 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2269 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2270 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2273 /* Need to replace the specified texture formats in case of big-endian.
2274 * These formats are formats that have channels with number of bits
2275 * not divisible by 8.
2276 * Mesa conversion functions don't swap bits for those formats, and because
2277 * we transmit this over a serial bus to the GPU (PCIe), the
2278 * bit-endianess is important!!!
2279 * In case we have an "opposite" format, just use that for the swizzling
2280 * information. If we don't have such an "opposite" format, we need
2281 * to use a fixed swizzle info instead (see below)
2283 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2284 format
= PIPE_FORMAT_A4R4_UNORM
;
2286 desc
= util_format_description(format
);
2290 /* Depth and stencil swizzling is handled separately. */
2291 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2292 /* Need to check for specific texture formats that don't have
2293 * an "opposite" format we can use. For those formats, we directly
2294 * specify the swizzling, which is the LE swizzling as defined in
2297 if (do_endian_swap
) {
2298 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2299 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2300 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2301 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2302 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2303 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2305 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2307 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2311 /* Colorspace (return non-RGB formats directly). */
2312 switch (desc
->colorspace
) {
2313 /* Depth stencil formats */
2314 case UTIL_FORMAT_COLORSPACE_ZS
:
2316 /* Depth sampler formats. */
2317 case PIPE_FORMAT_Z16_UNORM
:
2318 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2321 case PIPE_FORMAT_Z24X8_UNORM
:
2322 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2323 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2326 case PIPE_FORMAT_X8Z24_UNORM
:
2327 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2328 if (rscreen
->b
.chip_class
< EVERGREEN
)
2330 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2333 case PIPE_FORMAT_Z32_FLOAT
:
2334 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2335 result
= FMT_32_FLOAT
;
2337 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2338 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2339 result
= FMT_X24_8_32_FLOAT
;
2341 /* Stencil sampler formats. */
2342 case PIPE_FORMAT_S8_UINT
:
2343 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2344 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2347 case PIPE_FORMAT_X24S8_UINT
:
2348 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2349 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2352 case PIPE_FORMAT_S8X24_UINT
:
2353 if (rscreen
->b
.chip_class
< EVERGREEN
)
2355 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2356 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2359 case PIPE_FORMAT_X32_S8X24_UINT
:
2360 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2361 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2362 result
= FMT_X24_8_32_FLOAT
;
2368 case UTIL_FORMAT_COLORSPACE_YUV
:
2369 yuv_format
|= (1 << 30);
2371 case PIPE_FORMAT_UYVY
:
2372 case PIPE_FORMAT_YUYV
:
2376 goto out_unknown
; /* XXX */
2378 case UTIL_FORMAT_COLORSPACE_SRGB
:
2379 word4
|= S_038010_FORCE_DEGAMMA(1);
2386 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2388 case PIPE_FORMAT_RGTC1_SNORM
:
2389 case PIPE_FORMAT_LATC1_SNORM
:
2390 word4
|= sign_bit
[0];
2391 case PIPE_FORMAT_RGTC1_UNORM
:
2392 case PIPE_FORMAT_LATC1_UNORM
:
2395 case PIPE_FORMAT_RGTC2_SNORM
:
2396 case PIPE_FORMAT_LATC2_SNORM
:
2397 word4
|= sign_bit
[0] | sign_bit
[1];
2398 case PIPE_FORMAT_RGTC2_UNORM
:
2399 case PIPE_FORMAT_LATC2_UNORM
:
2407 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2409 case PIPE_FORMAT_DXT1_RGB
:
2410 case PIPE_FORMAT_DXT1_RGBA
:
2411 case PIPE_FORMAT_DXT1_SRGB
:
2412 case PIPE_FORMAT_DXT1_SRGBA
:
2414 is_srgb_valid
= TRUE
;
2416 case PIPE_FORMAT_DXT3_RGBA
:
2417 case PIPE_FORMAT_DXT3_SRGBA
:
2419 is_srgb_valid
= TRUE
;
2421 case PIPE_FORMAT_DXT5_RGBA
:
2422 case PIPE_FORMAT_DXT5_SRGBA
:
2424 is_srgb_valid
= TRUE
;
2431 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2432 if (rscreen
->b
.chip_class
< EVERGREEN
)
2436 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2437 case PIPE_FORMAT_BPTC_SRGBA
:
2439 is_srgb_valid
= TRUE
;
2441 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2442 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2444 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2452 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2454 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2455 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2458 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2459 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2467 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2468 result
= FMT_5_9_9_9_SHAREDEXP
;
2470 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2471 result
= FMT_10_11_11_FLOAT
;
2476 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2477 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2478 word4
|= sign_bit
[i
];
2482 /* R8G8Bx_SNORM - XXX CxV8U8 */
2484 /* See whether the components are of the same size. */
2485 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2486 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2489 /* Non-uniform formats. */
2491 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2492 desc
->channel
[0].pure_integer
)
2493 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2494 switch(desc
->nr_channels
) {
2496 if (desc
->channel
[0].size
== 5 &&
2497 desc
->channel
[1].size
== 6 &&
2498 desc
->channel
[2].size
== 5) {
2504 if (desc
->channel
[0].size
== 5 &&
2505 desc
->channel
[1].size
== 5 &&
2506 desc
->channel
[2].size
== 5 &&
2507 desc
->channel
[3].size
== 1) {
2508 result
= FMT_1_5_5_5
;
2511 if (desc
->channel
[0].size
== 10 &&
2512 desc
->channel
[1].size
== 10 &&
2513 desc
->channel
[2].size
== 10 &&
2514 desc
->channel
[3].size
== 2) {
2515 result
= FMT_2_10_10_10
;
2523 /* Find the first non-VOID channel. */
2524 for (i
= 0; i
< 4; i
++) {
2525 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2533 /* uniform formats */
2534 switch (desc
->channel
[i
].type
) {
2535 case UTIL_FORMAT_TYPE_UNSIGNED
:
2536 case UTIL_FORMAT_TYPE_SIGNED
:
2538 if (!desc
->channel
[i
].normalized
&&
2539 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2543 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2544 desc
->channel
[i
].pure_integer
)
2545 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2547 switch (desc
->channel
[i
].size
) {
2549 switch (desc
->nr_channels
) {
2554 result
= FMT_4_4_4_4
;
2559 switch (desc
->nr_channels
) {
2567 result
= FMT_8_8_8_8
;
2568 is_srgb_valid
= TRUE
;
2573 switch (desc
->nr_channels
) {
2581 result
= FMT_16_16_16_16
;
2586 switch (desc
->nr_channels
) {
2594 result
= FMT_32_32_32_32
;
2600 case UTIL_FORMAT_TYPE_FLOAT
:
2601 switch (desc
->channel
[i
].size
) {
2603 switch (desc
->nr_channels
) {
2605 result
= FMT_16_FLOAT
;
2608 result
= FMT_16_16_FLOAT
;
2611 result
= FMT_16_16_16_16_FLOAT
;
2616 switch (desc
->nr_channels
) {
2618 result
= FMT_32_FLOAT
;
2621 result
= FMT_32_32_FLOAT
;
2624 result
= FMT_32_32_32_32_FLOAT
;
2633 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2638 *yuv_format_p
= yuv_format
;
2641 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2645 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
2646 bool do_endian_swap
)
2648 const struct util_format_description
*desc
= util_format_description(format
);
2649 int channel
= util_format_get_first_non_void_channel(format
);
2654 #define HAS_SIZE(x,y,z,w) \
2655 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2656 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2658 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2659 return V_0280A0_COLOR_10_11_11_FLOAT
;
2661 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2665 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2667 switch (desc
->nr_channels
) {
2669 switch (desc
->channel
[0].size
) {
2671 return V_0280A0_COLOR_8
;
2674 return V_0280A0_COLOR_16_FLOAT
;
2676 return V_0280A0_COLOR_16
;
2679 return V_0280A0_COLOR_32_FLOAT
;
2681 return V_0280A0_COLOR_32
;
2685 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2686 switch (desc
->channel
[0].size
) {
2689 return V_0280A0_COLOR_4_4
;
2691 return ~0U; /* removed on Evergreen */
2693 return V_0280A0_COLOR_8_8
;
2696 return V_0280A0_COLOR_16_16_FLOAT
;
2698 return V_0280A0_COLOR_16_16
;
2701 return V_0280A0_COLOR_32_32_FLOAT
;
2703 return V_0280A0_COLOR_32_32
;
2705 } else if (HAS_SIZE(8,24,0,0)) {
2706 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
2707 } else if (HAS_SIZE(24,8,0,0)) {
2708 return V_0280A0_COLOR_8_24
;
2712 if (HAS_SIZE(5,6,5,0)) {
2713 return V_0280A0_COLOR_5_6_5
;
2714 } else if (HAS_SIZE(32,8,24,0)) {
2715 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2719 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2720 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2721 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2722 switch (desc
->channel
[0].size
) {
2724 return V_0280A0_COLOR_4_4_4_4
;
2726 return V_0280A0_COLOR_8_8_8_8
;
2729 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2731 return V_0280A0_COLOR_16_16_16_16
;
2734 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2736 return V_0280A0_COLOR_32_32_32_32
;
2738 } else if (HAS_SIZE(5,5,5,1)) {
2739 return V_0280A0_COLOR_1_5_5_5
;
2740 } else if (HAS_SIZE(10,10,10,2)) {
2741 return V_0280A0_COLOR_2_10_10_10
;
2748 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
2750 if (R600_BIG_ENDIAN
) {
2751 switch(colorformat
) {
2752 /* 8-bit buffers. */
2753 case V_0280A0_COLOR_4_4
:
2754 case V_0280A0_COLOR_8
:
2757 /* 16-bit buffers. */
2758 case V_0280A0_COLOR_8_8
:
2760 * No need to do endian swaps on array formats,
2761 * as mesa<-->pipe formats conversion take into account
2766 case V_0280A0_COLOR_5_6_5
:
2767 case V_0280A0_COLOR_1_5_5_5
:
2768 case V_0280A0_COLOR_4_4_4_4
:
2769 case V_0280A0_COLOR_16
:
2770 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
2772 /* 32-bit buffers. */
2773 case V_0280A0_COLOR_8_8_8_8
:
2775 * No need to do endian swaps on array formats,
2776 * as mesa<-->pipe formats conversion take into account
2781 case V_0280A0_COLOR_2_10_10_10
:
2782 case V_0280A0_COLOR_8_24
:
2783 case V_0280A0_COLOR_24_8
:
2784 case V_0280A0_COLOR_32_FLOAT
:
2785 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
2787 case V_0280A0_COLOR_16_16_FLOAT
:
2788 case V_0280A0_COLOR_16_16
:
2789 return ENDIAN_8IN16
;
2791 /* 64-bit buffers. */
2792 case V_0280A0_COLOR_16_16_16_16
:
2793 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2794 return ENDIAN_8IN16
;
2796 case V_0280A0_COLOR_32_32_FLOAT
:
2797 case V_0280A0_COLOR_32_32
:
2798 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2799 return ENDIAN_8IN32
;
2801 /* 128-bit buffers. */
2802 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2803 case V_0280A0_COLOR_32_32_32_32
:
2804 return ENDIAN_8IN32
;
2806 return ENDIAN_NONE
; /* Unsupported. */
2813 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2815 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2816 struct r600_resource
*rbuffer
= r600_resource(buf
);
2817 unsigned i
, shader
, mask
;
2818 struct r600_pipe_sampler_view
*view
;
2820 /* Reallocate the buffer in the same pipe_resource. */
2821 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
2823 /* We changed the buffer, now we need to bind it where the old one was bound. */
2824 /* Vertex buffers. */
2825 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2827 i
= u_bit_scan(&mask
);
2828 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
.resource
== &rbuffer
->b
.b
) {
2829 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2830 r600_vertex_buffers_dirty(rctx
);
2833 /* Streamout buffers. */
2834 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2835 if (rctx
->b
.streamout
.targets
[i
] &&
2836 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2837 if (rctx
->b
.streamout
.begin_emitted
) {
2838 r600_emit_streamout_end(&rctx
->b
);
2840 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2841 r600_streamout_buffers_dirty(&rctx
->b
);
2845 /* Constant buffers. */
2846 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2847 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2849 uint32_t mask
= state
->enabled_mask
;
2852 unsigned i
= u_bit_scan(&mask
);
2853 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2855 state
->dirty_mask
|= 1 << i
;
2859 r600_constant_buffers_dirty(rctx
, state
);
2863 /* Texture buffer objects - update the virtual addresses in descriptors. */
2864 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
2865 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2866 uint64_t offset
= view
->base
.u
.buf
.offset
;
2867 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2869 view
->tex_resource_words
[0] = va
;
2870 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2871 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2874 /* Texture buffer objects - make bindings dirty if needed. */
2875 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2876 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2878 uint32_t mask
= state
->enabled_mask
;
2881 unsigned i
= u_bit_scan(&mask
);
2882 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2884 state
->dirty_mask
|= 1 << i
;
2888 r600_sampler_views_dirty(rctx
, state
);
2893 static void r600_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
2895 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2897 /* Pipeline stat & streamout queries. */
2899 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
2900 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
2902 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
2903 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
2906 /* Occlusion queries. */
2907 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
2908 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
2909 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2913 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2914 bool include_draw_vbo
)
2916 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2919 /* keep this at the end of this file, please */
2920 void r600_init_common_state_functions(struct r600_context
*rctx
)
2922 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2923 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2924 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2925 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
2926 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
2927 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2928 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2929 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2930 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2931 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2932 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2933 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2934 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2935 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2936 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
2937 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
2938 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2939 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2940 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2941 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2942 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2943 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2944 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2945 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2946 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
2947 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
2948 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2949 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2950 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2951 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2952 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2953 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2954 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2955 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2956 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2957 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2958 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
2959 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2960 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2961 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;