2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
41 #include "nir/nir_to_tgsi_info.h"
42 #include "tgsi/tgsi_from_mesa.h"
44 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
47 cb
->buf
= CALLOC(1, 4 * num_dw
);
48 cb
->max_num_dw
= num_dw
;
51 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
56 void r600_add_atom(struct r600_context
*rctx
,
57 struct r600_atom
*atom
,
60 assert(id
< R600_NUM_ATOMS
);
61 assert(rctx
->atoms
[id
] == NULL
);
62 rctx
->atoms
[id
] = atom
;
66 void r600_init_atom(struct r600_context
*rctx
,
67 struct r600_atom
*atom
,
69 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
72 atom
->emit
= (void*)emit
;
73 atom
->num_dw
= num_dw
;
74 r600_add_atom(rctx
, atom
, id
);
77 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
79 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
82 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
84 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
85 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
86 unsigned alpha_ref
= a
->sx_alpha_ref
;
88 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
92 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
93 a
->sx_alpha_test_control
|
94 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
95 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
98 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
100 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
102 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
105 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
106 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
108 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
109 PIPE_BARRIER_SHADER_BUFFER
|
110 PIPE_BARRIER_TEXTURE
|
112 PIPE_BARRIER_STREAMOUT_BUFFER
|
113 PIPE_BARRIER_GLOBAL_BUFFER
)) {
114 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
|
115 R600_CONTEXT_INV_TEX_CACHE
;
118 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
120 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV
;
122 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
125 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
127 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
129 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
130 R600_CONTEXT_FLUSH_AND_INV_CB
|
131 R600_CONTEXT_FLUSH_AND_INV
|
132 R600_CONTEXT_WAIT_3D_IDLE
;
133 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
136 static unsigned r600_conv_pipe_prim(unsigned prim
)
138 static const unsigned prim_conv
[] = {
139 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
140 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
141 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
142 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
143 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
144 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
145 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
146 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
147 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
148 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
149 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
150 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
151 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
152 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
153 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
154 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
156 assert(prim
< ARRAY_SIZE(prim_conv
));
157 return prim_conv
[prim
];
160 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
162 static const int prim_conv
[] = {
163 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
164 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
165 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
166 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
167 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
168 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
169 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
170 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
171 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
172 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
173 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
174 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
175 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
176 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
177 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
178 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
180 assert(mode
< ARRAY_SIZE(prim_conv
));
182 return prim_conv
[mode
];
185 /* common state between evergreen and r600 */
187 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
188 struct r600_blend_state
*blend
, bool blend_disable
)
190 unsigned color_control
;
191 bool update_cb
= false;
193 rctx
->alpha_to_one
= blend
->alpha_to_one
;
194 rctx
->dual_src_blend
= blend
->dual_src_blend
;
196 if (!blend_disable
) {
197 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
198 color_control
= blend
->cb_color_control
;
200 /* Blending is disabled. */
201 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
202 color_control
= blend
->cb_color_control_no_blend
;
205 /* Update derived states. */
206 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
207 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
210 if (rctx
->b
.chip_class
<= R700
&&
211 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
212 rctx
->cb_misc_state
.cb_color_control
= color_control
;
215 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
216 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
220 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
222 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
223 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
224 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
228 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
230 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
231 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
234 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
238 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
241 static void r600_set_blend_color(struct pipe_context
*ctx
,
242 const struct pipe_blend_color
*state
)
244 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
246 rctx
->blend_color
.state
= *state
;
247 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
250 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
252 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
253 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
255 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
256 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
257 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
258 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
259 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
262 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
264 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
265 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
267 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
268 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
269 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
270 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
271 if (a
->last_draw_was_indirect
) {
272 a
->last_draw_was_indirect
= false;
273 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
277 static void r600_set_clip_state(struct pipe_context
*ctx
,
278 const struct pipe_clip_state
*state
)
280 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
282 rctx
->clip_state
.state
= *state
;
283 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
284 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
287 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
288 const struct r600_stencil_ref
*state
)
290 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
292 rctx
->stencil_ref
.state
= *state
;
293 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
296 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
298 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
299 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
301 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
302 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
303 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
304 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
305 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
306 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
307 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
308 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
309 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
312 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
313 const struct pipe_stencil_ref
*state
)
315 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
316 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
317 struct r600_stencil_ref ref
;
319 rctx
->stencil_ref
.pipe_state
= *state
;
324 ref
.ref_value
[0] = state
->ref_value
[0];
325 ref
.ref_value
[1] = state
->ref_value
[1];
326 ref
.valuemask
[0] = dsa
->valuemask
[0];
327 ref
.valuemask
[1] = dsa
->valuemask
[1];
328 ref
.writemask
[0] = dsa
->writemask
[0];
329 ref
.writemask
[1] = dsa
->writemask
[1];
331 r600_set_stencil_ref(ctx
, &ref
);
334 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
336 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
337 struct r600_dsa_state
*dsa
= state
;
338 struct r600_stencil_ref ref
;
341 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
345 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
347 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
348 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
349 ref
.valuemask
[0] = dsa
->valuemask
[0];
350 ref
.valuemask
[1] = dsa
->valuemask
[1];
351 ref
.writemask
[0] = dsa
->writemask
[0];
352 ref
.writemask
[1] = dsa
->writemask
[1];
353 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
354 rctx
->zwritemask
= dsa
->zwritemask
;
355 if (rctx
->b
.chip_class
>= EVERGREEN
) {
356 /* work around some issue when not writing to zbuffer
357 * we are having lockup on evergreen so do not enable
358 * hyperz when not writing zbuffer
360 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
364 r600_set_stencil_ref(ctx
, &ref
);
366 /* Update alphatest state. */
367 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
368 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
369 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
370 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
371 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
375 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
377 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
378 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
383 rctx
->rasterizer
= rs
;
385 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
387 if (rs
->offset_enable
&&
388 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
389 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
390 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
391 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
392 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
393 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
394 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
397 /* Update clip_misc_state. */
398 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
399 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
400 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
401 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
402 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
405 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
407 /* Re-emit PA_SC_LINE_STIPPLE. */
408 rctx
->last_primitive_type
= -1;
411 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
413 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
415 r600_release_command_buffer(&rs
->buffer
);
419 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
420 struct pipe_sampler_view
*state
)
422 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
424 if (view
->tex_resource
->gpu_address
&&
425 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
426 list_delinit(&view
->list
);
428 pipe_resource_reference(&state
->texture
, NULL
);
432 void r600_sampler_states_dirty(struct r600_context
*rctx
,
433 struct r600_sampler_states
*state
)
435 if (state
->dirty_mask
) {
436 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
437 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
440 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
441 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
442 r600_mark_atom_dirty(rctx
, &state
->atom
);
446 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
447 enum pipe_shader_type shader
,
449 unsigned count
, void **states
)
451 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
452 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
453 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
454 int seamless_cube_map
= -1;
456 /* This sets 1-bit for states with index >= count. */
457 uint32_t disable_mask
= ~((1ull << count
) - 1);
458 /* These are the new states set by this function. */
459 uint32_t new_mask
= 0;
461 assert(start
== 0); /* XXX fix below */
468 for (i
= 0; i
< count
; i
++) {
469 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
471 if (rstate
== dst
->states
.states
[i
]) {
476 if (rstate
->border_color_use
) {
477 dst
->states
.has_bordercolor_mask
|= 1 << i
;
479 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
481 seamless_cube_map
= rstate
->seamless_cube_map
;
485 disable_mask
|= 1 << i
;
489 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
490 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
492 dst
->states
.enabled_mask
&= ~disable_mask
;
493 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
494 dst
->states
.enabled_mask
|= new_mask
;
495 dst
->states
.dirty_mask
|= new_mask
;
496 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
498 r600_sampler_states_dirty(rctx
, &dst
->states
);
500 /* Seamless cubemap state. */
501 if (rctx
->b
.chip_class
<= R700
&&
502 seamless_cube_map
!= -1 &&
503 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
504 /* change in TA_CNTL_AUX need a pipeline flush */
505 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
506 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
507 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
511 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
516 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
518 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
519 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
521 if (rctx
->blend_state
.cso
== state
) {
522 ctx
->bind_blend_state(ctx
, NULL
);
525 r600_release_command_buffer(&blend
->buffer
);
526 r600_release_command_buffer(&blend
->buffer_no_blend
);
530 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
532 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
533 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
535 if (rctx
->dsa_state
.cso
== state
) {
536 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
539 r600_release_command_buffer(&dsa
->buffer
);
543 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
545 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
547 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
550 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
552 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
554 r600_resource_reference(&shader
->buffer
, NULL
);
558 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
560 if (rctx
->vertex_buffer_state
.dirty_mask
) {
561 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
562 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
563 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
567 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
568 unsigned start_slot
, unsigned count
,
569 const struct pipe_vertex_buffer
*input
)
571 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
572 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
573 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
575 uint32_t disable_mask
= 0;
576 /* These are the new buffers set by this function. */
577 uint32_t new_buffer_mask
= 0;
579 /* Set vertex buffers. */
581 for (i
= 0; i
< count
; i
++) {
582 if ((input
[i
].buffer
.resource
!= vb
[i
].buffer
.resource
) ||
583 (vb
[i
].stride
!= input
[i
].stride
) ||
584 (vb
[i
].buffer_offset
!= input
[i
].buffer_offset
) ||
585 (vb
[i
].is_user_buffer
!= input
[i
].is_user_buffer
)) {
586 if (input
[i
].buffer
.resource
) {
587 vb
[i
].stride
= input
[i
].stride
;
588 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
589 pipe_resource_reference(&vb
[i
].buffer
.resource
, input
[i
].buffer
.resource
);
590 new_buffer_mask
|= 1 << i
;
591 r600_context_add_resource_size(ctx
, input
[i
].buffer
.resource
);
593 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
594 disable_mask
|= 1 << i
;
599 for (i
= 0; i
< count
; i
++) {
600 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
602 disable_mask
= ((1ull << count
) - 1);
605 disable_mask
<<= start_slot
;
606 new_buffer_mask
<<= start_slot
;
608 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
609 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
610 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
611 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
613 r600_vertex_buffers_dirty(rctx
);
616 void r600_sampler_views_dirty(struct r600_context
*rctx
,
617 struct r600_samplerview_state
*state
)
619 if (state
->dirty_mask
) {
620 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
621 util_bitcount(state
->dirty_mask
);
622 r600_mark_atom_dirty(rctx
, &state
->atom
);
626 static void r600_set_sampler_views(struct pipe_context
*pipe
,
627 enum pipe_shader_type shader
,
628 unsigned start
, unsigned count
,
629 struct pipe_sampler_view
**views
)
631 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
632 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
633 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
634 uint32_t dirty_sampler_states_mask
= 0;
636 /* This sets 1-bit for textures with index >= count. */
637 uint32_t disable_mask
= ~((1ull << count
) - 1);
638 /* These are the new textures set by this function. */
639 uint32_t new_mask
= 0;
641 /* Set textures with index >= count to NULL. */
642 uint32_t remaining_mask
;
644 assert(start
== 0); /* XXX fix below */
651 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
653 while (remaining_mask
) {
654 i
= u_bit_scan(&remaining_mask
);
655 assert(dst
->views
.views
[i
]);
657 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
660 for (i
= 0; i
< count
; i
++) {
661 if (rviews
[i
] == dst
->views
.views
[i
]) {
666 struct r600_texture
*rtex
=
667 (struct r600_texture
*)rviews
[i
]->base
.texture
;
668 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
670 if (!is_buffer
&& rtex
->db_compatible
) {
671 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
673 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
676 /* Track compressed colorbuffers. */
677 if (!is_buffer
&& rtex
->cmask
.size
) {
678 dst
->views
.compressed_colortex_mask
|= 1 << i
;
680 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
683 /* Changing from array to non-arrays textures and vice versa requires
684 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
685 if (rctx
->b
.chip_class
<= R700
&&
686 (dst
->states
.enabled_mask
& (1 << i
)) &&
687 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
688 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
689 dirty_sampler_states_mask
|= 1 << i
;
692 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
694 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
696 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
697 disable_mask
|= 1 << i
;
701 dst
->views
.enabled_mask
&= ~disable_mask
;
702 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
703 dst
->views
.enabled_mask
|= new_mask
;
704 dst
->views
.dirty_mask
|= new_mask
;
705 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
706 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
707 dst
->views
.dirty_buffer_constants
= TRUE
;
708 r600_sampler_views_dirty(rctx
, &dst
->views
);
710 if (dirty_sampler_states_mask
) {
711 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
712 r600_sampler_states_dirty(rctx
, &dst
->states
);
716 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
718 uint32_t mask
= views
->enabled_mask
;
721 unsigned i
= u_bit_scan(&mask
);
722 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
724 if (res
&& res
->target
!= PIPE_BUFFER
) {
725 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
727 if (rtex
->cmask
.size
) {
728 views
->compressed_colortex_mask
|= 1 << i
;
730 views
->compressed_colortex_mask
&= ~(1 << i
);
736 static int r600_get_hw_atomic_count(const struct pipe_context
*ctx
,
737 enum pipe_shader_type shader
)
739 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
742 case PIPE_SHADER_FRAGMENT
:
743 case PIPE_SHADER_COMPUTE
:
746 case PIPE_SHADER_VERTEX
:
747 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
749 case PIPE_SHADER_GEOMETRY
:
750 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
751 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
753 case PIPE_SHADER_TESS_EVAL
:
754 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
755 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
756 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0);
758 case PIPE_SHADER_TESS_CTRL
:
759 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
760 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
761 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0) +
762 rctx
->tes_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
768 static void r600_update_compressed_colortex_mask_images(struct r600_image_state
*images
)
770 uint32_t mask
= images
->enabled_mask
;
773 unsigned i
= u_bit_scan(&mask
);
774 struct pipe_resource
*res
= images
->views
[i
].base
.resource
;
776 if (res
&& res
->target
!= PIPE_BUFFER
) {
777 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
779 if (rtex
->cmask
.size
) {
780 images
->compressed_colortex_mask
|= 1 << i
;
782 images
->compressed_colortex_mask
&= ~(1 << i
);
788 /* Compute the key for the hw shader variant */
789 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
790 const struct r600_pipe_shader_selector
*sel
,
791 union r600_shader_key
*key
)
793 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
794 memset(key
, 0, sizeof(*key
));
797 case PIPE_SHADER_VERTEX
: {
798 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
800 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
802 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
803 key
->vs
.as_gs_a
= true;
804 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
806 key
->vs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_VERTEX
);
809 case PIPE_SHADER_GEOMETRY
:
810 key
->gs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_GEOMETRY
);
811 key
->gs
.tri_strip_adj_fix
= rctx
->gs_tri_strip_adj_fix
;
813 case PIPE_SHADER_FRAGMENT
: {
814 if (rctx
->ps_shader
->info
.images_declared
)
815 key
->ps
.image_size_const_offset
= util_last_bit(rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.enabled_mask
);
816 key
->ps
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_FRAGMENT
);
817 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
818 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
819 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
820 !rctx
->framebuffer
.cb0_is_integer
;
821 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
822 /* Dual-source blending only makes sense with nr_cbufs == 1. */
823 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
824 key
->ps
.nr_cbufs
= 2;
827 case PIPE_SHADER_TESS_EVAL
:
828 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
829 key
->tes
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_EVAL
);
831 case PIPE_SHADER_TESS_CTRL
:
832 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
833 key
->tcs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_CTRL
);
835 case PIPE_SHADER_COMPUTE
:
842 /* Select the hw shader variant depending on the current state.
843 * (*dirty) is set to 1 if current variant was changed */
844 int r600_shader_select(struct pipe_context
*ctx
,
845 struct r600_pipe_shader_selector
* sel
,
848 union r600_shader_key key
;
849 struct r600_pipe_shader
* shader
= NULL
;
852 r600_shader_selector_key(ctx
, sel
, &key
);
854 /* Check if we don't need to change anything.
855 * This path is also used for most shaders that don't need multiple
856 * variants, it will cost just a computation of the key and this
858 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
862 /* lookup if we have other variants in the list */
863 if (sel
->num_shaders
> 1) {
864 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
866 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
872 p
->next_variant
= c
->next_variant
;
877 if (unlikely(!shader
)) {
878 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
879 shader
->selector
= sel
;
881 r
= r600_pipe_shader_create(ctx
, shader
, key
);
883 R600_ERR("Failed to build shader variant (type=%u) %d\n",
890 /* We don't know the value of nr_ps_max_color_exports until we built
891 * at least one variant, so we may need to recompute the key after
892 * building first variant. */
893 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
894 sel
->num_shaders
== 0) {
895 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
896 r600_shader_selector_key(ctx
, sel
, &key
);
899 memcpy(&shader
->key
, &key
, sizeof(key
));
906 shader
->next_variant
= sel
->current
;
907 sel
->current
= shader
;
912 struct r600_pipe_shader_selector
*r600_create_shader_state_tokens(struct pipe_context
*ctx
,
913 const void *prog
, enum pipe_shader_ir ir
,
914 unsigned pipe_shader_type
)
916 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
918 sel
->type
= pipe_shader_type
;
919 if (ir
== PIPE_SHADER_IR_TGSI
) {
920 sel
->tokens
= tgsi_dup_tokens((const struct tgsi_token
*)prog
);
921 tgsi_scan_shader(sel
->tokens
, &sel
->info
);
922 } else if (ir
== PIPE_SHADER_IR_NIR
){
923 sel
->nir
= nir_shader_clone(NULL
, (const nir_shader
*)prog
);
924 nir_tgsi_scan_shader(sel
->nir
, &sel
->info
, true);
929 static void *r600_create_shader_state(struct pipe_context
*ctx
,
930 const struct pipe_shader_state
*state
,
931 unsigned pipe_shader_type
)
934 struct r600_pipe_shader_selector
*sel
;
936 if (state
->type
== PIPE_SHADER_IR_TGSI
)
937 sel
= r600_create_shader_state_tokens(ctx
, state
->tokens
, state
->type
, pipe_shader_type
);
938 else if (state
->type
== PIPE_SHADER_IR_NIR
) {
939 sel
= r600_create_shader_state_tokens(ctx
, state
->ir
.nir
, state
->type
, pipe_shader_type
);
941 assert(0 && "Unknown shader type\n");
943 sel
->ir_type
= state
->type
;
944 sel
->so
= state
->stream_output
;
946 switch (pipe_shader_type
) {
947 case PIPE_SHADER_GEOMETRY
:
948 sel
->gs_output_prim
=
949 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
950 sel
->gs_max_out_vertices
=
951 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
952 sel
->gs_num_invocations
=
953 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
955 case PIPE_SHADER_VERTEX
:
956 case PIPE_SHADER_TESS_CTRL
:
957 sel
->lds_patch_outputs_written_mask
= 0;
958 sel
->lds_outputs_written_mask
= 0;
960 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
961 unsigned name
= sel
->info
.output_semantic_name
[i
];
962 unsigned index
= sel
->info
.output_semantic_index
[i
];
965 case TGSI_SEMANTIC_TESSINNER
:
966 case TGSI_SEMANTIC_TESSOUTER
:
967 case TGSI_SEMANTIC_PATCH
:
968 sel
->lds_patch_outputs_written_mask
|=
969 1ull << r600_get_lds_unique_index(name
, index
);
972 sel
->lds_outputs_written_mask
|=
973 1ull << r600_get_lds_unique_index(name
, index
);
984 static void *r600_create_ps_state(struct pipe_context
*ctx
,
985 const struct pipe_shader_state
*state
)
987 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
990 static void *r600_create_vs_state(struct pipe_context
*ctx
,
991 const struct pipe_shader_state
*state
)
993 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
996 static void *r600_create_gs_state(struct pipe_context
*ctx
,
997 const struct pipe_shader_state
*state
)
999 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
1002 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
1003 const struct pipe_shader_state
*state
)
1005 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
1008 static void *r600_create_tes_state(struct pipe_context
*ctx
,
1009 const struct pipe_shader_state
*state
)
1011 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
1014 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
1016 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1019 state
= rctx
->dummy_pixel_shader
;
1021 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
1024 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
1026 if (rctx
->gs_shader
)
1027 return &rctx
->gs_shader
->info
;
1028 else if (rctx
->tes_shader
)
1029 return &rctx
->tes_shader
->info
;
1030 else if (rctx
->vs_shader
)
1031 return &rctx
->vs_shader
->info
;
1036 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1038 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1040 if (!state
|| rctx
->vs_shader
== state
)
1043 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
1044 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1046 if (rctx
->vs_shader
->so
.num_outputs
)
1047 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
1050 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1052 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1054 if (state
== rctx
->gs_shader
)
1057 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
1058 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1063 if (rctx
->gs_shader
->so
.num_outputs
)
1064 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
1067 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1069 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1071 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
1074 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1076 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1078 if (state
== rctx
->tes_shader
)
1081 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
1082 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1087 if (rctx
->tes_shader
->so
.num_outputs
)
1088 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
1091 void r600_delete_shader_selector(struct pipe_context
*ctx
,
1092 struct r600_pipe_shader_selector
*sel
)
1094 struct r600_pipe_shader
*p
= sel
->current
, *c
;
1096 c
= p
->next_variant
;
1097 r600_pipe_shader_destroy(ctx
, p
);
1102 if (sel
->ir_type
== PIPE_SHADER_IR_TGSI
) {
1104 /* We might have converted the TGSI shader to a NIR shader */
1106 ralloc_free(sel
->nir
);
1108 else if (sel
->ir_type
== PIPE_SHADER_IR_NIR
)
1109 ralloc_free(sel
->nir
);
1114 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
1116 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1117 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1119 if (rctx
->ps_shader
== sel
) {
1120 rctx
->ps_shader
= NULL
;
1123 r600_delete_shader_selector(ctx
, sel
);
1126 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1128 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1129 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1131 if (rctx
->vs_shader
== sel
) {
1132 rctx
->vs_shader
= NULL
;
1135 r600_delete_shader_selector(ctx
, sel
);
1139 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1141 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1142 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1144 if (rctx
->gs_shader
== sel
) {
1145 rctx
->gs_shader
= NULL
;
1148 r600_delete_shader_selector(ctx
, sel
);
1151 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1153 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1154 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1156 if (rctx
->tcs_shader
== sel
) {
1157 rctx
->tcs_shader
= NULL
;
1160 r600_delete_shader_selector(ctx
, sel
);
1163 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1165 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1166 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1168 if (rctx
->tes_shader
== sel
) {
1169 rctx
->tes_shader
= NULL
;
1172 r600_delete_shader_selector(ctx
, sel
);
1175 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1177 if (state
->dirty_mask
) {
1178 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1179 : util_bitcount(state
->dirty_mask
)*19;
1180 r600_mark_atom_dirty(rctx
, &state
->atom
);
1184 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1185 enum pipe_shader_type shader
, uint index
,
1186 const struct pipe_constant_buffer
*input
)
1188 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1189 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1190 struct pipe_constant_buffer
*cb
;
1193 /* Note that the state tracker can unbind constant buffers by
1194 * passing NULL here.
1196 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1197 state
->enabled_mask
&= ~(1 << index
);
1198 state
->dirty_mask
&= ~(1 << index
);
1199 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1203 cb
= &state
->cb
[index
];
1204 cb
->buffer_size
= input
->buffer_size
;
1206 ptr
= input
->user_buffer
;
1209 /* Upload the user buffer. */
1210 if (R600_BIG_ENDIAN
) {
1212 unsigned i
, size
= input
->buffer_size
;
1214 if (!(tmpPtr
= malloc(size
))) {
1215 R600_ERR("Failed to allocate BE swap buffer.\n");
1219 for (i
= 0; i
< size
/ 4; ++i
) {
1220 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1223 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1224 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1227 u_upload_data(ctx
->stream_uploader
, 0,
1228 input
->buffer_size
, 256, ptr
,
1229 &cb
->buffer_offset
, &cb
->buffer
);
1231 /* account it in gtt */
1232 rctx
->b
.gtt
+= input
->buffer_size
;
1234 /* Setup the hw buffer. */
1235 cb
->buffer_offset
= input
->buffer_offset
;
1236 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1237 r600_context_add_resource_size(ctx
, input
->buffer
);
1240 state
->enabled_mask
|= 1 << index
;
1241 state
->dirty_mask
|= 1 << index
;
1242 r600_constant_buffers_dirty(rctx
, state
);
1245 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1247 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1249 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1252 rctx
->sample_mask
.sample_mask
= sample_mask
;
1253 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1256 void r600_update_driver_const_buffers(struct r600_context
*rctx
, bool compute_only
)
1260 struct pipe_constant_buffer cb
;
1263 start
= compute_only
? PIPE_SHADER_COMPUTE
: 0;
1264 end
= compute_only
? PIPE_SHADER_TYPES
: PIPE_SHADER_COMPUTE
;
1266 for (sh
= start
; sh
< end
; sh
++) {
1267 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1268 if (!info
->vs_ucp_dirty
&&
1269 !info
->texture_const_dirty
&&
1270 !info
->ps_sample_pos_dirty
&&
1271 !info
->tcs_default_levels_dirty
&&
1272 !info
->cs_block_grid_size_dirty
)
1275 ptr
= info
->constants
;
1276 size
= info
->alloc_size
;
1277 if (info
->vs_ucp_dirty
) {
1278 assert(sh
== PIPE_SHADER_VERTEX
);
1280 ptr
= rctx
->clip_state
.state
.ucp
;
1281 size
= R600_UCP_SIZE
;
1283 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1285 info
->vs_ucp_dirty
= false;
1288 else if (info
->ps_sample_pos_dirty
) {
1289 assert(sh
== PIPE_SHADER_FRAGMENT
);
1291 ptr
= rctx
->sample_positions
;
1292 size
= R600_UCP_SIZE
;
1294 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1296 info
->ps_sample_pos_dirty
= false;
1299 else if (info
->cs_block_grid_size_dirty
) {
1300 assert(sh
== PIPE_SHADER_COMPUTE
);
1302 ptr
= rctx
->cs_block_grid_sizes
;
1303 size
= R600_CS_BLOCK_GRID_SIZE
;
1305 memcpy(ptr
, rctx
->cs_block_grid_sizes
, R600_CS_BLOCK_GRID_SIZE
);
1307 info
->cs_block_grid_size_dirty
= false;
1310 else if (info
->tcs_default_levels_dirty
) {
1312 * We'd only really need this for default tcs shader.
1314 assert(sh
== PIPE_SHADER_TESS_CTRL
);
1316 ptr
= rctx
->tess_state
;
1317 size
= R600_TCS_DEFAULT_LEVELS_SIZE
;
1319 memcpy(ptr
, rctx
->tess_state
, R600_TCS_DEFAULT_LEVELS_SIZE
);
1321 info
->tcs_default_levels_dirty
= false;
1324 if (info
->texture_const_dirty
) {
1327 if (sh
== PIPE_SHADER_VERTEX
)
1328 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1329 if (sh
== PIPE_SHADER_FRAGMENT
)
1330 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1331 if (sh
== PIPE_SHADER_COMPUTE
)
1332 memcpy(ptr
, rctx
->cs_block_grid_sizes
, R600_CS_BLOCK_GRID_SIZE
);
1333 if (sh
== PIPE_SHADER_TESS_CTRL
)
1334 memcpy(ptr
, rctx
->tess_state
, R600_TCS_DEFAULT_LEVELS_SIZE
);
1336 info
->texture_const_dirty
= false;
1339 cb
.user_buffer
= ptr
;
1340 cb
.buffer_offset
= 0;
1341 cb
.buffer_size
= size
;
1342 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1343 pipe_resource_reference(&cb
.buffer
, NULL
);
1347 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1348 unsigned array_size
, uint32_t *base_offset
)
1350 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1351 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1352 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1353 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1355 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1356 info
->texture_const_dirty
= true;
1357 *base_offset
= R600_UCP_SIZE
;
1358 return info
->constants
;
1361 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1362 * doesn't require full swizzles it does need masking and setting alpha
1363 * to one, so we setup a set of 5 constants with the masks + alpha value
1364 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1365 * then OR the alpha with the value given here.
1366 * We use a 6th constant to store the txq buffer size in
1367 * we use 7th slot for number of cube layers in a cube map array.
1369 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1371 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1373 uint32_t array_size
;
1375 uint32_t *constants
;
1376 uint32_t base_offset
;
1377 if (!samplers
->views
.dirty_buffer_constants
)
1380 samplers
->views
.dirty_buffer_constants
= FALSE
;
1382 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1383 array_size
= bits
* 8 * sizeof(uint32_t);
1385 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1387 for (i
= 0; i
< bits
; i
++) {
1388 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1389 int offset
= (base_offset
/ 4) + i
* 8;
1390 const struct util_format_description
*desc
;
1391 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1393 for (j
= 0; j
< 4; j
++)
1394 if (j
< desc
->nr_channels
)
1395 constants
[offset
+j
] = 0xffffffff;
1397 constants
[offset
+j
] = 0x0;
1398 if (desc
->nr_channels
< 4) {
1399 if (desc
->channel
[0].pure_integer
)
1400 constants
[offset
+4] = 1;
1402 constants
[offset
+4] = fui(1.0);
1404 constants
[offset
+ 4] = 0;
1406 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.u
.buf
.size
/
1407 util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1408 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1414 /* On evergreen we store one value
1415 * 1. number of cube layers in a cube map array.
1417 void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1419 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1420 struct r600_image_state
*images
= NULL
;
1421 int bits
, sview_bits
, img_bits
;
1422 uint32_t array_size
;
1424 uint32_t *constants
;
1425 uint32_t base_offset
;
1427 if (shader_type
== PIPE_SHADER_FRAGMENT
) {
1428 images
= &rctx
->fragment_images
;
1429 } else if (shader_type
== PIPE_SHADER_COMPUTE
) {
1430 images
= &rctx
->compute_images
;
1433 if (!samplers
->views
.dirty_buffer_constants
&&
1434 !(images
&& images
->dirty_buffer_constants
))
1438 images
->dirty_buffer_constants
= FALSE
;
1439 samplers
->views
.dirty_buffer_constants
= FALSE
;
1441 bits
= sview_bits
= util_last_bit(samplers
->views
.enabled_mask
);
1443 bits
+= util_last_bit(images
->enabled_mask
);
1446 array_size
= bits
* sizeof(uint32_t);
1448 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1451 for (i
= 0; i
< sview_bits
; i
++) {
1452 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1453 uint32_t offset
= (base_offset
/ 4) + i
;
1454 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1458 for (i
= sview_bits
; i
< img_bits
; i
++) {
1459 int idx
= i
- sview_bits
;
1460 if (images
->enabled_mask
& (1 << idx
)) {
1461 uint32_t offset
= (base_offset
/ 4) + i
;
1462 constants
[offset
] = images
->views
[idx
].base
.resource
->array_size
/ 6;
1468 /* set sample xy locations as array of fragment shader constants */
1469 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1471 struct pipe_context
*ctx
= &rctx
->b
.b
;
1473 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1474 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1476 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1477 for (unsigned i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1478 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1479 /* Also fill in center-zeroed positions used for interpolateAtSample */
1480 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1481 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1484 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1487 static void update_shader_atom(struct pipe_context
*ctx
,
1488 struct r600_shader_state
*state
,
1489 struct r600_pipe_shader
*shader
)
1491 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1493 state
->shader
= shader
;
1495 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1496 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1498 state
->atom
.num_dw
= 0;
1500 r600_mark_atom_dirty(rctx
, &state
->atom
);
1503 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1505 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1506 rctx
->shader_stages
.geom_enable
= enable
;
1507 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1510 if (rctx
->gs_rings
.enable
!= enable
) {
1511 rctx
->gs_rings
.enable
= enable
;
1512 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1514 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1515 unsigned size
= 0x1C000;
1516 rctx
->gs_rings
.esgs_ring
.buffer
=
1517 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1518 PIPE_USAGE_DEFAULT
, size
);
1519 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1523 rctx
->gs_rings
.gsvs_ring
.buffer
=
1524 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1525 PIPE_USAGE_DEFAULT
, size
);
1526 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1530 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1531 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1532 if (rctx
->tes_shader
) {
1533 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1534 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1536 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1537 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1540 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1541 R600_GS_RING_CONST_BUFFER
, NULL
);
1542 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1543 R600_GS_RING_CONST_BUFFER
, NULL
);
1544 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1545 R600_GS_RING_CONST_BUFFER
, NULL
);
1550 static void r600_update_clip_state(struct r600_context
*rctx
,
1551 struct r600_pipe_shader
*current
)
1553 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1554 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1555 current
->shader
.cull_dist_write
!= rctx
->clip_misc_state
.cull_dist_write
||
1556 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1557 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1558 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1559 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1560 rctx
->clip_misc_state
.cull_dist_write
= current
->shader
.cull_dist_write
;
1561 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1562 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1563 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1567 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1569 struct ureg_src const0
, const1
;
1570 struct ureg_dst tessouter
, tessinner
;
1571 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1574 return; /* if we get here, we're screwed */
1576 assert(!rctx
->fixed_func_tcs_shader
);
1578 ureg_DECL_constant2D(ureg
, 0, 1, R600_BUFFER_INFO_CONST_BUFFER
);
1579 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 0),
1580 R600_BUFFER_INFO_CONST_BUFFER
);
1581 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 1),
1582 R600_BUFFER_INFO_CONST_BUFFER
);
1584 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1585 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1587 ureg_MOV(ureg
, tessouter
, const0
);
1588 ureg_MOV(ureg
, tessinner
, const1
);
1591 rctx
->fixed_func_tcs_shader
=
1592 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1595 void r600_update_compressed_resource_state(struct r600_context
*rctx
, bool compute_only
)
1600 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1601 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1602 rctx
->b
.last_compressed_colortex_counter
= counter
;
1605 r600_update_compressed_colortex_mask(&rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
);
1607 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1608 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1612 r600_update_compressed_colortex_mask_images(&rctx
->fragment_images
);
1613 r600_update_compressed_colortex_mask_images(&rctx
->compute_images
);
1616 /* Decompress textures if needed. */
1617 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1618 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1621 if (i
!= PIPE_SHADER_COMPUTE
)
1623 if (views
->compressed_depthtex_mask
) {
1624 r600_decompress_depth_textures(rctx
, views
);
1626 if (views
->compressed_colortex_mask
) {
1627 r600_decompress_color_textures(rctx
, views
);
1632 struct r600_image_state
*istate
;
1634 if (!compute_only
) {
1635 istate
= &rctx
->fragment_images
;
1636 if (istate
->compressed_depthtex_mask
)
1637 r600_decompress_depth_images(rctx
, istate
);
1638 if (istate
->compressed_colortex_mask
)
1639 r600_decompress_color_images(rctx
, istate
);
1642 istate
= &rctx
->compute_images
;
1643 if (istate
->compressed_depthtex_mask
)
1644 r600_decompress_depth_images(rctx
, istate
);
1645 if (istate
->compressed_colortex_mask
)
1646 r600_decompress_color_images(rctx
, istate
);
1650 /* update MEM_SCRATCH buffers if needed */
1651 void r600_setup_scratch_area_for_shader(struct r600_context
*rctx
,
1652 struct r600_pipe_shader
*shader
, struct r600_scratch_buffer
*scratch
,
1653 unsigned ring_base_reg
, unsigned item_size_reg
, unsigned ring_size_reg
)
1655 unsigned num_ses
= rctx
->screen
->b
.info
.max_se
;
1656 unsigned num_pipes
= rctx
->screen
->b
.info
.r600_max_quad_pipes
;
1657 unsigned nthreads
= 128;
1659 unsigned itemsize
= shader
->scratch_space_needed
* 4;
1660 unsigned size
= align(itemsize
* nthreads
* num_pipes
* num_ses
* 4, 256);
1662 if (scratch
->dirty
||
1663 unlikely(shader
->scratch_space_needed
!= scratch
->item_size
||
1664 size
> scratch
->size
)) {
1665 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
1667 scratch
->dirty
= false;
1669 if (size
> scratch
->size
) {
1670 // Release prior one if any
1671 if (scratch
->buffer
) {
1672 pipe_resource_reference((struct pipe_resource
**)&scratch
->buffer
, NULL
);
1675 scratch
->buffer
= (struct r600_resource
*)pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1676 PIPE_USAGE_DEFAULT
, size
);
1677 if (scratch
->buffer
) {
1678 scratch
->size
= size
;
1682 scratch
->item_size
= shader
->scratch_space_needed
;
1684 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1685 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1686 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1688 // multi-SE chips need programming per SE
1689 for (unsigned se
= 0; se
< num_ses
; se
++) {
1690 struct r600_resource
*rbuffer
= scratch
->buffer
;
1691 unsigned size_per_se
= size
/ num_ses
;
1693 // Direct to particular SE
1695 radeon_set_config_reg(cs
, EG_0802C_GRBM_GFX_INDEX
,
1696 S_0802C_INSTANCE_INDEX(0) |
1697 S_0802C_SE_INDEX(se
) |
1698 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1699 S_0802C_SE_BROADCAST_WRITES(0));
1702 radeon_set_config_reg(cs
, ring_base_reg
, (rbuffer
->gpu_address
+ size_per_se
* se
) >> 8);
1703 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1704 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1705 RADEON_USAGE_READWRITE
,
1706 RADEON_PRIO_SCRATCH_BUFFER
));
1707 radeon_set_context_reg(cs
, item_size_reg
, itemsize
);
1708 radeon_set_config_reg(cs
, ring_size_reg
, size_per_se
>> 8);
1711 // Restore broadcast mode
1713 radeon_set_config_reg(cs
, EG_0802C_GRBM_GFX_INDEX
,
1714 S_0802C_INSTANCE_INDEX(0) |
1715 S_0802C_SE_INDEX(0) |
1716 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1717 S_0802C_SE_BROADCAST_WRITES(1));
1720 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1721 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1722 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1726 void r600_setup_scratch_buffers(struct r600_context
*rctx
) {
1727 static const struct {
1731 } regs
[R600_NUM_HW_STAGES
] = {
1732 [R600_HW_STAGE_PS
] = { R_008C68_SQ_PSTMP_RING_BASE
, R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, R_008C6C_SQ_PSTMP_RING_SIZE
},
1733 [R600_HW_STAGE_VS
] = { R_008C60_SQ_VSTMP_RING_BASE
, R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, R_008C64_SQ_VSTMP_RING_SIZE
},
1734 [R600_HW_STAGE_GS
] = { R_008C58_SQ_GSTMP_RING_BASE
, R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, R_008C5C_SQ_GSTMP_RING_SIZE
},
1735 [R600_HW_STAGE_ES
] = { R_008C50_SQ_ESTMP_RING_BASE
, R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, R_008C54_SQ_ESTMP_RING_SIZE
}
1738 for (unsigned i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
1739 struct r600_pipe_shader
*stage
= rctx
->hw_shader_stages
[i
].shader
;
1741 if (stage
&& unlikely(stage
->scratch_space_needed
)) {
1742 r600_setup_scratch_area_for_shader(rctx
, stage
,
1743 &rctx
->scratch_buffers
[i
], regs
[i
].ring_base
, regs
[i
].item_size
, regs
[i
].ring_size
);
1748 #define SELECT_SHADER_OR_FAIL(x) do { \
1749 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1750 if (unlikely(!rctx->x##_shader->current)) \
1754 #define UPDATE_SHADER(hw, sw) do { \
1755 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1756 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1759 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1760 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1761 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1762 clip_so_current = rctx->sw##_shader->current; \
1766 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1767 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1768 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1769 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1770 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1774 #define SET_NULL_SHADER(hw) do { \
1775 if (rctx->hw_shader_stages[(hw)].shader) \
1776 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1779 static bool r600_update_derived_state(struct r600_context
*rctx
)
1781 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1782 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1783 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1785 bool need_buf_const
;
1786 struct r600_pipe_shader
*clip_so_current
= NULL
;
1788 if (!rctx
->blitter
->running
)
1789 r600_update_compressed_resource_state(rctx
, false);
1791 SELECT_SHADER_OR_FAIL(ps
);
1793 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1795 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1797 if (rctx
->gs_shader
)
1798 SELECT_SHADER_OR_FAIL(gs
);
1801 if (rctx
->tcs_shader
) {
1802 SELECT_SHADER_OR_FAIL(tcs
);
1804 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1805 } else if (rctx
->tes_shader
) {
1806 if (!rctx
->fixed_func_tcs_shader
) {
1807 r600_generate_fixed_func_tcs(rctx
);
1808 if (!rctx
->fixed_func_tcs_shader
)
1812 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1814 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1816 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1818 if (rctx
->tes_shader
) {
1819 SELECT_SHADER_OR_FAIL(tes
);
1822 SELECT_SHADER_OR_FAIL(vs
);
1824 if (rctx
->gs_shader
) {
1825 if (!rctx
->shader_stages
.geom_enable
) {
1826 rctx
->shader_stages
.geom_enable
= true;
1827 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1830 /* gs_shader provides GS and VS (copy shader) */
1831 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1833 /* vs_shader is used as ES */
1835 if (rctx
->tes_shader
) {
1836 /* VS goes to LS, TES goes to ES */
1837 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1838 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1840 /* vs_shader is used as ES */
1841 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1842 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1845 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1846 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1847 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1848 rctx
->shader_stages
.geom_enable
= false;
1849 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1852 if (rctx
->tes_shader
) {
1853 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1854 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1855 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1857 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1858 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1863 * XXX: I believe there's some fatal flaw in the dirty state logic when
1864 * enabling/disabling tes.
1865 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1866 * it will therefore overwrite the VS slots. If it now gets disabled,
1867 * the VS needs to rebind all buffer/resource/sampler slots - not only
1868 * has TES overwritten the corresponding slots, but when the VS was
1869 * operating as LS the things with correpsonding dirty bits got bound
1870 * to LS slots and won't reflect what is dirty as VS stage even if the
1871 * TES didn't overwrite it. The story for re-enabled TES is similar.
1872 * In any case, we're not allowed to submit any TES state when
1873 * TES is disabled (the state tracker may not do this but this looks
1874 * like an optimization to me, not something which can be relied on).
1877 /* Update clip misc state. */
1878 if (clip_so_current
) {
1879 r600_update_clip_state(rctx
, clip_so_current
);
1880 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1883 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1884 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1885 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1887 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
||
1888 rctx
->cb_misc_state
.ps_color_export_mask
!= rctx
->ps_shader
->current
->ps_color_export_mask
) {
1889 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1890 rctx
->cb_misc_state
.ps_color_export_mask
= rctx
->ps_shader
->current
->ps_color_export_mask
;
1891 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1894 if (rctx
->b
.chip_class
<= R700
) {
1895 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1897 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1898 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1899 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1903 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1904 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1905 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1907 if (rctx
->b
.chip_class
>= EVERGREEN
)
1908 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1910 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1913 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1915 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1917 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1918 evergreen_update_db_shader_control(rctx
);
1920 r600_update_db_shader_control(rctx
);
1923 /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */
1924 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1925 evergreen_setup_scratch_buffers(rctx
);
1927 r600_setup_scratch_buffers(rctx
);
1930 /* on R600 we stuff masks + txq info into one constant buffer */
1931 /* on evergreen we only need a txq info one */
1932 if (rctx
->ps_shader
) {
1933 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1934 if (need_buf_const
) {
1935 if (rctx
->b
.chip_class
< EVERGREEN
)
1936 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1938 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1942 if (rctx
->vs_shader
) {
1943 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1944 if (need_buf_const
) {
1945 if (rctx
->b
.chip_class
< EVERGREEN
)
1946 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1948 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1952 if (rctx
->gs_shader
) {
1953 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1954 if (need_buf_const
) {
1955 if (rctx
->b
.chip_class
< EVERGREEN
)
1956 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1958 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1962 if (rctx
->tes_shader
) {
1963 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1964 need_buf_const
= rctx
->tes_shader
->current
->shader
.uses_tex_buffers
||
1965 rctx
->tes_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1966 if (need_buf_const
) {
1967 eg_setup_buffer_constants(rctx
, PIPE_SHADER_TESS_EVAL
);
1969 if (rctx
->tcs_shader
) {
1970 need_buf_const
= rctx
->tcs_shader
->current
->shader
.uses_tex_buffers
||
1971 rctx
->tcs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1972 if (need_buf_const
) {
1973 eg_setup_buffer_constants(rctx
, PIPE_SHADER_TESS_CTRL
);
1978 r600_update_driver_const_buffers(rctx
, false);
1980 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1981 if (!r600_adjust_gprs(rctx
)) {
1982 /* discard rendering */
1987 if (rctx
->b
.chip_class
== EVERGREEN
) {
1988 if (!evergreen_adjust_gprs(rctx
)) {
1989 /* discard rendering */
1994 blend_disable
= (rctx
->dual_src_blend
&&
1995 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1997 if (blend_disable
!= rctx
->force_blend_disable
) {
1998 rctx
->force_blend_disable
= blend_disable
;
1999 r600_bind_blend_state_internal(rctx
,
2000 rctx
->blend_state
.cso
,
2007 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2009 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2010 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
2012 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
2013 state
->pa_cl_clip_cntl
|
2014 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
2015 S_028810_CLIP_DISABLE(state
->clip_disable
));
2016 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
2017 state
->pa_cl_vs_out_cntl
|
2018 (state
->clip_plane_enable
& state
->clip_dist_write
) |
2019 (state
->cull_dist_write
<< 8));
2020 /* reuse needs to be set off if we write oViewport */
2021 if (rctx
->b
.chip_class
>= EVERGREEN
)
2022 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
2023 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
2026 /* rast_prim is the primitive type after GS. */
2027 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
2029 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2030 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
2032 /* Skip this if not rendering lines. */
2033 if (rast_prim
!= PIPE_PRIM_LINES
&&
2034 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
2035 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
2036 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
2037 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
2040 if (rast_prim
== rctx
->last_rast_prim
)
2043 /* For lines, reset the stipple pattern at each primitive. Otherwise,
2044 * reset the stipple pattern at each packet (line strips, line loops).
2046 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
2047 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
2048 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
2049 rctx
->last_rast_prim
= rast_prim
;
2052 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
2054 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2055 struct pipe_resource
*indexbuf
= info
->has_user_indices
? NULL
: info
->index
.resource
;
2056 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2057 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
2058 bool has_user_indices
= info
->has_user_indices
;
2060 unsigned num_patches
, dirty_tex_counter
, index_offset
= 0;
2061 unsigned index_size
= info
->index_size
;
2063 struct r600_shader_atomic combined_atomics
[8];
2064 uint8_t atomic_used_mask
;
2066 if (!info
->indirect
&& !info
->count
&& (index_size
|| !info
->count_from_stream_output
)) {
2070 if (unlikely(!rctx
->vs_shader
)) {
2074 if (unlikely(!rctx
->ps_shader
&&
2075 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
2080 /* make sure that the gfx ring is only one active */
2081 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
2082 rctx
->b
.dma
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
2085 if (rctx
->cmd_buf_is_compute
) {
2086 rctx
->b
.gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
2087 rctx
->cmd_buf_is_compute
= false;
2090 /* Re-emit the framebuffer state if needed. */
2091 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
2092 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
2093 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
2094 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
2095 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
2098 if (rctx
->gs_shader
) {
2099 /* Determine whether the GS triangle strip adjacency fix should
2100 * be applied. Rotate every other triangle if
2101 * - triangle strips with adjacency are fed to the GS and
2102 * - primitive restart is disabled (the rotation doesn't help
2103 * when the restart occurs after an odd number of triangles).
2105 bool gs_tri_strip_adj_fix
=
2106 !rctx
->tes_shader
&&
2107 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
2108 !info
->primitive_restart
;
2109 if (gs_tri_strip_adj_fix
!= rctx
->gs_tri_strip_adj_fix
)
2110 rctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
2112 if (!r600_update_derived_state(rctx
)) {
2113 /* useless to render because current rendering command
2119 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
2120 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
2123 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2124 evergreen_emit_atomic_buffer_setup_count(rctx
, NULL
, combined_atomics
, &atomic_used_mask
);
2128 index_offset
+= info
->start
* index_size
;
2130 /* Translate 8-bit indices to 16-bit. */
2131 if (unlikely(index_size
== 1)) {
2132 struct pipe_resource
*out_buffer
= NULL
;
2133 unsigned out_offset
;
2135 unsigned start
, count
;
2137 if (likely(!info
->indirect
)) {
2139 count
= info
->count
;
2142 /* Have to get start/count from indirect buffer, slow path ahead... */
2143 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
->buffer
;
2144 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
2145 PIPE_TRANSFER_READ
);
2147 data
+= info
->indirect
->offset
/ sizeof(unsigned);
2148 start
= data
[2] * index_size
;
2157 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
2158 256, &out_offset
, &out_buffer
, &ptr
);
2162 util_shorten_ubyte_elts_to_userptr(
2163 &rctx
->b
.b
, info
, 0, 0, index_offset
, count
, ptr
);
2165 indexbuf
= out_buffer
;
2166 index_offset
= out_offset
;
2168 has_user_indices
= false;
2171 /* Upload the index buffer.
2172 * The upload is skipped for small index counts on little-endian machines
2173 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2174 * Indirect draws never use immediate indices.
2175 * Note: Instanced rendering in combination with immediate indices hangs. */
2176 if (has_user_indices
&& (R600_BIG_ENDIAN
|| info
->indirect
||
2177 info
->instance_count
> 1 ||
2178 info
->count
*index_size
> 20)) {
2180 u_upload_data(ctx
->stream_uploader
, 0,
2181 info
->count
* index_size
, 256,
2182 info
->index
.user
, &index_offset
, &indexbuf
);
2183 has_user_indices
= false;
2185 index_bias
= info
->index_bias
;
2187 index_bias
= info
->start
;
2190 /* Set the index offset and primitive restart. */
2191 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
2192 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
2193 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
2194 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
2195 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
2196 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
2197 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
2198 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
2201 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2202 if (rctx
->b
.chip_class
== R600
) {
2203 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
2204 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
2207 if (rctx
->b
.chip_class
>= EVERGREEN
)
2208 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
2211 r600_need_cs_space(rctx
, has_user_indices
? 5 : 0, TRUE
, util_bitcount(atomic_used_mask
));
2212 r600_flush_emit(rctx
);
2214 mask
= rctx
->dirty_atoms
;
2216 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
2219 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2220 evergreen_emit_atomic_buffer_setup(rctx
, false, combined_atomics
, atomic_used_mask
);
2223 if (rctx
->b
.chip_class
== CAYMAN
) {
2224 /* Copied from radeonsi. */
2225 unsigned primgroup_size
= 128; /* recommended without a GS */
2226 bool ia_switch_on_eop
= false;
2227 bool partial_vs_wave
= false;
2229 if (rctx
->gs_shader
)
2230 primgroup_size
= 64; /* recommended with a GS */
2232 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
2233 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
2234 ia_switch_on_eop
= true;
2237 if (r600_get_strmout_en(&rctx
->b
))
2238 partial_vs_wave
= true;
2240 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
2241 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
2242 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
2243 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
2246 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2247 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
2250 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
2251 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
2254 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2255 * even though it should have no effect on those. */
2256 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
2257 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
2258 unsigned prim
= info
->mode
;
2260 if (rctx
->gs_shader
) {
2261 prim
= rctx
->gs_shader
->gs_output_prim
;
2263 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
2265 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
2266 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
2267 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
2268 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
2270 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
2273 /* Update start instance. */
2274 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
2275 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
2276 rctx
->last_start_instance
= info
->start_instance
;
2279 /* Update the primitive type. */
2280 if (rctx
->last_primitive_type
!= info
->mode
) {
2281 r600_emit_rasterizer_prim_state(rctx
);
2282 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
2283 r600_conv_pipe_prim(info
->mode
));
2285 rctx
->last_primitive_type
= info
->mode
;
2289 if (likely(!info
->indirect
)) {
2290 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2291 radeon_emit(cs
, info
->instance_count
);
2293 uint64_t va
= r600_resource(info
->indirect
->buffer
)->gpu_address
;
2294 assert(rctx
->b
.chip_class
>= EVERGREEN
);
2296 // Invalidate so non-indirect draw calls reset this state
2297 rctx
->vgt_state
.last_draw_was_indirect
= true;
2298 rctx
->last_start_instance
= -1;
2300 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
2301 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
2302 radeon_emit(cs
, va
);
2303 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2305 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2306 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2307 (struct r600_resource
*)info
->indirect
->buffer
,
2309 RADEON_PRIO_DRAW_INDIRECT
));
2313 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2314 radeon_emit(cs
, index_size
== 4 ?
2315 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
2316 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
2318 if (has_user_indices
) {
2319 unsigned size_bytes
= info
->count
*index_size
;
2320 unsigned size_dw
= align(size_bytes
, 4) / 4;
2321 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
2322 radeon_emit(cs
, info
->count
);
2323 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
2324 radeon_emit_array(cs
, info
->index
.user
, size_dw
);
2326 uint64_t va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
2328 if (likely(!info
->indirect
)) {
2329 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
2330 radeon_emit(cs
, va
);
2331 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2332 radeon_emit(cs
, info
->count
);
2333 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2334 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2335 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2336 (struct r600_resource
*)indexbuf
,
2338 RADEON_PRIO_INDEX_BUFFER
));
2341 uint32_t max_size
= (indexbuf
->width0
- index_offset
) / index_size
;
2343 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
2344 radeon_emit(cs
, va
);
2345 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2347 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2348 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2349 (struct r600_resource
*)indexbuf
,
2351 RADEON_PRIO_INDEX_BUFFER
));
2353 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2354 radeon_emit(cs
, max_size
);
2356 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
2357 radeon_emit(cs
, info
->indirect
->offset
);
2358 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2362 if (unlikely(info
->count_from_stream_output
)) {
2363 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
2364 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
2366 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
2368 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
2369 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
2370 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
2371 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
2372 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
2373 radeon_emit(cs
, 0); /* unused */
2375 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2376 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2377 t
->buf_filled_size
, RADEON_USAGE_READ
,
2378 RADEON_PRIO_SO_FILLED_SIZE
));
2381 if (likely(!info
->indirect
)) {
2382 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
2383 radeon_emit(cs
, info
->count
);
2386 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
2387 radeon_emit(cs
, info
->indirect
->offset
);
2389 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2390 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2393 /* SMX returns CONTEXT_DONE too early workaround */
2394 if (rctx
->b
.family
== CHIP_R600
||
2395 rctx
->b
.family
== CHIP_RV610
||
2396 rctx
->b
.family
== CHIP_RV630
||
2397 rctx
->b
.family
== CHIP_RV635
) {
2398 /* if we have gs shader or streamout
2399 we need to do a wait idle after every draw */
2400 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2401 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2405 /* ES ring rolling over at EOP - workaround */
2406 if (rctx
->b
.chip_class
== R600
) {
2407 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2408 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2412 if (rctx
->b
.chip_class
>= EVERGREEN
)
2413 evergreen_emit_atomic_buffer_save(rctx
, false, combined_atomics
, &atomic_used_mask
);
2415 if (rctx
->trace_buf
)
2416 eg_trace_emit(rctx
);
2418 if (rctx
->framebuffer
.do_update_surf_dirtiness
) {
2419 /* Set the depth buffer as dirty. */
2420 if (rctx
->framebuffer
.state
.zsbuf
) {
2421 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2422 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2424 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2426 if (rtex
->surface
.has_stencil
)
2427 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2429 if (rctx
->framebuffer
.compressed_cb_mask
) {
2430 struct pipe_surface
*surf
;
2431 struct r600_texture
*rtex
;
2432 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2435 unsigned i
= u_bit_scan(&mask
);
2436 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2437 rtex
= (struct r600_texture
*)surf
->texture
;
2439 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2443 rctx
->framebuffer
.do_update_surf_dirtiness
= false;
2446 if (index_size
&& indexbuf
!= info
->index
.resource
)
2447 pipe_resource_reference(&indexbuf
, NULL
);
2448 rctx
->b
.num_draw_calls
++;
2451 uint32_t r600_translate_stencil_op(int s_op
)
2454 case PIPE_STENCIL_OP_KEEP
:
2455 return V_028800_STENCIL_KEEP
;
2456 case PIPE_STENCIL_OP_ZERO
:
2457 return V_028800_STENCIL_ZERO
;
2458 case PIPE_STENCIL_OP_REPLACE
:
2459 return V_028800_STENCIL_REPLACE
;
2460 case PIPE_STENCIL_OP_INCR
:
2461 return V_028800_STENCIL_INCR
;
2462 case PIPE_STENCIL_OP_DECR
:
2463 return V_028800_STENCIL_DECR
;
2464 case PIPE_STENCIL_OP_INCR_WRAP
:
2465 return V_028800_STENCIL_INCR_WRAP
;
2466 case PIPE_STENCIL_OP_DECR_WRAP
:
2467 return V_028800_STENCIL_DECR_WRAP
;
2468 case PIPE_STENCIL_OP_INVERT
:
2469 return V_028800_STENCIL_INVERT
;
2471 R600_ERR("Unknown stencil op %d", s_op
);
2478 uint32_t r600_translate_fill(uint32_t func
)
2481 case PIPE_POLYGON_MODE_FILL
:
2483 case PIPE_POLYGON_MODE_LINE
:
2485 case PIPE_POLYGON_MODE_POINT
:
2493 unsigned r600_tex_wrap(unsigned wrap
)
2497 case PIPE_TEX_WRAP_REPEAT
:
2498 return V_03C000_SQ_TEX_WRAP
;
2499 case PIPE_TEX_WRAP_CLAMP
:
2500 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2501 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2502 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2503 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2504 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2505 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2506 return V_03C000_SQ_TEX_MIRROR
;
2507 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2508 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2509 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2510 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2511 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2512 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2516 unsigned r600_tex_mipfilter(unsigned filter
)
2519 case PIPE_TEX_MIPFILTER_NEAREST
:
2520 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2521 case PIPE_TEX_MIPFILTER_LINEAR
:
2522 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2524 case PIPE_TEX_MIPFILTER_NONE
:
2525 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2529 unsigned r600_tex_compare(unsigned compare
)
2533 case PIPE_FUNC_NEVER
:
2534 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2535 case PIPE_FUNC_LESS
:
2536 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2537 case PIPE_FUNC_EQUAL
:
2538 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2539 case PIPE_FUNC_LEQUAL
:
2540 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2541 case PIPE_FUNC_GREATER
:
2542 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2543 case PIPE_FUNC_NOTEQUAL
:
2544 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2545 case PIPE_FUNC_GEQUAL
:
2546 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2547 case PIPE_FUNC_ALWAYS
:
2548 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2552 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2554 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2555 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2557 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2558 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2561 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2563 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2564 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2566 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2567 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2568 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2569 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2570 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2573 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2576 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2577 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2582 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2583 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2584 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2585 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2588 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2589 const unsigned char *swizzle_view
,
2593 unsigned char swizzle
[4];
2594 unsigned result
= 0;
2595 const uint32_t tex_swizzle_shift
[4] = {
2598 const uint32_t vtx_swizzle_shift
[4] = {
2601 const uint32_t swizzle_bit
[4] = {
2604 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2607 swizzle_shift
= vtx_swizzle_shift
;
2610 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2612 memcpy(swizzle
, swizzle_format
, 4);
2616 for (i
= 0; i
< 4; i
++) {
2617 switch (swizzle
[i
]) {
2618 case PIPE_SWIZZLE_Y
:
2619 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2621 case PIPE_SWIZZLE_Z
:
2622 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2624 case PIPE_SWIZZLE_W
:
2625 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2627 case PIPE_SWIZZLE_0
:
2628 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2630 case PIPE_SWIZZLE_1
:
2631 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2633 default: /* PIPE_SWIZZLE_X */
2634 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2640 /* texture format translate */
2641 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2642 enum pipe_format format
,
2643 const unsigned char *swizzle_view
,
2644 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2645 bool do_endian_swap
)
2647 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2648 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2649 const struct util_format_description
*desc
;
2650 boolean uniform
= TRUE
;
2651 bool is_srgb_valid
= FALSE
;
2652 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2653 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2654 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2655 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2656 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2659 const uint32_t sign_bit
[4] = {
2660 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2661 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2662 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2663 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2666 /* Need to replace the specified texture formats in case of big-endian.
2667 * These formats are formats that have channels with number of bits
2668 * not divisible by 8.
2669 * Mesa conversion functions don't swap bits for those formats, and because
2670 * we transmit this over a serial bus to the GPU (PCIe), the
2671 * bit-endianess is important!!!
2672 * In case we have an "opposite" format, just use that for the swizzling
2673 * information. If we don't have such an "opposite" format, we need
2674 * to use a fixed swizzle info instead (see below)
2676 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2677 format
= PIPE_FORMAT_A4R4_UNORM
;
2679 desc
= util_format_description(format
);
2683 /* Depth and stencil swizzling is handled separately. */
2684 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2685 /* Need to check for specific texture formats that don't have
2686 * an "opposite" format we can use. For those formats, we directly
2687 * specify the swizzling, which is the LE swizzling as defined in
2690 if (do_endian_swap
) {
2691 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2692 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2693 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2694 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2695 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2696 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2698 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2700 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2704 /* Colorspace (return non-RGB formats directly). */
2705 switch (desc
->colorspace
) {
2706 /* Depth stencil formats */
2707 case UTIL_FORMAT_COLORSPACE_ZS
:
2709 /* Depth sampler formats. */
2710 case PIPE_FORMAT_Z16_UNORM
:
2711 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2714 case PIPE_FORMAT_Z24X8_UNORM
:
2715 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2716 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2719 case PIPE_FORMAT_X8Z24_UNORM
:
2720 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2721 if (rscreen
->b
.chip_class
< EVERGREEN
)
2723 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2726 case PIPE_FORMAT_Z32_FLOAT
:
2727 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2728 result
= FMT_32_FLOAT
;
2730 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2731 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2732 result
= FMT_X24_8_32_FLOAT
;
2734 /* Stencil sampler formats. */
2735 case PIPE_FORMAT_S8_UINT
:
2736 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2737 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2740 case PIPE_FORMAT_X24S8_UINT
:
2741 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2742 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2745 case PIPE_FORMAT_S8X24_UINT
:
2746 if (rscreen
->b
.chip_class
< EVERGREEN
)
2748 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2749 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2752 case PIPE_FORMAT_X32_S8X24_UINT
:
2753 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2754 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2755 result
= FMT_X24_8_32_FLOAT
;
2761 case UTIL_FORMAT_COLORSPACE_YUV
:
2762 yuv_format
|= (1 << 30);
2764 case PIPE_FORMAT_UYVY
:
2765 case PIPE_FORMAT_YUYV
:
2769 goto out_unknown
; /* XXX */
2771 case UTIL_FORMAT_COLORSPACE_SRGB
:
2772 word4
|= S_038010_FORCE_DEGAMMA(1);
2779 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2781 case PIPE_FORMAT_RGTC1_SNORM
:
2782 case PIPE_FORMAT_LATC1_SNORM
:
2783 word4
|= sign_bit
[0];
2784 case PIPE_FORMAT_RGTC1_UNORM
:
2785 case PIPE_FORMAT_LATC1_UNORM
:
2788 case PIPE_FORMAT_RGTC2_SNORM
:
2789 case PIPE_FORMAT_LATC2_SNORM
:
2790 word4
|= sign_bit
[0] | sign_bit
[1];
2791 case PIPE_FORMAT_RGTC2_UNORM
:
2792 case PIPE_FORMAT_LATC2_UNORM
:
2800 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2802 case PIPE_FORMAT_DXT1_RGB
:
2803 case PIPE_FORMAT_DXT1_RGBA
:
2804 case PIPE_FORMAT_DXT1_SRGB
:
2805 case PIPE_FORMAT_DXT1_SRGBA
:
2807 is_srgb_valid
= TRUE
;
2809 case PIPE_FORMAT_DXT3_RGBA
:
2810 case PIPE_FORMAT_DXT3_SRGBA
:
2812 is_srgb_valid
= TRUE
;
2814 case PIPE_FORMAT_DXT5_RGBA
:
2815 case PIPE_FORMAT_DXT5_SRGBA
:
2817 is_srgb_valid
= TRUE
;
2824 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2825 if (rscreen
->b
.chip_class
< EVERGREEN
)
2829 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2830 case PIPE_FORMAT_BPTC_SRGBA
:
2832 is_srgb_valid
= TRUE
;
2834 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2835 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2837 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2845 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2847 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2848 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2851 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2852 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2860 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2861 result
= FMT_5_9_9_9_SHAREDEXP
;
2863 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2864 result
= FMT_10_11_11_FLOAT
;
2869 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2870 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2871 word4
|= sign_bit
[i
];
2875 /* R8G8Bx_SNORM - XXX CxV8U8 */
2877 /* See whether the components are of the same size. */
2878 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2879 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2882 /* Non-uniform formats. */
2884 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2885 desc
->channel
[0].pure_integer
)
2886 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2887 switch(desc
->nr_channels
) {
2889 if (desc
->channel
[0].size
== 5 &&
2890 desc
->channel
[1].size
== 6 &&
2891 desc
->channel
[2].size
== 5) {
2897 if (desc
->channel
[0].size
== 5 &&
2898 desc
->channel
[1].size
== 5 &&
2899 desc
->channel
[2].size
== 5 &&
2900 desc
->channel
[3].size
== 1) {
2901 result
= FMT_1_5_5_5
;
2904 if (desc
->channel
[0].size
== 10 &&
2905 desc
->channel
[1].size
== 10 &&
2906 desc
->channel
[2].size
== 10 &&
2907 desc
->channel
[3].size
== 2) {
2908 result
= FMT_2_10_10_10
;
2916 /* Find the first non-VOID channel. */
2917 for (i
= 0; i
< 4; i
++) {
2918 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2926 /* uniform formats */
2927 switch (desc
->channel
[i
].type
) {
2928 case UTIL_FORMAT_TYPE_UNSIGNED
:
2929 case UTIL_FORMAT_TYPE_SIGNED
:
2931 if (!desc
->channel
[i
].normalized
&&
2932 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2936 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2937 desc
->channel
[i
].pure_integer
)
2938 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2940 switch (desc
->channel
[i
].size
) {
2942 switch (desc
->nr_channels
) {
2947 result
= FMT_4_4_4_4
;
2952 switch (desc
->nr_channels
) {
2955 is_srgb_valid
= TRUE
;
2961 result
= FMT_8_8_8_8
;
2962 is_srgb_valid
= TRUE
;
2967 switch (desc
->nr_channels
) {
2975 result
= FMT_16_16_16_16
;
2980 switch (desc
->nr_channels
) {
2988 result
= FMT_32_32_32_32
;
2994 case UTIL_FORMAT_TYPE_FLOAT
:
2995 switch (desc
->channel
[i
].size
) {
2997 switch (desc
->nr_channels
) {
2999 result
= FMT_16_FLOAT
;
3002 result
= FMT_16_16_FLOAT
;
3005 result
= FMT_16_16_16_16_FLOAT
;
3010 switch (desc
->nr_channels
) {
3012 result
= FMT_32_FLOAT
;
3015 result
= FMT_32_32_FLOAT
;
3018 result
= FMT_32_32_32_32_FLOAT
;
3027 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
3032 *yuv_format_p
= yuv_format
;
3035 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
3039 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
3040 bool do_endian_swap
)
3042 const struct util_format_description
*desc
= util_format_description(format
);
3043 int channel
= util_format_get_first_non_void_channel(format
);
3048 #define HAS_SIZE(x,y,z,w) \
3049 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
3050 desc->channel[2].size == (z) && desc->channel[3].size == (w))
3052 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
3053 return V_0280A0_COLOR_10_11_11_FLOAT
;
3055 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
3059 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
3061 switch (desc
->nr_channels
) {
3063 switch (desc
->channel
[0].size
) {
3065 return V_0280A0_COLOR_8
;
3068 return V_0280A0_COLOR_16_FLOAT
;
3070 return V_0280A0_COLOR_16
;
3073 return V_0280A0_COLOR_32_FLOAT
;
3075 return V_0280A0_COLOR_32
;
3079 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
3080 switch (desc
->channel
[0].size
) {
3083 return V_0280A0_COLOR_4_4
;
3085 return ~0U; /* removed on Evergreen */
3087 return V_0280A0_COLOR_8_8
;
3090 return V_0280A0_COLOR_16_16_FLOAT
;
3092 return V_0280A0_COLOR_16_16
;
3095 return V_0280A0_COLOR_32_32_FLOAT
;
3097 return V_0280A0_COLOR_32_32
;
3099 } else if (HAS_SIZE(8,24,0,0)) {
3100 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
3101 } else if (HAS_SIZE(24,8,0,0)) {
3102 return V_0280A0_COLOR_8_24
;
3106 if (HAS_SIZE(5,6,5,0)) {
3107 return V_0280A0_COLOR_5_6_5
;
3108 } else if (HAS_SIZE(32,8,24,0)) {
3109 return V_0280A0_COLOR_X24_8_32_FLOAT
;
3113 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
3114 desc
->channel
[0].size
== desc
->channel
[2].size
&&
3115 desc
->channel
[0].size
== desc
->channel
[3].size
) {
3116 switch (desc
->channel
[0].size
) {
3118 return V_0280A0_COLOR_4_4_4_4
;
3120 return V_0280A0_COLOR_8_8_8_8
;
3123 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
3125 return V_0280A0_COLOR_16_16_16_16
;
3128 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
3130 return V_0280A0_COLOR_32_32_32_32
;
3132 } else if (HAS_SIZE(5,5,5,1)) {
3133 return V_0280A0_COLOR_1_5_5_5
;
3134 } else if (HAS_SIZE(10,10,10,2)) {
3135 return V_0280A0_COLOR_2_10_10_10
;
3142 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
3144 if (R600_BIG_ENDIAN
) {
3145 switch(colorformat
) {
3146 /* 8-bit buffers. */
3147 case V_0280A0_COLOR_4_4
:
3148 case V_0280A0_COLOR_8
:
3151 /* 16-bit buffers. */
3152 case V_0280A0_COLOR_8_8
:
3154 * No need to do endian swaps on array formats,
3155 * as mesa<-->pipe formats conversion take into account
3160 case V_0280A0_COLOR_5_6_5
:
3161 case V_0280A0_COLOR_1_5_5_5
:
3162 case V_0280A0_COLOR_4_4_4_4
:
3163 case V_0280A0_COLOR_16
:
3164 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
3166 /* 32-bit buffers. */
3167 case V_0280A0_COLOR_8_8_8_8
:
3169 * No need to do endian swaps on array formats,
3170 * as mesa<-->pipe formats conversion take into account
3175 case V_0280A0_COLOR_2_10_10_10
:
3176 case V_0280A0_COLOR_8_24
:
3177 case V_0280A0_COLOR_24_8
:
3178 case V_0280A0_COLOR_32_FLOAT
:
3179 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
3181 case V_0280A0_COLOR_16_16_FLOAT
:
3182 case V_0280A0_COLOR_16_16
:
3183 return ENDIAN_8IN16
;
3185 /* 64-bit buffers. */
3186 case V_0280A0_COLOR_16_16_16_16
:
3187 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
3188 return ENDIAN_8IN16
;
3190 case V_0280A0_COLOR_32_32_FLOAT
:
3191 case V_0280A0_COLOR_32_32
:
3192 case V_0280A0_COLOR_X24_8_32_FLOAT
:
3193 return ENDIAN_8IN32
;
3195 /* 128-bit buffers. */
3196 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
3197 case V_0280A0_COLOR_32_32_32_32
:
3198 return ENDIAN_8IN32
;
3200 return ENDIAN_NONE
; /* Unsupported. */
3207 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
3209 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3210 struct r600_resource
*rbuffer
= r600_resource(buf
);
3211 unsigned i
, shader
, mask
;
3212 struct r600_pipe_sampler_view
*view
;
3214 /* Reallocate the buffer in the same pipe_resource. */
3215 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
3217 /* We changed the buffer, now we need to bind it where the old one was bound. */
3218 /* Vertex buffers. */
3219 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
3221 i
= u_bit_scan(&mask
);
3222 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
.resource
== &rbuffer
->b
.b
) {
3223 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
3224 r600_vertex_buffers_dirty(rctx
);
3227 /* Streamout buffers. */
3228 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
3229 if (rctx
->b
.streamout
.targets
[i
] &&
3230 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
3231 if (rctx
->b
.streamout
.begin_emitted
) {
3232 r600_emit_streamout_end(&rctx
->b
);
3234 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
3235 r600_streamout_buffers_dirty(&rctx
->b
);
3239 /* Constant buffers. */
3240 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3241 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
3243 uint32_t mask
= state
->enabled_mask
;
3246 unsigned i
= u_bit_scan(&mask
);
3247 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
3249 state
->dirty_mask
|= 1 << i
;
3253 r600_constant_buffers_dirty(rctx
, state
);
3257 /* Texture buffer objects - update the virtual addresses in descriptors. */
3258 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
3259 if (view
->base
.texture
== &rbuffer
->b
.b
) {
3260 uint64_t offset
= view
->base
.u
.buf
.offset
;
3261 uint64_t va
= rbuffer
->gpu_address
+ offset
;
3263 view
->tex_resource_words
[0] = va
;
3264 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
3265 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
3268 /* Texture buffer objects - make bindings dirty if needed. */
3269 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3270 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
3272 uint32_t mask
= state
->enabled_mask
;
3275 unsigned i
= u_bit_scan(&mask
);
3276 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
3278 state
->dirty_mask
|= 1 << i
;
3282 r600_sampler_views_dirty(rctx
, state
);
3287 struct r600_image_state
*istate
= &rctx
->fragment_buffers
;
3289 uint32_t mask
= istate
->enabled_mask
;
3292 unsigned i
= u_bit_scan(&mask
);
3293 if (istate
->views
[i
].base
.resource
== &rbuffer
->b
.b
) {
3295 istate
->dirty_mask
|= 1 << i
;
3299 r600_mark_atom_dirty(rctx
, &istate
->atom
);
3305 static void r600_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
3307 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3309 /* Pipeline stat & streamout queries. */
3311 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
3312 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
3314 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
3315 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
3318 /* Occlusion queries. */
3319 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
3320 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
3321 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3325 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3326 bool include_draw_vbo
)
3328 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
, 0);
3331 /* keep this at the end of this file, please */
3332 void r600_init_common_state_functions(struct r600_context
*rctx
)
3334 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
3335 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
3336 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
3337 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
3338 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
3339 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
3340 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
3341 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
3342 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
3343 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
3344 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
3345 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
3346 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
3347 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
3348 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
3349 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
3350 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
3351 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
3352 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
3353 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
3354 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
3355 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
3356 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
3357 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
3358 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
3359 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
3360 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
3361 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
3362 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
3363 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
3364 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
3365 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
3366 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
3367 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
3368 rctx
->b
.b
.memory_barrier
= r600_memory_barrier
;
3369 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
3370 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
3371 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
3373 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
3374 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
3375 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;