projects / mesa.git / blob
? search:


1d9ff7bd6e7305c2a4d773d4c1e189adbf1dd7df
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 assert(!cb->buf);
43 cb->buf = CALLOC(1, 4 * num_dw);
44 cb->max_num_dw = num_dw;
45 }
46
47 void r600_release_command_buffer(struct r600_command_buffer *cb)
48 {
49 FREE(cb->buf);
50 }
51
52 void r600_add_atom(struct r600_context *rctx,
53 struct r600_atom *atom,
54 unsigned id)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->id = id;
60 }
61
62 void r600_init_atom(struct r600_context *rctx,
63 struct r600_atom *atom,
64 unsigned id,
65 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
66 unsigned num_dw)
67 {
68 atom->emit = (void*)emit;
69 atom->num_dw = num_dw;
70 r600_add_atom(rctx, atom, id);
71 }
72
73 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 r600_emit_command_buffer(rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
76 }
77
78 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
79 {
80 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
81 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
82 unsigned alpha_ref = a->sx_alpha_ref;
83
84 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
85 alpha_ref &= ~0x1FFF;
86 }
87
88 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
89 a->sx_alpha_test_control |
90 S_028410_ALPHA_TEST_BYPASS(a->bypass));
91 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
92 }
93
94 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
95 {
96 struct r600_context *rctx = (struct r600_context *)ctx;
97 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
98 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
99
100 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
101 PIPE_BARRIER_SHADER_BUFFER |
102 PIPE_BARRIER_TEXTURE |
103 PIPE_BARRIER_IMAGE |
104 PIPE_BARRIER_STREAMOUT_BUFFER |
105 PIPE_BARRIER_GLOBAL_BUFFER)) {
106 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
107 R600_CONTEXT_INV_TEX_CACHE;
108 }
109
110 if (flags & (PIPE_BARRIER_FRAMEBUFFER|
111 PIPE_BARRIER_IMAGE))
112 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
113
114 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
115 }
116
117 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 struct r600_context *rctx = (struct r600_context *)ctx;
120
121 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
122 R600_CONTEXT_FLUSH_AND_INV_CB |
123 R600_CONTEXT_FLUSH_AND_INV |
124 R600_CONTEXT_WAIT_3D_IDLE;
125 rctx->framebuffer.do_update_surf_dirtiness = true;
126 }
127
128 static unsigned r600_conv_pipe_prim(unsigned prim)
129 {
130 static const unsigned prim_conv[] = {
131 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
132 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
133 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
134 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
135 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
136 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
137 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
138 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
139 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
140 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
141 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
145 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
146 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
147 };
148 assert(prim < ARRAY_SIZE(prim_conv));
149 return prim_conv[prim];
150 }
151
152 unsigned r600_conv_prim_to_gs_out(unsigned mode)
153 {
154 static const int prim_conv[] = {
155 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
156 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
157 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
158 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
159 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
160 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
161 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
162 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
163 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
164 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
165 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
166 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
167 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
168 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
169 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
170 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
171 };
172 assert(mode < ARRAY_SIZE(prim_conv));
173
174 return prim_conv[mode];
175 }
176
177 /* common state between evergreen and r600 */
178
179 static void r600_bind_blend_state_internal(struct r600_context *rctx,
180 struct r600_blend_state *blend, bool blend_disable)
181 {
182 unsigned color_control;
183 bool update_cb = false;
184
185 rctx->alpha_to_one = blend->alpha_to_one;
186 rctx->dual_src_blend = blend->dual_src_blend;
187
188 if (!blend_disable) {
189 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
190 color_control = blend->cb_color_control;
191 } else {
192 /* Blending is disabled. */
193 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
194 color_control = blend->cb_color_control_no_blend;
195 }
196
197 /* Update derived states. */
198 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
199 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
200 update_cb = true;
201 }
202 if (rctx->b.chip_class <= R700 &&
203 rctx->cb_misc_state.cb_color_control != color_control) {
204 rctx->cb_misc_state.cb_color_control = color_control;
205 update_cb = true;
206 }
207 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
208 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
209 update_cb = true;
210 }
211 if (update_cb) {
212 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
213 }
214 if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) {
215 rctx->framebuffer.dual_src_blend = blend->dual_src_blend;
216 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
217 }
218 }
219
220 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
221 {
222 struct r600_context *rctx = (struct r600_context *)ctx;
223 struct r600_blend_state *blend = (struct r600_blend_state *)state;
224
225 if (!blend) {
226 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
227 return;
228 }
229
230 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
231 }
232
233 static void r600_set_blend_color(struct pipe_context *ctx,
234 const struct pipe_blend_color *state)
235 {
236 struct r600_context *rctx = (struct r600_context *)ctx;
237
238 rctx->blend_color.state = *state;
239 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
240 }
241
242 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
243 {
244 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
245 struct pipe_blend_color *state = &rctx->blend_color.state;
246
247 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
248 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
249 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
250 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
251 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
252 }
253
254 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
255 {
256 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
257 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
258
259 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
260 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
261 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
262 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
263 if (a->last_draw_was_indirect) {
264 a->last_draw_was_indirect = false;
265 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
266 }
267 }
268
269 static void r600_set_clip_state(struct pipe_context *ctx,
270 const struct pipe_clip_state *state)
271 {
272 struct r600_context *rctx = (struct r600_context *)ctx;
273
274 rctx->clip_state.state = *state;
275 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
276 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
277 }
278
279 static void r600_set_stencil_ref(struct pipe_context *ctx,
280 const struct r600_stencil_ref *state)
281 {
282 struct r600_context *rctx = (struct r600_context *)ctx;
283
284 rctx->stencil_ref.state = *state;
285 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
286 }
287
288 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
289 {
290 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
291 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
292
293 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
294 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
295 S_028430_STENCILREF(a->state.ref_value[0]) |
296 S_028430_STENCILMASK(a->state.valuemask[0]) |
297 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
298 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
299 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
300 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
301 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
302 }
303
304 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
305 const struct pipe_stencil_ref *state)
306 {
307 struct r600_context *rctx = (struct r600_context *)ctx;
308 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
309 struct r600_stencil_ref ref;
310
311 rctx->stencil_ref.pipe_state = *state;
312
313 if (!dsa)
314 return;
315
316 ref.ref_value[0] = state->ref_value[0];
317 ref.ref_value[1] = state->ref_value[1];
318 ref.valuemask[0] = dsa->valuemask[0];
319 ref.valuemask[1] = dsa->valuemask[1];
320 ref.writemask[0] = dsa->writemask[0];
321 ref.writemask[1] = dsa->writemask[1];
322
323 r600_set_stencil_ref(ctx, &ref);
324 }
325
326 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
327 {
328 struct r600_context *rctx = (struct r600_context *)ctx;
329 struct r600_dsa_state *dsa = state;
330 struct r600_stencil_ref ref;
331
332 if (!state) {
333 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
334 return;
335 }
336
337 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
338
339 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
340 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
341 ref.valuemask[0] = dsa->valuemask[0];
342 ref.valuemask[1] = dsa->valuemask[1];
343 ref.writemask[0] = dsa->writemask[0];
344 ref.writemask[1] = dsa->writemask[1];
345 if (rctx->zwritemask != dsa->zwritemask) {
346 rctx->zwritemask = dsa->zwritemask;
347 if (rctx->b.chip_class >= EVERGREEN) {
348 /* work around some issue when not writing to zbuffer
349 * we are having lockup on evergreen so do not enable
350 * hyperz when not writing zbuffer
351 */
352 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
353 }
354 }
355
356 r600_set_stencil_ref(ctx, &ref);
357
358 /* Update alphatest state. */
359 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
360 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
361 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
362 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
363 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
364 }
365 }
366
367 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
368 {
369 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
370 struct r600_context *rctx = (struct r600_context *)ctx;
371
372 if (!state)
373 return;
374
375 rctx->rasterizer = rs;
376
377 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
378
379 if (rs->offset_enable &&
380 (rs->offset_units != rctx->poly_offset_state.offset_units ||
381 rs->offset_scale != rctx->poly_offset_state.offset_scale ||
382 rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
383 rctx->poly_offset_state.offset_units = rs->offset_units;
384 rctx->poly_offset_state.offset_scale = rs->offset_scale;
385 rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
386 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
387 }
388
389 /* Update clip_misc_state. */
390 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
391 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
392 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
393 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
394 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
395 }
396
397 r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
398
399 /* Re-emit PA_SC_LINE_STIPPLE. */
400 rctx->last_primitive_type = -1;
401 }
402
403 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
404 {
405 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
406
407 r600_release_command_buffer(&rs->buffer);
408 FREE(rs);
409 }
410
411 static void r600_sampler_view_destroy(struct pipe_context *ctx,
412 struct pipe_sampler_view *state)
413 {
414 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
415
416 if (view->tex_resource->gpu_address &&
417 view->tex_resource->b.b.target == PIPE_BUFFER)
418 LIST_DELINIT(&view->list);
419
420 pipe_resource_reference(&state->texture, NULL);
421 FREE(view);
422 }
423
424 void r600_sampler_states_dirty(struct r600_context *rctx,
425 struct r600_sampler_states *state)
426 {
427 if (state->dirty_mask) {
428 if (state->dirty_mask & state->has_bordercolor_mask) {
429 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
430 }
431 state->atom.num_dw =
432 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
433 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
434 r600_mark_atom_dirty(rctx, &state->atom);
435 }
436 }
437
438 static void r600_bind_sampler_states(struct pipe_context *pipe,
439 enum pipe_shader_type shader,
440 unsigned start,
441 unsigned count, void **states)
442 {
443 struct r600_context *rctx = (struct r600_context *)pipe;
444 struct r600_textures_info *dst = &rctx->samplers[shader];
445 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
446 int seamless_cube_map = -1;
447 unsigned i;
448 /* This sets 1-bit for states with index >= count. */
449 uint32_t disable_mask = ~((1ull << count) - 1);
450 /* These are the new states set by this function. */
451 uint32_t new_mask = 0;
452
453 assert(start == 0); /* XXX fix below */
454
455 if (!states) {
456 disable_mask = ~0u;
457 count = 0;
458 }
459
460 for (i = 0; i < count; i++) {
461 struct r600_pipe_sampler_state *rstate = rstates[i];
462
463 if (rstate == dst->states.states[i]) {
464 continue;
465 }
466
467 if (rstate) {
468 if (rstate->border_color_use) {
469 dst->states.has_bordercolor_mask |= 1 << i;
470 } else {
471 dst->states.has_bordercolor_mask &= ~(1 << i);
472 }
473 seamless_cube_map = rstate->seamless_cube_map;
474
475 new_mask |= 1 << i;
476 } else {
477 disable_mask |= 1 << i;
478 }
479 }
480
481 memcpy(dst->states.states, rstates, sizeof(void*) * count);
482 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
483
484 dst->states.enabled_mask &= ~disable_mask;
485 dst->states.dirty_mask &= dst->states.enabled_mask;
486 dst->states.enabled_mask |= new_mask;
487 dst->states.dirty_mask |= new_mask;
488 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
489
490 r600_sampler_states_dirty(rctx, &dst->states);
491
492 /* Seamless cubemap state. */
493 if (rctx->b.chip_class <= R700 &&
494 seamless_cube_map != -1 &&
495 seamless_cube_map != rctx->seamless_cube_map.enabled) {
496 /* change in TA_CNTL_AUX need a pipeline flush */
497 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
498 rctx->seamless_cube_map.enabled = seamless_cube_map;
499 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
500 }
501 }
502
503 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
504 {
505 free(state);
506 }
507
508 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
509 {
510 struct r600_context *rctx = (struct r600_context *)ctx;
511 struct r600_blend_state *blend = (struct r600_blend_state*)state;
512
513 if (rctx->blend_state.cso == state) {
514 ctx->bind_blend_state(ctx, NULL);
515 }
516
517 r600_release_command_buffer(&blend->buffer);
518 r600_release_command_buffer(&blend->buffer_no_blend);
519 FREE(blend);
520 }
521
522 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
523 {
524 struct r600_context *rctx = (struct r600_context *)ctx;
525 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
526
527 if (rctx->dsa_state.cso == state) {
528 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
529 }
530
531 r600_release_command_buffer(&dsa->buffer);
532 free(dsa);
533 }
534
535 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
536 {
537 struct r600_context *rctx = (struct r600_context *)ctx;
538
539 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
540 }
541
542 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
543 {
544 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
545 r600_resource_reference(&shader->buffer, NULL);
546 FREE(shader);
547 }
548
549 void r600_vertex_buffers_dirty(struct r600_context *rctx)
550 {
551 if (rctx->vertex_buffer_state.dirty_mask) {
552 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
553 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
554 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
555 }
556 }
557
558 static void r600_set_vertex_buffers(struct pipe_context *ctx,
559 unsigned start_slot, unsigned count,
560 const struct pipe_vertex_buffer *input)
561 {
562 struct r600_context *rctx = (struct r600_context *)ctx;
563 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
564 struct pipe_vertex_buffer *vb = state->vb + start_slot;
565 unsigned i;
566 uint32_t disable_mask = 0;
567 /* These are the new buffers set by this function. */
568 uint32_t new_buffer_mask = 0;
569
570 /* Set vertex buffers. */
571 if (input) {
572 for (i = 0; i < count; i++) {
573 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
574 if (input[i].buffer.resource) {
575 vb[i].stride = input[i].stride;
576 vb[i].buffer_offset = input[i].buffer_offset;
577 pipe_resource_reference(&vb[i].buffer.resource, input[i].buffer.resource);
578 new_buffer_mask |= 1 << i;
579 r600_context_add_resource_size(ctx, input[i].buffer.resource);
580 } else {
581 pipe_resource_reference(&vb[i].buffer.resource, NULL);
582 disable_mask |= 1 << i;
583 }
584 }
585 }
586 } else {
587 for (i = 0; i < count; i++) {
588 pipe_resource_reference(&vb[i].buffer.resource, NULL);
589 }
590 disable_mask = ((1ull << count) - 1);
591 }
592
593 disable_mask <<= start_slot;
594 new_buffer_mask <<= start_slot;
595
596 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
597 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
598 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
599 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
600
601 r600_vertex_buffers_dirty(rctx);
602 }
603
604 void r600_sampler_views_dirty(struct r600_context *rctx,
605 struct r600_samplerview_state *state)
606 {
607 if (state->dirty_mask) {
608 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
609 util_bitcount(state->dirty_mask);
610 r600_mark_atom_dirty(rctx, &state->atom);
611 }
612 }
613
614 static void r600_set_sampler_views(struct pipe_context *pipe,
615 enum pipe_shader_type shader,
616 unsigned start, unsigned count,
617 struct pipe_sampler_view **views)
618 {
619 struct r600_context *rctx = (struct r600_context *) pipe;
620 struct r600_textures_info *dst = &rctx->samplers[shader];
621 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
622 uint32_t dirty_sampler_states_mask = 0;
623 unsigned i;
624 /* This sets 1-bit for textures with index >= count. */
625 uint32_t disable_mask = ~((1ull << count) - 1);
626 /* These are the new textures set by this function. */
627 uint32_t new_mask = 0;
628
629 /* Set textures with index >= count to NULL. */
630 uint32_t remaining_mask;
631
632 assert(start == 0); /* XXX fix below */
633
634 if (!views) {
635 disable_mask = ~0u;
636 count = 0;
637 }
638
639 remaining_mask = dst->views.enabled_mask & disable_mask;
640
641 while (remaining_mask) {
642 i = u_bit_scan(&remaining_mask);
643 assert(dst->views.views[i]);
644
645 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
646 }
647
648 for (i = 0; i < count; i++) {
649 if (rviews[i] == dst->views.views[i]) {
650 continue;
651 }
652
653 if (rviews[i]) {
654 struct r600_texture *rtex =
655 (struct r600_texture*)rviews[i]->base.texture;
656 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
657
658 if (!is_buffer && rtex->db_compatible) {
659 dst->views.compressed_depthtex_mask |= 1 << i;
660 } else {
661 dst->views.compressed_depthtex_mask &= ~(1 << i);
662 }
663
664 /* Track compressed colorbuffers. */
665 if (!is_buffer && rtex->cmask.size) {
666 dst->views.compressed_colortex_mask |= 1 << i;
667 } else {
668 dst->views.compressed_colortex_mask &= ~(1 << i);
669 }
670
671 /* Changing from array to non-arrays textures and vice versa requires
672 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
673 if (rctx->b.chip_class <= R700 &&
674 (dst->states.enabled_mask & (1 << i)) &&
675 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
676 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
677 dirty_sampler_states_mask |= 1 << i;
678 }
679
680 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
681 new_mask |= 1 << i;
682 r600_context_add_resource_size(pipe, views[i]->texture);
683 } else {
684 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
685 disable_mask |= 1 << i;
686 }
687 }
688
689 dst->views.enabled_mask &= ~disable_mask;
690 dst->views.dirty_mask &= dst->views.enabled_mask;
691 dst->views.enabled_mask |= new_mask;
692 dst->views.dirty_mask |= new_mask;
693 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
694 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
695 dst->views.dirty_buffer_constants = TRUE;
696 r600_sampler_views_dirty(rctx, &dst->views);
697
698 if (dirty_sampler_states_mask) {
699 dst->states.dirty_mask |= dirty_sampler_states_mask;
700 r600_sampler_states_dirty(rctx, &dst->states);
701 }
702 }
703
704 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
705 {
706 uint32_t mask = views->enabled_mask;
707
708 while (mask) {
709 unsigned i = u_bit_scan(&mask);
710 struct pipe_resource *res = views->views[i]->base.texture;
711
712 if (res && res->target != PIPE_BUFFER) {
713 struct r600_texture *rtex = (struct r600_texture *)res;
714
715 if (rtex->cmask.size) {
716 views->compressed_colortex_mask |= 1 << i;
717 } else {
718 views->compressed_colortex_mask &= ~(1 << i);
719 }
720 }
721 }
722 }
723
724 static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
725 enum pipe_shader_type shader)
726 {
727 const struct r600_context *rctx = (struct r600_context *)ctx;
728 int value = 0;
729 switch (shader) {
730 case PIPE_SHADER_FRAGMENT:
731 case PIPE_SHADER_COMPUTE:
732 default:
733 break;
734 case PIPE_SHADER_VERTEX:
735 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
736 break;
737 case PIPE_SHADER_GEOMETRY:
738 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
739 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
740 break;
741 case PIPE_SHADER_TESS_EVAL:
742 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
743 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
744 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0);
745 break;
746 case PIPE_SHADER_TESS_CTRL:
747 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
748 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
749 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0) +
750 rctx->tes_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
751 break;
752 }
753 return value;
754 }
755
756 static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
757 {
758 uint32_t mask = images->enabled_mask;
759
760 while (mask) {
761 unsigned i = u_bit_scan(&mask);
762 struct pipe_resource *res = images->views[i].base.resource;
763
764 if (res && res->target != PIPE_BUFFER) {
765 struct r600_texture *rtex = (struct r600_texture *)res;
766
767 if (rtex->cmask.size) {
768 images->compressed_colortex_mask |= 1 << i;
769 } else {
770 images->compressed_colortex_mask &= ~(1 << i);
771 }
772 }
773 }
774 }
775
776 /* Compute the key for the hw shader variant */
777 static inline void r600_shader_selector_key(const struct pipe_context *ctx,
778 const struct r600_pipe_shader_selector *sel,
779 union r600_shader_key *key)
780 {
781 const struct r600_context *rctx = (struct r600_context *)ctx;
782 memset(key, 0, sizeof(*key));
783
784 switch (sel->type) {
785 case PIPE_SHADER_VERTEX: {
786 key->vs.as_ls = (rctx->tes_shader != NULL);
787 if (!key->vs.as_ls)
788 key->vs.as_es = (rctx->gs_shader != NULL);
789
790 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
791 key->vs.as_gs_a = true;
792 key->vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
793 }
794 key->vs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_VERTEX);
795 break;
796 }
797 case PIPE_SHADER_GEOMETRY:
798 key->gs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_GEOMETRY);
799 key->gs.tri_strip_adj_fix = rctx->gs_tri_strip_adj_fix;
800 break;
801 case PIPE_SHADER_FRAGMENT: {
802 if (rctx->ps_shader->info.images_declared)
803 key->ps.image_size_const_offset = util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask);
804 key->ps.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_FRAGMENT);
805 key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
806 key->ps.alpha_to_one = rctx->alpha_to_one &&
807 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
808 !rctx->framebuffer.cb0_is_integer;
809 key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
810 /* Dual-source blending only makes sense with nr_cbufs == 1. */
811 if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend)
812 key->ps.nr_cbufs = 2;
813 break;
814 }
815 case PIPE_SHADER_TESS_EVAL:
816 key->tes.as_es = (rctx->gs_shader != NULL);
817 key->tes.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_EVAL);
818 break;
819 case PIPE_SHADER_TESS_CTRL:
820 key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
821 key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_CTRL);
822 break;
823 case PIPE_SHADER_COMPUTE:
824 break;
825 default:
826 assert(0);
827 }
828 }
829
830 /* Select the hw shader variant depending on the current state.
831 * (*dirty) is set to 1 if current variant was changed */
832 int r600_shader_select(struct pipe_context *ctx,
833 struct r600_pipe_shader_selector* sel,
834 bool *dirty)
835 {
836 union r600_shader_key key;
837 struct r600_pipe_shader * shader = NULL;
838 int r;
839
840 r600_shader_selector_key(ctx, sel, &key);
841
842 /* Check if we don't need to change anything.
843 * This path is also used for most shaders that don't need multiple
844 * variants, it will cost just a computation of the key and this
845 * test. */
846 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
847 return 0;
848 }
849
850 /* lookup if we have other variants in the list */
851 if (sel->num_shaders > 1) {
852 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
853
854 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
855 p = c;
856 c = c->next_variant;
857 }
858
859 if (c) {
860 p->next_variant = c->next_variant;
861 shader = c;
862 }
863 }
864
865 if (unlikely(!shader)) {
866 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
867 shader->selector = sel;
868
869 r = r600_pipe_shader_create(ctx, shader, key);
870 if (unlikely(r)) {
871 R600_ERR("Failed to build shader variant (type=%u) %d\n",
872 sel->type, r);
873 sel->current = NULL;
874 FREE(shader);
875 return r;
876 }
877
878 /* We don't know the value of nr_ps_max_color_exports until we built
879 * at least one variant, so we may need to recompute the key after
880 * building first variant. */
881 if (sel->type == PIPE_SHADER_FRAGMENT &&
882 sel->num_shaders == 0) {
883 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
884 r600_shader_selector_key(ctx, sel, &key);
885 }
886
887 memcpy(&shader->key, &key, sizeof(key));
888 sel->num_shaders++;
889 }
890
891 if (dirty)
892 *dirty = true;
893
894 shader->next_variant = sel->current;
895 sel->current = shader;
896
897 return 0;
898 }
899
900 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
901 const struct tgsi_token *tokens,
902 unsigned pipe_shader_type)
903 {
904 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
905
906 sel->type = pipe_shader_type;
907 sel->tokens = tgsi_dup_tokens(tokens);
908 tgsi_scan_shader(tokens, &sel->info);
909 return sel;
910 }
911
912 static void *r600_create_shader_state(struct pipe_context *ctx,
913 const struct pipe_shader_state *state,
914 unsigned pipe_shader_type)
915 {
916 int i;
917 struct r600_pipe_shader_selector *sel = r600_create_shader_state_tokens(ctx, state->tokens, pipe_shader_type);
918
919 sel->so = state->stream_output;
920
921 switch (pipe_shader_type) {
922 case PIPE_SHADER_GEOMETRY:
923 sel->gs_output_prim =
924 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
925 sel->gs_max_out_vertices =
926 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
927 sel->gs_num_invocations =
928 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
929 break;
930 case PIPE_SHADER_VERTEX:
931 case PIPE_SHADER_TESS_CTRL:
932 sel->lds_patch_outputs_written_mask = 0;
933 sel->lds_outputs_written_mask = 0;
934
935 for (i = 0; i < sel->info.num_outputs; i++) {
936 unsigned name = sel->info.output_semantic_name[i];
937 unsigned index = sel->info.output_semantic_index[i];
938
939 switch (name) {
940 case TGSI_SEMANTIC_TESSINNER:
941 case TGSI_SEMANTIC_TESSOUTER:
942 case TGSI_SEMANTIC_PATCH:
943 sel->lds_patch_outputs_written_mask |=
944 1ull << r600_get_lds_unique_index(name, index);
945 break;
946 default:
947 sel->lds_outputs_written_mask |=
948 1ull << r600_get_lds_unique_index(name, index);
949 }
950 }
951 break;
952 default:
953 break;
954 }
955
956 return sel;
957 }
958
959 static void *r600_create_ps_state(struct pipe_context *ctx,
960 const struct pipe_shader_state *state)
961 {
962 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
963 }
964
965 static void *r600_create_vs_state(struct pipe_context *ctx,
966 const struct pipe_shader_state *state)
967 {
968 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
969 }
970
971 static void *r600_create_gs_state(struct pipe_context *ctx,
972 const struct pipe_shader_state *state)
973 {
974 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
975 }
976
977 static void *r600_create_tcs_state(struct pipe_context *ctx,
978 const struct pipe_shader_state *state)
979 {
980 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
981 }
982
983 static void *r600_create_tes_state(struct pipe_context *ctx,
984 const struct pipe_shader_state *state)
985 {
986 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
987 }
988
989 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
990 {
991 struct r600_context *rctx = (struct r600_context *)ctx;
992
993 if (!state)
994 state = rctx->dummy_pixel_shader;
995
996 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
997 }
998
999 static struct tgsi_shader_info *r600_get_vs_info(struct r600_context *rctx)
1000 {
1001 if (rctx->gs_shader)
1002 return &rctx->gs_shader->info;
1003 else if (rctx->tes_shader)
1004 return &rctx->tes_shader->info;
1005 else if (rctx->vs_shader)
1006 return &rctx->vs_shader->info;
1007 else
1008 return NULL;
1009 }
1010
1011 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
1012 {
1013 struct r600_context *rctx = (struct r600_context *)ctx;
1014
1015 if (!state || rctx->vs_shader == state)
1016 return;
1017
1018 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
1019 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1020 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
1021 }
1022
1023 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
1024 {
1025 struct r600_context *rctx = (struct r600_context *)ctx;
1026
1027 if (state == rctx->gs_shader)
1028 return;
1029
1030 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
1031 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1032
1033 if (!state)
1034 return;
1035 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
1036 }
1037
1038 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
1039 {
1040 struct r600_context *rctx = (struct r600_context *)ctx;
1041
1042 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
1043 }
1044
1045 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
1046 {
1047 struct r600_context *rctx = (struct r600_context *)ctx;
1048
1049 if (state == rctx->tes_shader)
1050 return;
1051
1052 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
1053 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1054
1055 if (!state)
1056 return;
1057 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1058 }
1059
1060 void r600_delete_shader_selector(struct pipe_context *ctx,
1061 struct r600_pipe_shader_selector *sel)
1062 {
1063 struct r600_pipe_shader *p = sel->current, *c;
1064 while (p) {
1065 c = p->next_variant;
1066 r600_pipe_shader_destroy(ctx, p);
1067 free(p);
1068 p = c;
1069 }
1070
1071 free(sel->tokens);
1072 free(sel);
1073 }
1074
1075
1076 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1077 {
1078 struct r600_context *rctx = (struct r600_context *)ctx;
1079 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1080
1081 if (rctx->ps_shader == sel) {
1082 rctx->ps_shader = NULL;
1083 }
1084
1085 r600_delete_shader_selector(ctx, sel);
1086 }
1087
1088 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1089 {
1090 struct r600_context *rctx = (struct r600_context *)ctx;
1091 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1092
1093 if (rctx->vs_shader == sel) {
1094 rctx->vs_shader = NULL;
1095 }
1096
1097 r600_delete_shader_selector(ctx, sel);
1098 }
1099
1100
1101 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1102 {
1103 struct r600_context *rctx = (struct r600_context *)ctx;
1104 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1105
1106 if (rctx->gs_shader == sel) {
1107 rctx->gs_shader = NULL;
1108 }
1109
1110 r600_delete_shader_selector(ctx, sel);
1111 }
1112
1113 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1114 {
1115 struct r600_context *rctx = (struct r600_context *)ctx;
1116 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1117
1118 if (rctx->tcs_shader == sel) {
1119 rctx->tcs_shader = NULL;
1120 }
1121
1122 r600_delete_shader_selector(ctx, sel);
1123 }
1124
1125 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1126 {
1127 struct r600_context *rctx = (struct r600_context *)ctx;
1128 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1129
1130 if (rctx->tes_shader == sel) {
1131 rctx->tes_shader = NULL;
1132 }
1133
1134 r600_delete_shader_selector(ctx, sel);
1135 }
1136
1137 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1138 {
1139 if (state->dirty_mask) {
1140 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1141 : util_bitcount(state->dirty_mask)*19;
1142 r600_mark_atom_dirty(rctx, &state->atom);
1143 }
1144 }
1145
1146 static void r600_set_constant_buffer(struct pipe_context *ctx,
1147 enum pipe_shader_type shader, uint index,
1148 const struct pipe_constant_buffer *input)
1149 {
1150 struct r600_context *rctx = (struct r600_context *)ctx;
1151 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1152 struct pipe_constant_buffer *cb;
1153 const uint8_t *ptr;
1154
1155 /* Note that the state tracker can unbind constant buffers by
1156 * passing NULL here.
1157 */
1158 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1159 state->enabled_mask &= ~(1 << index);
1160 state->dirty_mask &= ~(1 << index);
1161 pipe_resource_reference(&state->cb[index].buffer, NULL);
1162 return;
1163 }
1164
1165 cb = &state->cb[index];
1166 cb->buffer_size = input->buffer_size;
1167
1168 ptr = input->user_buffer;
1169
1170 if (ptr) {
1171 /* Upload the user buffer. */
1172 if (R600_BIG_ENDIAN) {
1173 uint32_t *tmpPtr;
1174 unsigned i, size = input->buffer_size;
1175
1176 if (!(tmpPtr = malloc(size))) {
1177 R600_ERR("Failed to allocate BE swap buffer.\n");
1178 return;
1179 }
1180
1181 for (i = 0; i < size / 4; ++i) {
1182 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1183 }
1184
1185 u_upload_data(ctx->stream_uploader, 0, size, 256,
1186 tmpPtr, &cb->buffer_offset, &cb->buffer);
1187 free(tmpPtr);
1188 } else {
1189 u_upload_data(ctx->stream_uploader, 0,
1190 input->buffer_size, 256, ptr,
1191 &cb->buffer_offset, &cb->buffer);
1192 }
1193 /* account it in gtt */
1194 rctx->b.gtt += input->buffer_size;
1195 } else {
1196 /* Setup the hw buffer. */
1197 cb->buffer_offset = input->buffer_offset;
1198 pipe_resource_reference(&cb->buffer, input->buffer);
1199 r600_context_add_resource_size(ctx, input->buffer);
1200 }
1201
1202 state->enabled_mask |= 1 << index;
1203 state->dirty_mask |= 1 << index;
1204 r600_constant_buffers_dirty(rctx, state);
1205 }
1206
1207 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1208 {
1209 struct r600_context *rctx = (struct r600_context*)pipe;
1210
1211 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1212 return;
1213
1214 rctx->sample_mask.sample_mask = sample_mask;
1215 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1216 }
1217
1218 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only)
1219 {
1220 int sh, size;
1221 void *ptr;
1222 struct pipe_constant_buffer cb;
1223 int start, end;
1224
1225 start = compute_only ? PIPE_SHADER_COMPUTE : 0;
1226 end = compute_only ? PIPE_SHADER_TYPES : PIPE_SHADER_COMPUTE;
1227
1228 for (sh = start; sh < end; sh++) {
1229 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1230 if (!info->vs_ucp_dirty &&
1231 !info->texture_const_dirty &&
1232 !info->ps_sample_pos_dirty &&
1233 !info->cs_block_grid_size_dirty)
1234 continue;
1235
1236 ptr = info->constants;
1237 size = info->alloc_size;
1238 if (info->vs_ucp_dirty) {
1239 assert(sh == PIPE_SHADER_VERTEX);
1240 if (!size) {
1241 ptr = rctx->clip_state.state.ucp;
1242 size = R600_UCP_SIZE;
1243 } else {
1244 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1245 }
1246 info->vs_ucp_dirty = false;
1247 }
1248
1249 if (info->ps_sample_pos_dirty) {
1250 assert(sh == PIPE_SHADER_FRAGMENT);
1251 if (!size) {
1252 ptr = rctx->sample_positions;
1253 size = R600_UCP_SIZE;
1254 } else {
1255 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1256 }
1257 info->ps_sample_pos_dirty = false;
1258 }
1259
1260 if (info->cs_block_grid_size_dirty) {
1261 assert(sh == PIPE_SHADER_COMPUTE);
1262 if (!size) {
1263 ptr = rctx->cs_block_grid_sizes;
1264 size = R600_CS_BLOCK_GRID_SIZE;
1265 } else {
1266 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1267 }
1268 info->cs_block_grid_size_dirty = false;
1269 }
1270
1271 if (info->texture_const_dirty) {
1272 assert (ptr);
1273 assert (size);
1274 if (sh == PIPE_SHADER_VERTEX)
1275 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1276 if (sh == PIPE_SHADER_FRAGMENT)
1277 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1278 if (sh == PIPE_SHADER_COMPUTE)
1279 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1280 }
1281 info->texture_const_dirty = false;
1282
1283 cb.buffer = NULL;
1284 cb.user_buffer = ptr;
1285 cb.buffer_offset = 0;
1286 cb.buffer_size = size;
1287 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1288 pipe_resource_reference(&cb.buffer, NULL);
1289 }
1290 }
1291
1292 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1293 int array_size, uint32_t *base_offset)
1294 {
1295 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1296 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1297 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1298 info->alloc_size = array_size + R600_UCP_SIZE;
1299 }
1300 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1301 info->texture_const_dirty = true;
1302 *base_offset = R600_UCP_SIZE;
1303 return info->constants;
1304 }
1305 /*
1306 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1307 * doesn't require full swizzles it does need masking and setting alpha
1308 * to one, so we setup a set of 5 constants with the masks + alpha value
1309 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1310 * then OR the alpha with the value given here.
1311 * We use a 6th constant to store the txq buffer size in
1312 * we use 7th slot for number of cube layers in a cube map array.
1313 */
1314 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1315 {
1316 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1317 int bits;
1318 uint32_t array_size;
1319 int i, j;
1320 uint32_t *constants;
1321 uint32_t base_offset;
1322 if (!samplers->views.dirty_buffer_constants)
1323 return;
1324
1325 samplers->views.dirty_buffer_constants = FALSE;
1326
1327 bits = util_last_bit(samplers->views.enabled_mask);
1328 array_size = bits * 8 * sizeof(uint32_t);
1329
1330 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1331
1332 for (i = 0; i < bits; i++) {
1333 if (samplers->views.enabled_mask & (1 << i)) {
1334 int offset = (base_offset / 4) + i * 8;
1335 const struct util_format_description *desc;
1336 desc = util_format_description(samplers->views.views[i]->base.format);
1337
1338 for (j = 0; j < 4; j++)
1339 if (j < desc->nr_channels)
1340 constants[offset+j] = 0xffffffff;
1341 else
1342 constants[offset+j] = 0x0;
1343 if (desc->nr_channels < 4) {
1344 if (desc->channel[0].pure_integer)
1345 constants[offset+4] = 1;
1346 else
1347 constants[offset+4] = fui(1.0);
1348 } else
1349 constants[offset + 4] = 0;
1350
1351 constants[offset + 5] = samplers->views.views[i]->base.u.buf.size /
1352 util_format_get_blocksize(samplers->views.views[i]->base.format);
1353 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1354 }
1355 }
1356
1357 }
1358
1359 /* On evergreen we store one value
1360 * 1. buffer size for TXQ or
1361 * 2. number of cube layers in a cube map array.
1362 */
1363 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1364 {
1365 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1366 struct r600_image_state *images = NULL;
1367 struct r600_image_state *buffers = NULL;
1368 int bits, sview_bits, img_bits;
1369 uint32_t array_size;
1370 int i;
1371 uint32_t *constants;
1372 uint32_t base_offset;
1373
1374 if (shader_type == PIPE_SHADER_FRAGMENT) {
1375 images = &rctx->fragment_images;
1376 buffers = &rctx->fragment_buffers;
1377 } else if (shader_type == PIPE_SHADER_COMPUTE) {
1378 images = &rctx->compute_images;
1379 buffers = &rctx->compute_buffers;
1380 }
1381
1382 if (!samplers->views.dirty_buffer_constants &&
1383 !(images && images->dirty_buffer_constants) &&
1384 !(buffers && buffers->dirty_buffer_constants))
1385 return;
1386
1387 if (images)
1388 images->dirty_buffer_constants = FALSE;
1389 if (buffers)
1390 buffers->dirty_buffer_constants = FALSE;
1391 samplers->views.dirty_buffer_constants = FALSE;
1392
1393 bits = sview_bits = util_last_bit(samplers->views.enabled_mask);
1394 if (images)
1395 bits += util_last_bit(images->enabled_mask);
1396 img_bits = bits;
1397 if (buffers)
1398 bits += util_last_bit(buffers->enabled_mask);
1399 array_size = bits * sizeof(uint32_t);
1400
1401 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1402 &base_offset);
1403
1404 for (i = 0; i < sview_bits; i++) {
1405 if (samplers->views.enabled_mask & (1 << i)) {
1406 uint32_t offset = (base_offset / 4) + i;
1407 if (samplers->views.views[i]->base.target == PIPE_BUFFER) {
1408 constants[offset] = samplers->views.views[i]->base.u.buf.size /
1409 util_format_get_blocksize(samplers->views.views[i]->base.format);
1410 } else {
1411 constants[offset] = samplers->views.views[i]->base.texture->array_size / 6;
1412 }
1413 }
1414 }
1415 if (images) {
1416 for (i = sview_bits; i < img_bits; i++) {
1417 int idx = i - sview_bits;
1418 if (images->enabled_mask & (1 << idx)) {
1419 uint32_t offset = (base_offset / 4) + i;
1420 if (images->views[i].base.resource->target == PIPE_BUFFER) {
1421 constants[offset] = images->views[i].base.u.buf.size /
1422 util_format_get_blocksize(images->views[i].base.format);
1423 } else {
1424 constants[offset] = images->views[i].base.resource->array_size / 6;
1425 }
1426 }
1427 }
1428 }
1429 if (buffers) {
1430 for (i = img_bits; i < bits; i++) {
1431 int idx = i - img_bits;
1432 if (buffers->enabled_mask & (1 << idx)) {
1433 uint32_t offset = (base_offset / 4) + i;
1434 assert(buffers->views[i].base.resource->target == PIPE_BUFFER);
1435 constants[offset] = buffers->views[i].base.u.buf.size /
1436 util_format_get_blocksize(buffers->views[i].base.format);
1437 }
1438 }
1439 }
1440 }
1441
1442 /* set sample xy locations as array of fragment shader constants */
1443 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1444 {
1445 int i;
1446 struct pipe_context *ctx = &rctx->b.b;
1447
1448 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1449 assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4);
1450
1451 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1452 for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1453 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1454 /* Also fill in center-zeroed positions used for interpolateAtSample */
1455 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1456 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1457 }
1458
1459 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1460 }
1461
1462 static void update_shader_atom(struct pipe_context *ctx,
1463 struct r600_shader_state *state,
1464 struct r600_pipe_shader *shader)
1465 {
1466 struct r600_context *rctx = (struct r600_context *)ctx;
1467
1468 state->shader = shader;
1469 if (shader) {
1470 state->atom.num_dw = shader->command_buffer.num_dw;
1471 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1472 } else {
1473 state->atom.num_dw = 0;
1474 }
1475 r600_mark_atom_dirty(rctx, &state->atom);
1476 }
1477
1478 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1479 {
1480 if (rctx->shader_stages.geom_enable != enable) {
1481 rctx->shader_stages.geom_enable = enable;
1482 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1483 }
1484
1485 if (rctx->gs_rings.enable != enable) {
1486 rctx->gs_rings.enable = enable;
1487 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1488
1489 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1490 unsigned size = 0x1C000;
1491 rctx->gs_rings.esgs_ring.buffer =
1492 pipe_buffer_create(rctx->b.b.screen, 0,
1493 PIPE_USAGE_DEFAULT, size);
1494 rctx->gs_rings.esgs_ring.buffer_size = size;
1495
1496 size = 0x4000000;
1497
1498 rctx->gs_rings.gsvs_ring.buffer =
1499 pipe_buffer_create(rctx->b.b.screen, 0,
1500 PIPE_USAGE_DEFAULT, size);
1501 rctx->gs_rings.gsvs_ring.buffer_size = size;
1502 }
1503
1504 if (enable) {
1505 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1506 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1507 if (rctx->tes_shader) {
1508 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1509 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1510 } else {
1511 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1512 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1513 }
1514 } else {
1515 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1516 R600_GS_RING_CONST_BUFFER, NULL);
1517 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1518 R600_GS_RING_CONST_BUFFER, NULL);
1519 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1520 R600_GS_RING_CONST_BUFFER, NULL);
1521 }
1522 }
1523 }
1524
1525 static void r600_update_clip_state(struct r600_context *rctx,
1526 struct r600_pipe_shader *current)
1527 {
1528 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1529 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1530 current->shader.cull_dist_write != rctx->clip_misc_state.cull_dist_write ||
1531 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1532 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1533 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1534 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1535 rctx->clip_misc_state.cull_dist_write = current->shader.cull_dist_write;
1536 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1537 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1538 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1539 }
1540 }
1541
1542 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1543 {
1544 struct ureg_src const0, const1;
1545 struct ureg_dst tessouter, tessinner;
1546 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1547
1548 if (!ureg)
1549 return; /* if we get here, we're screwed */
1550
1551 assert(!rctx->fixed_func_tcs_shader);
1552
1553 ureg_DECL_constant2D(ureg, 0, 3, R600_LDS_INFO_CONST_BUFFER);
1554 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 2),
1555 R600_LDS_INFO_CONST_BUFFER);
1556 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 3),
1557 R600_LDS_INFO_CONST_BUFFER);
1558
1559 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1560 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1561
1562 ureg_MOV(ureg, tessouter, const0);
1563 ureg_MOV(ureg, tessinner, const1);
1564 ureg_END(ureg);
1565
1566 rctx->fixed_func_tcs_shader =
1567 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1568 }
1569
1570 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only)
1571 {
1572 unsigned i;
1573 unsigned counter;
1574
1575 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1576 if (counter != rctx->b.last_compressed_colortex_counter) {
1577 rctx->b.last_compressed_colortex_counter = counter;
1578
1579 if (compute_only) {
1580 r600_update_compressed_colortex_mask(&rctx->samplers[PIPE_SHADER_COMPUTE].views);
1581 } else {
1582 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1583 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1584 }
1585 }
1586 if (!compute_only)
1587 r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
1588 r600_update_compressed_colortex_mask_images(&rctx->compute_images);
1589 }
1590
1591 /* Decompress textures if needed. */
1592 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1593 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1594
1595 if (compute_only)
1596 if (i != PIPE_SHADER_COMPUTE)
1597 continue;
1598 if (views->compressed_depthtex_mask) {
1599 r600_decompress_depth_textures(rctx, views);
1600 }
1601 if (views->compressed_colortex_mask) {
1602 r600_decompress_color_textures(rctx, views);
1603 }
1604 }
1605
1606 {
1607 struct r600_image_state *istate;
1608
1609 if (!compute_only) {
1610 istate = &rctx->fragment_images;
1611 if (istate->compressed_depthtex_mask)
1612 r600_decompress_depth_images(rctx, istate);
1613 if (istate->compressed_colortex_mask)
1614 r600_decompress_color_images(rctx, istate);
1615 }
1616
1617 istate = &rctx->compute_images;
1618 if (istate->compressed_depthtex_mask)
1619 r600_decompress_depth_images(rctx, istate);
1620 if (istate->compressed_colortex_mask)
1621 r600_decompress_color_images(rctx, istate);
1622 }
1623 }
1624
1625 #define SELECT_SHADER_OR_FAIL(x) do { \
1626 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1627 if (unlikely(!rctx->x##_shader->current)) \
1628 return false; \
1629 } while(0)
1630
1631 #define UPDATE_SHADER(hw, sw) do { \
1632 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1633 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1634 } while(0)
1635
1636 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1637 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1638 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1639 clip_so_current = rctx->sw##_shader->current; \
1640 } \
1641 } while(0)
1642
1643 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1644 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1645 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1646 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1647 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1648 } \
1649 } while(0)
1650
1651 #define SET_NULL_SHADER(hw) do { \
1652 if (rctx->hw_shader_stages[(hw)].shader) \
1653 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1654 } while (0)
1655
1656 static bool r600_update_derived_state(struct r600_context *rctx)
1657 {
1658 struct pipe_context * ctx = (struct pipe_context*)rctx;
1659 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1660 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1661 bool blend_disable;
1662 bool need_buf_const;
1663 struct r600_pipe_shader *clip_so_current = NULL;
1664
1665 if (!rctx->blitter->running)
1666 r600_update_compressed_resource_state(rctx, false);
1667
1668 SELECT_SHADER_OR_FAIL(ps);
1669
1670 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1671
1672 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1673
1674 if (rctx->gs_shader)
1675 SELECT_SHADER_OR_FAIL(gs);
1676
1677 /* Hull Shader */
1678 if (rctx->tcs_shader) {
1679 SELECT_SHADER_OR_FAIL(tcs);
1680
1681 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1682 } else if (rctx->tes_shader) {
1683 if (!rctx->fixed_func_tcs_shader) {
1684 r600_generate_fixed_func_tcs(rctx);
1685 if (!rctx->fixed_func_tcs_shader)
1686 return false;
1687
1688 }
1689 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1690
1691 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1692 } else
1693 SET_NULL_SHADER(EG_HW_STAGE_HS);
1694
1695 if (rctx->tes_shader) {
1696 SELECT_SHADER_OR_FAIL(tes);
1697 }
1698
1699 SELECT_SHADER_OR_FAIL(vs);
1700
1701 if (rctx->gs_shader) {
1702 if (!rctx->shader_stages.geom_enable) {
1703 rctx->shader_stages.geom_enable = true;
1704 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1705 }
1706
1707 /* gs_shader provides GS and VS (copy shader) */
1708 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1709
1710 /* vs_shader is used as ES */
1711
1712 if (rctx->tes_shader) {
1713 /* VS goes to LS, TES goes to ES */
1714 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1715 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1716 } else {
1717 /* vs_shader is used as ES */
1718 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1719 SET_NULL_SHADER(EG_HW_STAGE_LS);
1720 }
1721 } else {
1722 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1723 SET_NULL_SHADER(R600_HW_STAGE_GS);
1724 SET_NULL_SHADER(R600_HW_STAGE_ES);
1725 rctx->shader_stages.geom_enable = false;
1726 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1727 }
1728
1729 if (rctx->tes_shader) {
1730 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1731 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1732 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1733 } else {
1734 SET_NULL_SHADER(EG_HW_STAGE_LS);
1735 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1736 }
1737 }
1738
1739 /* Update clip misc state. */
1740 if (clip_so_current) {
1741 r600_update_clip_state(rctx, clip_so_current);
1742 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1743 }
1744
1745 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1746 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1747 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1748
1749 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1750 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1751 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1752 }
1753
1754 if (rctx->b.chip_class <= R700) {
1755 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1756
1757 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1758 rctx->cb_misc_state.multiwrite = multiwrite;
1759 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1760 }
1761 }
1762
1763 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1764 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1765 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1766
1767 if (rctx->b.chip_class >= EVERGREEN)
1768 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1769 else
1770 r600_update_ps_state(ctx, rctx->ps_shader->current);
1771 }
1772
1773 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1774 }
1775 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
1776
1777 if (rctx->b.chip_class >= EVERGREEN) {
1778 evergreen_update_db_shader_control(rctx);
1779 } else {
1780 r600_update_db_shader_control(rctx);
1781 }
1782
1783 /* on R600 we stuff masks + txq info into one constant buffer */
1784 /* on evergreen we only need a txq info one */
1785 if (rctx->ps_shader) {
1786 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1787 if (need_buf_const) {
1788 if (rctx->b.chip_class < EVERGREEN)
1789 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1790 else
1791 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1792 }
1793 }
1794
1795 if (rctx->vs_shader) {
1796 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1797 if (need_buf_const) {
1798 if (rctx->b.chip_class < EVERGREEN)
1799 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1800 else
1801 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1802 }
1803 }
1804
1805 if (rctx->gs_shader) {
1806 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1807 if (need_buf_const) {
1808 if (rctx->b.chip_class < EVERGREEN)
1809 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1810 else
1811 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1812 }
1813 }
1814
1815 r600_update_driver_const_buffers(rctx, false);
1816
1817 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1818 if (!r600_adjust_gprs(rctx)) {
1819 /* discard rendering */
1820 return false;
1821 }
1822 }
1823
1824 if (rctx->b.chip_class == EVERGREEN) {
1825 if (!evergreen_adjust_gprs(rctx)) {
1826 /* discard rendering */
1827 return false;
1828 }
1829 }
1830
1831 blend_disable = (rctx->dual_src_blend &&
1832 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1833
1834 if (blend_disable != rctx->force_blend_disable) {
1835 rctx->force_blend_disable = blend_disable;
1836 r600_bind_blend_state_internal(rctx,
1837 rctx->blend_state.cso,
1838 blend_disable);
1839 }
1840
1841 return true;
1842 }
1843
1844 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1845 {
1846 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1847 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1848
1849 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1850 state->pa_cl_clip_cntl |
1851 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1852 S_028810_CLIP_DISABLE(state->clip_disable));
1853 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1854 state->pa_cl_vs_out_cntl |
1855 (state->clip_plane_enable & state->clip_dist_write) |
1856 (state->cull_dist_write << 8));
1857 /* reuse needs to be set off if we write oViewport */
1858 if (rctx->b.chip_class >= EVERGREEN)
1859 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
1860 S_028AB4_REUSE_OFF(state->vs_out_viewport));
1861 }
1862
1863 /* rast_prim is the primitive type after GS. */
1864 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
1865 {
1866 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1867 enum pipe_prim_type rast_prim = rctx->current_rast_prim;
1868
1869 /* Skip this if not rendering lines. */
1870 if (rast_prim != PIPE_PRIM_LINES &&
1871 rast_prim != PIPE_PRIM_LINE_LOOP &&
1872 rast_prim != PIPE_PRIM_LINE_STRIP &&
1873 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
1874 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
1875 return;
1876
1877 if (rast_prim == rctx->last_rast_prim)
1878 return;
1879
1880 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1881 * reset the stipple pattern at each packet (line strips, line loops).
1882 */
1883 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1884 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2) |
1885 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1886 rctx->last_rast_prim = rast_prim;
1887 }
1888
1889 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1890 {
1891 struct r600_context *rctx = (struct r600_context *)ctx;
1892 struct pipe_resource *indexbuf = info->has_user_indices ? NULL : info->index.resource;
1893 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1894 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
1895 bool has_user_indices = info->has_user_indices;
1896 uint64_t mask;
1897 unsigned num_patches, dirty_tex_counter, index_offset = 0;
1898 unsigned index_size = info->index_size;
1899 int index_bias;
1900 struct r600_shader_atomic combined_atomics[8];
1901 uint8_t atomic_used_mask;
1902
1903 if (!info->indirect && !info->count && (index_size || !info->count_from_stream_output)) {
1904 return;
1905 }
1906
1907 if (unlikely(!rctx->vs_shader)) {
1908 assert(0);
1909 return;
1910 }
1911 if (unlikely(!rctx->ps_shader &&
1912 (!rctx->rasterizer || !rctx->rasterizer->rasterizer_discard))) {
1913 assert(0);
1914 return;
1915 }
1916
1917 /* make sure that the gfx ring is only one active */
1918 if (radeon_emitted(rctx->b.dma.cs, 0)) {
1919 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1920 }
1921
1922 if (rctx->cmd_buf_is_compute) {
1923 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1924 rctx->cmd_buf_is_compute = false;
1925 }
1926
1927 /* Re-emit the framebuffer state if needed. */
1928 dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
1929 if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) {
1930 rctx->b.last_dirty_tex_counter = dirty_tex_counter;
1931 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1932 rctx->framebuffer.do_update_surf_dirtiness = true;
1933 }
1934
1935 if (rctx->gs_shader) {
1936 /* Determine whether the GS triangle strip adjacency fix should
1937 * be applied. Rotate every other triangle if
1938 * - triangle strips with adjacency are fed to the GS and
1939 * - primitive restart is disabled (the rotation doesn't help
1940 * when the restart occurs after an odd number of triangles).
1941 */
1942 bool gs_tri_strip_adj_fix =
1943 !rctx->tes_shader &&
1944 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1945 !info->primitive_restart;
1946 if (gs_tri_strip_adj_fix != rctx->gs_tri_strip_adj_fix)
1947 rctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1948 }
1949 if (!r600_update_derived_state(rctx)) {
1950 /* useless to render because current rendering command
1951 * can't be achieved
1952 */
1953 return;
1954 }
1955
1956 rctx->current_rast_prim = (rctx->gs_shader)? rctx->gs_shader->gs_output_prim
1957 : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
1958 : info->mode;
1959
1960 if (rctx->b.chip_class >= EVERGREEN)
1961 evergreen_emit_atomic_buffer_setup(rctx, NULL, combined_atomics, &atomic_used_mask);
1962
1963 if (index_size) {
1964 index_offset += info->start * index_size;
1965
1966 /* Translate 8-bit indices to 16-bit. */
1967 if (unlikely(index_size == 1)) {
1968 struct pipe_resource *out_buffer = NULL;
1969 unsigned out_offset;
1970 void *ptr;
1971 unsigned start, count;
1972
1973 if (likely(!info->indirect)) {
1974 start = 0;
1975 count = info->count;
1976 }
1977 else {
1978 /* Have to get start/count from indirect buffer, slow path ahead... */
1979 struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect->buffer;
1980 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
1981 PIPE_TRANSFER_READ);
1982 if (data) {
1983 data += info->indirect->offset / sizeof(unsigned);
1984 start = data[2] * index_size;
1985 count = data[0];
1986 }
1987 else {
1988 start = 0;
1989 count = 0;
1990 }
1991 }
1992
1993 u_upload_alloc(ctx->stream_uploader, start, count * 2,
1994 256, &out_offset, &out_buffer, &ptr);
1995 if (unlikely(!ptr))
1996 return;
1997
1998 util_shorten_ubyte_elts_to_userptr(
1999 &rctx->b.b, info, 0, 0, index_offset, count, ptr);
2000
2001 indexbuf = out_buffer;
2002 index_offset = out_offset;
2003 index_size = 2;
2004 has_user_indices = false;
2005 }
2006
2007 /* Upload the index buffer.
2008 * The upload is skipped for small index counts on little-endian machines
2009 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2010 * Indirect draws never use immediate indices.
2011 * Note: Instanced rendering in combination with immediate indices hangs. */
2012 if (has_user_indices && (R600_BIG_ENDIAN || info->indirect ||
2013 info->instance_count > 1 ||
2014 info->count*index_size > 20)) {
2015 indexbuf = NULL;
2016 u_upload_data(ctx->stream_uploader, 0,
2017 info->count * index_size, 256,
2018 info->index.user, &index_offset, &indexbuf);
2019 has_user_indices = false;
2020 }
2021 index_bias = info->index_bias;
2022 } else {
2023 index_bias = info->start;
2024 }
2025
2026 /* Set the index offset and primitive restart. */
2027 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info->primitive_restart ||
2028 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info->restart_index ||
2029 rctx->vgt_state.vgt_indx_offset != index_bias ||
2030 (rctx->vgt_state.last_draw_was_indirect && !info->indirect)) {
2031 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info->primitive_restart;
2032 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info->restart_index;
2033 rctx->vgt_state.vgt_indx_offset = index_bias;
2034 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
2035 }
2036
2037 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2038 if (rctx->b.chip_class == R600) {
2039 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
2040 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2041 }
2042
2043 if (rctx->b.chip_class >= EVERGREEN)
2044 evergreen_setup_tess_constants(rctx, info, &num_patches);
2045
2046 /* Emit states. */
2047 r600_need_cs_space(rctx, has_user_indices ? 5 : 0, TRUE);
2048 r600_flush_emit(rctx);
2049
2050 mask = rctx->dirty_atoms;
2051 while (mask != 0) {
2052 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
2053 }
2054
2055 if (rctx->b.chip_class == CAYMAN) {
2056 /* Copied from radeonsi. */
2057 unsigned primgroup_size = 128; /* recommended without a GS */
2058 bool ia_switch_on_eop = false;
2059 bool partial_vs_wave = false;
2060
2061 if (rctx->gs_shader)
2062 primgroup_size = 64; /* recommended with a GS */
2063
2064 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
2065 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
2066 ia_switch_on_eop = true;
2067 }
2068
2069 if (r600_get_strmout_en(&rctx->b))
2070 partial_vs_wave = true;
2071
2072 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
2073 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
2074 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
2075 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
2076 }
2077
2078 if (rctx->b.chip_class >= EVERGREEN) {
2079 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info,
2080 num_patches);
2081
2082 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
2083 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
2084 }
2085
2086 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2087 * even though it should have no effect on those. */
2088 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
2089 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
2090 unsigned prim = info->mode;
2091
2092 if (rctx->gs_shader) {
2093 prim = rctx->gs_shader->gs_output_prim;
2094 }
2095 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
2096
2097 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
2098 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
2099 info->mode == R600_PRIM_RECTANGLE_LIST) {
2100 su_sc_mode_cntl &= C_028814_CULL_FRONT;
2101 }
2102 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
2103 }
2104
2105 /* Update start instance. */
2106 if (!info->indirect && rctx->last_start_instance != info->start_instance) {
2107 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
2108 rctx->last_start_instance = info->start_instance;
2109 }
2110
2111 /* Update the primitive type. */
2112 if (rctx->last_primitive_type != info->mode) {
2113 r600_emit_rasterizer_prim_state(rctx);
2114 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2115 r600_conv_pipe_prim(info->mode));
2116
2117 rctx->last_primitive_type = info->mode;
2118 }
2119
2120 /* Draw packets. */
2121 if (likely(!info->indirect)) {
2122 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2123 radeon_emit(cs, info->instance_count);
2124 } else {
2125 uint64_t va = r600_resource(info->indirect->buffer)->gpu_address;
2126 assert(rctx->b.chip_class >= EVERGREEN);
2127
2128 // Invalidate so non-indirect draw calls reset this state
2129 rctx->vgt_state.last_draw_was_indirect = true;
2130 rctx->last_start_instance = -1;
2131
2132 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0));
2133 radeon_emit(cs, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE);
2134 radeon_emit(cs, va);
2135 radeon_emit(cs, (va >> 32UL) & 0xFF);
2136
2137 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2138 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2139 (struct r600_resource*)info->indirect->buffer,
2140 RADEON_USAGE_READ,
2141 RADEON_PRIO_DRAW_INDIRECT));
2142 }
2143
2144 if (index_size) {
2145 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2146 radeon_emit(cs, index_size == 4 ?
2147 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
2148 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)));
2149
2150 if (has_user_indices) {
2151 unsigned size_bytes = info->count*index_size;
2152 unsigned size_dw = align(size_bytes, 4) / 4;
2153 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
2154 radeon_emit(cs, info->count);
2155 radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
2156 radeon_emit_array(cs, info->index.user, size_dw);
2157 } else {
2158 uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
2159
2160 if (likely(!info->indirect)) {
2161 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit));
2162 radeon_emit(cs, va);
2163 radeon_emit(cs, (va >> 32UL) & 0xFF);
2164 radeon_emit(cs, info->count);
2165 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2166 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2167 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2168 (struct r600_resource*)indexbuf,
2169 RADEON_USAGE_READ,
2170 RADEON_PRIO_INDEX_BUFFER));
2171 }
2172 else {
2173 uint32_t max_size = (indexbuf->width0 - index_offset) / index_size;
2174
2175 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0));
2176 radeon_emit(cs, va);
2177 radeon_emit(cs, (va >> 32UL) & 0xFF);
2178
2179 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2180 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2181 (struct r600_resource*)indexbuf,
2182 RADEON_USAGE_READ,
2183 RADEON_PRIO_INDEX_BUFFER));
2184
2185 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
2186 radeon_emit(cs, max_size);
2187
2188 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
2189 radeon_emit(cs, info->indirect->offset);
2190 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2191 }
2192 }
2193 } else {
2194 if (unlikely(info->count_from_stream_output)) {
2195 struct r600_so_target *t = (struct r600_so_target*)info->count_from_stream_output;
2196 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
2197
2198 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
2199
2200 radeon_emit(cs, PKT3(PKT3_COPY_DW, 4, 0));
2201 radeon_emit(cs, COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG);
2202 radeon_emit(cs, va & 0xFFFFFFFFUL); /* src address lo */
2203 radeon_emit(cs, (va >> 32UL) & 0xFFUL); /* src address hi */
2204 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); /* dst register */
2205 radeon_emit(cs, 0); /* unused */
2206
2207 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2208 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2209 t->buf_filled_size, RADEON_USAGE_READ,
2210 RADEON_PRIO_SO_FILLED_SIZE));
2211 }
2212
2213 if (likely(!info->indirect)) {
2214 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
2215 radeon_emit(cs, info->count);
2216 }
2217 else {
2218 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
2219 radeon_emit(cs, info->indirect->offset);
2220 }
2221 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2222 (info->count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0));
2223 }
2224
2225 /* SMX returns CONTEXT_DONE too early workaround */
2226 if (rctx->b.family == CHIP_R600 ||
2227 rctx->b.family == CHIP_RV610 ||
2228 rctx->b.family == CHIP_RV630 ||
2229 rctx->b.family == CHIP_RV635) {
2230 /* if we have gs shader or streamout
2231 we need to do a wait idle after every draw */
2232 if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
2233 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2234 }
2235 }
2236
2237 /* ES ring rolling over at EOP - workaround */
2238 if (rctx->b.chip_class == R600) {
2239 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2240 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT));
2241 }
2242
2243
2244 if (rctx->b.chip_class >= EVERGREEN)
2245 evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, &atomic_used_mask);
2246
2247 if (rctx->trace_buf)
2248 eg_trace_emit(rctx);
2249
2250 if (rctx->framebuffer.do_update_surf_dirtiness) {
2251 /* Set the depth buffer as dirty. */
2252 if (rctx->framebuffer.state.zsbuf) {
2253 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2254 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2255
2256 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2257
2258 if (rtex->surface.has_stencil)
2259 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2260 }
2261 if (rctx->framebuffer.compressed_cb_mask) {
2262 struct pipe_surface *surf;
2263 struct r600_texture *rtex;
2264 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2265
2266 do {
2267 unsigned i = u_bit_scan(&mask);
2268 surf = rctx->framebuffer.state.cbufs[i];
2269 rtex = (struct r600_texture*)surf->texture;
2270
2271 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2272
2273 } while (mask);
2274 }
2275 rctx->framebuffer.do_update_surf_dirtiness = false;
2276 }
2277
2278 if (index_size && indexbuf != info->index.resource)
2279 pipe_resource_reference(&indexbuf, NULL);
2280 rctx->b.num_draw_calls++;
2281 }
2282
2283 uint32_t r600_translate_stencil_op(int s_op)
2284 {
2285 switch (s_op) {
2286 case PIPE_STENCIL_OP_KEEP:
2287 return V_028800_STENCIL_KEEP;
2288 case PIPE_STENCIL_OP_ZERO:
2289 return V_028800_STENCIL_ZERO;
2290 case PIPE_STENCIL_OP_REPLACE:
2291 return V_028800_STENCIL_REPLACE;
2292 case PIPE_STENCIL_OP_INCR:
2293 return V_028800_STENCIL_INCR;
2294 case PIPE_STENCIL_OP_DECR:
2295 return V_028800_STENCIL_DECR;
2296 case PIPE_STENCIL_OP_INCR_WRAP:
2297 return V_028800_STENCIL_INCR_WRAP;
2298 case PIPE_STENCIL_OP_DECR_WRAP:
2299 return V_028800_STENCIL_DECR_WRAP;
2300 case PIPE_STENCIL_OP_INVERT:
2301 return V_028800_STENCIL_INVERT;
2302 default:
2303 R600_ERR("Unknown stencil op %d", s_op);
2304 assert(0);
2305 break;
2306 }
2307 return 0;
2308 }
2309
2310 uint32_t r600_translate_fill(uint32_t func)
2311 {
2312 switch(func) {
2313 case PIPE_POLYGON_MODE_FILL:
2314 return 2;
2315 case PIPE_POLYGON_MODE_LINE:
2316 return 1;
2317 case PIPE_POLYGON_MODE_POINT:
2318 return 0;
2319 default:
2320 assert(0);
2321 return 0;
2322 }
2323 }
2324
2325 unsigned r600_tex_wrap(unsigned wrap)
2326 {
2327 switch (wrap) {
2328 default:
2329 case PIPE_TEX_WRAP_REPEAT:
2330 return V_03C000_SQ_TEX_WRAP;
2331 case PIPE_TEX_WRAP_CLAMP:
2332 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2333 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2334 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2335 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2336 return V_03C000_SQ_TEX_CLAMP_BORDER;
2337 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2338 return V_03C000_SQ_TEX_MIRROR;
2339 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2340 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2341 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2342 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2343 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2344 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2345 }
2346 }
2347
2348 unsigned r600_tex_mipfilter(unsigned filter)
2349 {
2350 switch (filter) {
2351 case PIPE_TEX_MIPFILTER_NEAREST:
2352 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2353 case PIPE_TEX_MIPFILTER_LINEAR:
2354 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2355 default:
2356 case PIPE_TEX_MIPFILTER_NONE:
2357 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2358 }
2359 }
2360
2361 unsigned r600_tex_compare(unsigned compare)
2362 {
2363 switch (compare) {
2364 default:
2365 case PIPE_FUNC_NEVER:
2366 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2367 case PIPE_FUNC_LESS:
2368 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2369 case PIPE_FUNC_EQUAL:
2370 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2371 case PIPE_FUNC_LEQUAL:
2372 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2373 case PIPE_FUNC_GREATER:
2374 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2375 case PIPE_FUNC_NOTEQUAL:
2376 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2377 case PIPE_FUNC_GEQUAL:
2378 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2379 case PIPE_FUNC_ALWAYS:
2380 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2381 }
2382 }
2383
2384 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2385 {
2386 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2387 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2388 (linear_filter &&
2389 (wrap == PIPE_TEX_WRAP_CLAMP ||
2390 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2391 }
2392
2393 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2394 {
2395 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2396 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2397
2398 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2399 state->border_color.ui[2] || state->border_color.ui[3]) &&
2400 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2401 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2402 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2403 }
2404
2405 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2406 {
2407
2408 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2409 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2410
2411 if (!shader)
2412 return;
2413
2414 r600_emit_command_buffer(cs, &shader->command_buffer);
2415 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2416 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2417 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY));
2418 }
2419
2420 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2421 const unsigned char *swizzle_view,
2422 boolean vtx)
2423 {
2424 unsigned i;
2425 unsigned char swizzle[4];
2426 unsigned result = 0;
2427 const uint32_t tex_swizzle_shift[4] = {
2428 16, 19, 22, 25,
2429 };
2430 const uint32_t vtx_swizzle_shift[4] = {
2431 3, 6, 9, 12,
2432 };
2433 const uint32_t swizzle_bit[4] = {
2434 0, 1, 2, 3,
2435 };
2436 const uint32_t *swizzle_shift = tex_swizzle_shift;
2437
2438 if (vtx)
2439 swizzle_shift = vtx_swizzle_shift;
2440
2441 if (swizzle_view) {
2442 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2443 } else {
2444 memcpy(swizzle, swizzle_format, 4);
2445 }
2446
2447 /* Get swizzle. */
2448 for (i = 0; i < 4; i++) {
2449 switch (swizzle[i]) {
2450 case PIPE_SWIZZLE_Y:
2451 result |= swizzle_bit[1] << swizzle_shift[i];
2452 break;
2453 case PIPE_SWIZZLE_Z:
2454 result |= swizzle_bit[2] << swizzle_shift[i];
2455 break;
2456 case PIPE_SWIZZLE_W:
2457 result |= swizzle_bit[3] << swizzle_shift[i];
2458 break;
2459 case PIPE_SWIZZLE_0:
2460 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2461 break;
2462 case PIPE_SWIZZLE_1:
2463 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2464 break;
2465 default: /* PIPE_SWIZZLE_X */
2466 result |= swizzle_bit[0] << swizzle_shift[i];
2467 }
2468 }
2469 return result;
2470 }
2471
2472 /* texture format translate */
2473 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2474 enum pipe_format format,
2475 const unsigned char *swizzle_view,
2476 uint32_t *word4_p, uint32_t *yuv_format_p,
2477 bool do_endian_swap)
2478 {
2479 struct r600_screen *rscreen = (struct r600_screen *)screen;
2480 uint32_t result = 0, word4 = 0, yuv_format = 0;
2481 const struct util_format_description *desc;
2482 boolean uniform = TRUE;
2483 bool is_srgb_valid = FALSE;
2484 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2485 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2486 const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
2487 const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
2488 const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
2489
2490 int i;
2491 const uint32_t sign_bit[4] = {
2492 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2493 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2494 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2495 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2496 };
2497
2498 /* Need to replace the specified texture formats in case of big-endian.
2499 * These formats are formats that have channels with number of bits
2500 * not divisible by 8.
2501 * Mesa conversion functions don't swap bits for those formats, and because
2502 * we transmit this over a serial bus to the GPU (PCIe), the
2503 * bit-endianess is important!!!
2504 * In case we have an "opposite" format, just use that for the swizzling
2505 * information. If we don't have such an "opposite" format, we need
2506 * to use a fixed swizzle info instead (see below)
2507 */
2508 if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
2509 format = PIPE_FORMAT_A4R4_UNORM;
2510
2511 desc = util_format_description(format);
2512 if (!desc)
2513 goto out_unknown;
2514
2515 /* Depth and stencil swizzling is handled separately. */
2516 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2517 /* Need to check for specific texture formats that don't have
2518 * an "opposite" format we can use. For those formats, we directly
2519 * specify the swizzling, which is the LE swizzling as defined in
2520 * u_format.csv
2521 */
2522 if (do_endian_swap) {
2523 if (format == PIPE_FORMAT_L4A4_UNORM)
2524 word4 |= r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, FALSE);
2525 else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
2526 word4 |= r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, FALSE);
2527 else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || format == PIPE_FORMAT_B5G6R5_UNORM)
2528 word4 |= r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, FALSE);
2529 else
2530 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2531 } else {
2532 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2533 }
2534 }
2535
2536 /* Colorspace (return non-RGB formats directly). */
2537 switch (desc->colorspace) {
2538 /* Depth stencil formats */
2539 case UTIL_FORMAT_COLORSPACE_ZS:
2540 switch (format) {
2541 /* Depth sampler formats. */
2542 case PIPE_FORMAT_Z16_UNORM:
2543 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2544 result = FMT_16;
2545 goto out_word4;
2546 case PIPE_FORMAT_Z24X8_UNORM:
2547 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2548 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2549 result = FMT_8_24;
2550 goto out_word4;
2551 case PIPE_FORMAT_X8Z24_UNORM:
2552 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2553 if (rscreen->b.chip_class < EVERGREEN)
2554 goto out_unknown;
2555 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2556 result = FMT_24_8;
2557 goto out_word4;
2558 case PIPE_FORMAT_Z32_FLOAT:
2559 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2560 result = FMT_32_FLOAT;
2561 goto out_word4;
2562 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2563 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2564 result = FMT_X24_8_32_FLOAT;
2565 goto out_word4;
2566 /* Stencil sampler formats. */
2567 case PIPE_FORMAT_S8_UINT:
2568 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2569 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2570 result = FMT_8;
2571 goto out_word4;
2572 case PIPE_FORMAT_X24S8_UINT:
2573 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2574 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2575 result = FMT_8_24;
2576 goto out_word4;
2577 case PIPE_FORMAT_S8X24_UINT:
2578 if (rscreen->b.chip_class < EVERGREEN)
2579 goto out_unknown;
2580 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2581 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2582 result = FMT_24_8;
2583 goto out_word4;
2584 case PIPE_FORMAT_X32_S8X24_UINT:
2585 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2586 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2587 result = FMT_X24_8_32_FLOAT;
2588 goto out_word4;
2589 default:
2590 goto out_unknown;
2591 }
2592
2593 case UTIL_FORMAT_COLORSPACE_YUV:
2594 yuv_format |= (1 << 30);
2595 switch (format) {
2596 case PIPE_FORMAT_UYVY:
2597 case PIPE_FORMAT_YUYV:
2598 default:
2599 break;
2600 }
2601 goto out_unknown; /* XXX */
2602
2603 case UTIL_FORMAT_COLORSPACE_SRGB:
2604 word4 |= S_038010_FORCE_DEGAMMA(1);
2605 break;
2606
2607 default:
2608 break;
2609 }
2610
2611 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2612 switch (format) {
2613 case PIPE_FORMAT_RGTC1_SNORM:
2614 case PIPE_FORMAT_LATC1_SNORM:
2615 word4 |= sign_bit[0];
2616 case PIPE_FORMAT_RGTC1_UNORM:
2617 case PIPE_FORMAT_LATC1_UNORM:
2618 result = FMT_BC4;
2619 goto out_word4;
2620 case PIPE_FORMAT_RGTC2_SNORM:
2621 case PIPE_FORMAT_LATC2_SNORM:
2622 word4 |= sign_bit[0] | sign_bit[1];
2623 case PIPE_FORMAT_RGTC2_UNORM:
2624 case PIPE_FORMAT_LATC2_UNORM:
2625 result = FMT_BC5;
2626 goto out_word4;
2627 default:
2628 goto out_unknown;
2629 }
2630 }
2631
2632 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2633 switch (format) {
2634 case PIPE_FORMAT_DXT1_RGB:
2635 case PIPE_FORMAT_DXT1_RGBA:
2636 case PIPE_FORMAT_DXT1_SRGB:
2637 case PIPE_FORMAT_DXT1_SRGBA:
2638 result = FMT_BC1;
2639 is_srgb_valid = TRUE;
2640 goto out_word4;
2641 case PIPE_FORMAT_DXT3_RGBA:
2642 case PIPE_FORMAT_DXT3_SRGBA:
2643 result = FMT_BC2;
2644 is_srgb_valid = TRUE;
2645 goto out_word4;
2646 case PIPE_FORMAT_DXT5_RGBA:
2647 case PIPE_FORMAT_DXT5_SRGBA:
2648 result = FMT_BC3;
2649 is_srgb_valid = TRUE;
2650 goto out_word4;
2651 default:
2652 goto out_unknown;
2653 }
2654 }
2655
2656 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2657 if (rscreen->b.chip_class < EVERGREEN)
2658 goto out_unknown;
2659
2660 switch (format) {
2661 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2662 case PIPE_FORMAT_BPTC_SRGBA:
2663 result = FMT_BC7;
2664 is_srgb_valid = TRUE;
2665 goto out_word4;
2666 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2667 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2668 /* fall through */
2669 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2670 result = FMT_BC6;
2671 goto out_word4;
2672 default:
2673 goto out_unknown;
2674 }
2675 }
2676
2677 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2678 switch (format) {
2679 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2680 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2681 result = FMT_GB_GR;
2682 goto out_word4;
2683 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2684 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2685 result = FMT_BG_RG;
2686 goto out_word4;
2687 default:
2688 goto out_unknown;
2689 }
2690 }
2691
2692 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2693 result = FMT_5_9_9_9_SHAREDEXP;
2694 goto out_word4;
2695 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2696 result = FMT_10_11_11_FLOAT;
2697 goto out_word4;
2698 }
2699
2700
2701 for (i = 0; i < desc->nr_channels; i++) {
2702 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2703 word4 |= sign_bit[i];
2704 }
2705 }
2706
2707 /* R8G8Bx_SNORM - XXX CxV8U8 */
2708
2709 /* See whether the components are of the same size. */
2710 for (i = 1; i < desc->nr_channels; i++) {
2711 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2712 }
2713
2714 /* Non-uniform formats. */
2715 if (!uniform) {
2716 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2717 desc->channel[0].pure_integer)
2718 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2719 switch(desc->nr_channels) {
2720 case 3:
2721 if (desc->channel[0].size == 5 &&
2722 desc->channel[1].size == 6 &&
2723 desc->channel[2].size == 5) {
2724 result = FMT_5_6_5;
2725 goto out_word4;
2726 }
2727 goto out_unknown;
2728 case 4:
2729 if (desc->channel[0].size == 5 &&
2730 desc->channel[1].size == 5 &&
2731 desc->channel[2].size == 5 &&
2732 desc->channel[3].size == 1) {
2733 result = FMT_1_5_5_5;
2734 goto out_word4;
2735 }
2736 if (desc->channel[0].size == 10 &&
2737 desc->channel[1].size == 10 &&
2738 desc->channel[2].size == 10 &&
2739 desc->channel[3].size == 2) {
2740 result = FMT_2_10_10_10;
2741 goto out_word4;
2742 }
2743 goto out_unknown;
2744 }
2745 goto out_unknown;
2746 }
2747
2748 /* Find the first non-VOID channel. */
2749 for (i = 0; i < 4; i++) {
2750 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2751 break;
2752 }
2753 }
2754
2755 if (i == 4)
2756 goto out_unknown;
2757
2758 /* uniform formats */
2759 switch (desc->channel[i].type) {
2760 case UTIL_FORMAT_TYPE_UNSIGNED:
2761 case UTIL_FORMAT_TYPE_SIGNED:
2762 #if 0
2763 if (!desc->channel[i].normalized &&
2764 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2765 goto out_unknown;
2766 }
2767 #endif
2768 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2769 desc->channel[i].pure_integer)
2770 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2771
2772 switch (desc->channel[i].size) {
2773 case 4:
2774 switch (desc->nr_channels) {
2775 case 2:
2776 result = FMT_4_4;
2777 goto out_word4;
2778 case 4:
2779 result = FMT_4_4_4_4;
2780 goto out_word4;
2781 }
2782 goto out_unknown;
2783 case 8:
2784 switch (desc->nr_channels) {
2785 case 1:
2786 result = FMT_8;
2787 goto out_word4;
2788 case 2:
2789 result = FMT_8_8;
2790 goto out_word4;
2791 case 4:
2792 result = FMT_8_8_8_8;
2793 is_srgb_valid = TRUE;
2794 goto out_word4;
2795 }
2796 goto out_unknown;
2797 case 16:
2798 switch (desc->nr_channels) {
2799 case 1:
2800 result = FMT_16;
2801 goto out_word4;
2802 case 2:
2803 result = FMT_16_16;
2804 goto out_word4;
2805 case 4:
2806 result = FMT_16_16_16_16;
2807 goto out_word4;
2808 }
2809 goto out_unknown;
2810 case 32:
2811 switch (desc->nr_channels) {
2812 case 1:
2813 result = FMT_32;
2814 goto out_word4;
2815 case 2:
2816 result = FMT_32_32;
2817 goto out_word4;
2818 case 4:
2819 result = FMT_32_32_32_32;
2820 goto out_word4;
2821 }
2822 }
2823 goto out_unknown;
2824
2825 case UTIL_FORMAT_TYPE_FLOAT:
2826 switch (desc->channel[i].size) {
2827 case 16:
2828 switch (desc->nr_channels) {
2829 case 1:
2830 result = FMT_16_FLOAT;
2831 goto out_word4;
2832 case 2:
2833 result = FMT_16_16_FLOAT;
2834 goto out_word4;
2835 case 4:
2836 result = FMT_16_16_16_16_FLOAT;
2837 goto out_word4;
2838 }
2839 goto out_unknown;
2840 case 32:
2841 switch (desc->nr_channels) {
2842 case 1:
2843 result = FMT_32_FLOAT;
2844 goto out_word4;
2845 case 2:
2846 result = FMT_32_32_FLOAT;
2847 goto out_word4;
2848 case 4:
2849 result = FMT_32_32_32_32_FLOAT;
2850 goto out_word4;
2851 }
2852 }
2853 goto out_unknown;
2854 }
2855
2856 out_word4:
2857
2858 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2859 return ~0;
2860 if (word4_p)
2861 *word4_p = word4;
2862 if (yuv_format_p)
2863 *yuv_format_p = yuv_format;
2864 return result;
2865 out_unknown:
2866 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2867 return ~0;
2868 }
2869
2870 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
2871 bool do_endian_swap)
2872 {
2873 const struct util_format_description *desc = util_format_description(format);
2874 int channel = util_format_get_first_non_void_channel(format);
2875 bool is_float;
2876 if (!desc)
2877 return ~0U;
2878
2879 #define HAS_SIZE(x,y,z,w) \
2880 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2881 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2882
2883 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2884 return V_0280A0_COLOR_10_11_11_FLOAT;
2885
2886 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2887 channel == -1)
2888 return ~0U;
2889
2890 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2891
2892 switch (desc->nr_channels) {
2893 case 1:
2894 switch (desc->channel[0].size) {
2895 case 8:
2896 return V_0280A0_COLOR_8;
2897 case 16:
2898 if (is_float)
2899 return V_0280A0_COLOR_16_FLOAT;
2900 else
2901 return V_0280A0_COLOR_16;
2902 case 32:
2903 if (is_float)
2904 return V_0280A0_COLOR_32_FLOAT;
2905 else
2906 return V_0280A0_COLOR_32;
2907 }
2908 break;
2909 case 2:
2910 if (desc->channel[0].size == desc->channel[1].size) {
2911 switch (desc->channel[0].size) {
2912 case 4:
2913 if (chip <= R700)
2914 return V_0280A0_COLOR_4_4;
2915 else
2916 return ~0U; /* removed on Evergreen */
2917 case 8:
2918 return V_0280A0_COLOR_8_8;
2919 case 16:
2920 if (is_float)
2921 return V_0280A0_COLOR_16_16_FLOAT;
2922 else
2923 return V_0280A0_COLOR_16_16;
2924 case 32:
2925 if (is_float)
2926 return V_0280A0_COLOR_32_32_FLOAT;
2927 else
2928 return V_0280A0_COLOR_32_32;
2929 }
2930 } else if (HAS_SIZE(8,24,0,0)) {
2931 return (do_endian_swap ? V_0280A0_COLOR_8_24 : V_0280A0_COLOR_24_8);
2932 } else if (HAS_SIZE(24,8,0,0)) {
2933 return V_0280A0_COLOR_8_24;
2934 }
2935 break;
2936 case 3:
2937 if (HAS_SIZE(5,6,5,0)) {
2938 return V_0280A0_COLOR_5_6_5;
2939 } else if (HAS_SIZE(32,8,24,0)) {
2940 return V_0280A0_COLOR_X24_8_32_FLOAT;
2941 }
2942 break;
2943 case 4:
2944 if (desc->channel[0].size == desc->channel[1].size &&
2945 desc->channel[0].size == desc->channel[2].size &&
2946 desc->channel[0].size == desc->channel[3].size) {
2947 switch (desc->channel[0].size) {
2948 case 4:
2949 return V_0280A0_COLOR_4_4_4_4;
2950 case 8:
2951 return V_0280A0_COLOR_8_8_8_8;
2952 case 16:
2953 if (is_float)
2954 return V_0280A0_COLOR_16_16_16_16_FLOAT;
2955 else
2956 return V_0280A0_COLOR_16_16_16_16;
2957 case 32:
2958 if (is_float)
2959 return V_0280A0_COLOR_32_32_32_32_FLOAT;
2960 else
2961 return V_0280A0_COLOR_32_32_32_32;
2962 }
2963 } else if (HAS_SIZE(5,5,5,1)) {
2964 return V_0280A0_COLOR_1_5_5_5;
2965 } else if (HAS_SIZE(10,10,10,2)) {
2966 return V_0280A0_COLOR_2_10_10_10;
2967 }
2968 break;
2969 }
2970 return ~0U;
2971 }
2972
2973 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
2974 {
2975 if (R600_BIG_ENDIAN) {
2976 switch(colorformat) {
2977 /* 8-bit buffers. */
2978 case V_0280A0_COLOR_4_4:
2979 case V_0280A0_COLOR_8:
2980 return ENDIAN_NONE;
2981
2982 /* 16-bit buffers. */
2983 case V_0280A0_COLOR_8_8:
2984 /*
2985 * No need to do endian swaps on array formats,
2986 * as mesa<-->pipe formats conversion take into account
2987 * the endianess
2988 */
2989 return ENDIAN_NONE;
2990
2991 case V_0280A0_COLOR_5_6_5:
2992 case V_0280A0_COLOR_1_5_5_5:
2993 case V_0280A0_COLOR_4_4_4_4:
2994 case V_0280A0_COLOR_16:
2995 return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
2996
2997 /* 32-bit buffers. */
2998 case V_0280A0_COLOR_8_8_8_8:
2999 /*
3000 * No need to do endian swaps on array formats,
3001 * as mesa<-->pipe formats conversion take into account
3002 * the endianess
3003 */
3004 return ENDIAN_NONE;
3005
3006 case V_0280A0_COLOR_2_10_10_10:
3007 case V_0280A0_COLOR_8_24:
3008 case V_0280A0_COLOR_24_8:
3009 case V_0280A0_COLOR_32_FLOAT:
3010 return (do_endian_swap ? ENDIAN_8IN32 : ENDIAN_NONE);
3011
3012 case V_0280A0_COLOR_16_16_FLOAT:
3013 case V_0280A0_COLOR_16_16:
3014 return ENDIAN_8IN16;
3015
3016 /* 64-bit buffers. */
3017 case V_0280A0_COLOR_16_16_16_16:
3018 case V_0280A0_COLOR_16_16_16_16_FLOAT:
3019 return ENDIAN_8IN16;
3020
3021 case V_0280A0_COLOR_32_32_FLOAT:
3022 case V_0280A0_COLOR_32_32:
3023 case V_0280A0_COLOR_X24_8_32_FLOAT:
3024 return ENDIAN_8IN32;
3025
3026 /* 128-bit buffers. */
3027 case V_0280A0_COLOR_32_32_32_32_FLOAT:
3028 case V_0280A0_COLOR_32_32_32_32:
3029 return ENDIAN_8IN32;
3030 default:
3031 return ENDIAN_NONE; /* Unsupported. */
3032 }
3033 } else {
3034 return ENDIAN_NONE;
3035 }
3036 }
3037
3038 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
3039 {
3040 struct r600_context *rctx = (struct r600_context*)ctx;
3041 struct r600_resource *rbuffer = r600_resource(buf);
3042 unsigned i, shader, mask;
3043 struct r600_pipe_sampler_view *view;
3044
3045 /* Reallocate the buffer in the same pipe_resource. */
3046 r600_alloc_resource(&rctx->screen->b, rbuffer);
3047
3048 /* We changed the buffer, now we need to bind it where the old one was bound. */
3049 /* Vertex buffers. */
3050 mask = rctx->vertex_buffer_state.enabled_mask;
3051 while (mask) {
3052 i = u_bit_scan(&mask);
3053 if (rctx->vertex_buffer_state.vb[i].buffer.resource == &rbuffer->b.b) {
3054 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
3055 r600_vertex_buffers_dirty(rctx);
3056 }
3057 }
3058 /* Streamout buffers. */
3059 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
3060 if (rctx->b.streamout.targets[i] &&
3061 rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
3062 if (rctx->b.streamout.begin_emitted) {
3063 r600_emit_streamout_end(&rctx->b);
3064 }
3065 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
3066 r600_streamout_buffers_dirty(&rctx->b);
3067 }
3068 }
3069
3070 /* Constant buffers. */
3071 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3072 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
3073 bool found = false;
3074 uint32_t mask = state->enabled_mask;
3075
3076 while (mask) {
3077 unsigned i = u_bit_scan(&mask);
3078 if (state->cb[i].buffer == &rbuffer->b.b) {
3079 found = true;
3080 state->dirty_mask |= 1 << i;
3081 }
3082 }
3083 if (found) {
3084 r600_constant_buffers_dirty(rctx, state);
3085 }
3086 }
3087
3088 /* Texture buffer objects - update the virtual addresses in descriptors. */
3089 LIST_FOR_EACH_ENTRY(view, &rctx->texture_buffers, list) {
3090 if (view->base.texture == &rbuffer->b.b) {
3091 uint64_t offset = view->base.u.buf.offset;
3092 uint64_t va = rbuffer->gpu_address + offset;
3093
3094 view->tex_resource_words[0] = va;
3095 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
3096 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
3097 }
3098 }
3099 /* Texture buffer objects - make bindings dirty if needed. */
3100 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3101 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
3102 bool found = false;
3103 uint32_t mask = state->enabled_mask;
3104
3105 while (mask) {
3106 unsigned i = u_bit_scan(&mask);
3107 if (state->views[i]->base.texture == &rbuffer->b.b) {
3108 found = true;
3109 state->dirty_mask |= 1 << i;
3110 }
3111 }
3112 if (found) {
3113 r600_sampler_views_dirty(rctx, state);
3114 }
3115 }
3116
3117 /* SSBOs */
3118 struct r600_image_state *istate = &rctx->fragment_buffers;
3119 {
3120 uint32_t mask = istate->enabled_mask;
3121 bool found = false;
3122 while (mask) {
3123 unsigned i = u_bit_scan(&mask);
3124 if (istate->views[i].base.resource == &rbuffer->b.b) {
3125 found = true;
3126 istate->dirty_mask |= 1 << i;
3127 }
3128 }
3129 if (found) {
3130 r600_mark_atom_dirty(rctx, &istate->atom);
3131 }
3132 }
3133
3134 }
3135
3136 static void r600_set_active_query_state(struct pipe_context *ctx, boolean enable)
3137 {
3138 struct r600_context *rctx = (struct r600_context*)ctx;
3139
3140 /* Pipeline stat & streamout queries. */
3141 if (enable) {
3142 rctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
3143 rctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
3144 } else {
3145 rctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
3146 rctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
3147 }
3148
3149 /* Occlusion queries. */
3150 if (rctx->db_misc_state.occlusion_queries_disabled != !enable) {
3151 rctx->db_misc_state.occlusion_queries_disabled = !enable;
3152 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3153 }
3154 }
3155
3156 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3157 bool include_draw_vbo)
3158 {
3159 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
3160 }
3161
3162 /* keep this at the end of this file, please */
3163 void r600_init_common_state_functions(struct r600_context *rctx)
3164 {
3165 rctx->b.b.create_fs_state = r600_create_ps_state;
3166 rctx->b.b.create_vs_state = r600_create_vs_state;
3167 rctx->b.b.create_gs_state = r600_create_gs_state;
3168 rctx->b.b.create_tcs_state = r600_create_tcs_state;
3169 rctx->b.b.create_tes_state = r600_create_tes_state;
3170 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
3171 rctx->b.b.bind_blend_state = r600_bind_blend_state;
3172 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
3173 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
3174 rctx->b.b.bind_fs_state = r600_bind_ps_state;
3175 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
3176 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
3177 rctx->b.b.bind_vs_state = r600_bind_vs_state;
3178 rctx->b.b.bind_gs_state = r600_bind_gs_state;
3179 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
3180 rctx->b.b.bind_tes_state = r600_bind_tes_state;
3181 rctx->b.b.delete_blend_state = r600_delete_blend_state;
3182 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
3183 rctx->b.b.delete_fs_state = r600_delete_ps_state;
3184 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
3185 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
3186 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
3187 rctx->b.b.delete_vs_state = r600_delete_vs_state;
3188 rctx->b.b.delete_gs_state = r600_delete_gs_state;
3189 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
3190 rctx->b.b.delete_tes_state = r600_delete_tes_state;
3191 rctx->b.b.set_blend_color = r600_set_blend_color;
3192 rctx->b.b.set_clip_state = r600_set_clip_state;
3193 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
3194 rctx->b.b.set_sample_mask = r600_set_sample_mask;
3195 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
3196 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
3197 rctx->b.b.set_sampler_views = r600_set_sampler_views;
3198 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
3199 rctx->b.b.memory_barrier = r600_memory_barrier;
3200 rctx->b.b.texture_barrier = r600_texture_barrier;
3201 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
3202 rctx->b.b.set_active_query_state = r600_set_active_query_state;
3203 rctx->b.b.draw_vbo = r600_draw_vbo;
3204 rctx->b.invalidate_buffer = r600_invalidate_buffer;
3205 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
3206 }