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[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 assert(!cb->buf);
43 cb->buf = CALLOC(1, 4 * num_dw);
44 cb->max_num_dw = num_dw;
45 }
46
47 void r600_release_command_buffer(struct r600_command_buffer *cb)
48 {
49 FREE(cb->buf);
50 }
51
52 void r600_add_atom(struct r600_context *rctx,
53 struct r600_atom *atom,
54 unsigned id)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->id = id;
60 }
61
62 void r600_init_atom(struct r600_context *rctx,
63 struct r600_atom *atom,
64 unsigned id,
65 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
66 unsigned num_dw)
67 {
68 atom->emit = (void*)emit;
69 atom->num_dw = num_dw;
70 r600_add_atom(rctx, atom, id);
71 }
72
73 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 r600_emit_command_buffer(rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
76 }
77
78 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
79 {
80 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
81 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
82 unsigned alpha_ref = a->sx_alpha_ref;
83
84 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
85 alpha_ref &= ~0x1FFF;
86 }
87
88 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
89 a->sx_alpha_test_control |
90 S_028410_ALPHA_TEST_BYPASS(a->bypass));
91 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
92 }
93
94 static void r600_texture_barrier(struct pipe_context *ctx)
95 {
96 struct r600_context *rctx = (struct r600_context *)ctx;
97
98 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
99 R600_CONTEXT_FLUSH_AND_INV_CB |
100 R600_CONTEXT_FLUSH_AND_INV |
101 R600_CONTEXT_WAIT_3D_IDLE;
102 }
103
104 static unsigned r600_conv_pipe_prim(unsigned prim)
105 {
106 static const unsigned prim_conv[] = {
107 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
108 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
109 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
110 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
111 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
112 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
113 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
114 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
115 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
116 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
117 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
118 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
119 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
120 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
121 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
122 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
123 };
124 assert(prim < Elements(prim_conv));
125 return prim_conv[prim];
126 }
127
128 unsigned r600_conv_prim_to_gs_out(unsigned mode)
129 {
130 static const int prim_conv[] = {
131 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
132 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
133 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
134 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
135 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
136 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
137 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
138 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
139 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
140 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
141 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
145 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
146 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
147 };
148 assert(mode < Elements(prim_conv));
149
150 return prim_conv[mode];
151 }
152
153 /* common state between evergreen and r600 */
154
155 static void r600_bind_blend_state_internal(struct r600_context *rctx,
156 struct r600_blend_state *blend, bool blend_disable)
157 {
158 unsigned color_control;
159 bool update_cb = false;
160
161 rctx->alpha_to_one = blend->alpha_to_one;
162 rctx->dual_src_blend = blend->dual_src_blend;
163
164 if (!blend_disable) {
165 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
166 color_control = blend->cb_color_control;
167 } else {
168 /* Blending is disabled. */
169 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
170 color_control = blend->cb_color_control_no_blend;
171 }
172
173 /* Update derived states. */
174 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
175 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
176 update_cb = true;
177 }
178 if (rctx->b.chip_class <= R700 &&
179 rctx->cb_misc_state.cb_color_control != color_control) {
180 rctx->cb_misc_state.cb_color_control = color_control;
181 update_cb = true;
182 }
183 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
184 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
185 update_cb = true;
186 }
187 if (update_cb) {
188 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
189 }
190 }
191
192 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
193 {
194 struct r600_context *rctx = (struct r600_context *)ctx;
195 struct r600_blend_state *blend = (struct r600_blend_state *)state;
196
197 if (!blend) {
198 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
199 return;
200 }
201
202 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
203 }
204
205 static void r600_set_blend_color(struct pipe_context *ctx,
206 const struct pipe_blend_color *state)
207 {
208 struct r600_context *rctx = (struct r600_context *)ctx;
209
210 rctx->blend_color.state = *state;
211 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
212 }
213
214 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
215 {
216 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
217 struct pipe_blend_color *state = &rctx->blend_color.state;
218
219 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
220 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
221 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
222 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
223 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
224 }
225
226 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
227 {
228 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
229 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
230
231 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
232 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
233 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
234 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
235 if (a->last_draw_was_indirect) {
236 a->last_draw_was_indirect = false;
237 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
238 }
239 }
240
241 static void r600_set_clip_state(struct pipe_context *ctx,
242 const struct pipe_clip_state *state)
243 {
244 struct r600_context *rctx = (struct r600_context *)ctx;
245
246 rctx->clip_state.state = *state;
247 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
248 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
249 }
250
251 static void r600_set_stencil_ref(struct pipe_context *ctx,
252 const struct r600_stencil_ref *state)
253 {
254 struct r600_context *rctx = (struct r600_context *)ctx;
255
256 rctx->stencil_ref.state = *state;
257 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
258 }
259
260 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
261 {
262 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
263 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
264
265 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
266 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
267 S_028430_STENCILREF(a->state.ref_value[0]) |
268 S_028430_STENCILMASK(a->state.valuemask[0]) |
269 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
270 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
271 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
272 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
273 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
274 }
275
276 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
277 const struct pipe_stencil_ref *state)
278 {
279 struct r600_context *rctx = (struct r600_context *)ctx;
280 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
281 struct r600_stencil_ref ref;
282
283 rctx->stencil_ref.pipe_state = *state;
284
285 if (!dsa)
286 return;
287
288 ref.ref_value[0] = state->ref_value[0];
289 ref.ref_value[1] = state->ref_value[1];
290 ref.valuemask[0] = dsa->valuemask[0];
291 ref.valuemask[1] = dsa->valuemask[1];
292 ref.writemask[0] = dsa->writemask[0];
293 ref.writemask[1] = dsa->writemask[1];
294
295 r600_set_stencil_ref(ctx, &ref);
296 }
297
298 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
299 {
300 struct r600_context *rctx = (struct r600_context *)ctx;
301 struct r600_dsa_state *dsa = state;
302 struct r600_stencil_ref ref;
303
304 if (!state) {
305 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
306 return;
307 }
308
309 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
310
311 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
312 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
313 ref.valuemask[0] = dsa->valuemask[0];
314 ref.valuemask[1] = dsa->valuemask[1];
315 ref.writemask[0] = dsa->writemask[0];
316 ref.writemask[1] = dsa->writemask[1];
317 if (rctx->zwritemask != dsa->zwritemask) {
318 rctx->zwritemask = dsa->zwritemask;
319 if (rctx->b.chip_class >= EVERGREEN) {
320 /* work around some issue when not writing to zbuffer
321 * we are having lockup on evergreen so do not enable
322 * hyperz when not writing zbuffer
323 */
324 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
325 }
326 }
327
328 r600_set_stencil_ref(ctx, &ref);
329
330 /* Update alphatest state. */
331 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
332 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
333 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
334 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
335 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
336 }
337 }
338
339 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
340 {
341 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
342 struct r600_context *rctx = (struct r600_context *)ctx;
343
344 if (!state)
345 return;
346
347 rctx->rasterizer = rs;
348
349 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
350
351 if (rs->offset_enable &&
352 (rs->offset_units != rctx->poly_offset_state.offset_units ||
353 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
354 rctx->poly_offset_state.offset_units = rs->offset_units;
355 rctx->poly_offset_state.offset_scale = rs->offset_scale;
356 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
357 }
358
359 /* Update clip_misc_state. */
360 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
361 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
362 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
363 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
364 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
365 }
366
367 /* Workaround for a missing scissor enable on r600. */
368 if (rctx->b.chip_class == R600 &&
369 rs->scissor_enable != rctx->scissor.enable) {
370 rctx->scissor.enable = rs->scissor_enable;
371 rctx->scissor.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
372 rctx->scissor.atom.num_dw = R600_MAX_VIEWPORTS * 4;
373 r600_mark_atom_dirty(rctx, &rctx->scissor.atom);
374 }
375
376 /* Re-emit PA_SC_LINE_STIPPLE. */
377 rctx->last_primitive_type = -1;
378 }
379
380 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
381 {
382 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
383
384 r600_release_command_buffer(&rs->buffer);
385 FREE(rs);
386 }
387
388 static void r600_sampler_view_destroy(struct pipe_context *ctx,
389 struct pipe_sampler_view *state)
390 {
391 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
392
393 if (view->tex_resource->gpu_address &&
394 view->tex_resource->b.b.target == PIPE_BUFFER)
395 LIST_DELINIT(&view->list);
396
397 pipe_resource_reference(&state->texture, NULL);
398 FREE(view);
399 }
400
401 void r600_sampler_states_dirty(struct r600_context *rctx,
402 struct r600_sampler_states *state)
403 {
404 if (state->dirty_mask) {
405 if (state->dirty_mask & state->has_bordercolor_mask) {
406 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
407 }
408 state->atom.num_dw =
409 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
410 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
411 r600_mark_atom_dirty(rctx, &state->atom);
412 }
413 }
414
415 static void r600_bind_sampler_states(struct pipe_context *pipe,
416 unsigned shader,
417 unsigned start,
418 unsigned count, void **states)
419 {
420 struct r600_context *rctx = (struct r600_context *)pipe;
421 struct r600_textures_info *dst = &rctx->samplers[shader];
422 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
423 int seamless_cube_map = -1;
424 unsigned i;
425 /* This sets 1-bit for states with index >= count. */
426 uint32_t disable_mask = ~((1ull << count) - 1);
427 /* These are the new states set by this function. */
428 uint32_t new_mask = 0;
429
430 assert(start == 0); /* XXX fix below */
431
432 if (!states) {
433 disable_mask = ~0u;
434 count = 0;
435 }
436
437 for (i = 0; i < count; i++) {
438 struct r600_pipe_sampler_state *rstate = rstates[i];
439
440 if (rstate == dst->states.states[i]) {
441 continue;
442 }
443
444 if (rstate) {
445 if (rstate->border_color_use) {
446 dst->states.has_bordercolor_mask |= 1 << i;
447 } else {
448 dst->states.has_bordercolor_mask &= ~(1 << i);
449 }
450 seamless_cube_map = rstate->seamless_cube_map;
451
452 new_mask |= 1 << i;
453 } else {
454 disable_mask |= 1 << i;
455 }
456 }
457
458 memcpy(dst->states.states, rstates, sizeof(void*) * count);
459 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
460
461 dst->states.enabled_mask &= ~disable_mask;
462 dst->states.dirty_mask &= dst->states.enabled_mask;
463 dst->states.enabled_mask |= new_mask;
464 dst->states.dirty_mask |= new_mask;
465 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
466
467 r600_sampler_states_dirty(rctx, &dst->states);
468
469 /* Seamless cubemap state. */
470 if (rctx->b.chip_class <= R700 &&
471 seamless_cube_map != -1 &&
472 seamless_cube_map != rctx->seamless_cube_map.enabled) {
473 /* change in TA_CNTL_AUX need a pipeline flush */
474 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
475 rctx->seamless_cube_map.enabled = seamless_cube_map;
476 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
477 }
478 }
479
480 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
481 {
482 free(state);
483 }
484
485 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
486 {
487 struct r600_context *rctx = (struct r600_context *)ctx;
488 struct r600_blend_state *blend = (struct r600_blend_state*)state;
489
490 if (rctx->blend_state.cso == state) {
491 ctx->bind_blend_state(ctx, NULL);
492 }
493
494 r600_release_command_buffer(&blend->buffer);
495 r600_release_command_buffer(&blend->buffer_no_blend);
496 FREE(blend);
497 }
498
499 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
500 {
501 struct r600_context *rctx = (struct r600_context *)ctx;
502 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
503
504 if (rctx->dsa_state.cso == state) {
505 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
506 }
507
508 r600_release_command_buffer(&dsa->buffer);
509 free(dsa);
510 }
511
512 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
513 {
514 struct r600_context *rctx = (struct r600_context *)ctx;
515
516 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
517 }
518
519 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
520 {
521 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
522 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
523 FREE(shader);
524 }
525
526 static void r600_set_index_buffer(struct pipe_context *ctx,
527 const struct pipe_index_buffer *ib)
528 {
529 struct r600_context *rctx = (struct r600_context *)ctx;
530
531 if (ib) {
532 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
533 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
534 r600_context_add_resource_size(ctx, ib->buffer);
535 } else {
536 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
537 }
538 }
539
540 void r600_vertex_buffers_dirty(struct r600_context *rctx)
541 {
542 if (rctx->vertex_buffer_state.dirty_mask) {
543 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
544 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
545 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
546 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
547 }
548 }
549
550 static void r600_set_vertex_buffers(struct pipe_context *ctx,
551 unsigned start_slot, unsigned count,
552 const struct pipe_vertex_buffer *input)
553 {
554 struct r600_context *rctx = (struct r600_context *)ctx;
555 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
556 struct pipe_vertex_buffer *vb = state->vb + start_slot;
557 unsigned i;
558 uint32_t disable_mask = 0;
559 /* These are the new buffers set by this function. */
560 uint32_t new_buffer_mask = 0;
561
562 /* Set vertex buffers. */
563 if (input) {
564 for (i = 0; i < count; i++) {
565 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
566 if (input[i].buffer) {
567 vb[i].stride = input[i].stride;
568 vb[i].buffer_offset = input[i].buffer_offset;
569 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
570 new_buffer_mask |= 1 << i;
571 r600_context_add_resource_size(ctx, input[i].buffer);
572 } else {
573 pipe_resource_reference(&vb[i].buffer, NULL);
574 disable_mask |= 1 << i;
575 }
576 }
577 }
578 } else {
579 for (i = 0; i < count; i++) {
580 pipe_resource_reference(&vb[i].buffer, NULL);
581 }
582 disable_mask = ((1ull << count) - 1);
583 }
584
585 disable_mask <<= start_slot;
586 new_buffer_mask <<= start_slot;
587
588 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
589 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
590 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
591 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
592
593 r600_vertex_buffers_dirty(rctx);
594 }
595
596 void r600_sampler_views_dirty(struct r600_context *rctx,
597 struct r600_samplerview_state *state)
598 {
599 if (state->dirty_mask) {
600 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
601 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
602 util_bitcount(state->dirty_mask);
603 r600_mark_atom_dirty(rctx, &state->atom);
604 }
605 }
606
607 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
608 unsigned start, unsigned count,
609 struct pipe_sampler_view **views)
610 {
611 struct r600_context *rctx = (struct r600_context *) pipe;
612 struct r600_textures_info *dst = &rctx->samplers[shader];
613 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
614 uint32_t dirty_sampler_states_mask = 0;
615 unsigned i;
616 /* This sets 1-bit for textures with index >= count. */
617 uint32_t disable_mask = ~((1ull << count) - 1);
618 /* These are the new textures set by this function. */
619 uint32_t new_mask = 0;
620
621 /* Set textures with index >= count to NULL. */
622 uint32_t remaining_mask;
623
624 assert(start == 0); /* XXX fix below */
625
626 if (!views) {
627 disable_mask = ~0u;
628 count = 0;
629 }
630
631 remaining_mask = dst->views.enabled_mask & disable_mask;
632
633 while (remaining_mask) {
634 i = u_bit_scan(&remaining_mask);
635 assert(dst->views.views[i]);
636
637 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
638 }
639
640 for (i = 0; i < count; i++) {
641 if (rviews[i] == dst->views.views[i]) {
642 continue;
643 }
644
645 if (rviews[i]) {
646 struct r600_texture *rtex =
647 (struct r600_texture*)rviews[i]->base.texture;
648 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
649
650 if (!is_buffer && rtex->is_depth && !rtex->is_flushing_texture) {
651 dst->views.compressed_depthtex_mask |= 1 << i;
652 } else {
653 dst->views.compressed_depthtex_mask &= ~(1 << i);
654 }
655
656 /* Track compressed colorbuffers. */
657 if (!is_buffer && rtex->cmask.size) {
658 dst->views.compressed_colortex_mask |= 1 << i;
659 } else {
660 dst->views.compressed_colortex_mask &= ~(1 << i);
661 }
662
663 /* Changing from array to non-arrays textures and vice versa requires
664 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
665 if (rctx->b.chip_class <= R700 &&
666 (dst->states.enabled_mask & (1 << i)) &&
667 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
668 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
669 dirty_sampler_states_mask |= 1 << i;
670 }
671
672 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
673 new_mask |= 1 << i;
674 r600_context_add_resource_size(pipe, views[i]->texture);
675 } else {
676 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
677 disable_mask |= 1 << i;
678 }
679 }
680
681 dst->views.enabled_mask &= ~disable_mask;
682 dst->views.dirty_mask &= dst->views.enabled_mask;
683 dst->views.enabled_mask |= new_mask;
684 dst->views.dirty_mask |= new_mask;
685 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
686 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
687 dst->views.dirty_buffer_constants = TRUE;
688 r600_sampler_views_dirty(rctx, &dst->views);
689
690 if (dirty_sampler_states_mask) {
691 dst->states.dirty_mask |= dirty_sampler_states_mask;
692 r600_sampler_states_dirty(rctx, &dst->states);
693 }
694 }
695
696 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
697 {
698 uint32_t mask = views->enabled_mask;
699
700 while (mask) {
701 unsigned i = u_bit_scan(&mask);
702 struct pipe_resource *res = views->views[i]->base.texture;
703
704 if (res && res->target != PIPE_BUFFER) {
705 struct r600_texture *rtex = (struct r600_texture *)res;
706
707 if (rtex->cmask.size) {
708 views->compressed_colortex_mask |= 1 << i;
709 } else {
710 views->compressed_colortex_mask &= ~(1 << i);
711 }
712 }
713 }
714 }
715
716 static void r600_set_viewport_states(struct pipe_context *ctx,
717 unsigned start_slot,
718 unsigned num_viewports,
719 const struct pipe_viewport_state *state)
720 {
721 struct r600_context *rctx = (struct r600_context *)ctx;
722 struct r600_viewport_state *rstate = &rctx->viewport;
723 int i;
724
725 for (i = start_slot; i < start_slot + num_viewports; i++)
726 rstate->state[i] = state[i - start_slot];
727 rstate->dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
728 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 8;
729 r600_mark_atom_dirty(rctx, &rctx->viewport.atom);
730 }
731
732 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
733 {
734 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
735 struct r600_viewport_state *rstate = &rctx->viewport;
736 struct pipe_viewport_state *state;
737 uint32_t dirty_mask;
738 unsigned i, offset;
739
740 dirty_mask = rstate->dirty_mask;
741 while (dirty_mask != 0) {
742 i = u_bit_scan(&dirty_mask);
743 offset = i * 6 * 4;
744 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
745 state = &rstate->state[i];
746 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
747 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
748 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
749 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
750 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
751 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
752 }
753 rstate->dirty_mask = 0;
754 rstate->atom.num_dw = 0;
755 }
756
757 /* Compute the key for the hw shader variant */
758 static inline union r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
759 struct r600_pipe_shader_selector * sel)
760 {
761 struct r600_context *rctx = (struct r600_context *)ctx;
762 union r600_shader_key key;
763 memset(&key, 0, sizeof(key));
764
765 switch (sel->type) {
766 case PIPE_SHADER_VERTEX: {
767 key.vs.as_ls = (rctx->tes_shader != NULL);
768 if (!key.vs.as_ls)
769 key.vs.as_es = (rctx->gs_shader != NULL);
770
771 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
772 key.vs.as_gs_a = true;
773 key.vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
774 }
775 break;
776 }
777 case PIPE_SHADER_GEOMETRY:
778 break;
779 case PIPE_SHADER_FRAGMENT: {
780 key.ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
781 key.ps.alpha_to_one = rctx->alpha_to_one &&
782 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
783 !rctx->framebuffer.cb0_is_integer;
784 key.ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
785 /* Dual-source blending only makes sense with nr_cbufs == 1. */
786 if (key.ps.nr_cbufs == 1 && rctx->dual_src_blend)
787 key.ps.nr_cbufs = 2;
788 break;
789 }
790 case PIPE_SHADER_TESS_EVAL:
791 key.tes.as_es = (rctx->gs_shader != NULL);
792 break;
793 case PIPE_SHADER_TESS_CTRL:
794 key.tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
795 break;
796 default:
797 assert(0);
798 }
799
800 return key;
801 }
802
803 /* Select the hw shader variant depending on the current state.
804 * (*dirty) is set to 1 if current variant was changed */
805 static int r600_shader_select(struct pipe_context *ctx,
806 struct r600_pipe_shader_selector* sel,
807 bool *dirty)
808 {
809 union r600_shader_key key;
810 struct r600_pipe_shader * shader = NULL;
811 int r;
812
813 memset(&key, 0, sizeof(key));
814 key = r600_shader_selector_key(ctx, sel);
815
816 /* Check if we don't need to change anything.
817 * This path is also used for most shaders that don't need multiple
818 * variants, it will cost just a computation of the key and this
819 * test. */
820 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
821 return 0;
822 }
823
824 /* lookup if we have other variants in the list */
825 if (sel->num_shaders > 1) {
826 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
827
828 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
829 p = c;
830 c = c->next_variant;
831 }
832
833 if (c) {
834 p->next_variant = c->next_variant;
835 shader = c;
836 }
837 }
838
839 if (unlikely(!shader)) {
840 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
841 shader->selector = sel;
842
843 r = r600_pipe_shader_create(ctx, shader, key);
844 if (unlikely(r)) {
845 R600_ERR("Failed to build shader variant (type=%u) %d\n",
846 sel->type, r);
847 sel->current = NULL;
848 FREE(shader);
849 return r;
850 }
851
852 /* We don't know the value of nr_ps_max_color_exports until we built
853 * at least one variant, so we may need to recompute the key after
854 * building first variant. */
855 if (sel->type == PIPE_SHADER_FRAGMENT &&
856 sel->num_shaders == 0) {
857 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
858 key = r600_shader_selector_key(ctx, sel);
859 }
860
861 memcpy(&shader->key, &key, sizeof(key));
862 sel->num_shaders++;
863 }
864
865 if (dirty)
866 *dirty = true;
867
868 shader->next_variant = sel->current;
869 sel->current = shader;
870
871 return 0;
872 }
873
874 static void *r600_create_shader_state(struct pipe_context *ctx,
875 const struct pipe_shader_state *state,
876 unsigned pipe_shader_type)
877 {
878 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
879 int i;
880
881 sel->type = pipe_shader_type;
882 sel->tokens = tgsi_dup_tokens(state->tokens);
883 sel->so = state->stream_output;
884 tgsi_scan_shader(state->tokens, &sel->info);
885
886 switch (pipe_shader_type) {
887 case PIPE_SHADER_GEOMETRY:
888 sel->gs_output_prim =
889 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
890 sel->gs_max_out_vertices =
891 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
892 sel->gs_num_invocations =
893 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
894 break;
895 case PIPE_SHADER_VERTEX:
896 case PIPE_SHADER_TESS_CTRL:
897 sel->lds_patch_outputs_written_mask = 0;
898 sel->lds_outputs_written_mask = 0;
899
900 for (i = 0; i < sel->info.num_outputs; i++) {
901 unsigned name = sel->info.output_semantic_name[i];
902 unsigned index = sel->info.output_semantic_index[i];
903
904 switch (name) {
905 case TGSI_SEMANTIC_TESSINNER:
906 case TGSI_SEMANTIC_TESSOUTER:
907 case TGSI_SEMANTIC_PATCH:
908 sel->lds_patch_outputs_written_mask |=
909 1llu << r600_get_lds_unique_index(name, index);
910 break;
911 default:
912 sel->lds_outputs_written_mask |=
913 1llu << r600_get_lds_unique_index(name, index);
914 }
915 }
916 break;
917 default:
918 break;
919 }
920
921 return sel;
922 }
923
924 static void *r600_create_ps_state(struct pipe_context *ctx,
925 const struct pipe_shader_state *state)
926 {
927 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
928 }
929
930 static void *r600_create_vs_state(struct pipe_context *ctx,
931 const struct pipe_shader_state *state)
932 {
933 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
934 }
935
936 static void *r600_create_gs_state(struct pipe_context *ctx,
937 const struct pipe_shader_state *state)
938 {
939 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
940 }
941
942 static void *r600_create_tcs_state(struct pipe_context *ctx,
943 const struct pipe_shader_state *state)
944 {
945 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
946 }
947
948 static void *r600_create_tes_state(struct pipe_context *ctx,
949 const struct pipe_shader_state *state)
950 {
951 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
952 }
953
954 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
955 {
956 struct r600_context *rctx = (struct r600_context *)ctx;
957
958 if (!state)
959 state = rctx->dummy_pixel_shader;
960
961 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
962 }
963
964 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
965 {
966 struct r600_context *rctx = (struct r600_context *)ctx;
967
968 if (!state)
969 return;
970
971 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
972 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
973 }
974
975 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
976 {
977 struct r600_context *rctx = (struct r600_context *)ctx;
978
979 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
980
981 if (!state)
982 return;
983 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
984 }
985
986 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
987 {
988 struct r600_context *rctx = (struct r600_context *)ctx;
989
990 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
991 }
992
993 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
994 {
995 struct r600_context *rctx = (struct r600_context *)ctx;
996
997 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
998
999 if (!state)
1000 return;
1001 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1002 }
1003
1004 static void r600_delete_shader_selector(struct pipe_context *ctx,
1005 struct r600_pipe_shader_selector *sel)
1006 {
1007 struct r600_pipe_shader *p = sel->current, *c;
1008 while (p) {
1009 c = p->next_variant;
1010 r600_pipe_shader_destroy(ctx, p);
1011 free(p);
1012 p = c;
1013 }
1014
1015 free(sel->tokens);
1016 free(sel);
1017 }
1018
1019
1020 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1021 {
1022 struct r600_context *rctx = (struct r600_context *)ctx;
1023 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1024
1025 if (rctx->ps_shader == sel) {
1026 rctx->ps_shader = NULL;
1027 }
1028
1029 r600_delete_shader_selector(ctx, sel);
1030 }
1031
1032 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1033 {
1034 struct r600_context *rctx = (struct r600_context *)ctx;
1035 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1036
1037 if (rctx->vs_shader == sel) {
1038 rctx->vs_shader = NULL;
1039 }
1040
1041 r600_delete_shader_selector(ctx, sel);
1042 }
1043
1044
1045 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1046 {
1047 struct r600_context *rctx = (struct r600_context *)ctx;
1048 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1049
1050 if (rctx->gs_shader == sel) {
1051 rctx->gs_shader = NULL;
1052 }
1053
1054 r600_delete_shader_selector(ctx, sel);
1055 }
1056
1057 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1058 {
1059 struct r600_context *rctx = (struct r600_context *)ctx;
1060 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1061
1062 if (rctx->tcs_shader == sel) {
1063 rctx->tcs_shader = NULL;
1064 }
1065
1066 r600_delete_shader_selector(ctx, sel);
1067 }
1068
1069 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1070 {
1071 struct r600_context *rctx = (struct r600_context *)ctx;
1072 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1073
1074 if (rctx->tes_shader == sel) {
1075 rctx->tes_shader = NULL;
1076 }
1077
1078 r600_delete_shader_selector(ctx, sel);
1079 }
1080
1081 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1082 {
1083 if (state->dirty_mask) {
1084 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
1085 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1086 : util_bitcount(state->dirty_mask)*19;
1087 r600_mark_atom_dirty(rctx, &state->atom);
1088 }
1089 }
1090
1091 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1092 struct pipe_constant_buffer *input)
1093 {
1094 struct r600_context *rctx = (struct r600_context *)ctx;
1095 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1096 struct pipe_constant_buffer *cb;
1097 const uint8_t *ptr;
1098
1099 /* Note that the state tracker can unbind constant buffers by
1100 * passing NULL here.
1101 */
1102 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1103 state->enabled_mask &= ~(1 << index);
1104 state->dirty_mask &= ~(1 << index);
1105 pipe_resource_reference(&state->cb[index].buffer, NULL);
1106 return;
1107 }
1108
1109 cb = &state->cb[index];
1110 cb->buffer_size = input->buffer_size;
1111
1112 ptr = input->user_buffer;
1113
1114 if (ptr) {
1115 /* Upload the user buffer. */
1116 if (R600_BIG_ENDIAN) {
1117 uint32_t *tmpPtr;
1118 unsigned i, size = input->buffer_size;
1119
1120 if (!(tmpPtr = malloc(size))) {
1121 R600_ERR("Failed to allocate BE swap buffer.\n");
1122 return;
1123 }
1124
1125 for (i = 0; i < size / 4; ++i) {
1126 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1127 }
1128
1129 u_upload_data(rctx->b.uploader, 0, size, 256, tmpPtr, &cb->buffer_offset, &cb->buffer);
1130 free(tmpPtr);
1131 } else {
1132 u_upload_data(rctx->b.uploader, 0, input->buffer_size, 256, ptr, &cb->buffer_offset, &cb->buffer);
1133 }
1134 /* account it in gtt */
1135 rctx->b.gtt += input->buffer_size;
1136 } else {
1137 /* Setup the hw buffer. */
1138 cb->buffer_offset = input->buffer_offset;
1139 pipe_resource_reference(&cb->buffer, input->buffer);
1140 r600_context_add_resource_size(ctx, input->buffer);
1141 }
1142
1143 state->enabled_mask |= 1 << index;
1144 state->dirty_mask |= 1 << index;
1145 r600_constant_buffers_dirty(rctx, state);
1146 }
1147
1148 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1149 {
1150 struct r600_context *rctx = (struct r600_context*)pipe;
1151
1152 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1153 return;
1154
1155 rctx->sample_mask.sample_mask = sample_mask;
1156 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1157 }
1158
1159 static void r600_update_driver_const_buffers(struct r600_context *rctx)
1160 {
1161 int sh, size;;
1162 void *ptr;
1163 struct pipe_constant_buffer cb;
1164 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
1165 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1166 if (!info->vs_ucp_dirty &&
1167 !info->texture_const_dirty &&
1168 !info->ps_sample_pos_dirty)
1169 continue;
1170
1171 ptr = info->constants;
1172 size = info->alloc_size;
1173 if (info->vs_ucp_dirty) {
1174 assert(sh == PIPE_SHADER_VERTEX);
1175 if (!size) {
1176 ptr = rctx->clip_state.state.ucp;
1177 size = R600_UCP_SIZE;
1178 } else {
1179 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1180 }
1181 info->vs_ucp_dirty = false;
1182 }
1183
1184 if (info->ps_sample_pos_dirty) {
1185 assert(sh == PIPE_SHADER_FRAGMENT);
1186 if (!size) {
1187 ptr = rctx->sample_positions;
1188 size = R600_UCP_SIZE;
1189 } else {
1190 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1191 }
1192 info->ps_sample_pos_dirty = false;
1193 }
1194
1195 if (info->texture_const_dirty) {
1196 assert (ptr);
1197 assert (size);
1198 if (sh == PIPE_SHADER_VERTEX)
1199 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1200 if (sh == PIPE_SHADER_FRAGMENT)
1201 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1202 }
1203 info->texture_const_dirty = false;
1204
1205 cb.buffer = NULL;
1206 cb.user_buffer = ptr;
1207 cb.buffer_offset = 0;
1208 cb.buffer_size = size;
1209 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1210 pipe_resource_reference(&cb.buffer, NULL);
1211 }
1212 }
1213
1214 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1215 int array_size, uint32_t *base_offset)
1216 {
1217 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1218 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1219 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1220 info->alloc_size = array_size + R600_UCP_SIZE;
1221 }
1222 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1223 info->texture_const_dirty = true;
1224 *base_offset = R600_UCP_SIZE;
1225 return info->constants;
1226 }
1227 /*
1228 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1229 * doesn't require full swizzles it does need masking and setting alpha
1230 * to one, so we setup a set of 5 constants with the masks + alpha value
1231 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1232 * then OR the alpha with the value given here.
1233 * We use a 6th constant to store the txq buffer size in
1234 * we use 7th slot for number of cube layers in a cube map array.
1235 */
1236 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1237 {
1238 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1239 int bits;
1240 uint32_t array_size;
1241 int i, j;
1242 uint32_t *constants;
1243 uint32_t base_offset;
1244 if (!samplers->views.dirty_buffer_constants)
1245 return;
1246
1247 samplers->views.dirty_buffer_constants = FALSE;
1248
1249 bits = util_last_bit(samplers->views.enabled_mask);
1250 array_size = bits * 8 * sizeof(uint32_t) * 4;
1251
1252 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1253
1254 for (i = 0; i < bits; i++) {
1255 if (samplers->views.enabled_mask & (1 << i)) {
1256 int offset = (base_offset / 4) + i * 8;
1257 const struct util_format_description *desc;
1258 desc = util_format_description(samplers->views.views[i]->base.format);
1259
1260 for (j = 0; j < 4; j++)
1261 if (j < desc->nr_channels)
1262 constants[offset+j] = 0xffffffff;
1263 else
1264 constants[offset+j] = 0x0;
1265 if (desc->nr_channels < 4) {
1266 if (desc->channel[0].pure_integer)
1267 constants[offset+4] = 1;
1268 else
1269 constants[offset+4] = fui(1.0);
1270 } else
1271 constants[offset + 4] = 0;
1272
1273 constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1274 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1275 }
1276 }
1277
1278 }
1279
1280 /* On evergreen we store two values
1281 * 1. buffer size for TXQ
1282 * 2. number of cube layers in a cube map array.
1283 */
1284 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1285 {
1286 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1287 int bits;
1288 uint32_t array_size;
1289 int i;
1290 uint32_t *constants;
1291 uint32_t base_offset;
1292 if (!samplers->views.dirty_buffer_constants)
1293 return;
1294
1295 samplers->views.dirty_buffer_constants = FALSE;
1296
1297 bits = util_last_bit(samplers->views.enabled_mask);
1298 array_size = bits * 2 * sizeof(uint32_t) * 4;
1299
1300 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1301 &base_offset);
1302
1303 for (i = 0; i < bits; i++) {
1304 if (samplers->views.enabled_mask & (1 << i)) {
1305 uint32_t offset = (base_offset / 4) + i * 2;
1306 constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1307 constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
1308 }
1309 }
1310 }
1311
1312 /* set sample xy locations as array of fragment shader constants */
1313 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1314 {
1315 int i;
1316 struct pipe_context *ctx = &rctx->b.b;
1317
1318 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1319 assert(rctx->framebuffer.nr_samples <= Elements(rctx->sample_positions)/4);
1320
1321 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1322 for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1323 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1324 /* Also fill in center-zeroed positions used for interpolateAtSample */
1325 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1326 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1327 }
1328
1329 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1330 }
1331
1332 static void update_shader_atom(struct pipe_context *ctx,
1333 struct r600_shader_state *state,
1334 struct r600_pipe_shader *shader)
1335 {
1336 struct r600_context *rctx = (struct r600_context *)ctx;
1337
1338 state->shader = shader;
1339 if (shader) {
1340 state->atom.num_dw = shader->command_buffer.num_dw;
1341 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1342 } else {
1343 state->atom.num_dw = 0;
1344 }
1345 r600_mark_atom_dirty(rctx, &state->atom);
1346 }
1347
1348 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1349 {
1350 if (rctx->shader_stages.geom_enable != enable) {
1351 rctx->shader_stages.geom_enable = enable;
1352 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1353 }
1354
1355 if (rctx->gs_rings.enable != enable) {
1356 rctx->gs_rings.enable = enable;
1357 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1358
1359 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1360 unsigned size = 0x1C000;
1361 rctx->gs_rings.esgs_ring.buffer =
1362 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1363 PIPE_USAGE_DEFAULT, size);
1364 rctx->gs_rings.esgs_ring.buffer_size = size;
1365
1366 size = 0x4000000;
1367
1368 rctx->gs_rings.gsvs_ring.buffer =
1369 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1370 PIPE_USAGE_DEFAULT, size);
1371 rctx->gs_rings.gsvs_ring.buffer_size = size;
1372 }
1373
1374 if (enable) {
1375 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1376 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1377 if (rctx->tes_shader) {
1378 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1379 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1380 } else {
1381 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1382 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1383 }
1384 } else {
1385 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1386 R600_GS_RING_CONST_BUFFER, NULL);
1387 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1388 R600_GS_RING_CONST_BUFFER, NULL);
1389 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1390 R600_GS_RING_CONST_BUFFER, NULL);
1391 }
1392 }
1393 }
1394
1395 static void r600_update_clip_state(struct r600_context *rctx,
1396 struct r600_pipe_shader *current)
1397 {
1398 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1399 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1400 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1401 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1402 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1403 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1404 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1405 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1406 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1407 }
1408 }
1409
1410 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1411 {
1412 struct ureg_src const0, const1;
1413 struct ureg_dst tessouter, tessinner;
1414 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1415
1416 if (!ureg)
1417 return; /* if we get here, we're screwed */
1418
1419 assert(!rctx->fixed_func_tcs_shader);
1420
1421 ureg_DECL_constant2D(ureg, 0, 3, R600_LDS_INFO_CONST_BUFFER);
1422 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 2),
1423 R600_LDS_INFO_CONST_BUFFER);
1424 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 3),
1425 R600_LDS_INFO_CONST_BUFFER);
1426
1427 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1428 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1429
1430 ureg_MOV(ureg, tessouter, const0);
1431 ureg_MOV(ureg, tessinner, const1);
1432 ureg_END(ureg);
1433
1434 rctx->fixed_func_tcs_shader =
1435 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1436 }
1437
1438 #define SELECT_SHADER_OR_FAIL(x) do { \
1439 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1440 if (unlikely(!rctx->x##_shader->current)) \
1441 return false; \
1442 } while(0)
1443
1444 #define UPDATE_SHADER(hw, sw) do { \
1445 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1446 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1447 } while(0)
1448
1449 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1450 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1451 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1452 clip_so_current = rctx->sw##_shader->current; \
1453 } \
1454 } while(0)
1455
1456 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1457 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1458 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1459 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1460 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1461 } \
1462 } while(0)
1463
1464 #define SET_NULL_SHADER(hw) do { \
1465 if (rctx->hw_shader_stages[(hw)].shader) \
1466 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1467 } while (0)
1468
1469 static bool r600_update_derived_state(struct r600_context *rctx)
1470 {
1471 struct pipe_context * ctx = (struct pipe_context*)rctx;
1472 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1473 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1474 bool blend_disable;
1475 bool need_buf_const;
1476 struct r600_pipe_shader *clip_so_current = NULL;
1477
1478 if (!rctx->blitter->running) {
1479 unsigned i;
1480 unsigned counter;
1481
1482 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1483 if (counter != rctx->b.last_compressed_colortex_counter) {
1484 rctx->b.last_compressed_colortex_counter = counter;
1485
1486 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1487 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1488 }
1489 }
1490
1491 /* Decompress textures if needed. */
1492 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1493 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1494 if (views->compressed_depthtex_mask) {
1495 r600_decompress_depth_textures(rctx, views);
1496 }
1497 if (views->compressed_colortex_mask) {
1498 r600_decompress_color_textures(rctx, views);
1499 }
1500 }
1501 }
1502
1503 SELECT_SHADER_OR_FAIL(ps);
1504
1505 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1506
1507 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1508
1509 if (rctx->gs_shader)
1510 SELECT_SHADER_OR_FAIL(gs);
1511
1512 /* Hull Shader */
1513 if (rctx->tcs_shader) {
1514 SELECT_SHADER_OR_FAIL(tcs);
1515
1516 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1517 } else if (rctx->tes_shader) {
1518 if (!rctx->fixed_func_tcs_shader) {
1519 r600_generate_fixed_func_tcs(rctx);
1520 if (!rctx->fixed_func_tcs_shader)
1521 return false;
1522
1523 }
1524 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1525
1526 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1527 } else
1528 SET_NULL_SHADER(EG_HW_STAGE_HS);
1529
1530 if (rctx->tes_shader) {
1531 SELECT_SHADER_OR_FAIL(tes);
1532 }
1533
1534 SELECT_SHADER_OR_FAIL(vs);
1535
1536 if (rctx->gs_shader) {
1537 if (!rctx->shader_stages.geom_enable) {
1538 rctx->shader_stages.geom_enable = true;
1539 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1540 }
1541
1542 /* gs_shader provides GS and VS (copy shader) */
1543 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1544
1545 /* vs_shader is used as ES */
1546
1547 if (rctx->tes_shader) {
1548 /* VS goes to LS, TES goes to ES */
1549 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1550 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1551 } else {
1552 /* vs_shader is used as ES */
1553 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1554 SET_NULL_SHADER(EG_HW_STAGE_LS);
1555 }
1556 } else {
1557 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1558 SET_NULL_SHADER(R600_HW_STAGE_GS);
1559 SET_NULL_SHADER(R600_HW_STAGE_ES);
1560 rctx->shader_stages.geom_enable = false;
1561 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1562 }
1563
1564 if (rctx->tes_shader) {
1565 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1566 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1567 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1568 } else {
1569 SET_NULL_SHADER(EG_HW_STAGE_LS);
1570 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1571 }
1572 }
1573
1574 /* Update clip misc state. */
1575 if (clip_so_current) {
1576 r600_update_clip_state(rctx, clip_so_current);
1577 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1578 }
1579
1580 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1581 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1582 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1583
1584 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1585 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1586 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1587 }
1588
1589 if (rctx->b.chip_class <= R700) {
1590 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1591
1592 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1593 rctx->cb_misc_state.multiwrite = multiwrite;
1594 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1595 }
1596 }
1597
1598 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1599 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1600 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1601
1602 if (rctx->b.chip_class >= EVERGREEN)
1603 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1604 else
1605 r600_update_ps_state(ctx, rctx->ps_shader->current);
1606 }
1607
1608 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1609 }
1610 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
1611
1612 if (rctx->b.chip_class >= EVERGREEN) {
1613 evergreen_update_db_shader_control(rctx);
1614 } else {
1615 r600_update_db_shader_control(rctx);
1616 }
1617
1618 /* on R600 we stuff masks + txq info into one constant buffer */
1619 /* on evergreen we only need a txq info one */
1620 if (rctx->ps_shader) {
1621 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1622 if (need_buf_const) {
1623 if (rctx->b.chip_class < EVERGREEN)
1624 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1625 else
1626 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1627 }
1628 }
1629
1630 if (rctx->vs_shader) {
1631 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1632 if (need_buf_const) {
1633 if (rctx->b.chip_class < EVERGREEN)
1634 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1635 else
1636 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1637 }
1638 }
1639
1640 if (rctx->gs_shader) {
1641 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1642 if (need_buf_const) {
1643 if (rctx->b.chip_class < EVERGREEN)
1644 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1645 else
1646 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1647 }
1648 }
1649
1650 r600_update_driver_const_buffers(rctx);
1651
1652 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1653 if (!r600_adjust_gprs(rctx)) {
1654 /* discard rendering */
1655 return false;
1656 }
1657 }
1658
1659 if (rctx->b.chip_class == EVERGREEN) {
1660 if (!evergreen_adjust_gprs(rctx)) {
1661 /* discard rendering */
1662 return false;
1663 }
1664 }
1665
1666 blend_disable = (rctx->dual_src_blend &&
1667 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1668
1669 if (blend_disable != rctx->force_blend_disable) {
1670 rctx->force_blend_disable = blend_disable;
1671 r600_bind_blend_state_internal(rctx,
1672 rctx->blend_state.cso,
1673 blend_disable);
1674 }
1675
1676 return true;
1677 }
1678
1679 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1680 {
1681 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1682 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1683
1684 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1685 state->pa_cl_clip_cntl |
1686 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1687 S_028810_CLIP_DISABLE(state->clip_disable));
1688 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1689 state->pa_cl_vs_out_cntl |
1690 (state->clip_plane_enable & state->clip_dist_write));
1691 /* reuse needs to be set off if we write oViewport */
1692 if (rctx->b.chip_class >= EVERGREEN)
1693 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
1694 S_028AB4_REUSE_OFF(state->vs_out_viewport));
1695 }
1696
1697 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1698 {
1699 struct r600_context *rctx = (struct r600_context *)ctx;
1700 struct pipe_draw_info info = *dinfo;
1701 struct pipe_index_buffer ib = {};
1702 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1703 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
1704 uint64_t mask;
1705 unsigned num_patches, dirty_fb_counter;
1706
1707 if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
1708 return;
1709 }
1710
1711 if (!rctx->vs_shader || !rctx->ps_shader) {
1712 assert(0);
1713 return;
1714 }
1715
1716 /* make sure that the gfx ring is only one active */
1717 if (rctx->b.dma.cs && rctx->b.dma.cs->cdw) {
1718 rctx->b.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1719 }
1720
1721 /* Re-emit the framebuffer state if needed. */
1722 dirty_fb_counter = p_atomic_read(&rctx->b.screen->dirty_fb_counter);
1723 if (dirty_fb_counter != rctx->b.last_dirty_fb_counter) {
1724 rctx->b.last_dirty_fb_counter = dirty_fb_counter;
1725 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1726 }
1727
1728 if (!r600_update_derived_state(rctx)) {
1729 /* useless to render because current rendering command
1730 * can't be achieved
1731 */
1732 return;
1733 }
1734
1735 if (info.indexed) {
1736 /* Initialize the index buffer struct. */
1737 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1738 ib.user_buffer = rctx->index_buffer.user_buffer;
1739 ib.index_size = rctx->index_buffer.index_size;
1740 ib.offset = rctx->index_buffer.offset;
1741 if (!info.indirect) {
1742 ib.offset += info.start * ib.index_size;
1743 }
1744
1745 /* Translate 8-bit indices to 16-bit. */
1746 if (unlikely(ib.index_size == 1)) {
1747 struct pipe_resource *out_buffer = NULL;
1748 unsigned out_offset;
1749 void *ptr;
1750 unsigned start, count;
1751
1752 if (likely(!info.indirect)) {
1753 start = 0;
1754 count = info.count;
1755 }
1756 else {
1757 /* Have to get start/count from indirect buffer, slow path ahead... */
1758 struct r600_resource *indirect_resource = (struct r600_resource *)info.indirect;
1759 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
1760 PIPE_TRANSFER_READ);
1761 if (data) {
1762 data += info.indirect_offset / sizeof(unsigned);
1763 start = data[2] * ib.index_size;
1764 count = data[0];
1765 }
1766 else {
1767 start = 0;
1768 count = 0;
1769 }
1770 }
1771
1772 u_upload_alloc(rctx->b.uploader, start, count * 2, 256,
1773 &out_offset, &out_buffer, &ptr);
1774
1775 util_shorten_ubyte_elts_to_userptr(
1776 &rctx->b.b, &ib, 0, ib.offset + start, count, ptr);
1777
1778 pipe_resource_reference(&ib.buffer, NULL);
1779 ib.user_buffer = NULL;
1780 ib.buffer = out_buffer;
1781 ib.offset = out_offset;
1782 ib.index_size = 2;
1783 }
1784
1785 /* Upload the index buffer.
1786 * The upload is skipped for small index counts on little-endian machines
1787 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1788 * Indirect draws never use immediate indices.
1789 * Note: Instanced rendering in combination with immediate indices hangs. */
1790 if (ib.user_buffer && (R600_BIG_ENDIAN || info.indirect ||
1791 info.instance_count > 1 ||
1792 info.count*ib.index_size > 20)) {
1793 u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size, 256,
1794 ib.user_buffer, &ib.offset, &ib.buffer);
1795 ib.user_buffer = NULL;
1796 }
1797 } else {
1798 info.index_bias = info.start;
1799 }
1800
1801 /* Set the index offset and primitive restart. */
1802 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1803 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1804 rctx->vgt_state.vgt_indx_offset != info.index_bias ||
1805 (rctx->vgt_state.last_draw_was_indirect && !info.indirect)) {
1806 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1807 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1808 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1809 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
1810 }
1811
1812 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1813 if (rctx->b.chip_class == R600) {
1814 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1815 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1816 }
1817
1818 if (rctx->b.chip_class >= EVERGREEN)
1819 evergreen_setup_tess_constants(rctx, &info, &num_patches);
1820
1821 /* Emit states. */
1822 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1823 r600_flush_emit(rctx);
1824
1825 mask = rctx->dirty_atoms;
1826 while (mask != 0) {
1827 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
1828 }
1829
1830 if (rctx->b.chip_class == CAYMAN) {
1831 /* Copied from radeonsi. */
1832 unsigned primgroup_size = 128; /* recommended without a GS */
1833 bool ia_switch_on_eop = false;
1834 bool partial_vs_wave = false;
1835
1836 if (rctx->gs_shader)
1837 primgroup_size = 64; /* recommended with a GS */
1838
1839 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
1840 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
1841 ia_switch_on_eop = true;
1842 }
1843
1844 if (rctx->b.streamout.streamout_enabled ||
1845 rctx->b.streamout.prims_gen_query_enabled)
1846 partial_vs_wave = true;
1847
1848 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
1849 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
1850 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
1851 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
1852 }
1853
1854 if (rctx->b.chip_class >= EVERGREEN) {
1855 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, &info,
1856 num_patches);
1857
1858 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
1859 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
1860 }
1861
1862 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1863 * even though it should have no effect on those. */
1864 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
1865 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
1866 unsigned prim = info.mode;
1867
1868 if (rctx->gs_shader) {
1869 prim = rctx->gs_shader->gs_output_prim;
1870 }
1871 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
1872
1873 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
1874 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
1875 info.mode == R600_PRIM_RECTANGLE_LIST) {
1876 su_sc_mode_cntl &= C_028814_CULL_FRONT;
1877 }
1878 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
1879 }
1880
1881 /* Update start instance. */
1882 if (!info.indirect && rctx->last_start_instance != info.start_instance) {
1883 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1884 rctx->last_start_instance = info.start_instance;
1885 }
1886
1887 /* Update the primitive type. */
1888 if (rctx->last_primitive_type != info.mode) {
1889 unsigned ls_mask = 0;
1890
1891 if (info.mode == PIPE_PRIM_LINES)
1892 ls_mask = 1;
1893 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1894 info.mode == PIPE_PRIM_LINE_LOOP)
1895 ls_mask = 2;
1896
1897 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1898 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1899 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1900 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1901 r600_conv_pipe_prim(info.mode));
1902
1903 rctx->last_primitive_type = info.mode;
1904 }
1905
1906 /* Draw packets. */
1907 if (!info.indirect) {
1908 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, 0);
1909 cs->buf[cs->cdw++] = info.instance_count;
1910 }
1911
1912 if (unlikely(info.indirect)) {
1913 uint64_t va = r600_resource(info.indirect)->gpu_address;
1914 assert(rctx->b.chip_class >= EVERGREEN);
1915
1916 // Invalidate so non-indirect draw calls reset this state
1917 rctx->vgt_state.last_draw_was_indirect = true;
1918 rctx->last_start_instance = -1;
1919
1920 cs->buf[cs->cdw++] = PKT3(EG_PKT3_SET_BASE, 2, 0);
1921 cs->buf[cs->cdw++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE;
1922 cs->buf[cs->cdw++] = va;
1923 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1924
1925 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1926 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1927 (struct r600_resource*)info.indirect,
1928 RADEON_USAGE_READ,
1929 RADEON_PRIO_DRAW_INDIRECT);
1930 }
1931
1932 if (info.indexed) {
1933 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, 0);
1934 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1935 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1936 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1937
1938 if (ib.user_buffer) {
1939 unsigned size_bytes = info.count*ib.index_size;
1940 unsigned size_dw = align(size_bytes, 4) / 4;
1941 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit);
1942 cs->buf[cs->cdw++] = info.count;
1943 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1944 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1945 cs->cdw += size_dw;
1946 } else {
1947 uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
1948
1949 if (likely(!info.indirect)) {
1950 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit);
1951 cs->buf[cs->cdw++] = va;
1952 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1953 cs->buf[cs->cdw++] = info.count;
1954 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1955 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1956 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1957 (struct r600_resource*)ib.buffer,
1958 RADEON_USAGE_READ,
1959 RADEON_PRIO_INDEX_BUFFER);
1960 }
1961 else {
1962 uint32_t max_size = (ib.buffer->width0 - ib.offset) / ib.index_size;
1963
1964 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BASE, 1, 0);
1965 cs->buf[cs->cdw++] = va;
1966 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1967
1968 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1969 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1970 (struct r600_resource*)ib.buffer,
1971 RADEON_USAGE_READ,
1972 RADEON_PRIO_INDEX_BUFFER);
1973
1974 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0);
1975 cs->buf[cs->cdw++] = max_size;
1976
1977 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit);
1978 cs->buf[cs->cdw++] = info.indirect_offset;
1979 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1980 }
1981 }
1982 } else {
1983 if (unlikely(info.count_from_stream_output)) {
1984 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1985 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
1986
1987 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1988
1989 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1990 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1991 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1992 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1993 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1994 cs->buf[cs->cdw++] = 0; /* unused */
1995
1996 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1997 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1998 t->buf_filled_size, RADEON_USAGE_READ,
1999 RADEON_PRIO_SO_FILLED_SIZE);
2000 }
2001
2002 if (likely(!info.indirect)) {
2003 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit);
2004 cs->buf[cs->cdw++] = info.count;
2005 }
2006 else {
2007 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit);
2008 cs->buf[cs->cdw++] = info.indirect_offset;
2009 }
2010 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2011 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
2012 }
2013
2014 /* SMX returns CONTEXT_DONE too early workaround */
2015 if (rctx->b.family == CHIP_R600 ||
2016 rctx->b.family == CHIP_RV610 ||
2017 rctx->b.family == CHIP_RV630 ||
2018 rctx->b.family == CHIP_RV635) {
2019 /* if we have gs shader or streamout
2020 we need to do a wait idle after every draw */
2021 if (rctx->gs_shader || rctx->b.streamout.streamout_enabled) {
2022 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2023 }
2024 }
2025
2026 /* ES ring rolling over at EOP - workaround */
2027 if (rctx->b.chip_class == R600) {
2028 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
2029 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT);
2030 }
2031
2032 if (rctx->screen->b.trace_bo) {
2033 r600_trace_emit(rctx);
2034 }
2035
2036 /* Set the depth buffer as dirty. */
2037 if (rctx->framebuffer.state.zsbuf) {
2038 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2039 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2040
2041 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2042
2043 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2044 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2045 }
2046 if (rctx->framebuffer.compressed_cb_mask) {
2047 struct pipe_surface *surf;
2048 struct r600_texture *rtex;
2049 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2050
2051 do {
2052 unsigned i = u_bit_scan(&mask);
2053 surf = rctx->framebuffer.state.cbufs[i];
2054 rtex = (struct r600_texture*)surf->texture;
2055
2056 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2057
2058 } while (mask);
2059 }
2060
2061 pipe_resource_reference(&ib.buffer, NULL);
2062 rctx->b.num_draw_calls++;
2063 }
2064
2065 uint32_t r600_translate_stencil_op(int s_op)
2066 {
2067 switch (s_op) {
2068 case PIPE_STENCIL_OP_KEEP:
2069 return V_028800_STENCIL_KEEP;
2070 case PIPE_STENCIL_OP_ZERO:
2071 return V_028800_STENCIL_ZERO;
2072 case PIPE_STENCIL_OP_REPLACE:
2073 return V_028800_STENCIL_REPLACE;
2074 case PIPE_STENCIL_OP_INCR:
2075 return V_028800_STENCIL_INCR;
2076 case PIPE_STENCIL_OP_DECR:
2077 return V_028800_STENCIL_DECR;
2078 case PIPE_STENCIL_OP_INCR_WRAP:
2079 return V_028800_STENCIL_INCR_WRAP;
2080 case PIPE_STENCIL_OP_DECR_WRAP:
2081 return V_028800_STENCIL_DECR_WRAP;
2082 case PIPE_STENCIL_OP_INVERT:
2083 return V_028800_STENCIL_INVERT;
2084 default:
2085 R600_ERR("Unknown stencil op %d", s_op);
2086 assert(0);
2087 break;
2088 }
2089 return 0;
2090 }
2091
2092 uint32_t r600_translate_fill(uint32_t func)
2093 {
2094 switch(func) {
2095 case PIPE_POLYGON_MODE_FILL:
2096 return 2;
2097 case PIPE_POLYGON_MODE_LINE:
2098 return 1;
2099 case PIPE_POLYGON_MODE_POINT:
2100 return 0;
2101 default:
2102 assert(0);
2103 return 0;
2104 }
2105 }
2106
2107 unsigned r600_tex_wrap(unsigned wrap)
2108 {
2109 switch (wrap) {
2110 default:
2111 case PIPE_TEX_WRAP_REPEAT:
2112 return V_03C000_SQ_TEX_WRAP;
2113 case PIPE_TEX_WRAP_CLAMP:
2114 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2115 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2116 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2117 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2118 return V_03C000_SQ_TEX_CLAMP_BORDER;
2119 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2120 return V_03C000_SQ_TEX_MIRROR;
2121 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2122 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2123 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2124 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2125 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2126 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2127 }
2128 }
2129
2130 unsigned r600_tex_filter(unsigned filter)
2131 {
2132 switch (filter) {
2133 default:
2134 case PIPE_TEX_FILTER_NEAREST:
2135 return V_03C000_SQ_TEX_XY_FILTER_POINT;
2136 case PIPE_TEX_FILTER_LINEAR:
2137 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
2138 }
2139 }
2140
2141 unsigned r600_tex_mipfilter(unsigned filter)
2142 {
2143 switch (filter) {
2144 case PIPE_TEX_MIPFILTER_NEAREST:
2145 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2146 case PIPE_TEX_MIPFILTER_LINEAR:
2147 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2148 default:
2149 case PIPE_TEX_MIPFILTER_NONE:
2150 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2151 }
2152 }
2153
2154 unsigned r600_tex_compare(unsigned compare)
2155 {
2156 switch (compare) {
2157 default:
2158 case PIPE_FUNC_NEVER:
2159 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2160 case PIPE_FUNC_LESS:
2161 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2162 case PIPE_FUNC_EQUAL:
2163 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2164 case PIPE_FUNC_LEQUAL:
2165 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2166 case PIPE_FUNC_GREATER:
2167 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2168 case PIPE_FUNC_NOTEQUAL:
2169 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2170 case PIPE_FUNC_GEQUAL:
2171 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2172 case PIPE_FUNC_ALWAYS:
2173 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2174 }
2175 }
2176
2177 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2178 {
2179 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2180 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2181 (linear_filter &&
2182 (wrap == PIPE_TEX_WRAP_CLAMP ||
2183 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2184 }
2185
2186 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2187 {
2188 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2189 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2190
2191 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2192 state->border_color.ui[2] || state->border_color.ui[3]) &&
2193 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2194 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2195 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2196 }
2197
2198 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2199 {
2200
2201 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2202 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2203
2204 if (!shader)
2205 return;
2206
2207 r600_emit_command_buffer(cs, &shader->command_buffer);
2208 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2209 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2210 RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER));
2211 }
2212
2213 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2214 const unsigned char *swizzle_view,
2215 boolean vtx)
2216 {
2217 unsigned i;
2218 unsigned char swizzle[4];
2219 unsigned result = 0;
2220 const uint32_t tex_swizzle_shift[4] = {
2221 16, 19, 22, 25,
2222 };
2223 const uint32_t vtx_swizzle_shift[4] = {
2224 3, 6, 9, 12,
2225 };
2226 const uint32_t swizzle_bit[4] = {
2227 0, 1, 2, 3,
2228 };
2229 const uint32_t *swizzle_shift = tex_swizzle_shift;
2230
2231 if (vtx)
2232 swizzle_shift = vtx_swizzle_shift;
2233
2234 if (swizzle_view) {
2235 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2236 } else {
2237 memcpy(swizzle, swizzle_format, 4);
2238 }
2239
2240 /* Get swizzle. */
2241 for (i = 0; i < 4; i++) {
2242 switch (swizzle[i]) {
2243 case UTIL_FORMAT_SWIZZLE_Y:
2244 result |= swizzle_bit[1] << swizzle_shift[i];
2245 break;
2246 case UTIL_FORMAT_SWIZZLE_Z:
2247 result |= swizzle_bit[2] << swizzle_shift[i];
2248 break;
2249 case UTIL_FORMAT_SWIZZLE_W:
2250 result |= swizzle_bit[3] << swizzle_shift[i];
2251 break;
2252 case UTIL_FORMAT_SWIZZLE_0:
2253 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2254 break;
2255 case UTIL_FORMAT_SWIZZLE_1:
2256 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2257 break;
2258 default: /* UTIL_FORMAT_SWIZZLE_X */
2259 result |= swizzle_bit[0] << swizzle_shift[i];
2260 }
2261 }
2262 return result;
2263 }
2264
2265 /* texture format translate */
2266 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2267 enum pipe_format format,
2268 const unsigned char *swizzle_view,
2269 uint32_t *word4_p, uint32_t *yuv_format_p)
2270 {
2271 struct r600_screen *rscreen = (struct r600_screen *)screen;
2272 uint32_t result = 0, word4 = 0, yuv_format = 0;
2273 const struct util_format_description *desc;
2274 boolean uniform = TRUE;
2275 bool is_srgb_valid = FALSE;
2276 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2277 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2278
2279 int i;
2280 const uint32_t sign_bit[4] = {
2281 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2282 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2283 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2284 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2285 };
2286 desc = util_format_description(format);
2287
2288 /* Depth and stencil swizzling is handled separately. */
2289 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2290 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2291 }
2292
2293 /* Colorspace (return non-RGB formats directly). */
2294 switch (desc->colorspace) {
2295 /* Depth stencil formats */
2296 case UTIL_FORMAT_COLORSPACE_ZS:
2297 switch (format) {
2298 /* Depth sampler formats. */
2299 case PIPE_FORMAT_Z16_UNORM:
2300 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2301 result = FMT_16;
2302 goto out_word4;
2303 case PIPE_FORMAT_Z24X8_UNORM:
2304 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2305 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2306 result = FMT_8_24;
2307 goto out_word4;
2308 case PIPE_FORMAT_X8Z24_UNORM:
2309 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2310 if (rscreen->b.chip_class < EVERGREEN)
2311 goto out_unknown;
2312 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2313 result = FMT_24_8;
2314 goto out_word4;
2315 case PIPE_FORMAT_Z32_FLOAT:
2316 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2317 result = FMT_32_FLOAT;
2318 goto out_word4;
2319 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2320 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2321 result = FMT_X24_8_32_FLOAT;
2322 goto out_word4;
2323 /* Stencil sampler formats. */
2324 case PIPE_FORMAT_S8_UINT:
2325 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2326 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2327 result = FMT_8;
2328 goto out_word4;
2329 case PIPE_FORMAT_X24S8_UINT:
2330 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2331 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2332 result = FMT_8_24;
2333 goto out_word4;
2334 case PIPE_FORMAT_S8X24_UINT:
2335 if (rscreen->b.chip_class < EVERGREEN)
2336 goto out_unknown;
2337 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2338 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2339 result = FMT_24_8;
2340 goto out_word4;
2341 case PIPE_FORMAT_X32_S8X24_UINT:
2342 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2343 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2344 result = FMT_X24_8_32_FLOAT;
2345 goto out_word4;
2346 default:
2347 goto out_unknown;
2348 }
2349
2350 case UTIL_FORMAT_COLORSPACE_YUV:
2351 yuv_format |= (1 << 30);
2352 switch (format) {
2353 case PIPE_FORMAT_UYVY:
2354 case PIPE_FORMAT_YUYV:
2355 default:
2356 break;
2357 }
2358 goto out_unknown; /* XXX */
2359
2360 case UTIL_FORMAT_COLORSPACE_SRGB:
2361 word4 |= S_038010_FORCE_DEGAMMA(1);
2362 break;
2363
2364 default:
2365 break;
2366 }
2367
2368 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2369 switch (format) {
2370 case PIPE_FORMAT_RGTC1_SNORM:
2371 case PIPE_FORMAT_LATC1_SNORM:
2372 word4 |= sign_bit[0];
2373 case PIPE_FORMAT_RGTC1_UNORM:
2374 case PIPE_FORMAT_LATC1_UNORM:
2375 result = FMT_BC4;
2376 goto out_word4;
2377 case PIPE_FORMAT_RGTC2_SNORM:
2378 case PIPE_FORMAT_LATC2_SNORM:
2379 word4 |= sign_bit[0] | sign_bit[1];
2380 case PIPE_FORMAT_RGTC2_UNORM:
2381 case PIPE_FORMAT_LATC2_UNORM:
2382 result = FMT_BC5;
2383 goto out_word4;
2384 default:
2385 goto out_unknown;
2386 }
2387 }
2388
2389 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2390 if (!util_format_s3tc_enabled) {
2391 goto out_unknown;
2392 }
2393
2394 switch (format) {
2395 case PIPE_FORMAT_DXT1_RGB:
2396 case PIPE_FORMAT_DXT1_RGBA:
2397 case PIPE_FORMAT_DXT1_SRGB:
2398 case PIPE_FORMAT_DXT1_SRGBA:
2399 result = FMT_BC1;
2400 is_srgb_valid = TRUE;
2401 goto out_word4;
2402 case PIPE_FORMAT_DXT3_RGBA:
2403 case PIPE_FORMAT_DXT3_SRGBA:
2404 result = FMT_BC2;
2405 is_srgb_valid = TRUE;
2406 goto out_word4;
2407 case PIPE_FORMAT_DXT5_RGBA:
2408 case PIPE_FORMAT_DXT5_SRGBA:
2409 result = FMT_BC3;
2410 is_srgb_valid = TRUE;
2411 goto out_word4;
2412 default:
2413 goto out_unknown;
2414 }
2415 }
2416
2417 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2418 if (rscreen->b.chip_class < EVERGREEN)
2419 goto out_unknown;
2420
2421 switch (format) {
2422 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2423 case PIPE_FORMAT_BPTC_SRGBA:
2424 result = FMT_BC7;
2425 is_srgb_valid = TRUE;
2426 goto out_word4;
2427 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2428 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2429 /* fall through */
2430 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2431 result = FMT_BC6;
2432 goto out_word4;
2433 default:
2434 goto out_unknown;
2435 }
2436 }
2437
2438 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2439 switch (format) {
2440 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2441 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2442 result = FMT_GB_GR;
2443 goto out_word4;
2444 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2445 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2446 result = FMT_BG_RG;
2447 goto out_word4;
2448 default:
2449 goto out_unknown;
2450 }
2451 }
2452
2453 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2454 result = FMT_5_9_9_9_SHAREDEXP;
2455 goto out_word4;
2456 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2457 result = FMT_10_11_11_FLOAT;
2458 goto out_word4;
2459 }
2460
2461
2462 for (i = 0; i < desc->nr_channels; i++) {
2463 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2464 word4 |= sign_bit[i];
2465 }
2466 }
2467
2468 /* R8G8Bx_SNORM - XXX CxV8U8 */
2469
2470 /* See whether the components are of the same size. */
2471 for (i = 1; i < desc->nr_channels; i++) {
2472 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2473 }
2474
2475 /* Non-uniform formats. */
2476 if (!uniform) {
2477 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2478 desc->channel[0].pure_integer)
2479 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2480 switch(desc->nr_channels) {
2481 case 3:
2482 if (desc->channel[0].size == 5 &&
2483 desc->channel[1].size == 6 &&
2484 desc->channel[2].size == 5) {
2485 result = FMT_5_6_5;
2486 goto out_word4;
2487 }
2488 goto out_unknown;
2489 case 4:
2490 if (desc->channel[0].size == 5 &&
2491 desc->channel[1].size == 5 &&
2492 desc->channel[2].size == 5 &&
2493 desc->channel[3].size == 1) {
2494 result = FMT_1_5_5_5;
2495 goto out_word4;
2496 }
2497 if (desc->channel[0].size == 10 &&
2498 desc->channel[1].size == 10 &&
2499 desc->channel[2].size == 10 &&
2500 desc->channel[3].size == 2) {
2501 result = FMT_2_10_10_10;
2502 goto out_word4;
2503 }
2504 goto out_unknown;
2505 }
2506 goto out_unknown;
2507 }
2508
2509 /* Find the first non-VOID channel. */
2510 for (i = 0; i < 4; i++) {
2511 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2512 break;
2513 }
2514 }
2515
2516 if (i == 4)
2517 goto out_unknown;
2518
2519 /* uniform formats */
2520 switch (desc->channel[i].type) {
2521 case UTIL_FORMAT_TYPE_UNSIGNED:
2522 case UTIL_FORMAT_TYPE_SIGNED:
2523 #if 0
2524 if (!desc->channel[i].normalized &&
2525 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2526 goto out_unknown;
2527 }
2528 #endif
2529 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2530 desc->channel[i].pure_integer)
2531 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2532
2533 switch (desc->channel[i].size) {
2534 case 4:
2535 switch (desc->nr_channels) {
2536 case 2:
2537 result = FMT_4_4;
2538 goto out_word4;
2539 case 4:
2540 result = FMT_4_4_4_4;
2541 goto out_word4;
2542 }
2543 goto out_unknown;
2544 case 8:
2545 switch (desc->nr_channels) {
2546 case 1:
2547 result = FMT_8;
2548 goto out_word4;
2549 case 2:
2550 result = FMT_8_8;
2551 goto out_word4;
2552 case 4:
2553 result = FMT_8_8_8_8;
2554 is_srgb_valid = TRUE;
2555 goto out_word4;
2556 }
2557 goto out_unknown;
2558 case 16:
2559 switch (desc->nr_channels) {
2560 case 1:
2561 result = FMT_16;
2562 goto out_word4;
2563 case 2:
2564 result = FMT_16_16;
2565 goto out_word4;
2566 case 4:
2567 result = FMT_16_16_16_16;
2568 goto out_word4;
2569 }
2570 goto out_unknown;
2571 case 32:
2572 switch (desc->nr_channels) {
2573 case 1:
2574 result = FMT_32;
2575 goto out_word4;
2576 case 2:
2577 result = FMT_32_32;
2578 goto out_word4;
2579 case 4:
2580 result = FMT_32_32_32_32;
2581 goto out_word4;
2582 }
2583 }
2584 goto out_unknown;
2585
2586 case UTIL_FORMAT_TYPE_FLOAT:
2587 switch (desc->channel[i].size) {
2588 case 16:
2589 switch (desc->nr_channels) {
2590 case 1:
2591 result = FMT_16_FLOAT;
2592 goto out_word4;
2593 case 2:
2594 result = FMT_16_16_FLOAT;
2595 goto out_word4;
2596 case 4:
2597 result = FMT_16_16_16_16_FLOAT;
2598 goto out_word4;
2599 }
2600 goto out_unknown;
2601 case 32:
2602 switch (desc->nr_channels) {
2603 case 1:
2604 result = FMT_32_FLOAT;
2605 goto out_word4;
2606 case 2:
2607 result = FMT_32_32_FLOAT;
2608 goto out_word4;
2609 case 4:
2610 result = FMT_32_32_32_32_FLOAT;
2611 goto out_word4;
2612 }
2613 }
2614 goto out_unknown;
2615 }
2616
2617 out_word4:
2618
2619 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2620 return ~0;
2621 if (word4_p)
2622 *word4_p = word4;
2623 if (yuv_format_p)
2624 *yuv_format_p = yuv_format;
2625 return result;
2626 out_unknown:
2627 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2628 return ~0;
2629 }
2630
2631 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format)
2632 {
2633 const struct util_format_description *desc = util_format_description(format);
2634 int channel = util_format_get_first_non_void_channel(format);
2635 bool is_float;
2636
2637 #define HAS_SIZE(x,y,z,w) \
2638 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2639 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2640
2641 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2642 return V_0280A0_COLOR_10_11_11_FLOAT;
2643
2644 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2645 channel == -1)
2646 return ~0U;
2647
2648 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2649
2650 switch (desc->nr_channels) {
2651 case 1:
2652 switch (desc->channel[0].size) {
2653 case 8:
2654 return V_0280A0_COLOR_8;
2655 case 16:
2656 if (is_float)
2657 return V_0280A0_COLOR_16_FLOAT;
2658 else
2659 return V_0280A0_COLOR_16;
2660 case 32:
2661 if (is_float)
2662 return V_0280A0_COLOR_32_FLOAT;
2663 else
2664 return V_0280A0_COLOR_32;
2665 }
2666 break;
2667 case 2:
2668 if (desc->channel[0].size == desc->channel[1].size) {
2669 switch (desc->channel[0].size) {
2670 case 4:
2671 if (chip <= R700)
2672 return V_0280A0_COLOR_4_4;
2673 else
2674 return ~0U; /* removed on Evergreen */
2675 case 8:
2676 return V_0280A0_COLOR_8_8;
2677 case 16:
2678 if (is_float)
2679 return V_0280A0_COLOR_16_16_FLOAT;
2680 else
2681 return V_0280A0_COLOR_16_16;
2682 case 32:
2683 if (is_float)
2684 return V_0280A0_COLOR_32_32_FLOAT;
2685 else
2686 return V_0280A0_COLOR_32_32;
2687 }
2688 } else if (HAS_SIZE(8,24,0,0)) {
2689 return V_0280A0_COLOR_24_8;
2690 } else if (HAS_SIZE(24,8,0,0)) {
2691 return V_0280A0_COLOR_8_24;
2692 }
2693 break;
2694 case 3:
2695 if (HAS_SIZE(5,6,5,0)) {
2696 return V_0280A0_COLOR_5_6_5;
2697 } else if (HAS_SIZE(32,8,24,0)) {
2698 return V_0280A0_COLOR_X24_8_32_FLOAT;
2699 }
2700 break;
2701 case 4:
2702 if (desc->channel[0].size == desc->channel[1].size &&
2703 desc->channel[0].size == desc->channel[2].size &&
2704 desc->channel[0].size == desc->channel[3].size) {
2705 switch (desc->channel[0].size) {
2706 case 4:
2707 return V_0280A0_COLOR_4_4_4_4;
2708 case 8:
2709 return V_0280A0_COLOR_8_8_8_8;
2710 case 16:
2711 if (is_float)
2712 return V_0280A0_COLOR_16_16_16_16_FLOAT;
2713 else
2714 return V_0280A0_COLOR_16_16_16_16;
2715 case 32:
2716 if (is_float)
2717 return V_0280A0_COLOR_32_32_32_32_FLOAT;
2718 else
2719 return V_0280A0_COLOR_32_32_32_32;
2720 }
2721 } else if (HAS_SIZE(5,5,5,1)) {
2722 return V_0280A0_COLOR_1_5_5_5;
2723 } else if (HAS_SIZE(10,10,10,2)) {
2724 return V_0280A0_COLOR_2_10_10_10;
2725 }
2726 break;
2727 }
2728 return ~0U;
2729 }
2730
2731 uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
2732 {
2733 if (R600_BIG_ENDIAN) {
2734 switch(colorformat) {
2735 /* 8-bit buffers. */
2736 case V_0280A0_COLOR_4_4:
2737 case V_0280A0_COLOR_8:
2738 return ENDIAN_NONE;
2739
2740 /* 16-bit buffers. */
2741 case V_0280A0_COLOR_5_6_5:
2742 case V_0280A0_COLOR_1_5_5_5:
2743 case V_0280A0_COLOR_4_4_4_4:
2744 case V_0280A0_COLOR_16:
2745 case V_0280A0_COLOR_8_8:
2746 return ENDIAN_8IN16;
2747
2748 /* 32-bit buffers. */
2749 case V_0280A0_COLOR_8_8_8_8:
2750 /*
2751 * No need to do endian swaps on four 8-bits components,
2752 * as mesa<-->pipe formats conversion take into account
2753 * the endianess
2754 */
2755 return ENDIAN_NONE;
2756
2757 case V_0280A0_COLOR_2_10_10_10:
2758 case V_0280A0_COLOR_8_24:
2759 case V_0280A0_COLOR_24_8:
2760 case V_0280A0_COLOR_32_FLOAT:
2761 case V_0280A0_COLOR_16_16_FLOAT:
2762 case V_0280A0_COLOR_16_16:
2763 return ENDIAN_8IN32;
2764
2765 /* 64-bit buffers. */
2766 case V_0280A0_COLOR_16_16_16_16:
2767 case V_0280A0_COLOR_16_16_16_16_FLOAT:
2768 return ENDIAN_8IN16;
2769
2770 case V_0280A0_COLOR_32_32_FLOAT:
2771 case V_0280A0_COLOR_32_32:
2772 case V_0280A0_COLOR_X24_8_32_FLOAT:
2773 return ENDIAN_8IN32;
2774
2775 /* 128-bit buffers. */
2776 case V_0280A0_COLOR_32_32_32_32_FLOAT:
2777 case V_0280A0_COLOR_32_32_32_32:
2778 return ENDIAN_8IN32;
2779 default:
2780 return ENDIAN_NONE; /* Unsupported. */
2781 }
2782 } else {
2783 return ENDIAN_NONE;
2784 }
2785 }
2786
2787 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2788 {
2789 struct r600_context *rctx = (struct r600_context*)ctx;
2790 struct r600_resource *rbuffer = r600_resource(buf);
2791 unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
2792 struct r600_pipe_sampler_view *view;
2793
2794 /* Reallocate the buffer in the same pipe_resource. */
2795 r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0,
2796 alignment, TRUE);
2797
2798 /* We changed the buffer, now we need to bind it where the old one was bound. */
2799 /* Vertex buffers. */
2800 mask = rctx->vertex_buffer_state.enabled_mask;
2801 while (mask) {
2802 i = u_bit_scan(&mask);
2803 if (rctx->vertex_buffer_state.vb[i].buffer == &rbuffer->b.b) {
2804 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2805 r600_vertex_buffers_dirty(rctx);
2806 }
2807 }
2808 /* Streamout buffers. */
2809 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2810 if (rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2811 if (rctx->b.streamout.begin_emitted) {
2812 r600_emit_streamout_end(&rctx->b);
2813 }
2814 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2815 r600_streamout_buffers_dirty(&rctx->b);
2816 }
2817 }
2818
2819 /* Constant buffers. */
2820 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2821 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2822 bool found = false;
2823 uint32_t mask = state->enabled_mask;
2824
2825 while (mask) {
2826 unsigned i = u_bit_scan(&mask);
2827 if (state->cb[i].buffer == &rbuffer->b.b) {
2828 found = true;
2829 state->dirty_mask |= 1 << i;
2830 }
2831 }
2832 if (found) {
2833 r600_constant_buffers_dirty(rctx, state);
2834 }
2835 }
2836
2837 /* Texture buffer objects - update the virtual addresses in descriptors. */
2838 LIST_FOR_EACH_ENTRY(view, &rctx->b.texture_buffers, list) {
2839 if (view->base.texture == &rbuffer->b.b) {
2840 unsigned stride = util_format_get_blocksize(view->base.format);
2841 uint64_t offset = (uint64_t)view->base.u.buf.first_element * stride;
2842 uint64_t va = rbuffer->gpu_address + offset;
2843
2844 view->tex_resource_words[0] = va;
2845 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
2846 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
2847 }
2848 }
2849 /* Texture buffer objects - make bindings dirty if needed. */
2850 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2851 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
2852 bool found = false;
2853 uint32_t mask = state->enabled_mask;
2854
2855 while (mask) {
2856 unsigned i = u_bit_scan(&mask);
2857 if (state->views[i]->base.texture == &rbuffer->b.b) {
2858 found = true;
2859 state->dirty_mask |= 1 << i;
2860 }
2861 }
2862 if (found) {
2863 r600_sampler_views_dirty(rctx, state);
2864 }
2865 }
2866 }
2867
2868 static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2869 {
2870 struct r600_context *rctx = (struct r600_context*)ctx;
2871
2872 if (rctx->db_misc_state.occlusion_query_enabled != enable) {
2873 rctx->db_misc_state.occlusion_query_enabled = enable;
2874 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2875 }
2876 }
2877
2878 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2879 bool include_draw_vbo)
2880 {
2881 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
2882 }
2883
2884 /* keep this at the end of this file, please */
2885 void r600_init_common_state_functions(struct r600_context *rctx)
2886 {
2887 rctx->b.b.create_fs_state = r600_create_ps_state;
2888 rctx->b.b.create_vs_state = r600_create_vs_state;
2889 rctx->b.b.create_gs_state = r600_create_gs_state;
2890 rctx->b.b.create_tcs_state = r600_create_tcs_state;
2891 rctx->b.b.create_tes_state = r600_create_tes_state;
2892 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2893 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2894 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2895 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2896 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2897 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2898 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2899 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2900 rctx->b.b.bind_gs_state = r600_bind_gs_state;
2901 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
2902 rctx->b.b.bind_tes_state = r600_bind_tes_state;
2903 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2904 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2905 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2906 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2907 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2908 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2909 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2910 rctx->b.b.delete_gs_state = r600_delete_gs_state;
2911 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
2912 rctx->b.b.delete_tes_state = r600_delete_tes_state;
2913 rctx->b.b.set_blend_color = r600_set_blend_color;
2914 rctx->b.b.set_clip_state = r600_set_clip_state;
2915 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2916 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2917 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2918 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2919 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2920 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2921 rctx->b.b.set_sampler_views = r600_set_sampler_views;
2922 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2923 rctx->b.b.texture_barrier = r600_texture_barrier;
2924 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2925 rctx->b.b.draw_vbo = r600_draw_vbo;
2926 rctx->b.invalidate_buffer = r600_invalidate_buffer;
2927 rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
2928 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
2929 }
2930
2931 void r600_trace_emit(struct r600_context *rctx)
2932 {
2933 struct r600_screen *rscreen = rctx->screen;
2934 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2935 uint64_t va;
2936 uint32_t reloc;
2937
2938 va = rscreen->b.trace_bo->gpu_address;
2939 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rscreen->b.trace_bo,
2940 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
2941 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2942 radeon_emit(cs, va & 0xFFFFFFFFUL);
2943 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2944 radeon_emit(cs, cs->cdw);
2945 radeon_emit(cs, rscreen->b.cs_count);
2946 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2947 radeon_emit(cs, reloc);
2948 }