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[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
36 {
37 struct radeon_winsys_cs *cs = rctx->cs;
38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
39
40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
42 cs->cdw += cb->atom.num_dw;
43 }
44
45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
46 {
47 cb->atom.emit = r600_emit_command_buffer;
48 cb->atom.num_dw = 0;
49 cb->atom.flags = flags;
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
60 {
61 struct radeon_winsys_cs *cs = rctx->cs;
62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
63
64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
69
70 a->flush_flags = 0;
71 }
72
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 struct radeon_winsys_cs *cs = rctx->cs;
76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
78 }
79
80 void r600_init_atom(struct r600_atom *atom,
81 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
82 unsigned num_dw, enum r600_atom_flags flags)
83 {
84 atom->emit = emit;
85 atom->num_dw = num_dw;
86 atom->flags = flags;
87 }
88
89 void r600_init_common_atoms(struct r600_context *rctx)
90 {
91 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
92 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
93 }
94
95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
96 {
97 unsigned flags = 0;
98
99 if (rctx->framebuffer.nr_cbufs) {
100 flags |= S_0085F0_CB_ACTION_ENA(1) |
101 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
102 }
103
104 /* Workaround for broken flushing on some R6xx chipsets. */
105 if (rctx->family == CHIP_RV670 ||
106 rctx->family == CHIP_RS780 ||
107 rctx->family == CHIP_RS880) {
108 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
109 S_0085F0_DEST_BASE_0_ENA(1);
110 }
111 return flags;
112 }
113
114 void r600_texture_barrier(struct pipe_context *ctx)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117
118 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
119 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
120 }
121
122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
123 {
124 static const int prim_conv[] = {
125 V_008958_DI_PT_POINTLIST,
126 V_008958_DI_PT_LINELIST,
127 V_008958_DI_PT_LINELOOP,
128 V_008958_DI_PT_LINESTRIP,
129 V_008958_DI_PT_TRILIST,
130 V_008958_DI_PT_TRISTRIP,
131 V_008958_DI_PT_TRIFAN,
132 V_008958_DI_PT_QUADLIST,
133 V_008958_DI_PT_QUADSTRIP,
134 V_008958_DI_PT_POLYGON,
135 -1,
136 -1,
137 -1,
138 -1
139 };
140
141 *prim = prim_conv[pprim];
142 if (*prim == -1) {
143 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
144 return false;
145 }
146 return true;
147 }
148
149 /* common state between evergreen and r600 */
150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
151 {
152 struct r600_context *rctx = (struct r600_context *)ctx;
153 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
154 struct r600_pipe_state *rstate;
155 bool update_cb = false;
156
157 if (state == NULL)
158 return;
159 rstate = &blend->rstate;
160 rctx->states[rstate->id] = rstate;
161 rctx->dual_src_blend = blend->dual_src_blend;
162 r600_context_pipe_state_set(rctx, rstate);
163
164 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
165 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
166 update_cb = true;
167 }
168 if (rctx->chip_class <= R700 &&
169 rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
170 rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
171 update_cb = true;
172 }
173 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
174 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
175 update_cb = true;
176 }
177 if (update_cb) {
178 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
179 }
180 }
181
182 void r600_set_blend_color(struct pipe_context *ctx,
183 const struct pipe_blend_color *state)
184 {
185 struct r600_context *rctx = (struct r600_context *)ctx;
186 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
187
188 if (rstate == NULL)
189 return;
190
191 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
192 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
193 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
194 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
195 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
196
197 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
198 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
199 r600_context_pipe_state_set(rctx, rstate);
200 }
201
202 static void r600_set_stencil_ref(struct pipe_context *ctx,
203 const struct r600_stencil_ref *state)
204 {
205 struct r600_context *rctx = (struct r600_context *)ctx;
206 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
207
208 if (rstate == NULL)
209 return;
210
211 rstate->id = R600_PIPE_STATE_STENCIL_REF;
212 r600_pipe_state_add_reg(rstate,
213 R_028430_DB_STENCILREFMASK,
214 S_028430_STENCILREF(state->ref_value[0]) |
215 S_028430_STENCILMASK(state->valuemask[0]) |
216 S_028430_STENCILWRITEMASK(state->writemask[0]));
217 r600_pipe_state_add_reg(rstate,
218 R_028434_DB_STENCILREFMASK_BF,
219 S_028434_STENCILREF_BF(state->ref_value[1]) |
220 S_028434_STENCILMASK_BF(state->valuemask[1]) |
221 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
222
223 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
224 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
225 r600_context_pipe_state_set(rctx, rstate);
226 }
227
228 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
229 const struct pipe_stencil_ref *state)
230 {
231 struct r600_context *rctx = (struct r600_context *)ctx;
232 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
233 struct r600_stencil_ref ref;
234
235 rctx->stencil_ref = *state;
236
237 if (!dsa)
238 return;
239
240 ref.ref_value[0] = state->ref_value[0];
241 ref.ref_value[1] = state->ref_value[1];
242 ref.valuemask[0] = dsa->valuemask[0];
243 ref.valuemask[1] = dsa->valuemask[1];
244 ref.writemask[0] = dsa->writemask[0];
245 ref.writemask[1] = dsa->writemask[1];
246
247 r600_set_stencil_ref(ctx, &ref);
248 }
249
250 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
251 {
252 struct r600_context *rctx = (struct r600_context *)ctx;
253 struct r600_pipe_dsa *dsa = state;
254 struct r600_pipe_state *rstate;
255 struct r600_stencil_ref ref;
256
257 if (state == NULL)
258 return;
259 rstate = &dsa->rstate;
260 rctx->states[rstate->id] = rstate;
261 rctx->sx_alpha_test_control &= ~0xff;
262 rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
263 rctx->alpha_ref = dsa->alpha_ref;
264 rctx->alpha_ref_dirty = true;
265 r600_context_pipe_state_set(rctx, rstate);
266
267 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
268 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
269 ref.valuemask[0] = dsa->valuemask[0];
270 ref.valuemask[1] = dsa->valuemask[1];
271 ref.writemask[0] = dsa->writemask[0];
272 ref.writemask[1] = dsa->writemask[1];
273
274 r600_set_stencil_ref(ctx, &ref);
275 }
276
277 void r600_set_max_scissor(struct r600_context *rctx)
278 {
279 /* Set a scissor state such that it doesn't do anything. */
280 struct pipe_scissor_state scissor;
281 scissor.minx = 0;
282 scissor.miny = 0;
283 scissor.maxx = 8192;
284 scissor.maxy = 8192;
285
286 r600_set_scissor_state(rctx, &scissor);
287 }
288
289 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
290 {
291 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
292 struct r600_context *rctx = (struct r600_context *)ctx;
293
294 if (state == NULL)
295 return;
296
297 rctx->sprite_coord_enable = rs->sprite_coord_enable;
298 rctx->two_side = rs->two_side;
299 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
300 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
301
302 rctx->rasterizer = rs;
303
304 rctx->states[rs->rstate.id] = &rs->rstate;
305 r600_context_pipe_state_set(rctx, &rs->rstate);
306
307 if (rctx->chip_class >= EVERGREEN) {
308 evergreen_polygon_offset_update(rctx);
309 } else {
310 r600_polygon_offset_update(rctx);
311 }
312
313 /* Workaround for a missing scissor enable on r600. */
314 if (rctx->chip_class == R600) {
315 if (rs->scissor_enable != rctx->scissor_enable) {
316 rctx->scissor_enable = rs->scissor_enable;
317
318 if (rs->scissor_enable) {
319 r600_set_scissor_state(rctx, &rctx->scissor_state);
320 } else {
321 r600_set_max_scissor(rctx);
322 }
323 }
324 }
325 }
326
327 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
328 {
329 struct r600_context *rctx = (struct r600_context *)ctx;
330 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
331
332 if (rctx->rasterizer == rs) {
333 rctx->rasterizer = NULL;
334 }
335 if (rctx->states[rs->rstate.id] == &rs->rstate) {
336 rctx->states[rs->rstate.id] = NULL;
337 }
338 free(rs);
339 }
340
341 void r600_sampler_view_destroy(struct pipe_context *ctx,
342 struct pipe_sampler_view *state)
343 {
344 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
345
346 pipe_resource_reference(&state->texture, NULL);
347 FREE(resource);
348 }
349
350 void r600_delete_state(struct pipe_context *ctx, void *state)
351 {
352 struct r600_context *rctx = (struct r600_context *)ctx;
353 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
354
355 if (rctx->states[rstate->id] == rstate) {
356 rctx->states[rstate->id] = NULL;
357 }
358 for (int i = 0; i < rstate->nregs; i++) {
359 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
360 }
361 free(rstate);
362 }
363
364 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
365 {
366 struct r600_context *rctx = (struct r600_context *)ctx;
367 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
368
369 rctx->vertex_elements = v;
370 if (v) {
371 r600_inval_shader_cache(rctx);
372
373 rctx->states[v->rstate.id] = &v->rstate;
374 r600_context_pipe_state_set(rctx, &v->rstate);
375 }
376 }
377
378 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
379 {
380 struct r600_context *rctx = (struct r600_context *)ctx;
381 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
382
383 if (rctx->states[v->rstate.id] == &v->rstate) {
384 rctx->states[v->rstate.id] = NULL;
385 }
386 if (rctx->vertex_elements == state)
387 rctx->vertex_elements = NULL;
388
389 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
390 FREE(state);
391 }
392
393 void r600_set_index_buffer(struct pipe_context *ctx,
394 const struct pipe_index_buffer *ib)
395 {
396 struct r600_context *rctx = (struct r600_context *)ctx;
397
398 if (ib) {
399 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
400 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
401 } else {
402 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
403 }
404 }
405
406 void r600_vertex_buffers_dirty(struct r600_context *rctx)
407 {
408 if (rctx->vertex_buffer_state.dirty_mask) {
409 r600_inval_vertex_cache(rctx);
410 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
411 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
412 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
413 }
414 }
415
416 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
417 const struct pipe_vertex_buffer *input)
418 {
419 struct r600_context *rctx = (struct r600_context *)ctx;
420 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
421 struct pipe_vertex_buffer *vb = state->vb;
422 unsigned i;
423 /* This sets 1-bit for buffers with index >= count. */
424 uint32_t disable_mask = ~((1ull << count) - 1);
425 /* These are the new buffers set by this function. */
426 uint32_t new_buffer_mask = 0;
427
428 /* Set buffers with index >= count to NULL. */
429 uint32_t remaining_buffers_mask =
430 rctx->vertex_buffer_state.enabled_mask & disable_mask;
431
432 while (remaining_buffers_mask) {
433 i = u_bit_scan(&remaining_buffers_mask);
434 pipe_resource_reference(&vb[i].buffer, NULL);
435 }
436
437 /* Set vertex buffers. */
438 for (i = 0; i < count; i++) {
439 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
440 if (input[i].buffer) {
441 vb[i].stride = input[i].stride;
442 vb[i].buffer_offset = input[i].buffer_offset;
443 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
444 new_buffer_mask |= 1 << i;
445 } else {
446 pipe_resource_reference(&vb[i].buffer, NULL);
447 disable_mask |= 1 << i;
448 }
449 }
450 }
451
452 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
453 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
454 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
455 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
456
457 r600_vertex_buffers_dirty(rctx);
458 }
459
460 void r600_set_sampler_views(struct r600_context *rctx,
461 struct r600_textures_info *dst,
462 unsigned count,
463 struct pipe_sampler_view **views,
464 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
465 {
466 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
467 unsigned i;
468
469 if (count)
470 r600_inval_texture_cache(rctx);
471
472 for (i = 0; i < count; i++) {
473 if (rviews[i] == dst->views[i]) {
474 continue;
475 }
476
477 if (rviews[i]) {
478 struct r600_resource_texture *rtex =
479 (struct r600_resource_texture*)rviews[i]->base.texture;
480
481 if (rtex->is_depth && !rtex->is_flushing_texture) {
482 dst->depth_texture_mask |= 1 << i;
483 } else {
484 dst->depth_texture_mask &= ~(1 << i);
485 }
486
487 /* Changing from array to non-arrays textures and vice
488 * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */
489 if (rctx->chip_class <= R700 &&
490 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
491 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
492 dst->samplers_dirty = true;
493 }
494
495 set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
496 } else {
497 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
498 dst->depth_texture_mask &= ~(1 << i);
499 }
500
501 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], views[i]);
502 }
503
504 for (i = count; i < dst->n_views; i++) {
505 if (dst->views[i]) {
506 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
507 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
508 }
509 }
510
511 dst->n_views = count;
512 }
513
514 void *r600_create_vertex_elements(struct pipe_context *ctx,
515 unsigned count,
516 const struct pipe_vertex_element *elements)
517 {
518 struct r600_context *rctx = (struct r600_context *)ctx;
519 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
520
521 assert(count < 32);
522 if (!v)
523 return NULL;
524
525 v->count = count;
526 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
527
528 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
529 FREE(v);
530 return NULL;
531 }
532
533 return v;
534 }
535
536 /* Compute the key for the hw shader variant */
537 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
538 struct r600_pipe_shader_selector * sel)
539 {
540 struct r600_context *rctx = (struct r600_context *)ctx;
541 unsigned key;
542
543 if (sel->type == PIPE_SHADER_FRAGMENT) {
544 key = rctx->two_side |
545 MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 1;
546 } else
547 key = 0;
548
549 return key;
550 }
551
552 /* Select the hw shader variant depending on the current state.
553 * (*dirty) is set to 1 if current variant was changed */
554 static int r600_shader_select(struct pipe_context *ctx,
555 struct r600_pipe_shader_selector* sel,
556 unsigned *dirty)
557 {
558 unsigned key;
559 struct r600_context *rctx = (struct r600_context *)ctx;
560 struct r600_pipe_shader * shader = NULL;
561 int r;
562
563 key = r600_shader_selector_key(ctx, sel);
564
565 /* Check if we don't need to change anything.
566 * This path is also used for most shaders that don't need multiple
567 * variants, it will cost just a computation of the key and this
568 * test. */
569 if (likely(sel->current && sel->current->key == key)) {
570 return 0;
571 }
572
573 /* lookup if we have other variants in the list */
574 if (sel->num_shaders > 1) {
575 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
576
577 while (c && c->key != key) {
578 p = c;
579 c = c->next_variant;
580 }
581
582 if (c) {
583 p->next_variant = c->next_variant;
584 shader = c;
585 }
586 }
587
588 if (unlikely(!shader)) {
589 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
590 shader->selector = sel;
591
592 r = r600_pipe_shader_create(ctx, shader);
593 if (unlikely(r)) {
594 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
595 sel->type, key, r);
596 sel->current = NULL;
597 return r;
598 }
599
600 /* We don't know the value of nr_ps_max_color_exports until we built
601 * at least one variant, so we may need to recompute the key after
602 * building first variant. */
603 if (sel->type == PIPE_SHADER_FRAGMENT &&
604 sel->num_shaders == 0) {
605 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
606 key = r600_shader_selector_key(ctx, sel);
607 }
608
609 shader->key = key;
610 sel->num_shaders++;
611 }
612
613 if (dirty)
614 *dirty = 1;
615
616 shader->next_variant = sel->current;
617 sel->current = shader;
618
619 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
620 r600_adjust_gprs(rctx);
621 }
622
623 if (rctx->ps_shader &&
624 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
625 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
626 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
627 }
628 return 0;
629 }
630
631 static void *r600_create_shader_state(struct pipe_context *ctx,
632 const struct pipe_shader_state *state,
633 unsigned pipe_shader_type)
634 {
635 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
636 int r;
637
638 sel->type = pipe_shader_type;
639 sel->tokens = tgsi_dup_tokens(state->tokens);
640 sel->so = state->stream_output;
641
642 r = r600_shader_select(ctx, sel, NULL);
643 if (r)
644 return NULL;
645
646 return sel;
647 }
648
649 void *r600_create_shader_state_ps(struct pipe_context *ctx,
650 const struct pipe_shader_state *state)
651 {
652 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
653 }
654
655 void *r600_create_shader_state_vs(struct pipe_context *ctx,
656 const struct pipe_shader_state *state)
657 {
658 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
659 }
660
661 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
662 {
663 struct r600_context *rctx = (struct r600_context *)ctx;
664
665 if (!state)
666 state = rctx->dummy_pixel_shader;
667
668 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
669 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
670
671 if (rctx->chip_class <= R700) {
672 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
673
674 if (rctx->cb_misc_state.multiwrite != multiwrite) {
675 rctx->cb_misc_state.multiwrite = multiwrite;
676 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
677 }
678
679 if (rctx->vs_shader)
680 r600_adjust_gprs(rctx);
681 }
682
683 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
684 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
685 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
686 }
687 }
688
689 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
690 {
691 struct r600_context *rctx = (struct r600_context *)ctx;
692
693 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
694 if (state) {
695 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
696
697 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
698 r600_adjust_gprs(rctx);
699 }
700 }
701
702 static void r600_delete_shader_selector(struct pipe_context *ctx,
703 struct r600_pipe_shader_selector *sel)
704 {
705 struct r600_pipe_shader *p = sel->current, *c;
706 while (p) {
707 c = p->next_variant;
708 r600_pipe_shader_destroy(ctx, p);
709 free(p);
710 p = c;
711 }
712
713 free(sel->tokens);
714 free(sel);
715 }
716
717
718 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
719 {
720 struct r600_context *rctx = (struct r600_context *)ctx;
721 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
722
723 if (rctx->ps_shader == sel) {
724 rctx->ps_shader = NULL;
725 }
726
727 r600_delete_shader_selector(ctx, sel);
728 }
729
730 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
731 {
732 struct r600_context *rctx = (struct r600_context *)ctx;
733 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
734
735 if (rctx->vs_shader == sel) {
736 rctx->vs_shader = NULL;
737 }
738
739 r600_delete_shader_selector(ctx, sel);
740 }
741
742 static void r600_update_alpha_ref(struct r600_context *rctx)
743 {
744 unsigned alpha_ref;
745 struct r600_pipe_state rstate;
746
747 alpha_ref = rctx->alpha_ref;
748 rstate.nregs = 0;
749 if (rctx->export_16bpc && rctx->chip_class >= EVERGREEN) {
750 alpha_ref &= ~0x1FFF;
751 }
752 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
753
754 r600_context_pipe_state_set(rctx, &rstate);
755 rctx->alpha_ref_dirty = false;
756 }
757
758 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
759 {
760 r600_inval_shader_cache(rctx);
761 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
762 : util_bitcount(state->dirty_mask)*19;
763 r600_atom_dirty(rctx, &state->atom);
764 }
765
766 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
767 struct pipe_constant_buffer *input)
768 {
769 struct r600_context *rctx = (struct r600_context *)ctx;
770 struct r600_constbuf_state *state;
771 struct pipe_constant_buffer *cb;
772 const uint8_t *ptr;
773
774 switch (shader) {
775 case PIPE_SHADER_VERTEX:
776 state = &rctx->vs_constbuf_state;
777 break;
778 case PIPE_SHADER_FRAGMENT:
779 state = &rctx->ps_constbuf_state;
780 break;
781 default:
782 return;
783 }
784
785 /* Note that the state tracker can unbind constant buffers by
786 * passing NULL here.
787 */
788 if (unlikely(!input)) {
789 state->enabled_mask &= ~(1 << index);
790 state->dirty_mask &= ~(1 << index);
791 pipe_resource_reference(&state->cb[index].buffer, NULL);
792 return;
793 }
794
795 cb = &state->cb[index];
796 cb->buffer_size = input->buffer_size;
797
798 ptr = input->user_buffer;
799
800 if (ptr) {
801 /* Upload the user buffer. */
802 if (R600_BIG_ENDIAN) {
803 uint32_t *tmpPtr;
804 unsigned i, size = input->buffer_size;
805
806 if (!(tmpPtr = malloc(size))) {
807 R600_ERR("Failed to allocate BE swap buffer.\n");
808 return;
809 }
810
811 for (i = 0; i < size / 4; ++i) {
812 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
813 }
814
815 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
816 free(tmpPtr);
817 } else {
818 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
819 }
820 } else {
821 /* Setup the hw buffer. */
822 cb->buffer_offset = input->buffer_offset;
823 pipe_resource_reference(&cb->buffer, input->buffer);
824 }
825
826 state->enabled_mask |= 1 << index;
827 state->dirty_mask |= 1 << index;
828 r600_constant_buffers_dirty(rctx, state);
829 }
830
831 struct pipe_stream_output_target *
832 r600_create_so_target(struct pipe_context *ctx,
833 struct pipe_resource *buffer,
834 unsigned buffer_offset,
835 unsigned buffer_size)
836 {
837 struct r600_context *rctx = (struct r600_context *)ctx;
838 struct r600_so_target *t;
839 void *ptr;
840
841 t = CALLOC_STRUCT(r600_so_target);
842 if (!t) {
843 return NULL;
844 }
845
846 t->b.reference.count = 1;
847 t->b.context = ctx;
848 pipe_resource_reference(&t->b.buffer, buffer);
849 t->b.buffer_offset = buffer_offset;
850 t->b.buffer_size = buffer_size;
851
852 t->filled_size = (struct r600_resource*)
853 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
854 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
855 memset(ptr, 0, t->filled_size->buf->size);
856 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
857
858 return &t->b;
859 }
860
861 void r600_so_target_destroy(struct pipe_context *ctx,
862 struct pipe_stream_output_target *target)
863 {
864 struct r600_so_target *t = (struct r600_so_target*)target;
865 pipe_resource_reference(&t->b.buffer, NULL);
866 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
867 FREE(t);
868 }
869
870 void r600_set_so_targets(struct pipe_context *ctx,
871 unsigned num_targets,
872 struct pipe_stream_output_target **targets,
873 unsigned append_bitmask)
874 {
875 struct r600_context *rctx = (struct r600_context *)ctx;
876 unsigned i;
877
878 /* Stop streamout. */
879 if (rctx->num_so_targets && !rctx->streamout_start) {
880 r600_context_streamout_end(rctx);
881 }
882
883 /* Set the new targets. */
884 for (i = 0; i < num_targets; i++) {
885 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
886 }
887 for (; i < rctx->num_so_targets; i++) {
888 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
889 }
890
891 rctx->num_so_targets = num_targets;
892 rctx->streamout_start = num_targets != 0;
893 rctx->streamout_append_bitmask = append_bitmask;
894 }
895
896 static void r600_update_derived_state(struct r600_context *rctx)
897 {
898 struct pipe_context * ctx = (struct pipe_context*)rctx;
899 unsigned ps_dirty = 0;
900
901 if (!rctx->blitter->running) {
902 /* Flush depth textures which need to be flushed. */
903 if (rctx->vs_samplers.depth_texture_mask) {
904 r600_flush_depth_textures(rctx, &rctx->vs_samplers);
905 }
906 if (rctx->ps_samplers.depth_texture_mask) {
907 r600_flush_depth_textures(rctx, &rctx->ps_samplers);
908 }
909 }
910
911 if (rctx->chip_class < EVERGREEN) {
912 r600_update_sampler_states(rctx);
913 }
914
915 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
916
917 if (rctx->alpha_ref_dirty) {
918 r600_update_alpha_ref(rctx);
919 }
920
921 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
922 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
923 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
924
925 if (rctx->chip_class >= EVERGREEN)
926 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
927 else
928 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
929
930 ps_dirty = 1;
931 }
932
933 if (ps_dirty)
934 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
935
936 if (rctx->chip_class >= EVERGREEN) {
937 evergreen_update_dual_export_state(rctx);
938 } else {
939 r600_update_dual_export_state(rctx);
940 }
941 }
942
943 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
944 {
945 static const int prim_conv[] = {
946 V_028A6C_OUTPRIM_TYPE_POINTLIST,
947 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
948 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
949 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
950 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
951 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
952 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
953 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
954 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
955 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
956 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
957 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
958 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
959 V_028A6C_OUTPRIM_TYPE_TRISTRIP
960 };
961 assert(mode < Elements(prim_conv));
962
963 return prim_conv[mode];
964 }
965
966 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
967 {
968 struct r600_context *rctx = (struct r600_context *)ctx;
969 struct pipe_draw_info info = *dinfo;
970 struct pipe_index_buffer ib = {};
971 unsigned prim, ls_mask = 0;
972 struct r600_block *dirty_block = NULL, *next_block = NULL;
973 struct r600_atom *state = NULL, *next_state = NULL;
974 struct radeon_winsys_cs *cs = rctx->cs;
975 uint64_t va;
976 uint8_t *ptr;
977
978 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
979 !r600_conv_pipe_prim(info.mode, &prim)) {
980 assert(0);
981 return;
982 }
983
984 if (!rctx->vs_shader) {
985 assert(0);
986 return;
987 }
988
989 r600_update_derived_state(rctx);
990
991 if (info.indexed) {
992 /* Initialize the index buffer struct. */
993 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
994 ib.user_buffer = rctx->index_buffer.user_buffer;
995 ib.index_size = rctx->index_buffer.index_size;
996 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
997
998 /* Translate or upload, if needed. */
999 r600_translate_index_buffer(rctx, &ib, info.count);
1000
1001 ptr = (uint8_t*)ib.user_buffer;
1002 if (!ib.buffer && ptr) {
1003 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1004 ptr, &ib.offset, &ib.buffer);
1005 }
1006 } else {
1007 info.index_bias = info.start;
1008 if (info.count_from_stream_output) {
1009 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
1010 }
1011 }
1012
1013 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
1014 rctx->vgt.id = R600_PIPE_STATE_VGT;
1015 rctx->vgt.nregs = 0;
1016 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
1017 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
1018 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
1019 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
1020 r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
1021 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
1022 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1023 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
1024 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
1025 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
1026 }
1027
1028 rctx->vgt.nregs = 0;
1029 r600_pipe_state_mod_reg(&rctx->vgt, prim);
1030 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
1031 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
1032 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
1033 r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
1034 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
1035 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
1036
1037 if (prim == V_008958_DI_PT_LINELIST)
1038 ls_mask = 1;
1039 else if (prim == V_008958_DI_PT_LINESTRIP)
1040 ls_mask = 2;
1041 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
1042 r600_pipe_state_mod_reg(&rctx->vgt,
1043 rctx->vs_shader->current->pa_cl_vs_out_cntl |
1044 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
1045 r600_pipe_state_mod_reg(&rctx->vgt,
1046 rctx->pa_cl_clip_cntl |
1047 (rctx->vs_shader->current->shader.clip_dist_write ||
1048 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
1049 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
1050
1051 r600_context_pipe_state_set(rctx, &rctx->vgt);
1052
1053 /* Emit states (the function expects that we emit at most 17 dwords here). */
1054 r600_need_cs_space(rctx, 0, TRUE);
1055
1056 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
1057 r600_emit_atom(rctx, state);
1058 }
1059 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1060 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1061 }
1062 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
1063 r600_context_block_resource_emit_dirty(rctx, dirty_block);
1064 }
1065 rctx->pm4_dirty_cdwords = 0;
1066
1067 /* Enable stream out if needed. */
1068 if (rctx->streamout_start) {
1069 r600_context_streamout_begin(rctx);
1070 rctx->streamout_start = FALSE;
1071 }
1072
1073 /* draw packet */
1074 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1075 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1076 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1077 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1078 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1079 cs->buf[cs->cdw++] = info.instance_count;
1080 if (info.indexed) {
1081 va = r600_resource_va(ctx->screen, ib.buffer);
1082 va += ib.offset;
1083 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1084 cs->buf[cs->cdw++] = va;
1085 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1086 cs->buf[cs->cdw++] = info.count;
1087 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1088 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1089 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1090 } else {
1091 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1092 cs->buf[cs->cdw++] = info.count;
1093 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1094 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1095 }
1096
1097 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
1098
1099 /* Set the depth buffer as dirty. */
1100 if (rctx->framebuffer.zsbuf) {
1101 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
1102 struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
1103
1104 rtex->dirty_db_mask |= 1 << surf->u.tex.level;
1105 }
1106
1107 pipe_resource_reference(&ib.buffer, NULL);
1108 }
1109
1110 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1111 struct r600_pipe_state *state,
1112 uint32_t offset, uint32_t value,
1113 uint32_t range_id, uint32_t block_id,
1114 struct r600_resource *bo,
1115 enum radeon_bo_usage usage)
1116
1117 {
1118 struct r600_range *range;
1119 struct r600_block *block;
1120
1121 if (bo) assert(usage);
1122
1123 range = &ctx->range[range_id];
1124 block = range->blocks[block_id];
1125 state->regs[state->nregs].block = block;
1126 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1127
1128 state->regs[state->nregs].value = value;
1129 state->regs[state->nregs].bo = bo;
1130 state->regs[state->nregs].bo_usage = usage;
1131
1132 state->nregs++;
1133 assert(state->nregs < R600_BLOCK_MAX_REG);
1134 }
1135
1136 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1137 struct r600_pipe_state *state,
1138 uint32_t offset, uint32_t value,
1139 uint32_t range_id, uint32_t block_id)
1140 {
1141 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1142 range_id, block_id, NULL, 0);
1143 }
1144
1145 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
1146 uint32_t offset, uint32_t value,
1147 struct r600_resource *bo,
1148 enum radeon_bo_usage usage)
1149 {
1150 if (bo) assert(usage);
1151
1152 state->regs[state->nregs].id = offset;
1153 state->regs[state->nregs].block = NULL;
1154 state->regs[state->nregs].value = value;
1155 state->regs[state->nregs].bo = bo;
1156 state->regs[state->nregs].bo_usage = usage;
1157
1158 state->nregs++;
1159 assert(state->nregs < R600_BLOCK_MAX_REG);
1160 }
1161
1162 uint32_t r600_translate_stencil_op(int s_op)
1163 {
1164 switch (s_op) {
1165 case PIPE_STENCIL_OP_KEEP:
1166 return V_028800_STENCIL_KEEP;
1167 case PIPE_STENCIL_OP_ZERO:
1168 return V_028800_STENCIL_ZERO;
1169 case PIPE_STENCIL_OP_REPLACE:
1170 return V_028800_STENCIL_REPLACE;
1171 case PIPE_STENCIL_OP_INCR:
1172 return V_028800_STENCIL_INCR;
1173 case PIPE_STENCIL_OP_DECR:
1174 return V_028800_STENCIL_DECR;
1175 case PIPE_STENCIL_OP_INCR_WRAP:
1176 return V_028800_STENCIL_INCR_WRAP;
1177 case PIPE_STENCIL_OP_DECR_WRAP:
1178 return V_028800_STENCIL_DECR_WRAP;
1179 case PIPE_STENCIL_OP_INVERT:
1180 return V_028800_STENCIL_INVERT;
1181 default:
1182 R600_ERR("Unknown stencil op %d", s_op);
1183 assert(0);
1184 break;
1185 }
1186 return 0;
1187 }
1188
1189 uint32_t r600_translate_fill(uint32_t func)
1190 {
1191 switch(func) {
1192 case PIPE_POLYGON_MODE_FILL:
1193 return 2;
1194 case PIPE_POLYGON_MODE_LINE:
1195 return 1;
1196 case PIPE_POLYGON_MODE_POINT:
1197 return 0;
1198 default:
1199 assert(0);
1200 return 0;
1201 }
1202 }
1203
1204 unsigned r600_tex_wrap(unsigned wrap)
1205 {
1206 switch (wrap) {
1207 default:
1208 case PIPE_TEX_WRAP_REPEAT:
1209 return V_03C000_SQ_TEX_WRAP;
1210 case PIPE_TEX_WRAP_CLAMP:
1211 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1212 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1213 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1214 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1215 return V_03C000_SQ_TEX_CLAMP_BORDER;
1216 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1217 return V_03C000_SQ_TEX_MIRROR;
1218 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1219 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1220 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1221 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1222 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1223 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1224 }
1225 }
1226
1227 unsigned r600_tex_filter(unsigned filter)
1228 {
1229 switch (filter) {
1230 default:
1231 case PIPE_TEX_FILTER_NEAREST:
1232 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1233 case PIPE_TEX_FILTER_LINEAR:
1234 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1235 }
1236 }
1237
1238 unsigned r600_tex_mipfilter(unsigned filter)
1239 {
1240 switch (filter) {
1241 case PIPE_TEX_MIPFILTER_NEAREST:
1242 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1243 case PIPE_TEX_MIPFILTER_LINEAR:
1244 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1245 default:
1246 case PIPE_TEX_MIPFILTER_NONE:
1247 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1248 }
1249 }
1250
1251 unsigned r600_tex_compare(unsigned compare)
1252 {
1253 switch (compare) {
1254 default:
1255 case PIPE_FUNC_NEVER:
1256 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1257 case PIPE_FUNC_LESS:
1258 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1259 case PIPE_FUNC_EQUAL:
1260 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1261 case PIPE_FUNC_LEQUAL:
1262 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1263 case PIPE_FUNC_GREATER:
1264 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1265 case PIPE_FUNC_NOTEQUAL:
1266 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1267 case PIPE_FUNC_GEQUAL:
1268 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1269 case PIPE_FUNC_ALWAYS:
1270 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1271 }
1272 }