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r600g/sb: dump sampler/resource index modes for textures.
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38
39 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
40 {
41 assert(!cb->buf);
42 cb->buf = CALLOC(1, 4 * num_dw);
43 cb->max_num_dw = num_dw;
44 }
45
46 void r600_release_command_buffer(struct r600_command_buffer *cb)
47 {
48 FREE(cb->buf);
49 }
50
51 void r600_add_atom(struct r600_context *rctx,
52 struct r600_atom *atom,
53 unsigned id)
54 {
55 assert(id < R600_NUM_ATOMS);
56 assert(rctx->atoms[id] == NULL);
57 rctx->atoms[id] = atom;
58 atom->id = id;
59 atom->dirty = false;
60 }
61
62 void r600_init_atom(struct r600_context *rctx,
63 struct r600_atom *atom,
64 unsigned id,
65 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
66 unsigned num_dw)
67 {
68 atom->emit = (void*)emit;
69 atom->num_dw = num_dw;
70 r600_add_atom(rctx, atom, id);
71 }
72
73 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
76 }
77
78 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
79 {
80 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
81 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
82 unsigned alpha_ref = a->sx_alpha_ref;
83
84 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
85 alpha_ref &= ~0x1FFF;
86 }
87
88 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
89 a->sx_alpha_test_control |
90 S_028410_ALPHA_TEST_BYPASS(a->bypass));
91 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
92 }
93
94 static void r600_texture_barrier(struct pipe_context *ctx)
95 {
96 struct r600_context *rctx = (struct r600_context *)ctx;
97
98 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
99 R600_CONTEXT_FLUSH_AND_INV_CB |
100 R600_CONTEXT_FLUSH_AND_INV |
101 R600_CONTEXT_WAIT_3D_IDLE;
102 }
103
104 static unsigned r600_conv_pipe_prim(unsigned prim)
105 {
106 static const unsigned prim_conv[] = {
107 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
108 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
109 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
110 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
111 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
112 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
113 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
114 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
115 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
116 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
117 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
118 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
119 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
120 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
121 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
122 };
123 assert(prim < Elements(prim_conv));
124 return prim_conv[prim];
125 }
126
127 unsigned r600_conv_prim_to_gs_out(unsigned mode)
128 {
129 static const int prim_conv[] = {
130 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
131 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
132 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
133 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
134 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
135 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
136 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
137 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
138 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
139 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
140 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
141 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
142 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
143 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
144 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
145 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
146 };
147 assert(mode < Elements(prim_conv));
148
149 return prim_conv[mode];
150 }
151
152 /* common state between evergreen and r600 */
153
154 static void r600_bind_blend_state_internal(struct r600_context *rctx,
155 struct r600_blend_state *blend, bool blend_disable)
156 {
157 unsigned color_control;
158 bool update_cb = false;
159
160 rctx->alpha_to_one = blend->alpha_to_one;
161 rctx->dual_src_blend = blend->dual_src_blend;
162
163 if (!blend_disable) {
164 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
165 color_control = blend->cb_color_control;
166 } else {
167 /* Blending is disabled. */
168 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
169 color_control = blend->cb_color_control_no_blend;
170 }
171
172 /* Update derived states. */
173 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
174 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
175 update_cb = true;
176 }
177 if (rctx->b.chip_class <= R700 &&
178 rctx->cb_misc_state.cb_color_control != color_control) {
179 rctx->cb_misc_state.cb_color_control = color_control;
180 update_cb = true;
181 }
182 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
183 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
184 update_cb = true;
185 }
186 if (update_cb) {
187 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
188 }
189 }
190
191 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
192 {
193 struct r600_context *rctx = (struct r600_context *)ctx;
194 struct r600_blend_state *blend = (struct r600_blend_state *)state;
195
196 if (blend == NULL) {
197 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
198 return;
199 }
200
201 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
202 }
203
204 static void r600_set_blend_color(struct pipe_context *ctx,
205 const struct pipe_blend_color *state)
206 {
207 struct r600_context *rctx = (struct r600_context *)ctx;
208
209 rctx->blend_color.state = *state;
210 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
211 }
212
213 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
214 {
215 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
216 struct pipe_blend_color *state = &rctx->blend_color.state;
217
218 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
219 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
220 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
221 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
222 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
223 }
224
225 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
226 {
227 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
228 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
229
230 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
231 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
232 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
233 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
234 if (a->last_draw_was_indirect) {
235 a->last_draw_was_indirect = false;
236 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
237 }
238 }
239
240 static void r600_set_clip_state(struct pipe_context *ctx,
241 const struct pipe_clip_state *state)
242 {
243 struct r600_context *rctx = (struct r600_context *)ctx;
244 struct pipe_constant_buffer cb;
245
246 rctx->clip_state.state = *state;
247 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
248
249 cb.buffer = NULL;
250 cb.user_buffer = state->ucp;
251 cb.buffer_offset = 0;
252 cb.buffer_size = 4*4*8;
253 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
254 pipe_resource_reference(&cb.buffer, NULL);
255 }
256
257 static void r600_set_stencil_ref(struct pipe_context *ctx,
258 const struct r600_stencil_ref *state)
259 {
260 struct r600_context *rctx = (struct r600_context *)ctx;
261
262 rctx->stencil_ref.state = *state;
263 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
264 }
265
266 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
267 {
268 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
269 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
270
271 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
272 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
273 S_028430_STENCILREF(a->state.ref_value[0]) |
274 S_028430_STENCILMASK(a->state.valuemask[0]) |
275 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
276 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
277 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
278 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
279 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
280 }
281
282 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
283 const struct pipe_stencil_ref *state)
284 {
285 struct r600_context *rctx = (struct r600_context *)ctx;
286 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
287 struct r600_stencil_ref ref;
288
289 rctx->stencil_ref.pipe_state = *state;
290
291 if (!dsa)
292 return;
293
294 ref.ref_value[0] = state->ref_value[0];
295 ref.ref_value[1] = state->ref_value[1];
296 ref.valuemask[0] = dsa->valuemask[0];
297 ref.valuemask[1] = dsa->valuemask[1];
298 ref.writemask[0] = dsa->writemask[0];
299 ref.writemask[1] = dsa->writemask[1];
300
301 r600_set_stencil_ref(ctx, &ref);
302 }
303
304 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
305 {
306 struct r600_context *rctx = (struct r600_context *)ctx;
307 struct r600_dsa_state *dsa = state;
308 struct r600_stencil_ref ref;
309
310 if (state == NULL) {
311 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
312 return;
313 }
314
315 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
316
317 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
318 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
319 ref.valuemask[0] = dsa->valuemask[0];
320 ref.valuemask[1] = dsa->valuemask[1];
321 ref.writemask[0] = dsa->writemask[0];
322 ref.writemask[1] = dsa->writemask[1];
323 if (rctx->zwritemask != dsa->zwritemask) {
324 rctx->zwritemask = dsa->zwritemask;
325 if (rctx->b.chip_class >= EVERGREEN) {
326 /* work around some issue when not writing to zbuffer
327 * we are having lockup on evergreen so do not enable
328 * hyperz when not writing zbuffer
329 */
330 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
331 }
332 }
333
334 r600_set_stencil_ref(ctx, &ref);
335
336 /* Update alphatest state. */
337 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
338 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
339 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
340 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
341 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
342 }
343 }
344
345 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
346 {
347 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
348 struct r600_context *rctx = (struct r600_context *)ctx;
349
350 if (state == NULL)
351 return;
352
353 rctx->rasterizer = rs;
354
355 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
356
357 if (rs->offset_enable &&
358 (rs->offset_units != rctx->poly_offset_state.offset_units ||
359 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
360 rctx->poly_offset_state.offset_units = rs->offset_units;
361 rctx->poly_offset_state.offset_scale = rs->offset_scale;
362 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
363 }
364
365 /* Update clip_misc_state. */
366 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
367 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
368 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
369 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
370 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
371 }
372
373 /* Workaround for a missing scissor enable on r600. */
374 if (rctx->b.chip_class == R600 &&
375 rs->scissor_enable != rctx->scissor[0].enable) {
376 rctx->scissor[0].enable = rs->scissor_enable;
377 r600_mark_atom_dirty(rctx, &rctx->scissor[0].atom);
378 }
379
380 /* Re-emit PA_SC_LINE_STIPPLE. */
381 rctx->last_primitive_type = -1;
382 }
383
384 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
385 {
386 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
387
388 r600_release_command_buffer(&rs->buffer);
389 FREE(rs);
390 }
391
392 static void r600_sampler_view_destroy(struct pipe_context *ctx,
393 struct pipe_sampler_view *state)
394 {
395 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
396
397 if (view->tex_resource->gpu_address &&
398 view->tex_resource->b.b.target == PIPE_BUFFER)
399 LIST_DELINIT(&view->list);
400
401 pipe_resource_reference(&state->texture, NULL);
402 FREE(view);
403 }
404
405 void r600_sampler_states_dirty(struct r600_context *rctx,
406 struct r600_sampler_states *state)
407 {
408 if (state->dirty_mask) {
409 if (state->dirty_mask & state->has_bordercolor_mask) {
410 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
411 }
412 state->atom.num_dw =
413 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
414 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
415 r600_mark_atom_dirty(rctx, &state->atom);
416 }
417 }
418
419 static void r600_bind_sampler_states(struct pipe_context *pipe,
420 unsigned shader,
421 unsigned start,
422 unsigned count, void **states)
423 {
424 struct r600_context *rctx = (struct r600_context *)pipe;
425 struct r600_textures_info *dst = &rctx->samplers[shader];
426 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
427 int seamless_cube_map = -1;
428 unsigned i;
429 /* This sets 1-bit for states with index >= count. */
430 uint32_t disable_mask = ~((1ull << count) - 1);
431 /* These are the new states set by this function. */
432 uint32_t new_mask = 0;
433
434 assert(start == 0); /* XXX fix below */
435
436 if (!states) {
437 disable_mask = ~0u;
438 count = 0;
439 }
440
441 for (i = 0; i < count; i++) {
442 struct r600_pipe_sampler_state *rstate = rstates[i];
443
444 if (rstate == dst->states.states[i]) {
445 continue;
446 }
447
448 if (rstate) {
449 if (rstate->border_color_use) {
450 dst->states.has_bordercolor_mask |= 1 << i;
451 } else {
452 dst->states.has_bordercolor_mask &= ~(1 << i);
453 }
454 seamless_cube_map = rstate->seamless_cube_map;
455
456 new_mask |= 1 << i;
457 } else {
458 disable_mask |= 1 << i;
459 }
460 }
461
462 memcpy(dst->states.states, rstates, sizeof(void*) * count);
463 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
464
465 dst->states.enabled_mask &= ~disable_mask;
466 dst->states.dirty_mask &= dst->states.enabled_mask;
467 dst->states.enabled_mask |= new_mask;
468 dst->states.dirty_mask |= new_mask;
469 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
470
471 r600_sampler_states_dirty(rctx, &dst->states);
472
473 /* Seamless cubemap state. */
474 if (rctx->b.chip_class <= R700 &&
475 seamless_cube_map != -1 &&
476 seamless_cube_map != rctx->seamless_cube_map.enabled) {
477 /* change in TA_CNTL_AUX need a pipeline flush */
478 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
479 rctx->seamless_cube_map.enabled = seamless_cube_map;
480 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
481 }
482 }
483
484 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
485 {
486 free(state);
487 }
488
489 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
490 {
491 struct r600_context *rctx = (struct r600_context *)ctx;
492 struct r600_blend_state *blend = (struct r600_blend_state*)state;
493
494 if (rctx->blend_state.cso == state) {
495 ctx->bind_blend_state(ctx, NULL);
496 }
497
498 r600_release_command_buffer(&blend->buffer);
499 r600_release_command_buffer(&blend->buffer_no_blend);
500 FREE(blend);
501 }
502
503 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
504 {
505 struct r600_context *rctx = (struct r600_context *)ctx;
506 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
507
508 if (rctx->dsa_state.cso == state) {
509 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
510 }
511
512 r600_release_command_buffer(&dsa->buffer);
513 free(dsa);
514 }
515
516 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
517 {
518 struct r600_context *rctx = (struct r600_context *)ctx;
519
520 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
521 }
522
523 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
524 {
525 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
526 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
527 FREE(shader);
528 }
529
530 static void r600_set_index_buffer(struct pipe_context *ctx,
531 const struct pipe_index_buffer *ib)
532 {
533 struct r600_context *rctx = (struct r600_context *)ctx;
534
535 if (ib) {
536 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
537 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
538 r600_context_add_resource_size(ctx, ib->buffer);
539 } else {
540 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
541 }
542 }
543
544 void r600_vertex_buffers_dirty(struct r600_context *rctx)
545 {
546 if (rctx->vertex_buffer_state.dirty_mask) {
547 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
548 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
549 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
550 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
551 }
552 }
553
554 static void r600_set_vertex_buffers(struct pipe_context *ctx,
555 unsigned start_slot, unsigned count,
556 const struct pipe_vertex_buffer *input)
557 {
558 struct r600_context *rctx = (struct r600_context *)ctx;
559 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
560 struct pipe_vertex_buffer *vb = state->vb + start_slot;
561 unsigned i;
562 uint32_t disable_mask = 0;
563 /* These are the new buffers set by this function. */
564 uint32_t new_buffer_mask = 0;
565
566 /* Set vertex buffers. */
567 if (input) {
568 for (i = 0; i < count; i++) {
569 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
570 if (input[i].buffer) {
571 vb[i].stride = input[i].stride;
572 vb[i].buffer_offset = input[i].buffer_offset;
573 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
574 new_buffer_mask |= 1 << i;
575 r600_context_add_resource_size(ctx, input[i].buffer);
576 } else {
577 pipe_resource_reference(&vb[i].buffer, NULL);
578 disable_mask |= 1 << i;
579 }
580 }
581 }
582 } else {
583 for (i = 0; i < count; i++) {
584 pipe_resource_reference(&vb[i].buffer, NULL);
585 }
586 disable_mask = ((1ull << count) - 1);
587 }
588
589 disable_mask <<= start_slot;
590 new_buffer_mask <<= start_slot;
591
592 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
593 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
594 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
595 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
596
597 r600_vertex_buffers_dirty(rctx);
598 }
599
600 void r600_sampler_views_dirty(struct r600_context *rctx,
601 struct r600_samplerview_state *state)
602 {
603 if (state->dirty_mask) {
604 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
605 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
606 util_bitcount(state->dirty_mask);
607 r600_mark_atom_dirty(rctx, &state->atom);
608 }
609 }
610
611 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
612 unsigned start, unsigned count,
613 struct pipe_sampler_view **views)
614 {
615 struct r600_context *rctx = (struct r600_context *) pipe;
616 struct r600_textures_info *dst = &rctx->samplers[shader];
617 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
618 uint32_t dirty_sampler_states_mask = 0;
619 unsigned i;
620 /* This sets 1-bit for textures with index >= count. */
621 uint32_t disable_mask = ~((1ull << count) - 1);
622 /* These are the new textures set by this function. */
623 uint32_t new_mask = 0;
624
625 /* Set textures with index >= count to NULL. */
626 uint32_t remaining_mask;
627
628 assert(start == 0); /* XXX fix below */
629
630 if (!views) {
631 disable_mask = ~0u;
632 count = 0;
633 }
634
635 remaining_mask = dst->views.enabled_mask & disable_mask;
636
637 while (remaining_mask) {
638 i = u_bit_scan(&remaining_mask);
639 assert(dst->views.views[i]);
640
641 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
642 }
643
644 for (i = 0; i < count; i++) {
645 if (rviews[i] == dst->views.views[i]) {
646 continue;
647 }
648
649 if (rviews[i]) {
650 struct r600_texture *rtex =
651 (struct r600_texture*)rviews[i]->base.texture;
652
653 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
654 if (rtex->is_depth && !rtex->is_flushing_texture) {
655 dst->views.compressed_depthtex_mask |= 1 << i;
656 } else {
657 dst->views.compressed_depthtex_mask &= ~(1 << i);
658 }
659
660 /* Track compressed colorbuffers. */
661 if (rtex->cmask.size) {
662 dst->views.compressed_colortex_mask |= 1 << i;
663 } else {
664 dst->views.compressed_colortex_mask &= ~(1 << i);
665 }
666 }
667 /* Changing from array to non-arrays textures and vice versa requires
668 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
669 if (rctx->b.chip_class <= R700 &&
670 (dst->states.enabled_mask & (1 << i)) &&
671 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
672 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
673 dirty_sampler_states_mask |= 1 << i;
674 }
675
676 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
677 new_mask |= 1 << i;
678 r600_context_add_resource_size(pipe, views[i]->texture);
679 } else {
680 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
681 disable_mask |= 1 << i;
682 }
683 }
684
685 dst->views.enabled_mask &= ~disable_mask;
686 dst->views.dirty_mask &= dst->views.enabled_mask;
687 dst->views.enabled_mask |= new_mask;
688 dst->views.dirty_mask |= new_mask;
689 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
690 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
691 dst->views.dirty_buffer_constants = TRUE;
692 r600_sampler_views_dirty(rctx, &dst->views);
693
694 if (dirty_sampler_states_mask) {
695 dst->states.dirty_mask |= dirty_sampler_states_mask;
696 r600_sampler_states_dirty(rctx, &dst->states);
697 }
698 }
699
700 static void r600_set_viewport_states(struct pipe_context *ctx,
701 unsigned start_slot,
702 unsigned num_viewports,
703 const struct pipe_viewport_state *state)
704 {
705 struct r600_context *rctx = (struct r600_context *)ctx;
706 int i;
707
708 for (i = start_slot; i < start_slot + num_viewports; i++) {
709 rctx->viewport[i].state = state[i - start_slot];
710 r600_mark_atom_dirty(rctx, &rctx->viewport[i].atom);
711 }
712 }
713
714 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
715 {
716 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
717 struct r600_viewport_state *rstate = (struct r600_viewport_state *)atom;
718 struct pipe_viewport_state *state = &rstate->state;
719 int offset = rstate->idx * 6 * 4;
720
721 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
722 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
723 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
724 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
725 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
726 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
727 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
728 }
729
730 /* Compute the key for the hw shader variant */
731 static inline union r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
732 struct r600_pipe_shader_selector * sel)
733 {
734 struct r600_context *rctx = (struct r600_context *)ctx;
735 union r600_shader_key key;
736 memset(&key, 0, sizeof(key));
737
738 switch (sel->type) {
739 case PIPE_SHADER_VERTEX: {
740 key.vs.as_es = (rctx->gs_shader != NULL);
741 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
742 key.vs.as_gs_a = true;
743 key.vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
744 }
745 break;
746 }
747 case PIPE_SHADER_GEOMETRY:
748 break;
749 case PIPE_SHADER_FRAGMENT: {
750 key.ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
751 key.ps.alpha_to_one = rctx->alpha_to_one &&
752 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
753 !rctx->framebuffer.cb0_is_integer;
754 key.ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
755 /* Dual-source blending only makes sense with nr_cbufs == 1. */
756 if (key.ps.nr_cbufs == 1 && rctx->dual_src_blend)
757 key.ps.nr_cbufs = 2;
758 break;
759 }
760 default:
761 assert(0);
762 }
763
764 return key;
765 }
766
767 /* Select the hw shader variant depending on the current state.
768 * (*dirty) is set to 1 if current variant was changed */
769 static int r600_shader_select(struct pipe_context *ctx,
770 struct r600_pipe_shader_selector* sel,
771 bool *dirty)
772 {
773 union r600_shader_key key;
774 struct r600_pipe_shader * shader = NULL;
775 int r;
776
777 memset(&key, 0, sizeof(key));
778 key = r600_shader_selector_key(ctx, sel);
779
780 /* Check if we don't need to change anything.
781 * This path is also used for most shaders that don't need multiple
782 * variants, it will cost just a computation of the key and this
783 * test. */
784 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
785 return 0;
786 }
787
788 /* lookup if we have other variants in the list */
789 if (sel->num_shaders > 1) {
790 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
791
792 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
793 p = c;
794 c = c->next_variant;
795 }
796
797 if (c) {
798 p->next_variant = c->next_variant;
799 shader = c;
800 }
801 }
802
803 if (unlikely(!shader)) {
804 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
805 shader->selector = sel;
806
807 r = r600_pipe_shader_create(ctx, shader, key);
808 if (unlikely(r)) {
809 R600_ERR("Failed to build shader variant (type=%u) %d\n",
810 sel->type, r);
811 sel->current = NULL;
812 FREE(shader);
813 return r;
814 }
815
816 /* We don't know the value of nr_ps_max_color_exports until we built
817 * at least one variant, so we may need to recompute the key after
818 * building first variant. */
819 if (sel->type == PIPE_SHADER_FRAGMENT &&
820 sel->num_shaders == 0) {
821 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
822 key = r600_shader_selector_key(ctx, sel);
823 }
824
825 memcpy(&shader->key, &key, sizeof(key));
826 sel->num_shaders++;
827 }
828
829 if (dirty)
830 *dirty = true;
831
832 shader->next_variant = sel->current;
833 sel->current = shader;
834
835 return 0;
836 }
837
838 static void *r600_create_shader_state(struct pipe_context *ctx,
839 const struct pipe_shader_state *state,
840 unsigned pipe_shader_type)
841 {
842 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
843
844 sel->type = pipe_shader_type;
845 sel->tokens = tgsi_dup_tokens(state->tokens);
846 sel->so = state->stream_output;
847 tgsi_scan_shader(state->tokens, &sel->info);
848
849 switch (pipe_shader_type) {
850 case PIPE_SHADER_GEOMETRY:
851 sel->gs_output_prim =
852 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
853 sel->gs_max_out_vertices =
854 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
855 sel->gs_num_invocations =
856 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
857 break;
858 }
859
860 return sel;
861 }
862
863 static void *r600_create_ps_state(struct pipe_context *ctx,
864 const struct pipe_shader_state *state)
865 {
866 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
867 }
868
869 static void *r600_create_vs_state(struct pipe_context *ctx,
870 const struct pipe_shader_state *state)
871 {
872 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
873 }
874
875 static void *r600_create_gs_state(struct pipe_context *ctx,
876 const struct pipe_shader_state *state)
877 {
878 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
879 }
880
881 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
882 {
883 struct r600_context *rctx = (struct r600_context *)ctx;
884
885 if (!state)
886 state = rctx->dummy_pixel_shader;
887
888 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
889 }
890
891 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
892 {
893 struct r600_context *rctx = (struct r600_context *)ctx;
894
895 if (!state)
896 return;
897
898 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
899 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
900 }
901
902 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
903 {
904 struct r600_context *rctx = (struct r600_context *)ctx;
905
906 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
907
908 if (!state)
909 return;
910 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
911 }
912
913 static void r600_delete_shader_selector(struct pipe_context *ctx,
914 struct r600_pipe_shader_selector *sel)
915 {
916 struct r600_pipe_shader *p = sel->current, *c;
917 while (p) {
918 c = p->next_variant;
919 r600_pipe_shader_destroy(ctx, p);
920 free(p);
921 p = c;
922 }
923
924 free(sel->tokens);
925 free(sel);
926 }
927
928
929 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
930 {
931 struct r600_context *rctx = (struct r600_context *)ctx;
932 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
933
934 if (rctx->ps_shader == sel) {
935 rctx->ps_shader = NULL;
936 }
937
938 r600_delete_shader_selector(ctx, sel);
939 }
940
941 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
942 {
943 struct r600_context *rctx = (struct r600_context *)ctx;
944 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
945
946 if (rctx->vs_shader == sel) {
947 rctx->vs_shader = NULL;
948 }
949
950 r600_delete_shader_selector(ctx, sel);
951 }
952
953
954 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
955 {
956 struct r600_context *rctx = (struct r600_context *)ctx;
957 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
958
959 if (rctx->gs_shader == sel) {
960 rctx->gs_shader = NULL;
961 }
962
963 r600_delete_shader_selector(ctx, sel);
964 }
965
966
967 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
968 {
969 if (state->dirty_mask) {
970 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
971 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
972 : util_bitcount(state->dirty_mask)*19;
973 r600_mark_atom_dirty(rctx, &state->atom);
974 }
975 }
976
977 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
978 struct pipe_constant_buffer *input)
979 {
980 struct r600_context *rctx = (struct r600_context *)ctx;
981 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
982 struct pipe_constant_buffer *cb;
983 const uint8_t *ptr;
984
985 /* Note that the state tracker can unbind constant buffers by
986 * passing NULL here.
987 */
988 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
989 state->enabled_mask &= ~(1 << index);
990 state->dirty_mask &= ~(1 << index);
991 pipe_resource_reference(&state->cb[index].buffer, NULL);
992 return;
993 }
994
995 cb = &state->cb[index];
996 cb->buffer_size = input->buffer_size;
997
998 ptr = input->user_buffer;
999
1000 if (ptr) {
1001 /* Upload the user buffer. */
1002 if (R600_BIG_ENDIAN) {
1003 uint32_t *tmpPtr;
1004 unsigned i, size = input->buffer_size;
1005
1006 if (!(tmpPtr = malloc(size))) {
1007 R600_ERR("Failed to allocate BE swap buffer.\n");
1008 return;
1009 }
1010
1011 for (i = 0; i < size / 4; ++i) {
1012 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1013 }
1014
1015 u_upload_data(rctx->b.uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
1016 free(tmpPtr);
1017 } else {
1018 u_upload_data(rctx->b.uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
1019 }
1020 /* account it in gtt */
1021 rctx->b.gtt += input->buffer_size;
1022 } else {
1023 /* Setup the hw buffer. */
1024 cb->buffer_offset = input->buffer_offset;
1025 pipe_resource_reference(&cb->buffer, input->buffer);
1026 r600_context_add_resource_size(ctx, input->buffer);
1027 }
1028
1029 state->enabled_mask |= 1 << index;
1030 state->dirty_mask |= 1 << index;
1031 r600_constant_buffers_dirty(rctx, state);
1032 }
1033
1034 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1035 {
1036 struct r600_context *rctx = (struct r600_context*)pipe;
1037
1038 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1039 return;
1040
1041 rctx->sample_mask.sample_mask = sample_mask;
1042 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1043 }
1044
1045 /*
1046 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1047 * doesn't require full swizzles it does need masking and setting alpha
1048 * to one, so we setup a set of 5 constants with the masks + alpha value
1049 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1050 * then OR the alpha with the value given here.
1051 * We use a 6th constant to store the txq buffer size in
1052 * we use 7th slot for number of cube layers in a cube map array.
1053 */
1054 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1055 {
1056 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1057 int bits;
1058 uint32_t array_size;
1059 struct pipe_constant_buffer cb;
1060 int i, j;
1061
1062 if (!samplers->views.dirty_buffer_constants)
1063 return;
1064
1065 samplers->views.dirty_buffer_constants = FALSE;
1066
1067 bits = util_last_bit(samplers->views.enabled_mask);
1068 array_size = bits * 8 * sizeof(uint32_t) * 4;
1069 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1070 memset(samplers->buffer_constants, 0, array_size);
1071 for (i = 0; i < bits; i++) {
1072 if (samplers->views.enabled_mask & (1 << i)) {
1073 int offset = i * 8;
1074 const struct util_format_description *desc;
1075 desc = util_format_description(samplers->views.views[i]->base.format);
1076
1077 for (j = 0; j < 4; j++)
1078 if (j < desc->nr_channels)
1079 samplers->buffer_constants[offset+j] = 0xffffffff;
1080 else
1081 samplers->buffer_constants[offset+j] = 0x0;
1082 if (desc->nr_channels < 4) {
1083 if (desc->channel[0].pure_integer)
1084 samplers->buffer_constants[offset+4] = 1;
1085 else
1086 samplers->buffer_constants[offset+4] = fui(1.0);
1087 } else
1088 samplers->buffer_constants[offset + 4] = 0;
1089
1090 samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1091 samplers->buffer_constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1092 }
1093 }
1094
1095 cb.buffer = NULL;
1096 cb.user_buffer = samplers->buffer_constants;
1097 cb.buffer_offset = 0;
1098 cb.buffer_size = array_size;
1099 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1100 pipe_resource_reference(&cb.buffer, NULL);
1101 }
1102
1103 /* On evergreen we store two values
1104 * 1. buffer size for TXQ
1105 * 2. number of cube layers in a cube map array.
1106 */
1107 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1108 {
1109 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1110 int bits;
1111 uint32_t array_size;
1112 struct pipe_constant_buffer cb;
1113 int i;
1114
1115 if (!samplers->views.dirty_buffer_constants)
1116 return;
1117
1118 samplers->views.dirty_buffer_constants = FALSE;
1119
1120 bits = util_last_bit(samplers->views.enabled_mask);
1121 array_size = bits * 2 * sizeof(uint32_t) * 4;
1122 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1123 memset(samplers->buffer_constants, 0, array_size);
1124 for (i = 0; i < bits; i++) {
1125 if (samplers->views.enabled_mask & (1 << i)) {
1126 uint32_t offset = i * 2;
1127 samplers->buffer_constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1128 samplers->buffer_constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
1129 }
1130 }
1131
1132 cb.buffer = NULL;
1133 cb.user_buffer = samplers->buffer_constants;
1134 cb.buffer_offset = 0;
1135 cb.buffer_size = array_size;
1136 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1137 pipe_resource_reference(&cb.buffer, NULL);
1138 }
1139
1140 /* set sample xy locations as array of fragment shader constants */
1141 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1142 {
1143 struct pipe_constant_buffer constbuf = {0};
1144 float values[4*16] = {0.0f};
1145 int i;
1146 struct pipe_context *ctx = &rctx->b.b;
1147
1148 assert(rctx->framebuffer.nr_samples <= Elements(values)/4);
1149 for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1150 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &values[4*i]);
1151 /* Also fill in center-zeroed positions used for interpolateAtSample */
1152 values[4*i + 2] = values[4*i + 0] - 0.5f;
1153 values[4*i + 3] = values[4*i + 1] - 0.5f;
1154 }
1155
1156 constbuf.user_buffer = values;
1157 constbuf.buffer_size = rctx->framebuffer.nr_samples * 4 * 4;
1158 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
1159 R600_SAMPLE_POSITIONS_CONST_BUFFER, &constbuf);
1160 pipe_resource_reference(&constbuf.buffer, NULL);
1161 }
1162
1163 static void update_shader_atom(struct pipe_context *ctx,
1164 struct r600_shader_state *state,
1165 struct r600_pipe_shader *shader)
1166 {
1167 struct r600_context *rctx = (struct r600_context *)ctx;
1168
1169 state->shader = shader;
1170 if (shader) {
1171 state->atom.num_dw = shader->command_buffer.num_dw;
1172 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1173 } else {
1174 state->atom.num_dw = 0;
1175 }
1176 r600_mark_atom_dirty(rctx, &state->atom);
1177 }
1178
1179 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1180 {
1181 if (rctx->shader_stages.geom_enable != enable) {
1182 rctx->shader_stages.geom_enable = enable;
1183 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1184 }
1185
1186 if (rctx->gs_rings.enable != enable) {
1187 rctx->gs_rings.enable = enable;
1188 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1189
1190 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1191 unsigned size = 0x1C000;
1192 rctx->gs_rings.esgs_ring.buffer =
1193 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1194 PIPE_USAGE_DEFAULT, size);
1195 rctx->gs_rings.esgs_ring.buffer_size = size;
1196
1197 size = 0x4000000;
1198
1199 rctx->gs_rings.gsvs_ring.buffer =
1200 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1201 PIPE_USAGE_DEFAULT, size);
1202 rctx->gs_rings.gsvs_ring.buffer_size = size;
1203 }
1204
1205 if (enable) {
1206 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1207 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1208 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1209 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1210 } else {
1211 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1212 R600_GS_RING_CONST_BUFFER, NULL);
1213 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1214 R600_GS_RING_CONST_BUFFER, NULL);
1215 }
1216 }
1217 }
1218
1219 static bool r600_update_derived_state(struct r600_context *rctx)
1220 {
1221 struct pipe_context * ctx = (struct pipe_context*)rctx;
1222 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1223 bool blend_disable;
1224 bool need_buf_const;
1225 if (!rctx->blitter->running) {
1226 unsigned i;
1227
1228 /* Decompress textures if needed. */
1229 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1230 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1231 if (views->compressed_depthtex_mask) {
1232 r600_decompress_depth_textures(rctx, views);
1233 }
1234 if (views->compressed_colortex_mask) {
1235 r600_decompress_color_textures(rctx, views);
1236 }
1237 }
1238 }
1239
1240 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1241 if (unlikely(!rctx->ps_shader->current))
1242 return false;
1243
1244 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1245
1246 if (rctx->gs_shader) {
1247 r600_shader_select(ctx, rctx->gs_shader, &gs_dirty);
1248 if (unlikely(!rctx->gs_shader->current))
1249 return false;
1250
1251 if (!rctx->shader_stages.geom_enable) {
1252 rctx->shader_stages.geom_enable = true;
1253 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1254 }
1255
1256 /* gs_shader provides GS and VS (copy shader) */
1257 if (unlikely(rctx->geometry_shader.shader != rctx->gs_shader->current)) {
1258 update_shader_atom(ctx, &rctx->geometry_shader, rctx->gs_shader->current);
1259 update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
1260 /* Update clip misc state. */
1261 if (rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1262 rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1263 rctx->clip_misc_state.clip_disable != rctx->gs_shader->current->shader.vs_position_window_space) {
1264 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl;
1265 rctx->clip_misc_state.clip_dist_write = rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write;
1266 rctx->clip_misc_state.clip_disable = rctx->gs_shader->current->shader.vs_position_window_space;
1267 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1268 }
1269 rctx->b.streamout.enabled_stream_buffers_mask = rctx->gs_shader->current->gs_copy_shader->enabled_stream_buffers_mask;
1270 }
1271
1272 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1273 if (unlikely(!rctx->vs_shader->current))
1274 return false;
1275
1276 /* vs_shader is used as ES */
1277 if (unlikely(vs_dirty || rctx->export_shader.shader != rctx->vs_shader->current)) {
1278 update_shader_atom(ctx, &rctx->export_shader, rctx->vs_shader->current);
1279 }
1280 } else {
1281 if (unlikely(rctx->geometry_shader.shader)) {
1282 update_shader_atom(ctx, &rctx->geometry_shader, NULL);
1283 update_shader_atom(ctx, &rctx->export_shader, NULL);
1284 rctx->shader_stages.geom_enable = false;
1285 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1286 }
1287
1288 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1289 if (unlikely(!rctx->vs_shader->current))
1290 return false;
1291
1292 if (unlikely(vs_dirty || rctx->vertex_shader.shader != rctx->vs_shader->current)) {
1293 update_shader_atom(ctx, &rctx->vertex_shader, rctx->vs_shader->current);
1294
1295 /* Update clip misc state. */
1296 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1297 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1298 rctx->clip_misc_state.clip_disable != rctx->vs_shader->current->shader.vs_position_window_space) {
1299 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
1300 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
1301 rctx->clip_misc_state.clip_disable = rctx->vs_shader->current->shader.vs_position_window_space;
1302 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1303 }
1304 rctx->b.streamout.enabled_stream_buffers_mask = rctx->vs_shader->current->enabled_stream_buffers_mask;
1305 }
1306 }
1307
1308
1309 if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader->current ||
1310 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1311 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1312
1313 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1314 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1315 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1316 }
1317
1318 if (rctx->b.chip_class <= R700) {
1319 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1320
1321 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1322 rctx->cb_misc_state.multiwrite = multiwrite;
1323 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1324 }
1325 }
1326
1327 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1328 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1329 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1330
1331 if (rctx->b.chip_class >= EVERGREEN)
1332 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1333 else
1334 r600_update_ps_state(ctx, rctx->ps_shader->current);
1335 }
1336
1337 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1338 update_shader_atom(ctx, &rctx->pixel_shader, rctx->ps_shader->current);
1339 }
1340
1341 if (rctx->b.chip_class >= EVERGREEN) {
1342 evergreen_update_db_shader_control(rctx);
1343 } else {
1344 r600_update_db_shader_control(rctx);
1345 }
1346
1347 /* on R600 we stuff masks + txq info into one constant buffer */
1348 /* on evergreen we only need a txq info one */
1349 if (rctx->ps_shader) {
1350 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1351 if (need_buf_const) {
1352 if (rctx->b.chip_class < EVERGREEN)
1353 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1354 else
1355 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1356 }
1357 }
1358
1359 if (rctx->vs_shader) {
1360 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1361 if (need_buf_const) {
1362 if (rctx->b.chip_class < EVERGREEN)
1363 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1364 else
1365 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1366 }
1367 }
1368
1369 if (rctx->gs_shader) {
1370 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1371 if (need_buf_const) {
1372 if (rctx->b.chip_class < EVERGREEN)
1373 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1374 else
1375 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1376 }
1377 }
1378
1379 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1380 if (!r600_adjust_gprs(rctx)) {
1381 /* discard rendering */
1382 return false;
1383 }
1384 }
1385
1386 blend_disable = (rctx->dual_src_blend &&
1387 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1388
1389 if (blend_disable != rctx->force_blend_disable) {
1390 rctx->force_blend_disable = blend_disable;
1391 r600_bind_blend_state_internal(rctx,
1392 rctx->blend_state.cso,
1393 blend_disable);
1394 }
1395
1396 return true;
1397 }
1398
1399 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1400 {
1401 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1402 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1403
1404 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1405 state->pa_cl_clip_cntl |
1406 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1407 S_028810_CLIP_DISABLE(state->clip_disable));
1408 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1409 state->pa_cl_vs_out_cntl |
1410 (state->clip_plane_enable & state->clip_dist_write));
1411 }
1412
1413 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1414 {
1415 struct r600_context *rctx = (struct r600_context *)ctx;
1416 struct pipe_draw_info info = *dinfo;
1417 struct pipe_index_buffer ib = {};
1418 unsigned i;
1419 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1420
1421 if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
1422 return;
1423 }
1424
1425 if (!rctx->vs_shader || !rctx->ps_shader) {
1426 assert(0);
1427 return;
1428 }
1429
1430 /* make sure that the gfx ring is only one active */
1431 if (rctx->b.rings.dma.cs && rctx->b.rings.dma.cs->cdw) {
1432 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1433 }
1434
1435 if (!r600_update_derived_state(rctx)) {
1436 /* useless to render because current rendering command
1437 * can't be achieved
1438 */
1439 return;
1440 }
1441
1442 if (info.indexed) {
1443 /* Initialize the index buffer struct. */
1444 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1445 ib.user_buffer = rctx->index_buffer.user_buffer;
1446 ib.index_size = rctx->index_buffer.index_size;
1447 ib.offset = rctx->index_buffer.offset;
1448 if (!info.indirect) {
1449 ib.offset += info.start * ib.index_size;
1450 }
1451
1452 /* Translate 8-bit indices to 16-bit. */
1453 if (unlikely(ib.index_size == 1)) {
1454 struct pipe_resource *out_buffer = NULL;
1455 unsigned out_offset;
1456 void *ptr;
1457 unsigned start, count;
1458
1459 if (likely(!info.indirect)) {
1460 start = 0;
1461 count = info.count;
1462 }
1463 else {
1464 /* Have to get start/count from indirect buffer, slow path ahead... */
1465 struct r600_resource *indirect_resource = (struct r600_resource *)info.indirect;
1466 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
1467 PIPE_TRANSFER_READ);
1468 if (data) {
1469 data += info.indirect_offset / sizeof(unsigned);
1470 start = data[2] * ib.index_size;
1471 count = data[0];
1472 }
1473 else {
1474 start = 0;
1475 count = 0;
1476 }
1477 }
1478
1479 u_upload_alloc(rctx->b.uploader, start, count * 2,
1480 &out_offset, &out_buffer, &ptr);
1481
1482 util_shorten_ubyte_elts_to_userptr(
1483 &rctx->b.b, &ib, 0, ib.offset + start, count, ptr);
1484
1485 pipe_resource_reference(&ib.buffer, NULL);
1486 ib.user_buffer = NULL;
1487 ib.buffer = out_buffer;
1488 ib.offset = out_offset;
1489 ib.index_size = 2;
1490 }
1491
1492 /* Upload the index buffer.
1493 * The upload is skipped for small index counts on little-endian machines
1494 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1495 * Indirect draws never use immediate indices.
1496 * Note: Instanced rendering in combination with immediate indices hangs. */
1497 if (ib.user_buffer && (R600_BIG_ENDIAN || info.indirect ||
1498 info.instance_count > 1 ||
1499 info.count*ib.index_size > 20)) {
1500 u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size,
1501 ib.user_buffer, &ib.offset, &ib.buffer);
1502 ib.user_buffer = NULL;
1503 }
1504 } else {
1505 info.index_bias = info.start;
1506 }
1507
1508 /* Set the index offset and primitive restart. */
1509 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1510 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1511 rctx->vgt_state.vgt_indx_offset != info.index_bias ||
1512 (rctx->vgt_state.last_draw_was_indirect && !info.indirect)) {
1513 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1514 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1515 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1516 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
1517 }
1518
1519 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1520 if (rctx->b.chip_class == R600) {
1521 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1522 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1523 }
1524
1525 /* Emit states. */
1526 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1527 r600_flush_emit(rctx);
1528
1529 i = r600_next_dirty_atom(rctx, 0);
1530 while (i < R600_NUM_ATOMS) {
1531 r600_emit_atom(rctx, rctx->atoms[i]);
1532 i = r600_next_dirty_atom(rctx, i + 1);
1533 }
1534
1535 if (rctx->b.chip_class == CAYMAN) {
1536 /* Copied from radeonsi. */
1537 unsigned primgroup_size = 128; /* recommended without a GS */
1538 bool ia_switch_on_eop = false;
1539 bool partial_vs_wave = false;
1540
1541 if (rctx->gs_shader)
1542 primgroup_size = 64; /* recommended with a GS */
1543
1544 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
1545 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
1546 ia_switch_on_eop = true;
1547 }
1548
1549 if (rctx->b.streamout.streamout_enabled ||
1550 rctx->b.streamout.prims_gen_query_enabled)
1551 partial_vs_wave = true;
1552
1553 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
1554 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
1555 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
1556 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
1557 }
1558
1559 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1560 * even though it should have no effect on those. */
1561 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
1562 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
1563 unsigned prim = info.mode;
1564
1565 if (rctx->gs_shader) {
1566 prim = rctx->gs_shader->gs_output_prim;
1567 }
1568 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
1569
1570 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
1571 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
1572 info.mode == R600_PRIM_RECTANGLE_LIST) {
1573 su_sc_mode_cntl &= C_028814_CULL_FRONT;
1574 }
1575 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
1576 }
1577
1578 /* Update start instance. */
1579 if (!info.indirect && rctx->last_start_instance != info.start_instance) {
1580 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1581 rctx->last_start_instance = info.start_instance;
1582 }
1583
1584 /* Update the primitive type. */
1585 if (rctx->last_primitive_type != info.mode) {
1586 unsigned ls_mask = 0;
1587
1588 if (info.mode == PIPE_PRIM_LINES)
1589 ls_mask = 1;
1590 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1591 info.mode == PIPE_PRIM_LINE_LOOP)
1592 ls_mask = 2;
1593
1594 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1595 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1596 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1597 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1598 r600_conv_pipe_prim(info.mode));
1599
1600 rctx->last_primitive_type = info.mode;
1601 }
1602
1603 /* Draw packets. */
1604 if (!info.indirect) {
1605 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->b.predicate_drawing);
1606 cs->buf[cs->cdw++] = info.instance_count;
1607 }
1608
1609 if (unlikely(info.indirect)) {
1610 uint64_t va = r600_resource(info.indirect)->gpu_address;
1611 assert(rctx->b.chip_class >= EVERGREEN);
1612
1613 // Invalidate so non-indirect draw calls reset this state
1614 rctx->vgt_state.last_draw_was_indirect = true;
1615 rctx->last_start_instance = -1;
1616
1617 cs->buf[cs->cdw++] = PKT3(EG_PKT3_SET_BASE, 2, rctx->b.predicate_drawing);
1618 cs->buf[cs->cdw++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE;
1619 cs->buf[cs->cdw++] = va;
1620 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1621
1622 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1623 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
1624 (struct r600_resource*)info.indirect,
1625 RADEON_USAGE_READ, RADEON_PRIO_MIN);
1626 }
1627
1628 if (info.indexed) {
1629 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->b.predicate_drawing);
1630 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1631 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1632 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1633
1634 if (ib.user_buffer) {
1635 unsigned size_bytes = info.count*ib.index_size;
1636 unsigned size_dw = align(size_bytes, 4) / 4;
1637 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->b.predicate_drawing);
1638 cs->buf[cs->cdw++] = info.count;
1639 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1640 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1641 cs->cdw += size_dw;
1642 } else {
1643 uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
1644
1645 if (likely(!info.indirect)) {
1646 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
1647 cs->buf[cs->cdw++] = va;
1648 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1649 cs->buf[cs->cdw++] = info.count;
1650 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1651 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1652 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
1653 (struct r600_resource*)ib.buffer,
1654 RADEON_USAGE_READ, RADEON_PRIO_MIN);
1655 }
1656 else {
1657 uint32_t max_size = (ib.buffer->width0 - ib.offset) / ib.index_size;
1658
1659 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BASE, 1, rctx->b.predicate_drawing);
1660 cs->buf[cs->cdw++] = va;
1661 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1662
1663 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1664 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
1665 (struct r600_resource*)ib.buffer,
1666 RADEON_USAGE_READ, RADEON_PRIO_MIN);
1667
1668 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, rctx->b.predicate_drawing);
1669 cs->buf[cs->cdw++] = max_size;
1670
1671 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, rctx->b.predicate_drawing);
1672 cs->buf[cs->cdw++] = info.indirect_offset;
1673 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1674 }
1675 }
1676 } else {
1677 if (unlikely(info.count_from_stream_output)) {
1678 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1679 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
1680
1681 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1682
1683 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1684 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1685 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1686 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1687 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1688 cs->buf[cs->cdw++] = 0; /* unused */
1689
1690 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1691 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx,
1692 t->buf_filled_size, RADEON_USAGE_READ,
1693 RADEON_PRIO_MIN);
1694 }
1695
1696 if (likely(!info.indirect)) {
1697 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
1698 cs->buf[cs->cdw++] = info.count;
1699 }
1700 else {
1701 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDIRECT, 1, rctx->b.predicate_drawing);
1702 cs->buf[cs->cdw++] = info.indirect_offset;
1703 }
1704 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1705 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1706 }
1707
1708 if (rctx->screen->b.trace_bo) {
1709 r600_trace_emit(rctx);
1710 }
1711
1712 /* Set the depth buffer as dirty. */
1713 if (rctx->framebuffer.state.zsbuf) {
1714 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1715 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1716
1717 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1718 }
1719 if (rctx->framebuffer.compressed_cb_mask) {
1720 struct pipe_surface *surf;
1721 struct r600_texture *rtex;
1722 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1723
1724 do {
1725 unsigned i = u_bit_scan(&mask);
1726 surf = rctx->framebuffer.state.cbufs[i];
1727 rtex = (struct r600_texture*)surf->texture;
1728
1729 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1730
1731 } while (mask);
1732 }
1733
1734 pipe_resource_reference(&ib.buffer, NULL);
1735 rctx->b.num_draw_calls++;
1736 }
1737
1738 uint32_t r600_translate_stencil_op(int s_op)
1739 {
1740 switch (s_op) {
1741 case PIPE_STENCIL_OP_KEEP:
1742 return V_028800_STENCIL_KEEP;
1743 case PIPE_STENCIL_OP_ZERO:
1744 return V_028800_STENCIL_ZERO;
1745 case PIPE_STENCIL_OP_REPLACE:
1746 return V_028800_STENCIL_REPLACE;
1747 case PIPE_STENCIL_OP_INCR:
1748 return V_028800_STENCIL_INCR;
1749 case PIPE_STENCIL_OP_DECR:
1750 return V_028800_STENCIL_DECR;
1751 case PIPE_STENCIL_OP_INCR_WRAP:
1752 return V_028800_STENCIL_INCR_WRAP;
1753 case PIPE_STENCIL_OP_DECR_WRAP:
1754 return V_028800_STENCIL_DECR_WRAP;
1755 case PIPE_STENCIL_OP_INVERT:
1756 return V_028800_STENCIL_INVERT;
1757 default:
1758 R600_ERR("Unknown stencil op %d", s_op);
1759 assert(0);
1760 break;
1761 }
1762 return 0;
1763 }
1764
1765 uint32_t r600_translate_fill(uint32_t func)
1766 {
1767 switch(func) {
1768 case PIPE_POLYGON_MODE_FILL:
1769 return 2;
1770 case PIPE_POLYGON_MODE_LINE:
1771 return 1;
1772 case PIPE_POLYGON_MODE_POINT:
1773 return 0;
1774 default:
1775 assert(0);
1776 return 0;
1777 }
1778 }
1779
1780 unsigned r600_tex_wrap(unsigned wrap)
1781 {
1782 switch (wrap) {
1783 default:
1784 case PIPE_TEX_WRAP_REPEAT:
1785 return V_03C000_SQ_TEX_WRAP;
1786 case PIPE_TEX_WRAP_CLAMP:
1787 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1788 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1789 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1790 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1791 return V_03C000_SQ_TEX_CLAMP_BORDER;
1792 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1793 return V_03C000_SQ_TEX_MIRROR;
1794 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1795 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1796 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1797 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1798 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1799 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1800 }
1801 }
1802
1803 unsigned r600_tex_filter(unsigned filter)
1804 {
1805 switch (filter) {
1806 default:
1807 case PIPE_TEX_FILTER_NEAREST:
1808 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1809 case PIPE_TEX_FILTER_LINEAR:
1810 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1811 }
1812 }
1813
1814 unsigned r600_tex_mipfilter(unsigned filter)
1815 {
1816 switch (filter) {
1817 case PIPE_TEX_MIPFILTER_NEAREST:
1818 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1819 case PIPE_TEX_MIPFILTER_LINEAR:
1820 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1821 default:
1822 case PIPE_TEX_MIPFILTER_NONE:
1823 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1824 }
1825 }
1826
1827 unsigned r600_tex_compare(unsigned compare)
1828 {
1829 switch (compare) {
1830 default:
1831 case PIPE_FUNC_NEVER:
1832 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1833 case PIPE_FUNC_LESS:
1834 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1835 case PIPE_FUNC_EQUAL:
1836 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1837 case PIPE_FUNC_LEQUAL:
1838 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1839 case PIPE_FUNC_GREATER:
1840 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1841 case PIPE_FUNC_NOTEQUAL:
1842 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1843 case PIPE_FUNC_GEQUAL:
1844 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1845 case PIPE_FUNC_ALWAYS:
1846 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1847 }
1848 }
1849
1850 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1851 {
1852 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1853 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1854 (linear_filter &&
1855 (wrap == PIPE_TEX_WRAP_CLAMP ||
1856 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1857 }
1858
1859 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1860 {
1861 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1862 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1863
1864 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1865 state->border_color.ui[2] || state->border_color.ui[3]) &&
1866 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1867 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1868 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1869 }
1870
1871 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1872 {
1873
1874 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1875 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
1876
1877 if (!shader)
1878 return;
1879
1880 r600_emit_command_buffer(cs, &shader->command_buffer);
1881 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1882 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, shader->bo,
1883 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1884 }
1885
1886 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1887 const unsigned char *swizzle_view,
1888 boolean vtx)
1889 {
1890 unsigned i;
1891 unsigned char swizzle[4];
1892 unsigned result = 0;
1893 const uint32_t tex_swizzle_shift[4] = {
1894 16, 19, 22, 25,
1895 };
1896 const uint32_t vtx_swizzle_shift[4] = {
1897 3, 6, 9, 12,
1898 };
1899 const uint32_t swizzle_bit[4] = {
1900 0, 1, 2, 3,
1901 };
1902 const uint32_t *swizzle_shift = tex_swizzle_shift;
1903
1904 if (vtx)
1905 swizzle_shift = vtx_swizzle_shift;
1906
1907 if (swizzle_view) {
1908 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1909 } else {
1910 memcpy(swizzle, swizzle_format, 4);
1911 }
1912
1913 /* Get swizzle. */
1914 for (i = 0; i < 4; i++) {
1915 switch (swizzle[i]) {
1916 case UTIL_FORMAT_SWIZZLE_Y:
1917 result |= swizzle_bit[1] << swizzle_shift[i];
1918 break;
1919 case UTIL_FORMAT_SWIZZLE_Z:
1920 result |= swizzle_bit[2] << swizzle_shift[i];
1921 break;
1922 case UTIL_FORMAT_SWIZZLE_W:
1923 result |= swizzle_bit[3] << swizzle_shift[i];
1924 break;
1925 case UTIL_FORMAT_SWIZZLE_0:
1926 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1927 break;
1928 case UTIL_FORMAT_SWIZZLE_1:
1929 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1930 break;
1931 default: /* UTIL_FORMAT_SWIZZLE_X */
1932 result |= swizzle_bit[0] << swizzle_shift[i];
1933 }
1934 }
1935 return result;
1936 }
1937
1938 /* texture format translate */
1939 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1940 enum pipe_format format,
1941 const unsigned char *swizzle_view,
1942 uint32_t *word4_p, uint32_t *yuv_format_p)
1943 {
1944 struct r600_screen *rscreen = (struct r600_screen *)screen;
1945 uint32_t result = 0, word4 = 0, yuv_format = 0;
1946 const struct util_format_description *desc;
1947 boolean uniform = TRUE;
1948 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1949 bool is_srgb_valid = FALSE;
1950 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1951 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1952
1953 int i;
1954 const uint32_t sign_bit[4] = {
1955 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1956 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1957 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1958 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1959 };
1960 desc = util_format_description(format);
1961
1962 /* Depth and stencil swizzling is handled separately. */
1963 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1964 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1965 }
1966
1967 /* Colorspace (return non-RGB formats directly). */
1968 switch (desc->colorspace) {
1969 /* Depth stencil formats */
1970 case UTIL_FORMAT_COLORSPACE_ZS:
1971 switch (format) {
1972 /* Depth sampler formats. */
1973 case PIPE_FORMAT_Z16_UNORM:
1974 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1975 result = FMT_16;
1976 goto out_word4;
1977 case PIPE_FORMAT_Z24X8_UNORM:
1978 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1979 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1980 result = FMT_8_24;
1981 goto out_word4;
1982 case PIPE_FORMAT_X8Z24_UNORM:
1983 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1984 if (rscreen->b.chip_class < EVERGREEN)
1985 goto out_unknown;
1986 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1987 result = FMT_24_8;
1988 goto out_word4;
1989 case PIPE_FORMAT_Z32_FLOAT:
1990 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1991 result = FMT_32_FLOAT;
1992 goto out_word4;
1993 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1994 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1995 result = FMT_X24_8_32_FLOAT;
1996 goto out_word4;
1997 /* Stencil sampler formats. */
1998 case PIPE_FORMAT_S8_UINT:
1999 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2000 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2001 result = FMT_8;
2002 goto out_word4;
2003 case PIPE_FORMAT_X24S8_UINT:
2004 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2005 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2006 result = FMT_8_24;
2007 goto out_word4;
2008 case PIPE_FORMAT_S8X24_UINT:
2009 if (rscreen->b.chip_class < EVERGREEN)
2010 goto out_unknown;
2011 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2012 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2013 result = FMT_24_8;
2014 goto out_word4;
2015 case PIPE_FORMAT_X32_S8X24_UINT:
2016 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2017 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2018 result = FMT_X24_8_32_FLOAT;
2019 goto out_word4;
2020 default:
2021 goto out_unknown;
2022 }
2023
2024 case UTIL_FORMAT_COLORSPACE_YUV:
2025 yuv_format |= (1 << 30);
2026 switch (format) {
2027 case PIPE_FORMAT_UYVY:
2028 case PIPE_FORMAT_YUYV:
2029 default:
2030 break;
2031 }
2032 goto out_unknown; /* XXX */
2033
2034 case UTIL_FORMAT_COLORSPACE_SRGB:
2035 word4 |= S_038010_FORCE_DEGAMMA(1);
2036 break;
2037
2038 default:
2039 break;
2040 }
2041
2042 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2043 if (!enable_s3tc)
2044 goto out_unknown;
2045
2046 switch (format) {
2047 case PIPE_FORMAT_RGTC1_SNORM:
2048 case PIPE_FORMAT_LATC1_SNORM:
2049 word4 |= sign_bit[0];
2050 case PIPE_FORMAT_RGTC1_UNORM:
2051 case PIPE_FORMAT_LATC1_UNORM:
2052 result = FMT_BC4;
2053 goto out_word4;
2054 case PIPE_FORMAT_RGTC2_SNORM:
2055 case PIPE_FORMAT_LATC2_SNORM:
2056 word4 |= sign_bit[0] | sign_bit[1];
2057 case PIPE_FORMAT_RGTC2_UNORM:
2058 case PIPE_FORMAT_LATC2_UNORM:
2059 result = FMT_BC5;
2060 goto out_word4;
2061 default:
2062 goto out_unknown;
2063 }
2064 }
2065
2066 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2067
2068 if (!enable_s3tc)
2069 goto out_unknown;
2070
2071 if (!util_format_s3tc_enabled) {
2072 goto out_unknown;
2073 }
2074
2075 switch (format) {
2076 case PIPE_FORMAT_DXT1_RGB:
2077 case PIPE_FORMAT_DXT1_RGBA:
2078 case PIPE_FORMAT_DXT1_SRGB:
2079 case PIPE_FORMAT_DXT1_SRGBA:
2080 result = FMT_BC1;
2081 is_srgb_valid = TRUE;
2082 goto out_word4;
2083 case PIPE_FORMAT_DXT3_RGBA:
2084 case PIPE_FORMAT_DXT3_SRGBA:
2085 result = FMT_BC2;
2086 is_srgb_valid = TRUE;
2087 goto out_word4;
2088 case PIPE_FORMAT_DXT5_RGBA:
2089 case PIPE_FORMAT_DXT5_SRGBA:
2090 result = FMT_BC3;
2091 is_srgb_valid = TRUE;
2092 goto out_word4;
2093 default:
2094 goto out_unknown;
2095 }
2096 }
2097
2098 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2099 if (!enable_s3tc)
2100 goto out_unknown;
2101
2102 if (rscreen->b.chip_class < EVERGREEN)
2103 goto out_unknown;
2104
2105 switch (format) {
2106 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2107 case PIPE_FORMAT_BPTC_SRGBA:
2108 result = FMT_BC7;
2109 is_srgb_valid = TRUE;
2110 goto out_word4;
2111 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2112 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2113 /* fall through */
2114 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2115 result = FMT_BC6;
2116 goto out_word4;
2117 default:
2118 goto out_unknown;
2119 }
2120 }
2121
2122 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2123 switch (format) {
2124 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2125 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2126 result = FMT_GB_GR;
2127 goto out_word4;
2128 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2129 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2130 result = FMT_BG_RG;
2131 goto out_word4;
2132 default:
2133 goto out_unknown;
2134 }
2135 }
2136
2137 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2138 result = FMT_5_9_9_9_SHAREDEXP;
2139 goto out_word4;
2140 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2141 result = FMT_10_11_11_FLOAT;
2142 goto out_word4;
2143 }
2144
2145
2146 for (i = 0; i < desc->nr_channels; i++) {
2147 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2148 word4 |= sign_bit[i];
2149 }
2150 }
2151
2152 /* R8G8Bx_SNORM - XXX CxV8U8 */
2153
2154 /* See whether the components are of the same size. */
2155 for (i = 1; i < desc->nr_channels; i++) {
2156 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2157 }
2158
2159 /* Non-uniform formats. */
2160 if (!uniform) {
2161 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2162 desc->channel[0].pure_integer)
2163 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2164 switch(desc->nr_channels) {
2165 case 3:
2166 if (desc->channel[0].size == 5 &&
2167 desc->channel[1].size == 6 &&
2168 desc->channel[2].size == 5) {
2169 result = FMT_5_6_5;
2170 goto out_word4;
2171 }
2172 goto out_unknown;
2173 case 4:
2174 if (desc->channel[0].size == 5 &&
2175 desc->channel[1].size == 5 &&
2176 desc->channel[2].size == 5 &&
2177 desc->channel[3].size == 1) {
2178 result = FMT_1_5_5_5;
2179 goto out_word4;
2180 }
2181 if (desc->channel[0].size == 10 &&
2182 desc->channel[1].size == 10 &&
2183 desc->channel[2].size == 10 &&
2184 desc->channel[3].size == 2) {
2185 result = FMT_2_10_10_10;
2186 goto out_word4;
2187 }
2188 goto out_unknown;
2189 }
2190 goto out_unknown;
2191 }
2192
2193 /* Find the first non-VOID channel. */
2194 for (i = 0; i < 4; i++) {
2195 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2196 break;
2197 }
2198 }
2199
2200 if (i == 4)
2201 goto out_unknown;
2202
2203 /* uniform formats */
2204 switch (desc->channel[i].type) {
2205 case UTIL_FORMAT_TYPE_UNSIGNED:
2206 case UTIL_FORMAT_TYPE_SIGNED:
2207 #if 0
2208 if (!desc->channel[i].normalized &&
2209 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2210 goto out_unknown;
2211 }
2212 #endif
2213 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2214 desc->channel[i].pure_integer)
2215 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2216
2217 switch (desc->channel[i].size) {
2218 case 4:
2219 switch (desc->nr_channels) {
2220 case 2:
2221 result = FMT_4_4;
2222 goto out_word4;
2223 case 4:
2224 result = FMT_4_4_4_4;
2225 goto out_word4;
2226 }
2227 goto out_unknown;
2228 case 8:
2229 switch (desc->nr_channels) {
2230 case 1:
2231 result = FMT_8;
2232 goto out_word4;
2233 case 2:
2234 result = FMT_8_8;
2235 goto out_word4;
2236 case 4:
2237 result = FMT_8_8_8_8;
2238 is_srgb_valid = TRUE;
2239 goto out_word4;
2240 }
2241 goto out_unknown;
2242 case 16:
2243 switch (desc->nr_channels) {
2244 case 1:
2245 result = FMT_16;
2246 goto out_word4;
2247 case 2:
2248 result = FMT_16_16;
2249 goto out_word4;
2250 case 4:
2251 result = FMT_16_16_16_16;
2252 goto out_word4;
2253 }
2254 goto out_unknown;
2255 case 32:
2256 switch (desc->nr_channels) {
2257 case 1:
2258 result = FMT_32;
2259 goto out_word4;
2260 case 2:
2261 result = FMT_32_32;
2262 goto out_word4;
2263 case 4:
2264 result = FMT_32_32_32_32;
2265 goto out_word4;
2266 }
2267 }
2268 goto out_unknown;
2269
2270 case UTIL_FORMAT_TYPE_FLOAT:
2271 switch (desc->channel[i].size) {
2272 case 16:
2273 switch (desc->nr_channels) {
2274 case 1:
2275 result = FMT_16_FLOAT;
2276 goto out_word4;
2277 case 2:
2278 result = FMT_16_16_FLOAT;
2279 goto out_word4;
2280 case 4:
2281 result = FMT_16_16_16_16_FLOAT;
2282 goto out_word4;
2283 }
2284 goto out_unknown;
2285 case 32:
2286 switch (desc->nr_channels) {
2287 case 1:
2288 result = FMT_32_FLOAT;
2289 goto out_word4;
2290 case 2:
2291 result = FMT_32_32_FLOAT;
2292 goto out_word4;
2293 case 4:
2294 result = FMT_32_32_32_32_FLOAT;
2295 goto out_word4;
2296 }
2297 }
2298 goto out_unknown;
2299 }
2300
2301 out_word4:
2302
2303 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2304 return ~0;
2305 if (word4_p)
2306 *word4_p = word4;
2307 if (yuv_format_p)
2308 *yuv_format_p = yuv_format;
2309 return result;
2310 out_unknown:
2311 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2312 return ~0;
2313 }
2314
2315 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format)
2316 {
2317 const struct util_format_description *desc = util_format_description(format);
2318 int channel = util_format_get_first_non_void_channel(format);
2319 bool is_float;
2320
2321 #define HAS_SIZE(x,y,z,w) \
2322 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2323 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2324
2325 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2326 return V_0280A0_COLOR_10_11_11_FLOAT;
2327
2328 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2329 channel == -1)
2330 return ~0U;
2331
2332 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2333
2334 switch (desc->nr_channels) {
2335 case 1:
2336 switch (desc->channel[0].size) {
2337 case 8:
2338 return V_0280A0_COLOR_8;
2339 case 16:
2340 if (is_float)
2341 return V_0280A0_COLOR_16_FLOAT;
2342 else
2343 return V_0280A0_COLOR_16;
2344 case 32:
2345 if (is_float)
2346 return V_0280A0_COLOR_32_FLOAT;
2347 else
2348 return V_0280A0_COLOR_32;
2349 }
2350 break;
2351 case 2:
2352 if (desc->channel[0].size == desc->channel[1].size) {
2353 switch (desc->channel[0].size) {
2354 case 4:
2355 if (chip <= R700)
2356 return V_0280A0_COLOR_4_4;
2357 else
2358 return ~0U; /* removed on Evergreen */
2359 case 8:
2360 return V_0280A0_COLOR_8_8;
2361 case 16:
2362 if (is_float)
2363 return V_0280A0_COLOR_16_16_FLOAT;
2364 else
2365 return V_0280A0_COLOR_16_16;
2366 case 32:
2367 if (is_float)
2368 return V_0280A0_COLOR_32_32_FLOAT;
2369 else
2370 return V_0280A0_COLOR_32_32;
2371 }
2372 } else if (HAS_SIZE(8,24,0,0)) {
2373 return V_0280A0_COLOR_24_8;
2374 } else if (HAS_SIZE(24,8,0,0)) {
2375 return V_0280A0_COLOR_8_24;
2376 }
2377 break;
2378 case 3:
2379 if (HAS_SIZE(5,6,5,0)) {
2380 return V_0280A0_COLOR_5_6_5;
2381 } else if (HAS_SIZE(32,8,24,0)) {
2382 return V_0280A0_COLOR_X24_8_32_FLOAT;
2383 }
2384 break;
2385 case 4:
2386 if (desc->channel[0].size == desc->channel[1].size &&
2387 desc->channel[0].size == desc->channel[2].size &&
2388 desc->channel[0].size == desc->channel[3].size) {
2389 switch (desc->channel[0].size) {
2390 case 4:
2391 return V_0280A0_COLOR_4_4_4_4;
2392 case 8:
2393 return V_0280A0_COLOR_8_8_8_8;
2394 case 16:
2395 if (is_float)
2396 return V_0280A0_COLOR_16_16_16_16_FLOAT;
2397 else
2398 return V_0280A0_COLOR_16_16_16_16;
2399 case 32:
2400 if (is_float)
2401 return V_0280A0_COLOR_32_32_32_32_FLOAT;
2402 else
2403 return V_0280A0_COLOR_32_32_32_32;
2404 }
2405 } else if (HAS_SIZE(5,5,5,1)) {
2406 return V_0280A0_COLOR_1_5_5_5;
2407 } else if (HAS_SIZE(10,10,10,2)) {
2408 return V_0280A0_COLOR_2_10_10_10;
2409 }
2410 break;
2411 }
2412 return ~0U;
2413 }
2414
2415 uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
2416 {
2417 if (R600_BIG_ENDIAN) {
2418 switch(colorformat) {
2419 /* 8-bit buffers. */
2420 case V_0280A0_COLOR_4_4:
2421 case V_0280A0_COLOR_8:
2422 return ENDIAN_NONE;
2423
2424 /* 16-bit buffers. */
2425 case V_0280A0_COLOR_5_6_5:
2426 case V_0280A0_COLOR_1_5_5_5:
2427 case V_0280A0_COLOR_4_4_4_4:
2428 case V_0280A0_COLOR_16:
2429 case V_0280A0_COLOR_8_8:
2430 return ENDIAN_8IN16;
2431
2432 /* 32-bit buffers. */
2433 case V_0280A0_COLOR_8_8_8_8:
2434 case V_0280A0_COLOR_2_10_10_10:
2435 case V_0280A0_COLOR_8_24:
2436 case V_0280A0_COLOR_24_8:
2437 case V_0280A0_COLOR_32_FLOAT:
2438 case V_0280A0_COLOR_16_16_FLOAT:
2439 case V_0280A0_COLOR_16_16:
2440 return ENDIAN_8IN32;
2441
2442 /* 64-bit buffers. */
2443 case V_0280A0_COLOR_16_16_16_16:
2444 case V_0280A0_COLOR_16_16_16_16_FLOAT:
2445 return ENDIAN_8IN16;
2446
2447 case V_0280A0_COLOR_32_32_FLOAT:
2448 case V_0280A0_COLOR_32_32:
2449 case V_0280A0_COLOR_X24_8_32_FLOAT:
2450 return ENDIAN_8IN32;
2451
2452 /* 128-bit buffers. */
2453 case V_0280A0_COLOR_32_32_32_32_FLOAT:
2454 case V_0280A0_COLOR_32_32_32_32:
2455 return ENDIAN_8IN32;
2456 default:
2457 return ENDIAN_NONE; /* Unsupported. */
2458 }
2459 } else {
2460 return ENDIAN_NONE;
2461 }
2462 }
2463
2464 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2465 {
2466 struct r600_context *rctx = (struct r600_context*)ctx;
2467 struct r600_resource *rbuffer = r600_resource(buf);
2468 unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
2469 struct r600_pipe_sampler_view *view;
2470
2471 /* Reallocate the buffer in the same pipe_resource. */
2472 r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0,
2473 alignment, TRUE);
2474
2475 /* We changed the buffer, now we need to bind it where the old one was bound. */
2476 /* Vertex buffers. */
2477 mask = rctx->vertex_buffer_state.enabled_mask;
2478 while (mask) {
2479 i = u_bit_scan(&mask);
2480 if (rctx->vertex_buffer_state.vb[i].buffer == &rbuffer->b.b) {
2481 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2482 r600_vertex_buffers_dirty(rctx);
2483 }
2484 }
2485 /* Streamout buffers. */
2486 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2487 if (rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2488 if (rctx->b.streamout.begin_emitted) {
2489 r600_emit_streamout_end(&rctx->b);
2490 }
2491 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2492 r600_streamout_buffers_dirty(&rctx->b);
2493 }
2494 }
2495
2496 /* Constant buffers. */
2497 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2498 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2499 bool found = false;
2500 uint32_t mask = state->enabled_mask;
2501
2502 while (mask) {
2503 unsigned i = u_bit_scan(&mask);
2504 if (state->cb[i].buffer == &rbuffer->b.b) {
2505 found = true;
2506 state->dirty_mask |= 1 << i;
2507 }
2508 }
2509 if (found) {
2510 r600_constant_buffers_dirty(rctx, state);
2511 }
2512 }
2513
2514 /* Texture buffer objects - update the virtual addresses in descriptors. */
2515 LIST_FOR_EACH_ENTRY(view, &rctx->b.texture_buffers, list) {
2516 if (view->base.texture == &rbuffer->b.b) {
2517 unsigned stride = util_format_get_blocksize(view->base.format);
2518 uint64_t offset = (uint64_t)view->base.u.buf.first_element * stride;
2519 uint64_t va = rbuffer->gpu_address + offset;
2520
2521 view->tex_resource_words[0] = va;
2522 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
2523 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
2524 }
2525 }
2526 /* Texture buffer objects - make bindings dirty if needed. */
2527 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2528 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
2529 bool found = false;
2530 uint32_t mask = state->enabled_mask;
2531
2532 while (mask) {
2533 unsigned i = u_bit_scan(&mask);
2534 if (state->views[i]->base.texture == &rbuffer->b.b) {
2535 found = true;
2536 state->dirty_mask |= 1 << i;
2537 }
2538 }
2539 if (found) {
2540 r600_sampler_views_dirty(rctx, state);
2541 }
2542 }
2543 }
2544
2545 static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2546 {
2547 struct r600_context *rctx = (struct r600_context*)ctx;
2548
2549 if (rctx->db_misc_state.occlusion_query_enabled != enable) {
2550 rctx->db_misc_state.occlusion_query_enabled = enable;
2551 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2552 }
2553 }
2554
2555 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2556 bool include_draw_vbo)
2557 {
2558 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
2559 }
2560
2561 /* keep this at the end of this file, please */
2562 void r600_init_common_state_functions(struct r600_context *rctx)
2563 {
2564 rctx->b.b.create_fs_state = r600_create_ps_state;
2565 rctx->b.b.create_vs_state = r600_create_vs_state;
2566 rctx->b.b.create_gs_state = r600_create_gs_state;
2567 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2568 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2569 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2570 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2571 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2572 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2573 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2574 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2575 rctx->b.b.bind_gs_state = r600_bind_gs_state;
2576 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2577 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2578 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2579 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2580 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2581 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2582 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2583 rctx->b.b.delete_gs_state = r600_delete_gs_state;
2584 rctx->b.b.set_blend_color = r600_set_blend_color;
2585 rctx->b.b.set_clip_state = r600_set_clip_state;
2586 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2587 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2588 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2589 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2590 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2591 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2592 rctx->b.b.set_sampler_views = r600_set_sampler_views;
2593 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2594 rctx->b.b.texture_barrier = r600_texture_barrier;
2595 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2596 rctx->b.b.draw_vbo = r600_draw_vbo;
2597 rctx->b.invalidate_buffer = r600_invalidate_buffer;
2598 rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
2599 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
2600 }
2601
2602 void r600_trace_emit(struct r600_context *rctx)
2603 {
2604 struct r600_screen *rscreen = rctx->screen;
2605 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2606 uint64_t va;
2607 uint32_t reloc;
2608
2609 va = rscreen->b.trace_bo->gpu_address;
2610 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
2611 RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
2612 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2613 radeon_emit(cs, va & 0xFFFFFFFFUL);
2614 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2615 radeon_emit(cs, cs->cdw);
2616 radeon_emit(cs, rscreen->b.cs_count);
2617 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2618 radeon_emit(cs, reloc);
2619 }