r600g: fix glean clipflat test.
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include <util/u_memory.h>
28 #include <util/u_format.h>
29 #include <pipebuffer/pb_buffer.h>
30 #include "pipe/p_shader_tokens.h"
31 #include "r600_pipe.h"
32 #include "r600d.h"
33
34 /* common state between evergreen and r600 */
35 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
36 {
37 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
38 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
39 struct r600_pipe_state *rstate;
40
41 if (state == NULL)
42 return;
43 rstate = &blend->rstate;
44 rctx->states[rstate->id] = rstate;
45 rctx->cb_target_mask = blend->cb_target_mask;
46 r600_context_pipe_state_set(&rctx->ctx, rstate);
47 }
48
49 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
50 {
51 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
52 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
53
54 if (state == NULL)
55 return;
56
57 rctx->flatshade = rs->flatshade;
58 rctx->sprite_coord_enable = rs->sprite_coord_enable;
59 rctx->rasterizer = rs;
60
61 rctx->states[rs->rstate.id] = &rs->rstate;
62 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
63
64 if (rctx->family >= CHIP_CEDAR) {
65 evergreen_polygon_offset_update(rctx);
66 } else {
67 r600_polygon_offset_update(rctx);
68 }
69 }
70
71 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
72 {
73 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
74 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
75
76 if (rctx->rasterizer == rs) {
77 rctx->rasterizer = NULL;
78 }
79 if (rctx->states[rs->rstate.id] == &rs->rstate) {
80 rctx->states[rs->rstate.id] = NULL;
81 }
82 free(rs);
83 }
84
85 void r600_sampler_view_destroy(struct pipe_context *ctx,
86 struct pipe_sampler_view *state)
87 {
88 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
89
90 pipe_resource_reference(&state->texture, NULL);
91 FREE(resource);
92 }
93
94 void r600_bind_state(struct pipe_context *ctx, void *state)
95 {
96 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
97 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
98
99 if (state == NULL)
100 return;
101 rctx->states[rstate->id] = rstate;
102 r600_context_pipe_state_set(&rctx->ctx, rstate);
103 }
104
105 void r600_delete_state(struct pipe_context *ctx, void *state)
106 {
107 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
108 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
109
110 if (rctx->states[rstate->id] == rstate) {
111 rctx->states[rstate->id] = NULL;
112 }
113 for (int i = 0; i < rstate->nregs; i++) {
114 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
115 }
116 free(rstate);
117 }
118
119 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
120 {
121 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
122 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
123
124 rctx->vertex_elements = v;
125 if (v) {
126 u_vbuf_mgr_bind_vertex_elements(rctx->vbuf_mgr, state,
127 v->vmgr_elements);
128
129 rctx->states[v->rstate.id] = &v->rstate;
130 r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
131 }
132 }
133
134 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
135 {
136 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
137 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
138
139 if (rctx->states[v->rstate.id] == &v->rstate) {
140 rctx->states[v->rstate.id] = NULL;
141 }
142 if (rctx->vertex_elements == state)
143 rctx->vertex_elements = NULL;
144
145 r600_bo_reference(rctx->radeon, &v->fetch_shader, NULL);
146 u_vbuf_mgr_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
147 FREE(state);
148 }
149
150
151 void r600_set_index_buffer(struct pipe_context *ctx,
152 const struct pipe_index_buffer *ib)
153 {
154 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
155
156 if (ib) {
157 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
158 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
159 } else {
160 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
161 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
162 }
163
164 /* TODO make this more like a state */
165 }
166
167 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
168 const struct pipe_vertex_buffer *buffers)
169 {
170 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
171 int i;
172
173 /* Zero states. */
174 for (i = 0; i < count; i++) {
175 if (!buffers[i].buffer) {
176 if (rctx->family >= CHIP_CEDAR) {
177 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
178 } else {
179 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
180 }
181 }
182 }
183 for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
184 if (rctx->family >= CHIP_CEDAR) {
185 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
186 } else {
187 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
188 }
189 }
190
191 u_vbuf_mgr_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
192 }
193
194 void *r600_create_vertex_elements(struct pipe_context *ctx,
195 unsigned count,
196 const struct pipe_vertex_element *elements)
197 {
198 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
199 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
200
201 assert(count < 32);
202 if (!v)
203 return NULL;
204
205 v->count = count;
206 v->vmgr_elements =
207 u_vbuf_mgr_create_vertex_elements(rctx->vbuf_mgr, count,
208 elements, v->elements);
209
210 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
211 FREE(v);
212 return NULL;
213 }
214
215 return v;
216 }
217
218 void *r600_create_shader_state(struct pipe_context *ctx,
219 const struct pipe_shader_state *state)
220 {
221 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
222 int r;
223
224 r = r600_pipe_shader_create(ctx, shader, state->tokens);
225 if (r) {
226 return NULL;
227 }
228 return shader;
229 }
230
231 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
232 {
233 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
234
235 /* TODO delete old shader */
236 rctx->ps_shader = (struct r600_pipe_shader *)state;
237 if (state) {
238 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
239 }
240 }
241
242 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
243 {
244 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
245
246 /* TODO delete old shader */
247 rctx->vs_shader = (struct r600_pipe_shader *)state;
248 if (state) {
249 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
250 }
251 }
252
253 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
254 {
255 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
256 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
257
258 if (rctx->ps_shader == shader) {
259 rctx->ps_shader = NULL;
260 }
261
262 r600_pipe_shader_destroy(ctx, shader);
263 free(shader);
264 }
265
266 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
267 {
268 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
269 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
270
271 if (rctx->vs_shader == shader) {
272 rctx->vs_shader = NULL;
273 }
274
275 r600_pipe_shader_destroy(ctx, shader);
276 free(shader);
277 }
278
279 /* FIXME optimize away spi update when it's not needed */
280 static void r600_spi_update(struct r600_pipe_context *rctx, unsigned prim)
281 {
282 struct r600_pipe_shader *shader = rctx->ps_shader;
283 struct r600_pipe_state rstate;
284 struct r600_shader *rshader = &shader->shader;
285 unsigned i, tmp;
286
287 rstate.nregs = 0;
288 for (i = 0; i < rshader->ninput; i++) {
289 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
290
291 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
292 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
293 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
294 tmp |= S_028644_FLAT_SHADE(rctx->flatshade);
295 }
296
297 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
298 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
299 tmp |= S_028644_PT_SPRITE_TEX(1);
300 }
301
302 if (rctx->family < CHIP_CEDAR) {
303 if (rshader->input[i].centroid)
304 tmp |= S_028644_SEL_CENTROID(1);
305
306 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
307 tmp |= S_028644_SEL_LINEAR(1);
308 }
309
310 r600_pipe_state_add_reg(&rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
311 }
312
313 if (prim == PIPE_PRIM_QUADS || prim == PIPE_PRIM_QUAD_STRIP || prim == PIPE_PRIM_POLYGON) {
314 r600_pipe_state_add_reg(&rstate, R_028814_PA_SU_SC_MODE_CNTL,
315 S_028814_PROVOKING_VTX_LAST(1),
316 S_028814_PROVOKING_VTX_LAST(1), NULL);
317 }
318 r600_context_pipe_state_set(&rctx->ctx, &rstate);
319 }
320
321 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
322 struct pipe_resource *buffer)
323 {
324 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
325 struct r600_resource_buffer *rbuffer = r600_buffer(buffer);
326 struct r600_pipe_state *rstate;
327 uint32_t offset;
328
329 /* Note that the state tracker can unbind constant buffers by
330 * passing NULL here.
331 */
332 if (buffer == NULL) {
333 return;
334 }
335
336 r600_upload_const_buffer(rctx, &rbuffer, &offset);
337 offset += r600_bo_offset(rbuffer->r.bo);
338
339 switch (shader) {
340 case PIPE_SHADER_VERTEX:
341 rctx->vs_const_buffer.nregs = 0;
342 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
343 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
344 ALIGN_DIVUP(buffer->width0 >> 4, 16),
345 0xFFFFFFFF, NULL);
346 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
347 R_028980_ALU_CONST_CACHE_VS_0,
348 offset >> 8, 0xFFFFFFFF, rbuffer->r.bo);
349 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
350
351 rstate = &rctx->vs_const_buffer_resource[index];
352 rstate->id = R600_PIPE_STATE_RESOURCE;
353 rstate->nregs = 0;
354 if (rctx->family >= CHIP_CEDAR) {
355 evergreen_pipe_set_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
356 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
357 } else {
358 r600_pipe_set_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
359 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
360 }
361 break;
362 case PIPE_SHADER_FRAGMENT:
363 rctx->ps_const_buffer.nregs = 0;
364 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
365 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
366 ALIGN_DIVUP(buffer->width0 >> 4, 16),
367 0xFFFFFFFF, NULL);
368 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
369 R_028940_ALU_CONST_CACHE_PS_0,
370 offset >> 8, 0xFFFFFFFF, rbuffer->r.bo);
371 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
372
373 rstate = &rctx->ps_const_buffer_resource[index];
374 rstate->id = R600_PIPE_STATE_RESOURCE;
375 rstate->nregs = 0;
376 if (rctx->family >= CHIP_CEDAR) {
377 evergreen_pipe_set_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
378 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
379 } else {
380 r600_pipe_set_buffer_resource(rctx, rstate, &rbuffer->r, offset, 16);
381 r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
382 }
383 break;
384 default:
385 R600_ERR("unsupported %d\n", shader);
386 return;
387 }
388
389 if (buffer != &rbuffer->r.b.b.b)
390 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
391 }
392
393 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
394 {
395 struct r600_pipe_state *rstate;
396 struct r600_resource *rbuffer;
397 struct pipe_vertex_buffer *vertex_buffer;
398 unsigned i, count, offset;
399
400 if (rctx->vertex_elements->vbuffer_need_offset) {
401 /* one resource per vertex elements */
402 count = rctx->vertex_elements->count;
403 } else {
404 /* bind vertex buffer once */
405 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
406 }
407
408 for (i = 0 ; i < count; i++) {
409 rstate = &rctx->fs_resource[i];
410 rstate->id = R600_PIPE_STATE_RESOURCE;
411 rstate->nregs = 0;
412
413 if (rctx->vertex_elements->vbuffer_need_offset) {
414 /* one resource per vertex elements */
415 unsigned vbuffer_index;
416 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
417 vertex_buffer = &rctx->vbuf_mgr->vertex_buffer[vbuffer_index];
418 rbuffer = (struct r600_resource*)rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
419 offset = rctx->vertex_elements->vbuffer_offset[i];
420 } else {
421 /* bind vertex buffer once */
422 vertex_buffer = &rctx->vbuf_mgr->vertex_buffer[i];
423 rbuffer = (struct r600_resource*)rctx->vbuf_mgr->real_vertex_buffer[i];
424 offset = 0;
425 }
426 if (vertex_buffer == NULL || rbuffer == NULL)
427 continue;
428 offset += vertex_buffer->buffer_offset + r600_bo_offset(rbuffer->bo);
429
430 if (rctx->family >= CHIP_CEDAR) {
431 evergreen_pipe_set_buffer_resource(rctx, rstate, rbuffer, offset, vertex_buffer->stride);
432 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
433 } else {
434 r600_pipe_set_buffer_resource(rctx, rstate, rbuffer, offset, vertex_buffer->stride);
435 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
436 }
437 }
438 }
439
440 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
441 {
442 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
443 struct r600_resource *rbuffer;
444 u32 vgt_dma_index_type, vgt_dma_swap_mode, vgt_draw_initiator, mask;
445 struct r600_draw rdraw;
446 struct r600_pipe_state vgt;
447 struct r600_drawl draw = {};
448 unsigned prim;
449
450 r600_flush_depth_textures(rctx);
451 u_vbuf_mgr_draw_begin(rctx->vbuf_mgr, info, NULL, NULL);
452 r600_vertex_buffer_update(rctx);
453
454 draw.info = *info;
455 draw.ctx = ctx;
456 if (info->indexed && rctx->index_buffer.buffer) {
457 draw.info.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
458 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
459
460 r600_translate_index_buffer(rctx, &draw.index_buffer,
461 &rctx->index_buffer.index_size,
462 &draw.info.start,
463 info->count);
464
465 draw.index_size = rctx->index_buffer.index_size;
466 draw.index_buffer_offset = draw.info.start * draw.index_size;
467 draw.info.start = 0;
468
469 if (u_vbuf_resource(draw.index_buffer)->user_ptr) {
470 r600_upload_index_buffer(rctx, &draw);
471 }
472 } else {
473 draw.info.index_bias = info->start;
474 }
475
476 vgt_dma_swap_mode = 0;
477 switch (draw.index_size) {
478 case 2:
479 vgt_draw_initiator = 0;
480 vgt_dma_index_type = 0;
481 #ifdef PIPE_ARCH_BIG_ENDIAN
482 vgt_dma_swap_mode = ENDIAN_8IN16;
483 #endif
484 break;
485 case 4:
486 vgt_draw_initiator = 0;
487 vgt_dma_index_type = 1;
488 #ifdef PIPE_ARCH_BIG_ENDIAN
489 vgt_dma_swap_mode = ENDIAN_8IN32;
490 #endif
491 break;
492 case 0:
493 vgt_draw_initiator = 2;
494 vgt_dma_index_type = 0;
495 break;
496 default:
497 R600_ERR("unsupported index size %d\n", draw.index_size);
498 return;
499 }
500 if (r600_conv_pipe_prim(draw.info.mode, &prim))
501 return;
502 if (unlikely(rctx->ps_shader == NULL)) {
503 R600_ERR("missing vertex shader\n");
504 return;
505 }
506 if (unlikely(rctx->vs_shader == NULL)) {
507 R600_ERR("missing vertex shader\n");
508 return;
509 }
510 /* there should be enough input */
511 if (rctx->vertex_elements->count < rctx->vs_shader->shader.bc.nresource) {
512 R600_ERR("%d resources provided, expecting %d\n",
513 rctx->vertex_elements->count, rctx->vs_shader->shader.bc.nresource);
514 return;
515 }
516
517 r600_spi_update(rctx, draw.info.mode);
518
519 mask = 0;
520 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
521 mask |= (0xF << (i * 4));
522 }
523
524 vgt.id = R600_PIPE_STATE_VGT;
525 vgt.nregs = 0;
526 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
527 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.info.index_bias, 0xFFFFFFFF, NULL);
528 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.info.max_index, 0xFFFFFFFF, NULL);
529 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.info.min_index, 0xFFFFFFFF, NULL);
530 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
531 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
532 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, draw.info.start_instance, 0xFFFFFFFF, NULL);
533 r600_context_pipe_state_set(&rctx->ctx, &vgt);
534
535 rdraw.vgt_num_indices = draw.info.count;
536 rdraw.vgt_num_instances = draw.info.instance_count;
537 rdraw.vgt_index_type = vgt_dma_index_type | (vgt_dma_swap_mode << 2);
538 rdraw.vgt_draw_initiator = vgt_draw_initiator;
539 rdraw.indices = NULL;
540 if (draw.index_buffer) {
541 rbuffer = (struct r600_resource*)draw.index_buffer;
542 rdraw.indices = rbuffer->bo;
543 rdraw.indices_bo_offset = draw.index_buffer_offset;
544 }
545
546 if (rctx->family >= CHIP_CEDAR) {
547 evergreen_context_draw(&rctx->ctx, &rdraw);
548 } else {
549 r600_context_draw(&rctx->ctx, &rdraw);
550 }
551
552 if (rctx->framebuffer.zsbuf)
553 {
554 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
555 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
556 }
557
558 pipe_resource_reference(&draw.index_buffer, NULL);
559
560 u_vbuf_mgr_draw_end(rctx->vbuf_mgr);
561 }