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u_upload_mgr: pass alignment to u_upload_alloc manually
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 assert(!cb->buf);
43 cb->buf = CALLOC(1, 4 * num_dw);
44 cb->max_num_dw = num_dw;
45 }
46
47 void r600_release_command_buffer(struct r600_command_buffer *cb)
48 {
49 FREE(cb->buf);
50 }
51
52 void r600_add_atom(struct r600_context *rctx,
53 struct r600_atom *atom,
54 unsigned id)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->id = id;
60 }
61
62 void r600_init_atom(struct r600_context *rctx,
63 struct r600_atom *atom,
64 unsigned id,
65 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
66 unsigned num_dw)
67 {
68 atom->emit = (void*)emit;
69 atom->num_dw = num_dw;
70 r600_add_atom(rctx, atom, id);
71 }
72
73 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 r600_emit_command_buffer(rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
76 }
77
78 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
79 {
80 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
81 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
82 unsigned alpha_ref = a->sx_alpha_ref;
83
84 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
85 alpha_ref &= ~0x1FFF;
86 }
87
88 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
89 a->sx_alpha_test_control |
90 S_028410_ALPHA_TEST_BYPASS(a->bypass));
91 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
92 }
93
94 static void r600_texture_barrier(struct pipe_context *ctx)
95 {
96 struct r600_context *rctx = (struct r600_context *)ctx;
97
98 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
99 R600_CONTEXT_FLUSH_AND_INV_CB |
100 R600_CONTEXT_FLUSH_AND_INV |
101 R600_CONTEXT_WAIT_3D_IDLE;
102 }
103
104 static unsigned r600_conv_pipe_prim(unsigned prim)
105 {
106 static const unsigned prim_conv[] = {
107 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
108 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
109 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
110 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
111 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
112 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
113 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
114 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
115 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
116 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
117 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
118 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
119 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
120 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
121 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
122 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
123 };
124 assert(prim < Elements(prim_conv));
125 return prim_conv[prim];
126 }
127
128 unsigned r600_conv_prim_to_gs_out(unsigned mode)
129 {
130 static const int prim_conv[] = {
131 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
132 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
133 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
134 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
135 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
136 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
137 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
138 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
139 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
140 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
141 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
145 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
146 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
147 };
148 assert(mode < Elements(prim_conv));
149
150 return prim_conv[mode];
151 }
152
153 /* common state between evergreen and r600 */
154
155 static void r600_bind_blend_state_internal(struct r600_context *rctx,
156 struct r600_blend_state *blend, bool blend_disable)
157 {
158 unsigned color_control;
159 bool update_cb = false;
160
161 rctx->alpha_to_one = blend->alpha_to_one;
162 rctx->dual_src_blend = blend->dual_src_blend;
163
164 if (!blend_disable) {
165 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
166 color_control = blend->cb_color_control;
167 } else {
168 /* Blending is disabled. */
169 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
170 color_control = blend->cb_color_control_no_blend;
171 }
172
173 /* Update derived states. */
174 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
175 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
176 update_cb = true;
177 }
178 if (rctx->b.chip_class <= R700 &&
179 rctx->cb_misc_state.cb_color_control != color_control) {
180 rctx->cb_misc_state.cb_color_control = color_control;
181 update_cb = true;
182 }
183 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
184 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
185 update_cb = true;
186 }
187 if (update_cb) {
188 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
189 }
190 }
191
192 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
193 {
194 struct r600_context *rctx = (struct r600_context *)ctx;
195 struct r600_blend_state *blend = (struct r600_blend_state *)state;
196
197 if (!blend) {
198 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
199 return;
200 }
201
202 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
203 }
204
205 static void r600_set_blend_color(struct pipe_context *ctx,
206 const struct pipe_blend_color *state)
207 {
208 struct r600_context *rctx = (struct r600_context *)ctx;
209
210 rctx->blend_color.state = *state;
211 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
212 }
213
214 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
215 {
216 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
217 struct pipe_blend_color *state = &rctx->blend_color.state;
218
219 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
220 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
221 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
222 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
223 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
224 }
225
226 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
227 {
228 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
229 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
230
231 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
232 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
233 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
234 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
235 if (a->last_draw_was_indirect) {
236 a->last_draw_was_indirect = false;
237 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
238 }
239 }
240
241 static void r600_set_clip_state(struct pipe_context *ctx,
242 const struct pipe_clip_state *state)
243 {
244 struct r600_context *rctx = (struct r600_context *)ctx;
245
246 rctx->clip_state.state = *state;
247 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
248 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
249 }
250
251 static void r600_set_stencil_ref(struct pipe_context *ctx,
252 const struct r600_stencil_ref *state)
253 {
254 struct r600_context *rctx = (struct r600_context *)ctx;
255
256 rctx->stencil_ref.state = *state;
257 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
258 }
259
260 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
261 {
262 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
263 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
264
265 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
266 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
267 S_028430_STENCILREF(a->state.ref_value[0]) |
268 S_028430_STENCILMASK(a->state.valuemask[0]) |
269 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
270 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
271 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
272 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
273 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
274 }
275
276 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
277 const struct pipe_stencil_ref *state)
278 {
279 struct r600_context *rctx = (struct r600_context *)ctx;
280 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
281 struct r600_stencil_ref ref;
282
283 rctx->stencil_ref.pipe_state = *state;
284
285 if (!dsa)
286 return;
287
288 ref.ref_value[0] = state->ref_value[0];
289 ref.ref_value[1] = state->ref_value[1];
290 ref.valuemask[0] = dsa->valuemask[0];
291 ref.valuemask[1] = dsa->valuemask[1];
292 ref.writemask[0] = dsa->writemask[0];
293 ref.writemask[1] = dsa->writemask[1];
294
295 r600_set_stencil_ref(ctx, &ref);
296 }
297
298 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
299 {
300 struct r600_context *rctx = (struct r600_context *)ctx;
301 struct r600_dsa_state *dsa = state;
302 struct r600_stencil_ref ref;
303
304 if (!state) {
305 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
306 return;
307 }
308
309 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
310
311 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
312 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
313 ref.valuemask[0] = dsa->valuemask[0];
314 ref.valuemask[1] = dsa->valuemask[1];
315 ref.writemask[0] = dsa->writemask[0];
316 ref.writemask[1] = dsa->writemask[1];
317 if (rctx->zwritemask != dsa->zwritemask) {
318 rctx->zwritemask = dsa->zwritemask;
319 if (rctx->b.chip_class >= EVERGREEN) {
320 /* work around some issue when not writing to zbuffer
321 * we are having lockup on evergreen so do not enable
322 * hyperz when not writing zbuffer
323 */
324 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
325 }
326 }
327
328 r600_set_stencil_ref(ctx, &ref);
329
330 /* Update alphatest state. */
331 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
332 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
333 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
334 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
335 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
336 }
337 }
338
339 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
340 {
341 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
342 struct r600_context *rctx = (struct r600_context *)ctx;
343
344 if (!state)
345 return;
346
347 rctx->rasterizer = rs;
348
349 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
350
351 if (rs->offset_enable &&
352 (rs->offset_units != rctx->poly_offset_state.offset_units ||
353 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
354 rctx->poly_offset_state.offset_units = rs->offset_units;
355 rctx->poly_offset_state.offset_scale = rs->offset_scale;
356 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
357 }
358
359 /* Update clip_misc_state. */
360 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
361 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
362 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
363 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
364 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
365 }
366
367 /* Workaround for a missing scissor enable on r600. */
368 if (rctx->b.chip_class == R600 &&
369 rs->scissor_enable != rctx->scissor.enable) {
370 rctx->scissor.enable = rs->scissor_enable;
371 rctx->scissor.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
372 rctx->scissor.atom.num_dw = R600_MAX_VIEWPORTS * 4;
373 r600_mark_atom_dirty(rctx, &rctx->scissor.atom);
374 }
375
376 /* Re-emit PA_SC_LINE_STIPPLE. */
377 rctx->last_primitive_type = -1;
378 }
379
380 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
381 {
382 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
383
384 r600_release_command_buffer(&rs->buffer);
385 FREE(rs);
386 }
387
388 static void r600_sampler_view_destroy(struct pipe_context *ctx,
389 struct pipe_sampler_view *state)
390 {
391 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
392
393 if (view->tex_resource->gpu_address &&
394 view->tex_resource->b.b.target == PIPE_BUFFER)
395 LIST_DELINIT(&view->list);
396
397 pipe_resource_reference(&state->texture, NULL);
398 FREE(view);
399 }
400
401 void r600_sampler_states_dirty(struct r600_context *rctx,
402 struct r600_sampler_states *state)
403 {
404 if (state->dirty_mask) {
405 if (state->dirty_mask & state->has_bordercolor_mask) {
406 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
407 }
408 state->atom.num_dw =
409 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
410 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
411 r600_mark_atom_dirty(rctx, &state->atom);
412 }
413 }
414
415 static void r600_bind_sampler_states(struct pipe_context *pipe,
416 unsigned shader,
417 unsigned start,
418 unsigned count, void **states)
419 {
420 struct r600_context *rctx = (struct r600_context *)pipe;
421 struct r600_textures_info *dst = &rctx->samplers[shader];
422 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
423 int seamless_cube_map = -1;
424 unsigned i;
425 /* This sets 1-bit for states with index >= count. */
426 uint32_t disable_mask = ~((1ull << count) - 1);
427 /* These are the new states set by this function. */
428 uint32_t new_mask = 0;
429
430 assert(start == 0); /* XXX fix below */
431
432 if (!states) {
433 disable_mask = ~0u;
434 count = 0;
435 }
436
437 for (i = 0; i < count; i++) {
438 struct r600_pipe_sampler_state *rstate = rstates[i];
439
440 if (rstate == dst->states.states[i]) {
441 continue;
442 }
443
444 if (rstate) {
445 if (rstate->border_color_use) {
446 dst->states.has_bordercolor_mask |= 1 << i;
447 } else {
448 dst->states.has_bordercolor_mask &= ~(1 << i);
449 }
450 seamless_cube_map = rstate->seamless_cube_map;
451
452 new_mask |= 1 << i;
453 } else {
454 disable_mask |= 1 << i;
455 }
456 }
457
458 memcpy(dst->states.states, rstates, sizeof(void*) * count);
459 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
460
461 dst->states.enabled_mask &= ~disable_mask;
462 dst->states.dirty_mask &= dst->states.enabled_mask;
463 dst->states.enabled_mask |= new_mask;
464 dst->states.dirty_mask |= new_mask;
465 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
466
467 r600_sampler_states_dirty(rctx, &dst->states);
468
469 /* Seamless cubemap state. */
470 if (rctx->b.chip_class <= R700 &&
471 seamless_cube_map != -1 &&
472 seamless_cube_map != rctx->seamless_cube_map.enabled) {
473 /* change in TA_CNTL_AUX need a pipeline flush */
474 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
475 rctx->seamless_cube_map.enabled = seamless_cube_map;
476 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
477 }
478 }
479
480 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
481 {
482 free(state);
483 }
484
485 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
486 {
487 struct r600_context *rctx = (struct r600_context *)ctx;
488 struct r600_blend_state *blend = (struct r600_blend_state*)state;
489
490 if (rctx->blend_state.cso == state) {
491 ctx->bind_blend_state(ctx, NULL);
492 }
493
494 r600_release_command_buffer(&blend->buffer);
495 r600_release_command_buffer(&blend->buffer_no_blend);
496 FREE(blend);
497 }
498
499 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
500 {
501 struct r600_context *rctx = (struct r600_context *)ctx;
502 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
503
504 if (rctx->dsa_state.cso == state) {
505 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
506 }
507
508 r600_release_command_buffer(&dsa->buffer);
509 free(dsa);
510 }
511
512 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
513 {
514 struct r600_context *rctx = (struct r600_context *)ctx;
515
516 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
517 }
518
519 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
520 {
521 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
522 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
523 FREE(shader);
524 }
525
526 static void r600_set_index_buffer(struct pipe_context *ctx,
527 const struct pipe_index_buffer *ib)
528 {
529 struct r600_context *rctx = (struct r600_context *)ctx;
530
531 if (ib) {
532 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
533 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
534 r600_context_add_resource_size(ctx, ib->buffer);
535 } else {
536 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
537 }
538 }
539
540 void r600_vertex_buffers_dirty(struct r600_context *rctx)
541 {
542 if (rctx->vertex_buffer_state.dirty_mask) {
543 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
544 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
545 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
546 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
547 }
548 }
549
550 static void r600_set_vertex_buffers(struct pipe_context *ctx,
551 unsigned start_slot, unsigned count,
552 const struct pipe_vertex_buffer *input)
553 {
554 struct r600_context *rctx = (struct r600_context *)ctx;
555 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
556 struct pipe_vertex_buffer *vb = state->vb + start_slot;
557 unsigned i;
558 uint32_t disable_mask = 0;
559 /* These are the new buffers set by this function. */
560 uint32_t new_buffer_mask = 0;
561
562 /* Set vertex buffers. */
563 if (input) {
564 for (i = 0; i < count; i++) {
565 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
566 if (input[i].buffer) {
567 vb[i].stride = input[i].stride;
568 vb[i].buffer_offset = input[i].buffer_offset;
569 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
570 new_buffer_mask |= 1 << i;
571 r600_context_add_resource_size(ctx, input[i].buffer);
572 } else {
573 pipe_resource_reference(&vb[i].buffer, NULL);
574 disable_mask |= 1 << i;
575 }
576 }
577 }
578 } else {
579 for (i = 0; i < count; i++) {
580 pipe_resource_reference(&vb[i].buffer, NULL);
581 }
582 disable_mask = ((1ull << count) - 1);
583 }
584
585 disable_mask <<= start_slot;
586 new_buffer_mask <<= start_slot;
587
588 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
589 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
590 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
591 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
592
593 r600_vertex_buffers_dirty(rctx);
594 }
595
596 void r600_sampler_views_dirty(struct r600_context *rctx,
597 struct r600_samplerview_state *state)
598 {
599 if (state->dirty_mask) {
600 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
601 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
602 util_bitcount(state->dirty_mask);
603 r600_mark_atom_dirty(rctx, &state->atom);
604 }
605 }
606
607 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
608 unsigned start, unsigned count,
609 struct pipe_sampler_view **views)
610 {
611 struct r600_context *rctx = (struct r600_context *) pipe;
612 struct r600_textures_info *dst = &rctx->samplers[shader];
613 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
614 uint32_t dirty_sampler_states_mask = 0;
615 unsigned i;
616 /* This sets 1-bit for textures with index >= count. */
617 uint32_t disable_mask = ~((1ull << count) - 1);
618 /* These are the new textures set by this function. */
619 uint32_t new_mask = 0;
620
621 /* Set textures with index >= count to NULL. */
622 uint32_t remaining_mask;
623
624 assert(start == 0); /* XXX fix below */
625
626 if (!views) {
627 disable_mask = ~0u;
628 count = 0;
629 }
630
631 remaining_mask = dst->views.enabled_mask & disable_mask;
632
633 while (remaining_mask) {
634 i = u_bit_scan(&remaining_mask);
635 assert(dst->views.views[i]);
636
637 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
638 }
639
640 for (i = 0; i < count; i++) {
641 if (rviews[i] == dst->views.views[i]) {
642 continue;
643 }
644
645 if (rviews[i]) {
646 struct r600_texture *rtex =
647 (struct r600_texture*)rviews[i]->base.texture;
648
649 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
650 if (rtex->is_depth && !rtex->is_flushing_texture) {
651 dst->views.compressed_depthtex_mask |= 1 << i;
652 } else {
653 dst->views.compressed_depthtex_mask &= ~(1 << i);
654 }
655
656 /* Track compressed colorbuffers. */
657 if (rtex->cmask.size) {
658 dst->views.compressed_colortex_mask |= 1 << i;
659 } else {
660 dst->views.compressed_colortex_mask &= ~(1 << i);
661 }
662 }
663 /* Changing from array to non-arrays textures and vice versa requires
664 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
665 if (rctx->b.chip_class <= R700 &&
666 (dst->states.enabled_mask & (1 << i)) &&
667 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
668 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
669 dirty_sampler_states_mask |= 1 << i;
670 }
671
672 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
673 new_mask |= 1 << i;
674 r600_context_add_resource_size(pipe, views[i]->texture);
675 } else {
676 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
677 disable_mask |= 1 << i;
678 }
679 }
680
681 dst->views.enabled_mask &= ~disable_mask;
682 dst->views.dirty_mask &= dst->views.enabled_mask;
683 dst->views.enabled_mask |= new_mask;
684 dst->views.dirty_mask |= new_mask;
685 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
686 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
687 dst->views.dirty_buffer_constants = TRUE;
688 r600_sampler_views_dirty(rctx, &dst->views);
689
690 if (dirty_sampler_states_mask) {
691 dst->states.dirty_mask |= dirty_sampler_states_mask;
692 r600_sampler_states_dirty(rctx, &dst->states);
693 }
694 }
695
696 static void r600_set_viewport_states(struct pipe_context *ctx,
697 unsigned start_slot,
698 unsigned num_viewports,
699 const struct pipe_viewport_state *state)
700 {
701 struct r600_context *rctx = (struct r600_context *)ctx;
702 struct r600_viewport_state *rstate = &rctx->viewport;
703 int i;
704
705 for (i = start_slot; i < start_slot + num_viewports; i++)
706 rstate->state[i] = state[i - start_slot];
707 rstate->dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
708 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 8;
709 r600_mark_atom_dirty(rctx, &rctx->viewport.atom);
710 }
711
712 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
713 {
714 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
715 struct r600_viewport_state *rstate = &rctx->viewport;
716 struct pipe_viewport_state *state;
717 uint32_t dirty_mask;
718 unsigned i, offset;
719
720 dirty_mask = rstate->dirty_mask;
721 while (dirty_mask != 0) {
722 i = u_bit_scan(&dirty_mask);
723 offset = i * 6 * 4;
724 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
725 state = &rstate->state[i];
726 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
727 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
728 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
729 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
730 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
731 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
732 }
733 rstate->dirty_mask = 0;
734 rstate->atom.num_dw = 0;
735 }
736
737 /* Compute the key for the hw shader variant */
738 static inline union r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
739 struct r600_pipe_shader_selector * sel)
740 {
741 struct r600_context *rctx = (struct r600_context *)ctx;
742 union r600_shader_key key;
743 memset(&key, 0, sizeof(key));
744
745 switch (sel->type) {
746 case PIPE_SHADER_VERTEX: {
747 key.vs.as_ls = (rctx->tes_shader != NULL);
748 if (!key.vs.as_ls)
749 key.vs.as_es = (rctx->gs_shader != NULL);
750
751 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
752 key.vs.as_gs_a = true;
753 key.vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
754 }
755 break;
756 }
757 case PIPE_SHADER_GEOMETRY:
758 break;
759 case PIPE_SHADER_FRAGMENT: {
760 key.ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
761 key.ps.alpha_to_one = rctx->alpha_to_one &&
762 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
763 !rctx->framebuffer.cb0_is_integer;
764 key.ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
765 /* Dual-source blending only makes sense with nr_cbufs == 1. */
766 if (key.ps.nr_cbufs == 1 && rctx->dual_src_blend)
767 key.ps.nr_cbufs = 2;
768 break;
769 }
770 case PIPE_SHADER_TESS_EVAL:
771 key.tes.as_es = (rctx->gs_shader != NULL);
772 break;
773 case PIPE_SHADER_TESS_CTRL:
774 key.tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
775 break;
776 default:
777 assert(0);
778 }
779
780 return key;
781 }
782
783 /* Select the hw shader variant depending on the current state.
784 * (*dirty) is set to 1 if current variant was changed */
785 static int r600_shader_select(struct pipe_context *ctx,
786 struct r600_pipe_shader_selector* sel,
787 bool *dirty)
788 {
789 union r600_shader_key key;
790 struct r600_pipe_shader * shader = NULL;
791 int r;
792
793 memset(&key, 0, sizeof(key));
794 key = r600_shader_selector_key(ctx, sel);
795
796 /* Check if we don't need to change anything.
797 * This path is also used for most shaders that don't need multiple
798 * variants, it will cost just a computation of the key and this
799 * test. */
800 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
801 return 0;
802 }
803
804 /* lookup if we have other variants in the list */
805 if (sel->num_shaders > 1) {
806 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
807
808 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
809 p = c;
810 c = c->next_variant;
811 }
812
813 if (c) {
814 p->next_variant = c->next_variant;
815 shader = c;
816 }
817 }
818
819 if (unlikely(!shader)) {
820 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
821 shader->selector = sel;
822
823 r = r600_pipe_shader_create(ctx, shader, key);
824 if (unlikely(r)) {
825 R600_ERR("Failed to build shader variant (type=%u) %d\n",
826 sel->type, r);
827 sel->current = NULL;
828 FREE(shader);
829 return r;
830 }
831
832 /* We don't know the value of nr_ps_max_color_exports until we built
833 * at least one variant, so we may need to recompute the key after
834 * building first variant. */
835 if (sel->type == PIPE_SHADER_FRAGMENT &&
836 sel->num_shaders == 0) {
837 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
838 key = r600_shader_selector_key(ctx, sel);
839 }
840
841 memcpy(&shader->key, &key, sizeof(key));
842 sel->num_shaders++;
843 }
844
845 if (dirty)
846 *dirty = true;
847
848 shader->next_variant = sel->current;
849 sel->current = shader;
850
851 return 0;
852 }
853
854 static void *r600_create_shader_state(struct pipe_context *ctx,
855 const struct pipe_shader_state *state,
856 unsigned pipe_shader_type)
857 {
858 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
859 int i;
860
861 sel->type = pipe_shader_type;
862 sel->tokens = tgsi_dup_tokens(state->tokens);
863 sel->so = state->stream_output;
864 tgsi_scan_shader(state->tokens, &sel->info);
865
866 switch (pipe_shader_type) {
867 case PIPE_SHADER_GEOMETRY:
868 sel->gs_output_prim =
869 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
870 sel->gs_max_out_vertices =
871 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
872 sel->gs_num_invocations =
873 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
874 break;
875 case PIPE_SHADER_VERTEX:
876 case PIPE_SHADER_TESS_CTRL:
877 sel->lds_patch_outputs_written_mask = 0;
878 sel->lds_outputs_written_mask = 0;
879
880 for (i = 0; i < sel->info.num_outputs; i++) {
881 unsigned name = sel->info.output_semantic_name[i];
882 unsigned index = sel->info.output_semantic_index[i];
883
884 switch (name) {
885 case TGSI_SEMANTIC_TESSINNER:
886 case TGSI_SEMANTIC_TESSOUTER:
887 case TGSI_SEMANTIC_PATCH:
888 sel->lds_patch_outputs_written_mask |=
889 1llu << r600_get_lds_unique_index(name, index);
890 break;
891 default:
892 sel->lds_outputs_written_mask |=
893 1llu << r600_get_lds_unique_index(name, index);
894 }
895 }
896 break;
897 default:
898 break;
899 }
900
901 return sel;
902 }
903
904 static void *r600_create_ps_state(struct pipe_context *ctx,
905 const struct pipe_shader_state *state)
906 {
907 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
908 }
909
910 static void *r600_create_vs_state(struct pipe_context *ctx,
911 const struct pipe_shader_state *state)
912 {
913 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
914 }
915
916 static void *r600_create_gs_state(struct pipe_context *ctx,
917 const struct pipe_shader_state *state)
918 {
919 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
920 }
921
922 static void *r600_create_tcs_state(struct pipe_context *ctx,
923 const struct pipe_shader_state *state)
924 {
925 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
926 }
927
928 static void *r600_create_tes_state(struct pipe_context *ctx,
929 const struct pipe_shader_state *state)
930 {
931 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
932 }
933
934 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
935 {
936 struct r600_context *rctx = (struct r600_context *)ctx;
937
938 if (!state)
939 state = rctx->dummy_pixel_shader;
940
941 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
942 }
943
944 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
945 {
946 struct r600_context *rctx = (struct r600_context *)ctx;
947
948 if (!state)
949 return;
950
951 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
952 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
953 }
954
955 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
956 {
957 struct r600_context *rctx = (struct r600_context *)ctx;
958
959 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
960
961 if (!state)
962 return;
963 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
964 }
965
966 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
967 {
968 struct r600_context *rctx = (struct r600_context *)ctx;
969
970 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
971 }
972
973 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
974 {
975 struct r600_context *rctx = (struct r600_context *)ctx;
976
977 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
978
979 if (!state)
980 return;
981 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
982 }
983
984 static void r600_delete_shader_selector(struct pipe_context *ctx,
985 struct r600_pipe_shader_selector *sel)
986 {
987 struct r600_pipe_shader *p = sel->current, *c;
988 while (p) {
989 c = p->next_variant;
990 r600_pipe_shader_destroy(ctx, p);
991 free(p);
992 p = c;
993 }
994
995 free(sel->tokens);
996 free(sel);
997 }
998
999
1000 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1001 {
1002 struct r600_context *rctx = (struct r600_context *)ctx;
1003 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1004
1005 if (rctx->ps_shader == sel) {
1006 rctx->ps_shader = NULL;
1007 }
1008
1009 r600_delete_shader_selector(ctx, sel);
1010 }
1011
1012 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1013 {
1014 struct r600_context *rctx = (struct r600_context *)ctx;
1015 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1016
1017 if (rctx->vs_shader == sel) {
1018 rctx->vs_shader = NULL;
1019 }
1020
1021 r600_delete_shader_selector(ctx, sel);
1022 }
1023
1024
1025 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1026 {
1027 struct r600_context *rctx = (struct r600_context *)ctx;
1028 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1029
1030 if (rctx->gs_shader == sel) {
1031 rctx->gs_shader = NULL;
1032 }
1033
1034 r600_delete_shader_selector(ctx, sel);
1035 }
1036
1037 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1038 {
1039 struct r600_context *rctx = (struct r600_context *)ctx;
1040 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1041
1042 if (rctx->tcs_shader == sel) {
1043 rctx->tcs_shader = NULL;
1044 }
1045
1046 r600_delete_shader_selector(ctx, sel);
1047 }
1048
1049 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1050 {
1051 struct r600_context *rctx = (struct r600_context *)ctx;
1052 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1053
1054 if (rctx->tes_shader == sel) {
1055 rctx->tes_shader = NULL;
1056 }
1057
1058 r600_delete_shader_selector(ctx, sel);
1059 }
1060
1061 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1062 {
1063 if (state->dirty_mask) {
1064 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
1065 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1066 : util_bitcount(state->dirty_mask)*19;
1067 r600_mark_atom_dirty(rctx, &state->atom);
1068 }
1069 }
1070
1071 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1072 struct pipe_constant_buffer *input)
1073 {
1074 struct r600_context *rctx = (struct r600_context *)ctx;
1075 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1076 struct pipe_constant_buffer *cb;
1077 const uint8_t *ptr;
1078
1079 /* Note that the state tracker can unbind constant buffers by
1080 * passing NULL here.
1081 */
1082 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1083 state->enabled_mask &= ~(1 << index);
1084 state->dirty_mask &= ~(1 << index);
1085 pipe_resource_reference(&state->cb[index].buffer, NULL);
1086 return;
1087 }
1088
1089 cb = &state->cb[index];
1090 cb->buffer_size = input->buffer_size;
1091
1092 ptr = input->user_buffer;
1093
1094 if (ptr) {
1095 /* Upload the user buffer. */
1096 if (R600_BIG_ENDIAN) {
1097 uint32_t *tmpPtr;
1098 unsigned i, size = input->buffer_size;
1099
1100 if (!(tmpPtr = malloc(size))) {
1101 R600_ERR("Failed to allocate BE swap buffer.\n");
1102 return;
1103 }
1104
1105 for (i = 0; i < size / 4; ++i) {
1106 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1107 }
1108
1109 u_upload_data(rctx->b.uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
1110 free(tmpPtr);
1111 } else {
1112 u_upload_data(rctx->b.uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
1113 }
1114 /* account it in gtt */
1115 rctx->b.gtt += input->buffer_size;
1116 } else {
1117 /* Setup the hw buffer. */
1118 cb->buffer_offset = input->buffer_offset;
1119 pipe_resource_reference(&cb->buffer, input->buffer);
1120 r600_context_add_resource_size(ctx, input->buffer);
1121 }
1122
1123 state->enabled_mask |= 1 << index;
1124 state->dirty_mask |= 1 << index;
1125 r600_constant_buffers_dirty(rctx, state);
1126 }
1127
1128 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1129 {
1130 struct r600_context *rctx = (struct r600_context*)pipe;
1131
1132 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1133 return;
1134
1135 rctx->sample_mask.sample_mask = sample_mask;
1136 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1137 }
1138
1139 static void r600_update_driver_const_buffers(struct r600_context *rctx)
1140 {
1141 int sh, size;;
1142 void *ptr;
1143 struct pipe_constant_buffer cb;
1144 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
1145 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1146 if (!info->vs_ucp_dirty &&
1147 !info->texture_const_dirty &&
1148 !info->ps_sample_pos_dirty)
1149 continue;
1150
1151 ptr = info->constants;
1152 size = info->alloc_size;
1153 if (info->vs_ucp_dirty) {
1154 assert(sh == PIPE_SHADER_VERTEX);
1155 if (!size) {
1156 ptr = rctx->clip_state.state.ucp;
1157 size = R600_UCP_SIZE;
1158 } else {
1159 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1160 }
1161 info->vs_ucp_dirty = false;
1162 }
1163
1164 if (info->ps_sample_pos_dirty) {
1165 assert(sh == PIPE_SHADER_FRAGMENT);
1166 if (!size) {
1167 ptr = rctx->sample_positions;
1168 size = R600_UCP_SIZE;
1169 } else {
1170 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1171 }
1172 info->ps_sample_pos_dirty = false;
1173 }
1174
1175 if (info->texture_const_dirty) {
1176 assert (ptr);
1177 assert (size);
1178 if (sh == PIPE_SHADER_VERTEX)
1179 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1180 if (sh == PIPE_SHADER_FRAGMENT)
1181 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1182 }
1183 info->texture_const_dirty = false;
1184
1185 cb.buffer = NULL;
1186 cb.user_buffer = ptr;
1187 cb.buffer_offset = 0;
1188 cb.buffer_size = size;
1189 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1190 pipe_resource_reference(&cb.buffer, NULL);
1191 }
1192 }
1193
1194 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1195 int array_size, uint32_t *base_offset)
1196 {
1197 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1198 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1199 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1200 info->alloc_size = array_size + R600_UCP_SIZE;
1201 }
1202 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1203 info->texture_const_dirty = true;
1204 *base_offset = R600_UCP_SIZE;
1205 return info->constants;
1206 }
1207 /*
1208 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1209 * doesn't require full swizzles it does need masking and setting alpha
1210 * to one, so we setup a set of 5 constants with the masks + alpha value
1211 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1212 * then OR the alpha with the value given here.
1213 * We use a 6th constant to store the txq buffer size in
1214 * we use 7th slot for number of cube layers in a cube map array.
1215 */
1216 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1217 {
1218 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1219 int bits;
1220 uint32_t array_size;
1221 int i, j;
1222 uint32_t *constants;
1223 uint32_t base_offset;
1224 if (!samplers->views.dirty_buffer_constants)
1225 return;
1226
1227 samplers->views.dirty_buffer_constants = FALSE;
1228
1229 bits = util_last_bit(samplers->views.enabled_mask);
1230 array_size = bits * 8 * sizeof(uint32_t) * 4;
1231
1232 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1233
1234 for (i = 0; i < bits; i++) {
1235 if (samplers->views.enabled_mask & (1 << i)) {
1236 int offset = (base_offset / 4) + i * 8;
1237 const struct util_format_description *desc;
1238 desc = util_format_description(samplers->views.views[i]->base.format);
1239
1240 for (j = 0; j < 4; j++)
1241 if (j < desc->nr_channels)
1242 constants[offset+j] = 0xffffffff;
1243 else
1244 constants[offset+j] = 0x0;
1245 if (desc->nr_channels < 4) {
1246 if (desc->channel[0].pure_integer)
1247 constants[offset+4] = 1;
1248 else
1249 constants[offset+4] = fui(1.0);
1250 } else
1251 constants[offset + 4] = 0;
1252
1253 constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1254 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1255 }
1256 }
1257
1258 }
1259
1260 /* On evergreen we store two values
1261 * 1. buffer size for TXQ
1262 * 2. number of cube layers in a cube map array.
1263 */
1264 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1265 {
1266 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1267 int bits;
1268 uint32_t array_size;
1269 int i;
1270 uint32_t *constants;
1271 uint32_t base_offset;
1272 if (!samplers->views.dirty_buffer_constants)
1273 return;
1274
1275 samplers->views.dirty_buffer_constants = FALSE;
1276
1277 bits = util_last_bit(samplers->views.enabled_mask);
1278 array_size = bits * 2 * sizeof(uint32_t) * 4;
1279
1280 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1281 &base_offset);
1282
1283 for (i = 0; i < bits; i++) {
1284 if (samplers->views.enabled_mask & (1 << i)) {
1285 uint32_t offset = (base_offset / 4) + i * 2;
1286 constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1287 constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
1288 }
1289 }
1290 }
1291
1292 /* set sample xy locations as array of fragment shader constants */
1293 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1294 {
1295 int i;
1296 struct pipe_context *ctx = &rctx->b.b;
1297
1298 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1299 assert(rctx->framebuffer.nr_samples <= Elements(rctx->sample_positions)/4);
1300
1301 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1302 for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1303 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1304 /* Also fill in center-zeroed positions used for interpolateAtSample */
1305 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1306 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1307 }
1308
1309 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1310 }
1311
1312 static void update_shader_atom(struct pipe_context *ctx,
1313 struct r600_shader_state *state,
1314 struct r600_pipe_shader *shader)
1315 {
1316 struct r600_context *rctx = (struct r600_context *)ctx;
1317
1318 state->shader = shader;
1319 if (shader) {
1320 state->atom.num_dw = shader->command_buffer.num_dw;
1321 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1322 } else {
1323 state->atom.num_dw = 0;
1324 }
1325 r600_mark_atom_dirty(rctx, &state->atom);
1326 }
1327
1328 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1329 {
1330 if (rctx->shader_stages.geom_enable != enable) {
1331 rctx->shader_stages.geom_enable = enable;
1332 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1333 }
1334
1335 if (rctx->gs_rings.enable != enable) {
1336 rctx->gs_rings.enable = enable;
1337 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1338
1339 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1340 unsigned size = 0x1C000;
1341 rctx->gs_rings.esgs_ring.buffer =
1342 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1343 PIPE_USAGE_DEFAULT, size);
1344 rctx->gs_rings.esgs_ring.buffer_size = size;
1345
1346 size = 0x4000000;
1347
1348 rctx->gs_rings.gsvs_ring.buffer =
1349 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1350 PIPE_USAGE_DEFAULT, size);
1351 rctx->gs_rings.gsvs_ring.buffer_size = size;
1352 }
1353
1354 if (enable) {
1355 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1356 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1357 if (rctx->tes_shader) {
1358 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1359 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1360 } else {
1361 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1362 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1363 }
1364 } else {
1365 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1366 R600_GS_RING_CONST_BUFFER, NULL);
1367 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1368 R600_GS_RING_CONST_BUFFER, NULL);
1369 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1370 R600_GS_RING_CONST_BUFFER, NULL);
1371 }
1372 }
1373 }
1374
1375 static void r600_update_clip_state(struct r600_context *rctx,
1376 struct r600_pipe_shader *current)
1377 {
1378 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1379 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1380 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1381 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1382 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1383 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1384 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1385 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1386 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1387 }
1388 }
1389
1390 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1391 {
1392 struct ureg_src const0, const1;
1393 struct ureg_dst tessouter, tessinner;
1394 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1395
1396 if (!ureg)
1397 return; /* if we get here, we're screwed */
1398
1399 assert(!rctx->fixed_func_tcs_shader);
1400
1401 ureg_DECL_constant2D(ureg, 0, 3, R600_LDS_INFO_CONST_BUFFER);
1402 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 2),
1403 R600_LDS_INFO_CONST_BUFFER);
1404 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 3),
1405 R600_LDS_INFO_CONST_BUFFER);
1406
1407 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1408 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1409
1410 ureg_MOV(ureg, tessouter, const0);
1411 ureg_MOV(ureg, tessinner, const1);
1412 ureg_END(ureg);
1413
1414 rctx->fixed_func_tcs_shader =
1415 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1416 }
1417
1418 #define SELECT_SHADER_OR_FAIL(x) do { \
1419 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1420 if (unlikely(!rctx->x##_shader->current)) \
1421 return false; \
1422 } while(0)
1423
1424 #define UPDATE_SHADER(hw, sw) do { \
1425 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1426 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1427 } while(0)
1428
1429 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1430 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1431 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1432 clip_so_current = rctx->sw##_shader->current; \
1433 } \
1434 } while(0)
1435
1436 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1437 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1438 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1439 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1440 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1441 } \
1442 } while(0)
1443
1444 #define SET_NULL_SHADER(hw) do { \
1445 if (rctx->hw_shader_stages[(hw)].shader) \
1446 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1447 } while (0)
1448
1449 static bool r600_update_derived_state(struct r600_context *rctx)
1450 {
1451 struct pipe_context * ctx = (struct pipe_context*)rctx;
1452 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1453 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1454 bool blend_disable;
1455 bool need_buf_const;
1456 struct r600_pipe_shader *clip_so_current = NULL;
1457
1458 if (!rctx->blitter->running) {
1459 unsigned i;
1460
1461 /* Decompress textures if needed. */
1462 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1463 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1464 if (views->compressed_depthtex_mask) {
1465 r600_decompress_depth_textures(rctx, views);
1466 }
1467 if (views->compressed_colortex_mask) {
1468 r600_decompress_color_textures(rctx, views);
1469 }
1470 }
1471 }
1472
1473 SELECT_SHADER_OR_FAIL(ps);
1474
1475 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1476
1477 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1478
1479 if (rctx->gs_shader)
1480 SELECT_SHADER_OR_FAIL(gs);
1481
1482 /* Hull Shader */
1483 if (rctx->tcs_shader) {
1484 SELECT_SHADER_OR_FAIL(tcs);
1485
1486 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1487 } else if (rctx->tes_shader) {
1488 if (!rctx->fixed_func_tcs_shader) {
1489 r600_generate_fixed_func_tcs(rctx);
1490 if (!rctx->fixed_func_tcs_shader)
1491 return false;
1492
1493 }
1494 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1495
1496 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1497 } else
1498 SET_NULL_SHADER(EG_HW_STAGE_HS);
1499
1500 if (rctx->tes_shader) {
1501 SELECT_SHADER_OR_FAIL(tes);
1502 }
1503
1504 SELECT_SHADER_OR_FAIL(vs);
1505
1506 if (rctx->gs_shader) {
1507 if (!rctx->shader_stages.geom_enable) {
1508 rctx->shader_stages.geom_enable = true;
1509 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1510 }
1511
1512 /* gs_shader provides GS and VS (copy shader) */
1513 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1514
1515 /* vs_shader is used as ES */
1516
1517 if (rctx->tes_shader) {
1518 /* VS goes to LS, TES goes to ES */
1519 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1520 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1521 } else {
1522 /* vs_shader is used as ES */
1523 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1524 SET_NULL_SHADER(EG_HW_STAGE_LS);
1525 }
1526 } else {
1527 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1528 SET_NULL_SHADER(R600_HW_STAGE_GS);
1529 SET_NULL_SHADER(R600_HW_STAGE_ES);
1530 rctx->shader_stages.geom_enable = false;
1531 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1532 }
1533
1534 if (rctx->tes_shader) {
1535 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1536 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1537 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1538 } else {
1539 SET_NULL_SHADER(EG_HW_STAGE_LS);
1540 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1541 }
1542 }
1543
1544 /* Update clip misc state. */
1545 if (clip_so_current) {
1546 r600_update_clip_state(rctx, clip_so_current);
1547 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1548 }
1549
1550 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1551 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1552 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1553
1554 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1555 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1556 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1557 }
1558
1559 if (rctx->b.chip_class <= R700) {
1560 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1561
1562 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1563 rctx->cb_misc_state.multiwrite = multiwrite;
1564 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1565 }
1566 }
1567
1568 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1569 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1570 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1571
1572 if (rctx->b.chip_class >= EVERGREEN)
1573 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1574 else
1575 r600_update_ps_state(ctx, rctx->ps_shader->current);
1576 }
1577
1578 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1579 }
1580 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
1581
1582 if (rctx->b.chip_class >= EVERGREEN) {
1583 evergreen_update_db_shader_control(rctx);
1584 } else {
1585 r600_update_db_shader_control(rctx);
1586 }
1587
1588 /* on R600 we stuff masks + txq info into one constant buffer */
1589 /* on evergreen we only need a txq info one */
1590 if (rctx->ps_shader) {
1591 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1592 if (need_buf_const) {
1593 if (rctx->b.chip_class < EVERGREEN)
1594 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1595 else
1596 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1597 }
1598 }
1599
1600 if (rctx->vs_shader) {
1601 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1602 if (need_buf_const) {
1603 if (rctx->b.chip_class < EVERGREEN)
1604 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1605 else
1606 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1607 }
1608 }
1609
1610 if (rctx->gs_shader) {
1611 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1612 if (need_buf_const) {
1613 if (rctx->b.chip_class < EVERGREEN)
1614 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1615 else
1616 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1617 }
1618 }
1619
1620 r600_update_driver_const_buffers(rctx);
1621
1622 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1623 if (!r600_adjust_gprs(rctx)) {
1624 /* discard rendering */
1625 return false;
1626 }
1627 }
1628
1629 if (rctx->b.chip_class == EVERGREEN) {
1630 if (!evergreen_adjust_gprs(rctx)) {
1631 /* discard rendering */
1632 return false;
1633 }
1634 }
1635
1636 blend_disable = (rctx->dual_src_blend &&
1637 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1638
1639 if (blend_disable != rctx->force_blend_disable) {
1640 rctx->force_blend_disable = blend_disable;
1641 r600_bind_blend_state_internal(rctx,
1642 rctx->blend_state.cso,
1643 blend_disable);
1644 }
1645
1646 return true;
1647 }
1648
1649 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1650 {
1651 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1652 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1653
1654 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1655 state->pa_cl_clip_cntl |
1656 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1657 S_028810_CLIP_DISABLE(state->clip_disable));
1658 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1659 state->pa_cl_vs_out_cntl |
1660 (state->clip_plane_enable & state->clip_dist_write));
1661 /* reuse needs to be set off if we write oViewport */
1662 if (rctx->b.chip_class >= EVERGREEN)
1663 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
1664 S_028AB4_REUSE_OFF(state->vs_out_viewport));
1665 }
1666
1667 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1668 {
1669 struct r600_context *rctx = (struct r600_context *)ctx;
1670 struct pipe_draw_info info = *dinfo;
1671 struct pipe_index_buffer ib = {};
1672 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1673 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
1674 uint64_t mask;
1675 unsigned num_patches;
1676
1677 if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
1678 return;
1679 }
1680
1681 if (!rctx->vs_shader || !rctx->ps_shader) {
1682 assert(0);
1683 return;
1684 }
1685
1686 /* make sure that the gfx ring is only one active */
1687 if (rctx->b.dma.cs && rctx->b.dma.cs->cdw) {
1688 rctx->b.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1689 }
1690
1691 if (!r600_update_derived_state(rctx)) {
1692 /* useless to render because current rendering command
1693 * can't be achieved
1694 */
1695 return;
1696 }
1697
1698 if (info.indexed) {
1699 /* Initialize the index buffer struct. */
1700 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1701 ib.user_buffer = rctx->index_buffer.user_buffer;
1702 ib.index_size = rctx->index_buffer.index_size;
1703 ib.offset = rctx->index_buffer.offset;
1704 if (!info.indirect) {
1705 ib.offset += info.start * ib.index_size;
1706 }
1707
1708 /* Translate 8-bit indices to 16-bit. */
1709 if (unlikely(ib.index_size == 1)) {
1710 struct pipe_resource *out_buffer = NULL;
1711 unsigned out_offset;
1712 void *ptr;
1713 unsigned start, count;
1714
1715 if (likely(!info.indirect)) {
1716 start = 0;
1717 count = info.count;
1718 }
1719 else {
1720 /* Have to get start/count from indirect buffer, slow path ahead... */
1721 struct r600_resource *indirect_resource = (struct r600_resource *)info.indirect;
1722 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
1723 PIPE_TRANSFER_READ);
1724 if (data) {
1725 data += info.indirect_offset / sizeof(unsigned);
1726 start = data[2] * ib.index_size;
1727 count = data[0];
1728 }
1729 else {
1730 start = 0;
1731 count = 0;
1732 }
1733 }
1734
1735 u_upload_alloc(rctx->b.uploader, start, count * 2, 256,
1736 &out_offset, &out_buffer, &ptr);
1737
1738 util_shorten_ubyte_elts_to_userptr(
1739 &rctx->b.b, &ib, 0, ib.offset + start, count, ptr);
1740
1741 pipe_resource_reference(&ib.buffer, NULL);
1742 ib.user_buffer = NULL;
1743 ib.buffer = out_buffer;
1744 ib.offset = out_offset;
1745 ib.index_size = 2;
1746 }
1747
1748 /* Upload the index buffer.
1749 * The upload is skipped for small index counts on little-endian machines
1750 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1751 * Indirect draws never use immediate indices.
1752 * Note: Instanced rendering in combination with immediate indices hangs. */
1753 if (ib.user_buffer && (R600_BIG_ENDIAN || info.indirect ||
1754 info.instance_count > 1 ||
1755 info.count*ib.index_size > 20)) {
1756 u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size,
1757 ib.user_buffer, &ib.offset, &ib.buffer);
1758 ib.user_buffer = NULL;
1759 }
1760 } else {
1761 info.index_bias = info.start;
1762 }
1763
1764 /* Set the index offset and primitive restart. */
1765 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1766 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1767 rctx->vgt_state.vgt_indx_offset != info.index_bias ||
1768 (rctx->vgt_state.last_draw_was_indirect && !info.indirect)) {
1769 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1770 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1771 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1772 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
1773 }
1774
1775 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1776 if (rctx->b.chip_class == R600) {
1777 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1778 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1779 }
1780
1781 if (rctx->b.chip_class >= EVERGREEN)
1782 evergreen_setup_tess_constants(rctx, &info, &num_patches);
1783
1784 /* Emit states. */
1785 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1786 r600_flush_emit(rctx);
1787
1788 mask = rctx->dirty_atoms;
1789 while (mask != 0) {
1790 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
1791 }
1792
1793 if (rctx->b.chip_class == CAYMAN) {
1794 /* Copied from radeonsi. */
1795 unsigned primgroup_size = 128; /* recommended without a GS */
1796 bool ia_switch_on_eop = false;
1797 bool partial_vs_wave = false;
1798
1799 if (rctx->gs_shader)
1800 primgroup_size = 64; /* recommended with a GS */
1801
1802 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
1803 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
1804 ia_switch_on_eop = true;
1805 }
1806
1807 if (rctx->b.streamout.streamout_enabled ||
1808 rctx->b.streamout.prims_gen_query_enabled)
1809 partial_vs_wave = true;
1810
1811 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
1812 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
1813 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
1814 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
1815 }
1816
1817 if (rctx->b.chip_class >= EVERGREEN) {
1818 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, &info,
1819 num_patches);
1820
1821 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
1822 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
1823 }
1824
1825 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1826 * even though it should have no effect on those. */
1827 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
1828 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
1829 unsigned prim = info.mode;
1830
1831 if (rctx->gs_shader) {
1832 prim = rctx->gs_shader->gs_output_prim;
1833 }
1834 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
1835
1836 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
1837 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
1838 info.mode == R600_PRIM_RECTANGLE_LIST) {
1839 su_sc_mode_cntl &= C_028814_CULL_FRONT;
1840 }
1841 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
1842 }
1843
1844 /* Update start instance. */
1845 if (!info.indirect && rctx->last_start_instance != info.start_instance) {
1846 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1847 rctx->last_start_instance = info.start_instance;
1848 }
1849
1850 /* Update the primitive type. */
1851 if (rctx->last_primitive_type != info.mode) {
1852 unsigned ls_mask = 0;
1853
1854 if (info.mode == PIPE_PRIM_LINES)
1855 ls_mask = 1;
1856 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1857 info.mode == PIPE_PRIM_LINE_LOOP)
1858 ls_mask = 2;
1859
1860 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1861 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1862 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1863 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1864 r600_conv_pipe_prim(info.mode));
1865
1866 rctx->last_primitive_type = info.mode;
1867 }
1868
1869 /* Draw packets. */
1870 if (!info.indirect) {
1871 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, 0);
1872 cs->buf[cs->cdw++] = info.instance_count;
1873 }
1874
1875 if (unlikely(info.indirect)) {
1876 uint64_t va = r600_resource(info.indirect)->gpu_address;
1877 assert(rctx->b.chip_class >= EVERGREEN);
1878
1879 // Invalidate so non-indirect draw calls reset this state
1880 rctx->vgt_state.last_draw_was_indirect = true;
1881 rctx->last_start_instance = -1;
1882
1883 cs->buf[cs->cdw++] = PKT3(EG_PKT3_SET_BASE, 2, 0);
1884 cs->buf[cs->cdw++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE;
1885 cs->buf[cs->cdw++] = va;
1886 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1887
1888 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1889 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1890 (struct r600_resource*)info.indirect,
1891 RADEON_USAGE_READ,
1892 RADEON_PRIO_DRAW_INDIRECT);
1893 }
1894
1895 if (info.indexed) {
1896 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, 0);
1897 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1898 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1899 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1900
1901 if (ib.user_buffer) {
1902 unsigned size_bytes = info.count*ib.index_size;
1903 unsigned size_dw = align(size_bytes, 4) / 4;
1904 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit);
1905 cs->buf[cs->cdw++] = info.count;
1906 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1907 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1908 cs->cdw += size_dw;
1909 } else {
1910 uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
1911
1912 if (likely(!info.indirect)) {
1913 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit);
1914 cs->buf[cs->cdw++] = va;
1915 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1916 cs->buf[cs->cdw++] = info.count;
1917 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1918 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1919 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1920 (struct r600_resource*)ib.buffer,
1921 RADEON_USAGE_READ,
1922 RADEON_PRIO_INDEX_BUFFER);
1923 }
1924 else {
1925 uint32_t max_size = (ib.buffer->width0 - ib.offset) / ib.index_size;
1926
1927 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BASE, 1, 0);
1928 cs->buf[cs->cdw++] = va;
1929 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1930
1931 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1932 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1933 (struct r600_resource*)ib.buffer,
1934 RADEON_USAGE_READ,
1935 RADEON_PRIO_INDEX_BUFFER);
1936
1937 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0);
1938 cs->buf[cs->cdw++] = max_size;
1939
1940 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit);
1941 cs->buf[cs->cdw++] = info.indirect_offset;
1942 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1943 }
1944 }
1945 } else {
1946 if (unlikely(info.count_from_stream_output)) {
1947 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1948 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
1949
1950 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1951
1952 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1953 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1954 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1955 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1956 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1957 cs->buf[cs->cdw++] = 0; /* unused */
1958
1959 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1960 cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1961 t->buf_filled_size, RADEON_USAGE_READ,
1962 RADEON_PRIO_SO_FILLED_SIZE);
1963 }
1964
1965 if (likely(!info.indirect)) {
1966 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit);
1967 cs->buf[cs->cdw++] = info.count;
1968 }
1969 else {
1970 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit);
1971 cs->buf[cs->cdw++] = info.indirect_offset;
1972 }
1973 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1974 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1975 }
1976
1977 /* SMX returns CONTEXT_DONE too early workaround */
1978 if (rctx->b.family == CHIP_R600 ||
1979 rctx->b.family == CHIP_RV610 ||
1980 rctx->b.family == CHIP_RV630 ||
1981 rctx->b.family == CHIP_RV635) {
1982 /* if we have gs shader or streamout
1983 we need to do a wait idle after every draw */
1984 if (rctx->gs_shader || rctx->b.streamout.streamout_enabled) {
1985 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1986 }
1987 }
1988
1989 /* ES ring rolling over at EOP - workaround */
1990 if (rctx->b.chip_class == R600) {
1991 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
1992 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT);
1993 }
1994
1995 if (rctx->screen->b.trace_bo) {
1996 r600_trace_emit(rctx);
1997 }
1998
1999 /* Set the depth buffer as dirty. */
2000 if (rctx->framebuffer.state.zsbuf) {
2001 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2002 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2003
2004 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2005
2006 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2007 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2008 }
2009 if (rctx->framebuffer.compressed_cb_mask) {
2010 struct pipe_surface *surf;
2011 struct r600_texture *rtex;
2012 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2013
2014 do {
2015 unsigned i = u_bit_scan(&mask);
2016 surf = rctx->framebuffer.state.cbufs[i];
2017 rtex = (struct r600_texture*)surf->texture;
2018
2019 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2020
2021 } while (mask);
2022 }
2023
2024 pipe_resource_reference(&ib.buffer, NULL);
2025 rctx->b.num_draw_calls++;
2026 }
2027
2028 uint32_t r600_translate_stencil_op(int s_op)
2029 {
2030 switch (s_op) {
2031 case PIPE_STENCIL_OP_KEEP:
2032 return V_028800_STENCIL_KEEP;
2033 case PIPE_STENCIL_OP_ZERO:
2034 return V_028800_STENCIL_ZERO;
2035 case PIPE_STENCIL_OP_REPLACE:
2036 return V_028800_STENCIL_REPLACE;
2037 case PIPE_STENCIL_OP_INCR:
2038 return V_028800_STENCIL_INCR;
2039 case PIPE_STENCIL_OP_DECR:
2040 return V_028800_STENCIL_DECR;
2041 case PIPE_STENCIL_OP_INCR_WRAP:
2042 return V_028800_STENCIL_INCR_WRAP;
2043 case PIPE_STENCIL_OP_DECR_WRAP:
2044 return V_028800_STENCIL_DECR_WRAP;
2045 case PIPE_STENCIL_OP_INVERT:
2046 return V_028800_STENCIL_INVERT;
2047 default:
2048 R600_ERR("Unknown stencil op %d", s_op);
2049 assert(0);
2050 break;
2051 }
2052 return 0;
2053 }
2054
2055 uint32_t r600_translate_fill(uint32_t func)
2056 {
2057 switch(func) {
2058 case PIPE_POLYGON_MODE_FILL:
2059 return 2;
2060 case PIPE_POLYGON_MODE_LINE:
2061 return 1;
2062 case PIPE_POLYGON_MODE_POINT:
2063 return 0;
2064 default:
2065 assert(0);
2066 return 0;
2067 }
2068 }
2069
2070 unsigned r600_tex_wrap(unsigned wrap)
2071 {
2072 switch (wrap) {
2073 default:
2074 case PIPE_TEX_WRAP_REPEAT:
2075 return V_03C000_SQ_TEX_WRAP;
2076 case PIPE_TEX_WRAP_CLAMP:
2077 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2078 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2079 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2080 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2081 return V_03C000_SQ_TEX_CLAMP_BORDER;
2082 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2083 return V_03C000_SQ_TEX_MIRROR;
2084 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2085 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2086 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2087 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2088 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2089 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2090 }
2091 }
2092
2093 unsigned r600_tex_filter(unsigned filter)
2094 {
2095 switch (filter) {
2096 default:
2097 case PIPE_TEX_FILTER_NEAREST:
2098 return V_03C000_SQ_TEX_XY_FILTER_POINT;
2099 case PIPE_TEX_FILTER_LINEAR:
2100 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
2101 }
2102 }
2103
2104 unsigned r600_tex_mipfilter(unsigned filter)
2105 {
2106 switch (filter) {
2107 case PIPE_TEX_MIPFILTER_NEAREST:
2108 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2109 case PIPE_TEX_MIPFILTER_LINEAR:
2110 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2111 default:
2112 case PIPE_TEX_MIPFILTER_NONE:
2113 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2114 }
2115 }
2116
2117 unsigned r600_tex_compare(unsigned compare)
2118 {
2119 switch (compare) {
2120 default:
2121 case PIPE_FUNC_NEVER:
2122 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2123 case PIPE_FUNC_LESS:
2124 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2125 case PIPE_FUNC_EQUAL:
2126 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2127 case PIPE_FUNC_LEQUAL:
2128 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2129 case PIPE_FUNC_GREATER:
2130 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2131 case PIPE_FUNC_NOTEQUAL:
2132 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2133 case PIPE_FUNC_GEQUAL:
2134 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2135 case PIPE_FUNC_ALWAYS:
2136 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2137 }
2138 }
2139
2140 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2141 {
2142 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2143 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2144 (linear_filter &&
2145 (wrap == PIPE_TEX_WRAP_CLAMP ||
2146 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2147 }
2148
2149 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2150 {
2151 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2152 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2153
2154 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2155 state->border_color.ui[2] || state->border_color.ui[3]) &&
2156 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2157 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2158 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2159 }
2160
2161 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2162 {
2163
2164 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2165 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2166
2167 if (!shader)
2168 return;
2169
2170 r600_emit_command_buffer(cs, &shader->command_buffer);
2171 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2172 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2173 RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER));
2174 }
2175
2176 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2177 const unsigned char *swizzle_view,
2178 boolean vtx)
2179 {
2180 unsigned i;
2181 unsigned char swizzle[4];
2182 unsigned result = 0;
2183 const uint32_t tex_swizzle_shift[4] = {
2184 16, 19, 22, 25,
2185 };
2186 const uint32_t vtx_swizzle_shift[4] = {
2187 3, 6, 9, 12,
2188 };
2189 const uint32_t swizzle_bit[4] = {
2190 0, 1, 2, 3,
2191 };
2192 const uint32_t *swizzle_shift = tex_swizzle_shift;
2193
2194 if (vtx)
2195 swizzle_shift = vtx_swizzle_shift;
2196
2197 if (swizzle_view) {
2198 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2199 } else {
2200 memcpy(swizzle, swizzle_format, 4);
2201 }
2202
2203 /* Get swizzle. */
2204 for (i = 0; i < 4; i++) {
2205 switch (swizzle[i]) {
2206 case UTIL_FORMAT_SWIZZLE_Y:
2207 result |= swizzle_bit[1] << swizzle_shift[i];
2208 break;
2209 case UTIL_FORMAT_SWIZZLE_Z:
2210 result |= swizzle_bit[2] << swizzle_shift[i];
2211 break;
2212 case UTIL_FORMAT_SWIZZLE_W:
2213 result |= swizzle_bit[3] << swizzle_shift[i];
2214 break;
2215 case UTIL_FORMAT_SWIZZLE_0:
2216 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2217 break;
2218 case UTIL_FORMAT_SWIZZLE_1:
2219 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2220 break;
2221 default: /* UTIL_FORMAT_SWIZZLE_X */
2222 result |= swizzle_bit[0] << swizzle_shift[i];
2223 }
2224 }
2225 return result;
2226 }
2227
2228 /* texture format translate */
2229 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2230 enum pipe_format format,
2231 const unsigned char *swizzle_view,
2232 uint32_t *word4_p, uint32_t *yuv_format_p)
2233 {
2234 struct r600_screen *rscreen = (struct r600_screen *)screen;
2235 uint32_t result = 0, word4 = 0, yuv_format = 0;
2236 const struct util_format_description *desc;
2237 boolean uniform = TRUE;
2238 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
2239 bool is_srgb_valid = FALSE;
2240 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2241 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2242
2243 int i;
2244 const uint32_t sign_bit[4] = {
2245 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2246 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2247 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2248 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2249 };
2250 desc = util_format_description(format);
2251
2252 /* Depth and stencil swizzling is handled separately. */
2253 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2254 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2255 }
2256
2257 /* Colorspace (return non-RGB formats directly). */
2258 switch (desc->colorspace) {
2259 /* Depth stencil formats */
2260 case UTIL_FORMAT_COLORSPACE_ZS:
2261 switch (format) {
2262 /* Depth sampler formats. */
2263 case PIPE_FORMAT_Z16_UNORM:
2264 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2265 result = FMT_16;
2266 goto out_word4;
2267 case PIPE_FORMAT_Z24X8_UNORM:
2268 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2269 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2270 result = FMT_8_24;
2271 goto out_word4;
2272 case PIPE_FORMAT_X8Z24_UNORM:
2273 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2274 if (rscreen->b.chip_class < EVERGREEN)
2275 goto out_unknown;
2276 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2277 result = FMT_24_8;
2278 goto out_word4;
2279 case PIPE_FORMAT_Z32_FLOAT:
2280 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2281 result = FMT_32_FLOAT;
2282 goto out_word4;
2283 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2284 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2285 result = FMT_X24_8_32_FLOAT;
2286 goto out_word4;
2287 /* Stencil sampler formats. */
2288 case PIPE_FORMAT_S8_UINT:
2289 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2290 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2291 result = FMT_8;
2292 goto out_word4;
2293 case PIPE_FORMAT_X24S8_UINT:
2294 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2295 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2296 result = FMT_8_24;
2297 goto out_word4;
2298 case PIPE_FORMAT_S8X24_UINT:
2299 if (rscreen->b.chip_class < EVERGREEN)
2300 goto out_unknown;
2301 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2302 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2303 result = FMT_24_8;
2304 goto out_word4;
2305 case PIPE_FORMAT_X32_S8X24_UINT:
2306 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2307 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2308 result = FMT_X24_8_32_FLOAT;
2309 goto out_word4;
2310 default:
2311 goto out_unknown;
2312 }
2313
2314 case UTIL_FORMAT_COLORSPACE_YUV:
2315 yuv_format |= (1 << 30);
2316 switch (format) {
2317 case PIPE_FORMAT_UYVY:
2318 case PIPE_FORMAT_YUYV:
2319 default:
2320 break;
2321 }
2322 goto out_unknown; /* XXX */
2323
2324 case UTIL_FORMAT_COLORSPACE_SRGB:
2325 word4 |= S_038010_FORCE_DEGAMMA(1);
2326 break;
2327
2328 default:
2329 break;
2330 }
2331
2332 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2333 if (!enable_s3tc)
2334 goto out_unknown;
2335
2336 switch (format) {
2337 case PIPE_FORMAT_RGTC1_SNORM:
2338 case PIPE_FORMAT_LATC1_SNORM:
2339 word4 |= sign_bit[0];
2340 case PIPE_FORMAT_RGTC1_UNORM:
2341 case PIPE_FORMAT_LATC1_UNORM:
2342 result = FMT_BC4;
2343 goto out_word4;
2344 case PIPE_FORMAT_RGTC2_SNORM:
2345 case PIPE_FORMAT_LATC2_SNORM:
2346 word4 |= sign_bit[0] | sign_bit[1];
2347 case PIPE_FORMAT_RGTC2_UNORM:
2348 case PIPE_FORMAT_LATC2_UNORM:
2349 result = FMT_BC5;
2350 goto out_word4;
2351 default:
2352 goto out_unknown;
2353 }
2354 }
2355
2356 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2357
2358 if (!enable_s3tc)
2359 goto out_unknown;
2360
2361 if (!util_format_s3tc_enabled) {
2362 goto out_unknown;
2363 }
2364
2365 switch (format) {
2366 case PIPE_FORMAT_DXT1_RGB:
2367 case PIPE_FORMAT_DXT1_RGBA:
2368 case PIPE_FORMAT_DXT1_SRGB:
2369 case PIPE_FORMAT_DXT1_SRGBA:
2370 result = FMT_BC1;
2371 is_srgb_valid = TRUE;
2372 goto out_word4;
2373 case PIPE_FORMAT_DXT3_RGBA:
2374 case PIPE_FORMAT_DXT3_SRGBA:
2375 result = FMT_BC2;
2376 is_srgb_valid = TRUE;
2377 goto out_word4;
2378 case PIPE_FORMAT_DXT5_RGBA:
2379 case PIPE_FORMAT_DXT5_SRGBA:
2380 result = FMT_BC3;
2381 is_srgb_valid = TRUE;
2382 goto out_word4;
2383 default:
2384 goto out_unknown;
2385 }
2386 }
2387
2388 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2389 if (!enable_s3tc)
2390 goto out_unknown;
2391
2392 if (rscreen->b.chip_class < EVERGREEN)
2393 goto out_unknown;
2394
2395 switch (format) {
2396 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2397 case PIPE_FORMAT_BPTC_SRGBA:
2398 result = FMT_BC7;
2399 is_srgb_valid = TRUE;
2400 goto out_word4;
2401 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2402 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2403 /* fall through */
2404 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2405 result = FMT_BC6;
2406 goto out_word4;
2407 default:
2408 goto out_unknown;
2409 }
2410 }
2411
2412 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2413 switch (format) {
2414 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2415 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2416 result = FMT_GB_GR;
2417 goto out_word4;
2418 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2419 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2420 result = FMT_BG_RG;
2421 goto out_word4;
2422 default:
2423 goto out_unknown;
2424 }
2425 }
2426
2427 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2428 result = FMT_5_9_9_9_SHAREDEXP;
2429 goto out_word4;
2430 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2431 result = FMT_10_11_11_FLOAT;
2432 goto out_word4;
2433 }
2434
2435
2436 for (i = 0; i < desc->nr_channels; i++) {
2437 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2438 word4 |= sign_bit[i];
2439 }
2440 }
2441
2442 /* R8G8Bx_SNORM - XXX CxV8U8 */
2443
2444 /* See whether the components are of the same size. */
2445 for (i = 1; i < desc->nr_channels; i++) {
2446 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2447 }
2448
2449 /* Non-uniform formats. */
2450 if (!uniform) {
2451 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2452 desc->channel[0].pure_integer)
2453 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2454 switch(desc->nr_channels) {
2455 case 3:
2456 if (desc->channel[0].size == 5 &&
2457 desc->channel[1].size == 6 &&
2458 desc->channel[2].size == 5) {
2459 result = FMT_5_6_5;
2460 goto out_word4;
2461 }
2462 goto out_unknown;
2463 case 4:
2464 if (desc->channel[0].size == 5 &&
2465 desc->channel[1].size == 5 &&
2466 desc->channel[2].size == 5 &&
2467 desc->channel[3].size == 1) {
2468 result = FMT_1_5_5_5;
2469 goto out_word4;
2470 }
2471 if (desc->channel[0].size == 10 &&
2472 desc->channel[1].size == 10 &&
2473 desc->channel[2].size == 10 &&
2474 desc->channel[3].size == 2) {
2475 result = FMT_2_10_10_10;
2476 goto out_word4;
2477 }
2478 goto out_unknown;
2479 }
2480 goto out_unknown;
2481 }
2482
2483 /* Find the first non-VOID channel. */
2484 for (i = 0; i < 4; i++) {
2485 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2486 break;
2487 }
2488 }
2489
2490 if (i == 4)
2491 goto out_unknown;
2492
2493 /* uniform formats */
2494 switch (desc->channel[i].type) {
2495 case UTIL_FORMAT_TYPE_UNSIGNED:
2496 case UTIL_FORMAT_TYPE_SIGNED:
2497 #if 0
2498 if (!desc->channel[i].normalized &&
2499 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2500 goto out_unknown;
2501 }
2502 #endif
2503 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2504 desc->channel[i].pure_integer)
2505 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2506
2507 switch (desc->channel[i].size) {
2508 case 4:
2509 switch (desc->nr_channels) {
2510 case 2:
2511 result = FMT_4_4;
2512 goto out_word4;
2513 case 4:
2514 result = FMT_4_4_4_4;
2515 goto out_word4;
2516 }
2517 goto out_unknown;
2518 case 8:
2519 switch (desc->nr_channels) {
2520 case 1:
2521 result = FMT_8;
2522 goto out_word4;
2523 case 2:
2524 result = FMT_8_8;
2525 goto out_word4;
2526 case 4:
2527 result = FMT_8_8_8_8;
2528 is_srgb_valid = TRUE;
2529 goto out_word4;
2530 }
2531 goto out_unknown;
2532 case 16:
2533 switch (desc->nr_channels) {
2534 case 1:
2535 result = FMT_16;
2536 goto out_word4;
2537 case 2:
2538 result = FMT_16_16;
2539 goto out_word4;
2540 case 4:
2541 result = FMT_16_16_16_16;
2542 goto out_word4;
2543 }
2544 goto out_unknown;
2545 case 32:
2546 switch (desc->nr_channels) {
2547 case 1:
2548 result = FMT_32;
2549 goto out_word4;
2550 case 2:
2551 result = FMT_32_32;
2552 goto out_word4;
2553 case 4:
2554 result = FMT_32_32_32_32;
2555 goto out_word4;
2556 }
2557 }
2558 goto out_unknown;
2559
2560 case UTIL_FORMAT_TYPE_FLOAT:
2561 switch (desc->channel[i].size) {
2562 case 16:
2563 switch (desc->nr_channels) {
2564 case 1:
2565 result = FMT_16_FLOAT;
2566 goto out_word4;
2567 case 2:
2568 result = FMT_16_16_FLOAT;
2569 goto out_word4;
2570 case 4:
2571 result = FMT_16_16_16_16_FLOAT;
2572 goto out_word4;
2573 }
2574 goto out_unknown;
2575 case 32:
2576 switch (desc->nr_channels) {
2577 case 1:
2578 result = FMT_32_FLOAT;
2579 goto out_word4;
2580 case 2:
2581 result = FMT_32_32_FLOAT;
2582 goto out_word4;
2583 case 4:
2584 result = FMT_32_32_32_32_FLOAT;
2585 goto out_word4;
2586 }
2587 }
2588 goto out_unknown;
2589 }
2590
2591 out_word4:
2592
2593 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2594 return ~0;
2595 if (word4_p)
2596 *word4_p = word4;
2597 if (yuv_format_p)
2598 *yuv_format_p = yuv_format;
2599 return result;
2600 out_unknown:
2601 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2602 return ~0;
2603 }
2604
2605 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format)
2606 {
2607 const struct util_format_description *desc = util_format_description(format);
2608 int channel = util_format_get_first_non_void_channel(format);
2609 bool is_float;
2610
2611 #define HAS_SIZE(x,y,z,w) \
2612 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2613 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2614
2615 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2616 return V_0280A0_COLOR_10_11_11_FLOAT;
2617
2618 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2619 channel == -1)
2620 return ~0U;
2621
2622 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2623
2624 switch (desc->nr_channels) {
2625 case 1:
2626 switch (desc->channel[0].size) {
2627 case 8:
2628 return V_0280A0_COLOR_8;
2629 case 16:
2630 if (is_float)
2631 return V_0280A0_COLOR_16_FLOAT;
2632 else
2633 return V_0280A0_COLOR_16;
2634 case 32:
2635 if (is_float)
2636 return V_0280A0_COLOR_32_FLOAT;
2637 else
2638 return V_0280A0_COLOR_32;
2639 }
2640 break;
2641 case 2:
2642 if (desc->channel[0].size == desc->channel[1].size) {
2643 switch (desc->channel[0].size) {
2644 case 4:
2645 if (chip <= R700)
2646 return V_0280A0_COLOR_4_4;
2647 else
2648 return ~0U; /* removed on Evergreen */
2649 case 8:
2650 return V_0280A0_COLOR_8_8;
2651 case 16:
2652 if (is_float)
2653 return V_0280A0_COLOR_16_16_FLOAT;
2654 else
2655 return V_0280A0_COLOR_16_16;
2656 case 32:
2657 if (is_float)
2658 return V_0280A0_COLOR_32_32_FLOAT;
2659 else
2660 return V_0280A0_COLOR_32_32;
2661 }
2662 } else if (HAS_SIZE(8,24,0,0)) {
2663 return V_0280A0_COLOR_24_8;
2664 } else if (HAS_SIZE(24,8,0,0)) {
2665 return V_0280A0_COLOR_8_24;
2666 }
2667 break;
2668 case 3:
2669 if (HAS_SIZE(5,6,5,0)) {
2670 return V_0280A0_COLOR_5_6_5;
2671 } else if (HAS_SIZE(32,8,24,0)) {
2672 return V_0280A0_COLOR_X24_8_32_FLOAT;
2673 }
2674 break;
2675 case 4:
2676 if (desc->channel[0].size == desc->channel[1].size &&
2677 desc->channel[0].size == desc->channel[2].size &&
2678 desc->channel[0].size == desc->channel[3].size) {
2679 switch (desc->channel[0].size) {
2680 case 4:
2681 return V_0280A0_COLOR_4_4_4_4;
2682 case 8:
2683 return V_0280A0_COLOR_8_8_8_8;
2684 case 16:
2685 if (is_float)
2686 return V_0280A0_COLOR_16_16_16_16_FLOAT;
2687 else
2688 return V_0280A0_COLOR_16_16_16_16;
2689 case 32:
2690 if (is_float)
2691 return V_0280A0_COLOR_32_32_32_32_FLOAT;
2692 else
2693 return V_0280A0_COLOR_32_32_32_32;
2694 }
2695 } else if (HAS_SIZE(5,5,5,1)) {
2696 return V_0280A0_COLOR_1_5_5_5;
2697 } else if (HAS_SIZE(10,10,10,2)) {
2698 return V_0280A0_COLOR_2_10_10_10;
2699 }
2700 break;
2701 }
2702 return ~0U;
2703 }
2704
2705 uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
2706 {
2707 if (R600_BIG_ENDIAN) {
2708 switch(colorformat) {
2709 /* 8-bit buffers. */
2710 case V_0280A0_COLOR_4_4:
2711 case V_0280A0_COLOR_8:
2712 return ENDIAN_NONE;
2713
2714 /* 16-bit buffers. */
2715 case V_0280A0_COLOR_5_6_5:
2716 case V_0280A0_COLOR_1_5_5_5:
2717 case V_0280A0_COLOR_4_4_4_4:
2718 case V_0280A0_COLOR_16:
2719 case V_0280A0_COLOR_8_8:
2720 return ENDIAN_8IN16;
2721
2722 /* 32-bit buffers. */
2723 case V_0280A0_COLOR_8_8_8_8:
2724 case V_0280A0_COLOR_2_10_10_10:
2725 case V_0280A0_COLOR_8_24:
2726 case V_0280A0_COLOR_24_8:
2727 case V_0280A0_COLOR_32_FLOAT:
2728 case V_0280A0_COLOR_16_16_FLOAT:
2729 case V_0280A0_COLOR_16_16:
2730 return ENDIAN_8IN32;
2731
2732 /* 64-bit buffers. */
2733 case V_0280A0_COLOR_16_16_16_16:
2734 case V_0280A0_COLOR_16_16_16_16_FLOAT:
2735 return ENDIAN_8IN16;
2736
2737 case V_0280A0_COLOR_32_32_FLOAT:
2738 case V_0280A0_COLOR_32_32:
2739 case V_0280A0_COLOR_X24_8_32_FLOAT:
2740 return ENDIAN_8IN32;
2741
2742 /* 128-bit buffers. */
2743 case V_0280A0_COLOR_32_32_32_32_FLOAT:
2744 case V_0280A0_COLOR_32_32_32_32:
2745 return ENDIAN_8IN32;
2746 default:
2747 return ENDIAN_NONE; /* Unsupported. */
2748 }
2749 } else {
2750 return ENDIAN_NONE;
2751 }
2752 }
2753
2754 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2755 {
2756 struct r600_context *rctx = (struct r600_context*)ctx;
2757 struct r600_resource *rbuffer = r600_resource(buf);
2758 unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
2759 struct r600_pipe_sampler_view *view;
2760
2761 /* Reallocate the buffer in the same pipe_resource. */
2762 r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0,
2763 alignment, TRUE);
2764
2765 /* We changed the buffer, now we need to bind it where the old one was bound. */
2766 /* Vertex buffers. */
2767 mask = rctx->vertex_buffer_state.enabled_mask;
2768 while (mask) {
2769 i = u_bit_scan(&mask);
2770 if (rctx->vertex_buffer_state.vb[i].buffer == &rbuffer->b.b) {
2771 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2772 r600_vertex_buffers_dirty(rctx);
2773 }
2774 }
2775 /* Streamout buffers. */
2776 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2777 if (rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2778 if (rctx->b.streamout.begin_emitted) {
2779 r600_emit_streamout_end(&rctx->b);
2780 }
2781 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2782 r600_streamout_buffers_dirty(&rctx->b);
2783 }
2784 }
2785
2786 /* Constant buffers. */
2787 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2788 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2789 bool found = false;
2790 uint32_t mask = state->enabled_mask;
2791
2792 while (mask) {
2793 unsigned i = u_bit_scan(&mask);
2794 if (state->cb[i].buffer == &rbuffer->b.b) {
2795 found = true;
2796 state->dirty_mask |= 1 << i;
2797 }
2798 }
2799 if (found) {
2800 r600_constant_buffers_dirty(rctx, state);
2801 }
2802 }
2803
2804 /* Texture buffer objects - update the virtual addresses in descriptors. */
2805 LIST_FOR_EACH_ENTRY(view, &rctx->b.texture_buffers, list) {
2806 if (view->base.texture == &rbuffer->b.b) {
2807 unsigned stride = util_format_get_blocksize(view->base.format);
2808 uint64_t offset = (uint64_t)view->base.u.buf.first_element * stride;
2809 uint64_t va = rbuffer->gpu_address + offset;
2810
2811 view->tex_resource_words[0] = va;
2812 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
2813 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
2814 }
2815 }
2816 /* Texture buffer objects - make bindings dirty if needed. */
2817 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2818 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
2819 bool found = false;
2820 uint32_t mask = state->enabled_mask;
2821
2822 while (mask) {
2823 unsigned i = u_bit_scan(&mask);
2824 if (state->views[i]->base.texture == &rbuffer->b.b) {
2825 found = true;
2826 state->dirty_mask |= 1 << i;
2827 }
2828 }
2829 if (found) {
2830 r600_sampler_views_dirty(rctx, state);
2831 }
2832 }
2833 }
2834
2835 static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2836 {
2837 struct r600_context *rctx = (struct r600_context*)ctx;
2838
2839 if (rctx->db_misc_state.occlusion_query_enabled != enable) {
2840 rctx->db_misc_state.occlusion_query_enabled = enable;
2841 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2842 }
2843 }
2844
2845 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2846 bool include_draw_vbo)
2847 {
2848 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
2849 }
2850
2851 /* keep this at the end of this file, please */
2852 void r600_init_common_state_functions(struct r600_context *rctx)
2853 {
2854 rctx->b.b.create_fs_state = r600_create_ps_state;
2855 rctx->b.b.create_vs_state = r600_create_vs_state;
2856 rctx->b.b.create_gs_state = r600_create_gs_state;
2857 rctx->b.b.create_tcs_state = r600_create_tcs_state;
2858 rctx->b.b.create_tes_state = r600_create_tes_state;
2859 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2860 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2861 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2862 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2863 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2864 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2865 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2866 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2867 rctx->b.b.bind_gs_state = r600_bind_gs_state;
2868 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
2869 rctx->b.b.bind_tes_state = r600_bind_tes_state;
2870 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2871 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2872 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2873 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2874 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2875 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2876 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2877 rctx->b.b.delete_gs_state = r600_delete_gs_state;
2878 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
2879 rctx->b.b.delete_tes_state = r600_delete_tes_state;
2880 rctx->b.b.set_blend_color = r600_set_blend_color;
2881 rctx->b.b.set_clip_state = r600_set_clip_state;
2882 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2883 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2884 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2885 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2886 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2887 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2888 rctx->b.b.set_sampler_views = r600_set_sampler_views;
2889 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2890 rctx->b.b.texture_barrier = r600_texture_barrier;
2891 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2892 rctx->b.b.draw_vbo = r600_draw_vbo;
2893 rctx->b.invalidate_buffer = r600_invalidate_buffer;
2894 rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
2895 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
2896 }
2897
2898 void r600_trace_emit(struct r600_context *rctx)
2899 {
2900 struct r600_screen *rscreen = rctx->screen;
2901 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2902 uint64_t va;
2903 uint32_t reloc;
2904
2905 va = rscreen->b.trace_bo->gpu_address;
2906 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rscreen->b.trace_bo,
2907 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
2908 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2909 radeon_emit(cs, va & 0xFFFFFFFFUL);
2910 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2911 radeon_emit(cs, cs->cdw);
2912 radeon_emit(cs, rscreen->b.cs_count);
2913 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2914 radeon_emit(cs, reloc);
2915 }