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r600g: implement timestamp query and get_timestamp hook
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
36 {
37 struct radeon_winsys_cs *cs = rctx->cs;
38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
39
40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
42 cs->cdw += cb->atom.num_dw;
43 }
44
45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
46 {
47 cb->atom.emit = r600_emit_command_buffer;
48 cb->atom.num_dw = 0;
49 cb->atom.flags = flags;
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
60 {
61 struct radeon_winsys_cs *cs = rctx->cs;
62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
63
64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
69
70 a->flush_flags = 0;
71 }
72
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 struct radeon_winsys_cs *cs = rctx->cs;
76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
78 }
79
80 void r600_init_atom(struct r600_atom *atom,
81 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
82 unsigned num_dw, enum r600_atom_flags flags)
83 {
84 atom->emit = emit;
85 atom->num_dw = num_dw;
86 atom->flags = flags;
87 }
88
89 static void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
90 {
91 struct radeon_winsys_cs *cs = rctx->cs;
92 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
93 unsigned alpha_ref = a->sx_alpha_ref;
94
95 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
96 alpha_ref &= ~0x1FFF;
97 }
98
99 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
100 a->sx_alpha_test_control |
101 S_028410_ALPHA_TEST_BYPASS(a->bypass));
102 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
103 }
104
105 void r600_init_common_atoms(struct r600_context *rctx)
106 {
107 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
108 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
109 r600_init_atom(&rctx->alphatest_state.atom, r600_emit_alphatest_state, 3, 0);
110 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
111 }
112
113 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
114 {
115 unsigned flags = 0;
116
117 if (rctx->framebuffer.nr_cbufs) {
118 flags |= S_0085F0_CB_ACTION_ENA(1) |
119 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
120 }
121
122 /* Workaround for broken flushing on some R6xx chipsets. */
123 if (rctx->family == CHIP_RV670 ||
124 rctx->family == CHIP_RS780 ||
125 rctx->family == CHIP_RS880) {
126 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
127 S_0085F0_DEST_BASE_0_ENA(1);
128 }
129 return flags;
130 }
131
132 void r600_texture_barrier(struct pipe_context *ctx)
133 {
134 struct r600_context *rctx = (struct r600_context *)ctx;
135
136 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
137 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
138 }
139
140 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
141 {
142 static const int prim_conv[] = {
143 V_008958_DI_PT_POINTLIST,
144 V_008958_DI_PT_LINELIST,
145 V_008958_DI_PT_LINELOOP,
146 V_008958_DI_PT_LINESTRIP,
147 V_008958_DI_PT_TRILIST,
148 V_008958_DI_PT_TRISTRIP,
149 V_008958_DI_PT_TRIFAN,
150 V_008958_DI_PT_QUADLIST,
151 V_008958_DI_PT_QUADSTRIP,
152 V_008958_DI_PT_POLYGON,
153 -1,
154 -1,
155 -1,
156 -1
157 };
158
159 *prim = prim_conv[pprim];
160 if (*prim == -1) {
161 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
162 return false;
163 }
164 return true;
165 }
166
167 /* common state between evergreen and r600 */
168 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
169 {
170 struct r600_context *rctx = (struct r600_context *)ctx;
171 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
172 struct r600_pipe_state *rstate;
173 bool update_cb = false;
174
175 if (state == NULL)
176 return;
177 rstate = &blend->rstate;
178 rctx->states[rstate->id] = rstate;
179 rctx->dual_src_blend = blend->dual_src_blend;
180 rctx->alpha_to_one = blend->alpha_to_one;
181 r600_context_pipe_state_set(rctx, rstate);
182
183 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
184 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
185 update_cb = true;
186 }
187 if (rctx->chip_class <= R700 &&
188 rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
189 rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
190 update_cb = true;
191 }
192 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
193 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
194 update_cb = true;
195 }
196 if (update_cb) {
197 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
198 }
199 }
200
201 void r600_set_blend_color(struct pipe_context *ctx,
202 const struct pipe_blend_color *state)
203 {
204 struct r600_context *rctx = (struct r600_context *)ctx;
205 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
206
207 if (rstate == NULL)
208 return;
209
210 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
211 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
212 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
213 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
214 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
215
216 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
217 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
218 r600_context_pipe_state_set(rctx, rstate);
219 }
220
221 static void r600_set_stencil_ref(struct pipe_context *ctx,
222 const struct r600_stencil_ref *state)
223 {
224 struct r600_context *rctx = (struct r600_context *)ctx;
225 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
226
227 if (rstate == NULL)
228 return;
229
230 rstate->id = R600_PIPE_STATE_STENCIL_REF;
231 r600_pipe_state_add_reg(rstate,
232 R_028430_DB_STENCILREFMASK,
233 S_028430_STENCILREF(state->ref_value[0]) |
234 S_028430_STENCILMASK(state->valuemask[0]) |
235 S_028430_STENCILWRITEMASK(state->writemask[0]));
236 r600_pipe_state_add_reg(rstate,
237 R_028434_DB_STENCILREFMASK_BF,
238 S_028434_STENCILREF_BF(state->ref_value[1]) |
239 S_028434_STENCILMASK_BF(state->valuemask[1]) |
240 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
241
242 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
243 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
244 r600_context_pipe_state_set(rctx, rstate);
245 }
246
247 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
248 const struct pipe_stencil_ref *state)
249 {
250 struct r600_context *rctx = (struct r600_context *)ctx;
251 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
252 struct r600_stencil_ref ref;
253
254 rctx->stencil_ref = *state;
255
256 if (!dsa)
257 return;
258
259 ref.ref_value[0] = state->ref_value[0];
260 ref.ref_value[1] = state->ref_value[1];
261 ref.valuemask[0] = dsa->valuemask[0];
262 ref.valuemask[1] = dsa->valuemask[1];
263 ref.writemask[0] = dsa->writemask[0];
264 ref.writemask[1] = dsa->writemask[1];
265
266 r600_set_stencil_ref(ctx, &ref);
267 }
268
269 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
270 {
271 struct r600_context *rctx = (struct r600_context *)ctx;
272 struct r600_pipe_dsa *dsa = state;
273 struct r600_pipe_state *rstate;
274 struct r600_stencil_ref ref;
275
276 if (state == NULL)
277 return;
278 rstate = &dsa->rstate;
279 rctx->states[rstate->id] = rstate;
280 r600_context_pipe_state_set(rctx, rstate);
281
282 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
283 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
284 ref.valuemask[0] = dsa->valuemask[0];
285 ref.valuemask[1] = dsa->valuemask[1];
286 ref.writemask[0] = dsa->writemask[0];
287 ref.writemask[1] = dsa->writemask[1];
288
289 r600_set_stencil_ref(ctx, &ref);
290
291 /* Update alphatest state. */
292 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
293 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
294 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
295 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
296 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
297 }
298 }
299
300 void r600_set_max_scissor(struct r600_context *rctx)
301 {
302 /* Set a scissor state such that it doesn't do anything. */
303 struct pipe_scissor_state scissor;
304 scissor.minx = 0;
305 scissor.miny = 0;
306 scissor.maxx = 8192;
307 scissor.maxy = 8192;
308
309 r600_set_scissor_state(rctx, &scissor);
310 }
311
312 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
313 {
314 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
315 struct r600_context *rctx = (struct r600_context *)ctx;
316
317 if (state == NULL)
318 return;
319
320 rctx->sprite_coord_enable = rs->sprite_coord_enable;
321 rctx->two_side = rs->two_side;
322 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
323 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
324 rctx->multisample_enable = rs->multisample_enable;
325
326 rctx->rasterizer = rs;
327
328 rctx->states[rs->rstate.id] = &rs->rstate;
329 r600_context_pipe_state_set(rctx, &rs->rstate);
330
331 if (rctx->chip_class >= EVERGREEN) {
332 evergreen_polygon_offset_update(rctx);
333 } else {
334 r600_polygon_offset_update(rctx);
335 }
336
337 /* Workaround for a missing scissor enable on r600. */
338 if (rctx->chip_class == R600) {
339 if (rs->scissor_enable != rctx->scissor_enable) {
340 rctx->scissor_enable = rs->scissor_enable;
341
342 if (rs->scissor_enable) {
343 r600_set_scissor_state(rctx, &rctx->scissor_state);
344 } else {
345 r600_set_max_scissor(rctx);
346 }
347 }
348 }
349 }
350
351 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
352 {
353 struct r600_context *rctx = (struct r600_context *)ctx;
354 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
355
356 if (rctx->rasterizer == rs) {
357 rctx->rasterizer = NULL;
358 }
359 if (rctx->states[rs->rstate.id] == &rs->rstate) {
360 rctx->states[rs->rstate.id] = NULL;
361 }
362 free(rs);
363 }
364
365 void r600_sampler_view_destroy(struct pipe_context *ctx,
366 struct pipe_sampler_view *state)
367 {
368 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
369
370 pipe_resource_reference(&state->texture, NULL);
371 FREE(resource);
372 }
373
374 static void r600_bind_samplers(struct r600_context *rctx,
375 struct r600_textures_info *dst,
376 unsigned count, void **states)
377 {
378 int seamless_cube_map = -1;
379 unsigned i;
380
381 memcpy(dst->samplers, states, sizeof(void*) * count);
382 dst->n_samplers = count;
383 dst->atom_sampler.num_dw = 0;
384
385 for (i = 0; i < count; i++) {
386 struct r600_pipe_sampler_state *sampler = states[i];
387
388 if (sampler == NULL) {
389 continue;
390 }
391 if (sampler->border_color_use) {
392 dst->atom_sampler.num_dw += 11;
393 rctx->flags |= R600_PARTIAL_FLUSH;
394 } else {
395 dst->atom_sampler.num_dw += 5;
396 }
397 seamless_cube_map = sampler->seamless_cube_map;
398 }
399 if (rctx->chip_class <= R700 && seamless_cube_map != -1 && seamless_cube_map != rctx->seamless_cube_map.enabled) {
400 /* change in TA_CNTL_AUX need a pipeline flush */
401 rctx->flags |= R600_PARTIAL_FLUSH;
402 rctx->seamless_cube_map.enabled = seamless_cube_map;
403 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
404 }
405 if (dst->atom_sampler.num_dw) {
406 r600_atom_dirty(rctx, &dst->atom_sampler);
407 }
408 }
409
410 void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
411 {
412 struct r600_context *rctx = (struct r600_context *)ctx;
413 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
414 }
415
416 void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
417 {
418 struct r600_context *rctx = (struct r600_context *)ctx;
419 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
420 }
421
422 void r600_delete_sampler(struct pipe_context *ctx, void *state)
423 {
424 free(state);
425 }
426
427 void r600_delete_state(struct pipe_context *ctx, void *state)
428 {
429 struct r600_context *rctx = (struct r600_context *)ctx;
430 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
431
432 if (rctx->states[rstate->id] == rstate) {
433 rctx->states[rstate->id] = NULL;
434 }
435 for (int i = 0; i < rstate->nregs; i++) {
436 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
437 }
438 free(rstate);
439 }
440
441 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
442 {
443 struct r600_context *rctx = (struct r600_context *)ctx;
444 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
445
446 rctx->vertex_elements = v;
447 if (v) {
448 r600_inval_shader_cache(rctx);
449
450 rctx->states[v->rstate.id] = &v->rstate;
451 r600_context_pipe_state_set(rctx, &v->rstate);
452 }
453 }
454
455 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
456 {
457 struct r600_context *rctx = (struct r600_context *)ctx;
458 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
459
460 if (rctx->states[v->rstate.id] == &v->rstate) {
461 rctx->states[v->rstate.id] = NULL;
462 }
463 if (rctx->vertex_elements == state)
464 rctx->vertex_elements = NULL;
465
466 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
467 FREE(state);
468 }
469
470 void r600_set_index_buffer(struct pipe_context *ctx,
471 const struct pipe_index_buffer *ib)
472 {
473 struct r600_context *rctx = (struct r600_context *)ctx;
474
475 if (ib) {
476 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
477 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
478 } else {
479 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
480 }
481 }
482
483 void r600_vertex_buffers_dirty(struct r600_context *rctx)
484 {
485 if (rctx->vertex_buffer_state.dirty_mask) {
486 r600_inval_vertex_cache(rctx);
487 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
488 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
489 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
490 }
491 }
492
493 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
494 const struct pipe_vertex_buffer *input)
495 {
496 struct r600_context *rctx = (struct r600_context *)ctx;
497 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
498 struct pipe_vertex_buffer *vb = state->vb;
499 unsigned i;
500 /* This sets 1-bit for buffers with index >= count. */
501 uint32_t disable_mask = ~((1ull << count) - 1);
502 /* These are the new buffers set by this function. */
503 uint32_t new_buffer_mask = 0;
504
505 /* Set buffers with index >= count to NULL. */
506 uint32_t remaining_buffers_mask =
507 rctx->vertex_buffer_state.enabled_mask & disable_mask;
508
509 while (remaining_buffers_mask) {
510 i = u_bit_scan(&remaining_buffers_mask);
511 pipe_resource_reference(&vb[i].buffer, NULL);
512 }
513
514 /* Set vertex buffers. */
515 for (i = 0; i < count; i++) {
516 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
517 if (input[i].buffer) {
518 vb[i].stride = input[i].stride;
519 vb[i].buffer_offset = input[i].buffer_offset;
520 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
521 new_buffer_mask |= 1 << i;
522 } else {
523 pipe_resource_reference(&vb[i].buffer, NULL);
524 disable_mask |= 1 << i;
525 }
526 }
527 }
528
529 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
530 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
531 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
532 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
533
534 r600_vertex_buffers_dirty(rctx);
535 }
536
537 void r600_sampler_views_dirty(struct r600_context *rctx,
538 struct r600_samplerview_state *state)
539 {
540 if (state->dirty_mask) {
541 r600_inval_texture_cache(rctx);
542 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
543 util_bitcount(state->dirty_mask);
544 r600_atom_dirty(rctx, &state->atom);
545 }
546 }
547
548 void r600_set_sampler_views(struct r600_context *rctx,
549 struct r600_textures_info *dst,
550 unsigned count,
551 struct pipe_sampler_view **views)
552 {
553 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
554 unsigned i;
555 /* This sets 1-bit for textures with index >= count. */
556 uint32_t disable_mask = ~((1ull << count) - 1);
557 /* These are the new textures set by this function. */
558 uint32_t new_mask = 0;
559
560 /* Set textures with index >= count to NULL. */
561 uint32_t remaining_mask = dst->views.enabled_mask & disable_mask;
562
563 while (remaining_mask) {
564 i = u_bit_scan(&remaining_mask);
565 assert(dst->views.views[i]);
566
567 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
568 }
569
570 for (i = 0; i < count; i++) {
571 if (rviews[i] == dst->views.views[i]) {
572 continue;
573 }
574
575 if (rviews[i]) {
576 struct r600_resource_texture *rtex =
577 (struct r600_resource_texture*)rviews[i]->base.texture;
578
579 if (rtex->is_depth && !rtex->is_flushing_texture) {
580 dst->views.depth_texture_mask |= 1 << i;
581 } else {
582 dst->views.depth_texture_mask &= ~(1 << i);
583 }
584
585 /* Changing from array to non-arrays textures and vice
586 * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */
587 if (rctx->chip_class <= R700 &&
588 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
589 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
590 r600_atom_dirty(rctx, &dst->atom_sampler);
591 }
592
593 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
594 new_mask |= 1 << i;
595 } else {
596 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
597 disable_mask |= 1 << i;
598 }
599 }
600
601 dst->views.enabled_mask &= ~disable_mask;
602 dst->views.dirty_mask &= dst->views.enabled_mask;
603 dst->views.enabled_mask |= new_mask;
604 dst->views.dirty_mask |= new_mask;
605 dst->views.depth_texture_mask &= dst->views.enabled_mask;
606
607 r600_sampler_views_dirty(rctx, &dst->views);
608 }
609
610 void *r600_create_vertex_elements(struct pipe_context *ctx,
611 unsigned count,
612 const struct pipe_vertex_element *elements)
613 {
614 struct r600_context *rctx = (struct r600_context *)ctx;
615 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
616
617 assert(count < 32);
618 if (!v)
619 return NULL;
620
621 v->count = count;
622 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
623
624 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
625 FREE(v);
626 return NULL;
627 }
628
629 return v;
630 }
631
632 /* Compute the key for the hw shader variant */
633 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
634 struct r600_pipe_shader_selector * sel)
635 {
636 struct r600_context *rctx = (struct r600_context *)ctx;
637 unsigned key;
638
639 if (sel->type == PIPE_SHADER_FRAGMENT) {
640 key = rctx->two_side |
641 ((rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer) << 1) |
642 (MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 2);
643 } else
644 key = 0;
645
646 return key;
647 }
648
649 /* Select the hw shader variant depending on the current state.
650 * (*dirty) is set to 1 if current variant was changed */
651 static int r600_shader_select(struct pipe_context *ctx,
652 struct r600_pipe_shader_selector* sel,
653 unsigned *dirty)
654 {
655 unsigned key;
656 struct r600_context *rctx = (struct r600_context *)ctx;
657 struct r600_pipe_shader * shader = NULL;
658 int r;
659
660 key = r600_shader_selector_key(ctx, sel);
661
662 /* Check if we don't need to change anything.
663 * This path is also used for most shaders that don't need multiple
664 * variants, it will cost just a computation of the key and this
665 * test. */
666 if (likely(sel->current && sel->current->key == key)) {
667 return 0;
668 }
669
670 /* lookup if we have other variants in the list */
671 if (sel->num_shaders > 1) {
672 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
673
674 while (c && c->key != key) {
675 p = c;
676 c = c->next_variant;
677 }
678
679 if (c) {
680 p->next_variant = c->next_variant;
681 shader = c;
682 }
683 }
684
685 if (unlikely(!shader)) {
686 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
687 shader->selector = sel;
688
689 r = r600_pipe_shader_create(ctx, shader);
690 if (unlikely(r)) {
691 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
692 sel->type, key, r);
693 sel->current = NULL;
694 return r;
695 }
696
697 /* We don't know the value of nr_ps_max_color_exports until we built
698 * at least one variant, so we may need to recompute the key after
699 * building first variant. */
700 if (sel->type == PIPE_SHADER_FRAGMENT &&
701 sel->num_shaders == 0) {
702 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
703 key = r600_shader_selector_key(ctx, sel);
704 }
705
706 shader->key = key;
707 sel->num_shaders++;
708 }
709
710 if (dirty)
711 *dirty = 1;
712
713 shader->next_variant = sel->current;
714 sel->current = shader;
715
716 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
717 r600_adjust_gprs(rctx);
718 }
719
720 if (rctx->ps_shader &&
721 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
722 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
723 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
724 }
725 return 0;
726 }
727
728 static void *r600_create_shader_state(struct pipe_context *ctx,
729 const struct pipe_shader_state *state,
730 unsigned pipe_shader_type)
731 {
732 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
733 int r;
734
735 sel->type = pipe_shader_type;
736 sel->tokens = tgsi_dup_tokens(state->tokens);
737 sel->so = state->stream_output;
738
739 r = r600_shader_select(ctx, sel, NULL);
740 if (r)
741 return NULL;
742
743 return sel;
744 }
745
746 void *r600_create_shader_state_ps(struct pipe_context *ctx,
747 const struct pipe_shader_state *state)
748 {
749 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
750 }
751
752 void *r600_create_shader_state_vs(struct pipe_context *ctx,
753 const struct pipe_shader_state *state)
754 {
755 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
756 }
757
758 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
759 {
760 struct r600_context *rctx = (struct r600_context *)ctx;
761
762 if (!state)
763 state = rctx->dummy_pixel_shader;
764
765 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
766 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
767
768 if (rctx->chip_class <= R700) {
769 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
770
771 if (rctx->cb_misc_state.multiwrite != multiwrite) {
772 rctx->cb_misc_state.multiwrite = multiwrite;
773 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
774 }
775
776 if (rctx->vs_shader)
777 r600_adjust_gprs(rctx);
778 }
779
780 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
781 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
782 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
783 }
784 }
785
786 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
787 {
788 struct r600_context *rctx = (struct r600_context *)ctx;
789
790 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
791 if (state) {
792 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
793
794 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
795 r600_adjust_gprs(rctx);
796 }
797 }
798
799 static void r600_delete_shader_selector(struct pipe_context *ctx,
800 struct r600_pipe_shader_selector *sel)
801 {
802 struct r600_pipe_shader *p = sel->current, *c;
803 while (p) {
804 c = p->next_variant;
805 r600_pipe_shader_destroy(ctx, p);
806 free(p);
807 p = c;
808 }
809
810 free(sel->tokens);
811 free(sel);
812 }
813
814
815 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
816 {
817 struct r600_context *rctx = (struct r600_context *)ctx;
818 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
819
820 if (rctx->ps_shader == sel) {
821 rctx->ps_shader = NULL;
822 }
823
824 r600_delete_shader_selector(ctx, sel);
825 }
826
827 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
828 {
829 struct r600_context *rctx = (struct r600_context *)ctx;
830 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
831
832 if (rctx->vs_shader == sel) {
833 rctx->vs_shader = NULL;
834 }
835
836 r600_delete_shader_selector(ctx, sel);
837 }
838
839 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
840 {
841 if (state->dirty_mask) {
842 r600_inval_shader_cache(rctx);
843 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
844 : util_bitcount(state->dirty_mask)*19;
845 r600_atom_dirty(rctx, &state->atom);
846 }
847 }
848
849 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
850 struct pipe_constant_buffer *input)
851 {
852 struct r600_context *rctx = (struct r600_context *)ctx;
853 struct r600_constbuf_state *state;
854 struct pipe_constant_buffer *cb;
855 const uint8_t *ptr;
856
857 switch (shader) {
858 case PIPE_SHADER_VERTEX:
859 state = &rctx->vs_constbuf_state;
860 break;
861 case PIPE_SHADER_FRAGMENT:
862 state = &rctx->ps_constbuf_state;
863 break;
864 default:
865 return;
866 }
867
868 /* Note that the state tracker can unbind constant buffers by
869 * passing NULL here.
870 */
871 if (unlikely(!input)) {
872 state->enabled_mask &= ~(1 << index);
873 state->dirty_mask &= ~(1 << index);
874 pipe_resource_reference(&state->cb[index].buffer, NULL);
875 return;
876 }
877
878 cb = &state->cb[index];
879 cb->buffer_size = input->buffer_size;
880
881 ptr = input->user_buffer;
882
883 if (ptr) {
884 /* Upload the user buffer. */
885 if (R600_BIG_ENDIAN) {
886 uint32_t *tmpPtr;
887 unsigned i, size = input->buffer_size;
888
889 if (!(tmpPtr = malloc(size))) {
890 R600_ERR("Failed to allocate BE swap buffer.\n");
891 return;
892 }
893
894 for (i = 0; i < size / 4; ++i) {
895 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
896 }
897
898 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
899 free(tmpPtr);
900 } else {
901 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
902 }
903 } else {
904 /* Setup the hw buffer. */
905 cb->buffer_offset = input->buffer_offset;
906 pipe_resource_reference(&cb->buffer, input->buffer);
907 }
908
909 state->enabled_mask |= 1 << index;
910 state->dirty_mask |= 1 << index;
911 r600_constant_buffers_dirty(rctx, state);
912 }
913
914 struct pipe_stream_output_target *
915 r600_create_so_target(struct pipe_context *ctx,
916 struct pipe_resource *buffer,
917 unsigned buffer_offset,
918 unsigned buffer_size)
919 {
920 struct r600_context *rctx = (struct r600_context *)ctx;
921 struct r600_so_target *t;
922 void *ptr;
923
924 t = CALLOC_STRUCT(r600_so_target);
925 if (!t) {
926 return NULL;
927 }
928
929 t->b.reference.count = 1;
930 t->b.context = ctx;
931 pipe_resource_reference(&t->b.buffer, buffer);
932 t->b.buffer_offset = buffer_offset;
933 t->b.buffer_size = buffer_size;
934
935 t->filled_size = (struct r600_resource*)
936 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
937 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
938 memset(ptr, 0, t->filled_size->buf->size);
939 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
940
941 return &t->b;
942 }
943
944 void r600_so_target_destroy(struct pipe_context *ctx,
945 struct pipe_stream_output_target *target)
946 {
947 struct r600_so_target *t = (struct r600_so_target*)target;
948 pipe_resource_reference(&t->b.buffer, NULL);
949 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
950 FREE(t);
951 }
952
953 void r600_set_so_targets(struct pipe_context *ctx,
954 unsigned num_targets,
955 struct pipe_stream_output_target **targets,
956 unsigned append_bitmask)
957 {
958 struct r600_context *rctx = (struct r600_context *)ctx;
959 unsigned i;
960
961 /* Stop streamout. */
962 if (rctx->num_so_targets && !rctx->streamout_start) {
963 r600_context_streamout_end(rctx);
964 }
965
966 /* Set the new targets. */
967 for (i = 0; i < num_targets; i++) {
968 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
969 }
970 for (; i < rctx->num_so_targets; i++) {
971 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
972 }
973
974 rctx->num_so_targets = num_targets;
975 rctx->streamout_start = num_targets != 0;
976 rctx->streamout_append_bitmask = append_bitmask;
977 }
978
979 void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
980 {
981 struct r600_context *rctx = (struct r600_context*)pipe;
982
983 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
984 return;
985
986 rctx->sample_mask.sample_mask = sample_mask;
987 r600_atom_dirty(rctx, &rctx->sample_mask.atom);
988 }
989
990 static void r600_update_derived_state(struct r600_context *rctx)
991 {
992 struct pipe_context * ctx = (struct pipe_context*)rctx;
993 unsigned ps_dirty = 0;
994
995 if (!rctx->blitter->running) {
996 /* Flush depth textures which need to be flushed. */
997 if (rctx->vs_samplers.views.depth_texture_mask) {
998 r600_flush_depth_textures(rctx, &rctx->vs_samplers.views);
999 }
1000 if (rctx->ps_samplers.views.depth_texture_mask) {
1001 r600_flush_depth_textures(rctx, &rctx->ps_samplers.views);
1002 }
1003 }
1004
1005 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1006
1007 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
1008 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
1009 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1010
1011 if (rctx->chip_class >= EVERGREEN)
1012 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1013 else
1014 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1015
1016 ps_dirty = 1;
1017 }
1018
1019 if (ps_dirty)
1020 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1021
1022 if (rctx->chip_class >= EVERGREEN) {
1023 evergreen_update_dual_export_state(rctx);
1024 } else {
1025 r600_update_dual_export_state(rctx);
1026 }
1027 }
1028
1029 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1030 {
1031 static const int prim_conv[] = {
1032 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1033 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1034 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1035 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1036 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1037 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1038 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1039 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1040 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1041 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1042 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1043 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1044 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1045 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1046 };
1047 assert(mode < Elements(prim_conv));
1048
1049 return prim_conv[mode];
1050 }
1051
1052 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1053 {
1054 struct r600_context *rctx = (struct r600_context *)ctx;
1055 struct pipe_draw_info info = *dinfo;
1056 struct pipe_index_buffer ib = {};
1057 unsigned prim, ls_mask = 0;
1058 struct r600_block *dirty_block = NULL, *next_block = NULL;
1059 struct r600_atom *state = NULL, *next_state = NULL;
1060 struct radeon_winsys_cs *cs = rctx->cs;
1061 uint64_t va;
1062 uint8_t *ptr;
1063
1064 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
1065 !r600_conv_pipe_prim(info.mode, &prim)) {
1066 assert(0);
1067 return;
1068 }
1069
1070 if (!rctx->vs_shader) {
1071 assert(0);
1072 return;
1073 }
1074
1075 r600_update_derived_state(rctx);
1076
1077 /* partial flush triggered by border color change */
1078 if (rctx->flags & R600_PARTIAL_FLUSH) {
1079 rctx->flags &= ~R600_PARTIAL_FLUSH;
1080 r600_write_value(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1081 r600_write_value(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1082 }
1083
1084 if (info.indexed) {
1085 /* Initialize the index buffer struct. */
1086 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1087 ib.user_buffer = rctx->index_buffer.user_buffer;
1088 ib.index_size = rctx->index_buffer.index_size;
1089 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1090
1091 /* Translate or upload, if needed. */
1092 r600_translate_index_buffer(rctx, &ib, info.count);
1093
1094 ptr = (uint8_t*)ib.user_buffer;
1095 if (!ib.buffer && ptr) {
1096 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1097 ptr, &ib.offset, &ib.buffer);
1098 }
1099 } else {
1100 info.index_bias = info.start;
1101 }
1102
1103 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
1104 rctx->vgt.id = R600_PIPE_STATE_VGT;
1105 rctx->vgt.nregs = 0;
1106 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
1107 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
1108 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
1109 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
1110 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
1111 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1112 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
1113 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
1114 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
1115 }
1116
1117 rctx->vgt.nregs = 0;
1118 r600_pipe_state_mod_reg(&rctx->vgt, prim);
1119 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
1120 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
1121 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
1122 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
1123 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
1124
1125 if (prim == V_008958_DI_PT_LINELIST)
1126 ls_mask = 1;
1127 else if (prim == V_008958_DI_PT_LINESTRIP ||
1128 prim == V_008958_DI_PT_LINELOOP)
1129 ls_mask = 2;
1130 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
1131 r600_pipe_state_mod_reg(&rctx->vgt,
1132 rctx->vs_shader->current->pa_cl_vs_out_cntl |
1133 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
1134 r600_pipe_state_mod_reg(&rctx->vgt,
1135 rctx->pa_cl_clip_cntl |
1136 (rctx->vs_shader->current->shader.clip_dist_write ||
1137 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
1138 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
1139
1140 r600_context_pipe_state_set(rctx, &rctx->vgt);
1141
1142 /* Enable stream out if needed. */
1143 if (rctx->streamout_start) {
1144 r600_context_streamout_begin(rctx);
1145 rctx->streamout_start = FALSE;
1146 }
1147
1148 /* Emit states (the function expects that we emit at most 17 dwords here). */
1149 r600_need_cs_space(rctx, 0, TRUE);
1150
1151 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
1152 r600_emit_atom(rctx, state);
1153 }
1154 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1155 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1156 }
1157 rctx->pm4_dirty_cdwords = 0;
1158
1159 /* draw packet */
1160 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1161 cs->buf[cs->cdw++] = info.instance_count;
1162 if (info.indexed) {
1163 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1164 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1165 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1166 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1167
1168 va = r600_resource_va(ctx->screen, ib.buffer);
1169 va += ib.offset;
1170 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1171 cs->buf[cs->cdw++] = va;
1172 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1173 cs->buf[cs->cdw++] = info.count;
1174 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1175 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1176 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1177 } else {
1178 if (info.count_from_stream_output) {
1179 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1180 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
1181
1182 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1183
1184 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1185 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1186 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1187 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1188 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1189 cs->buf[cs->cdw++] = 0; /* unused */
1190
1191 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1192 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
1193 }
1194
1195 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1196 cs->buf[cs->cdw++] = info.count;
1197 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1198 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1199 }
1200
1201 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
1202
1203 /* Set the depth buffer as dirty. */
1204 if (rctx->framebuffer.zsbuf) {
1205 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
1206 struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
1207
1208 rtex->dirty_db_mask |= 1 << surf->u.tex.level;
1209 }
1210
1211 pipe_resource_reference(&ib.buffer, NULL);
1212 }
1213
1214 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1215 struct r600_pipe_state *state,
1216 uint32_t offset, uint32_t value,
1217 uint32_t range_id, uint32_t block_id,
1218 struct r600_resource *bo,
1219 enum radeon_bo_usage usage)
1220
1221 {
1222 struct r600_range *range;
1223 struct r600_block *block;
1224
1225 if (bo) assert(usage);
1226
1227 range = &ctx->range[range_id];
1228 block = range->blocks[block_id];
1229 state->regs[state->nregs].block = block;
1230 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1231
1232 state->regs[state->nregs].value = value;
1233 state->regs[state->nregs].bo = bo;
1234 state->regs[state->nregs].bo_usage = usage;
1235
1236 state->nregs++;
1237 assert(state->nregs < R600_BLOCK_MAX_REG);
1238 }
1239
1240 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1241 struct r600_pipe_state *state,
1242 uint32_t offset, uint32_t value,
1243 uint32_t range_id, uint32_t block_id)
1244 {
1245 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1246 range_id, block_id, NULL, 0);
1247 }
1248
1249 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
1250 uint32_t offset, uint32_t value,
1251 struct r600_resource *bo,
1252 enum radeon_bo_usage usage)
1253 {
1254 if (bo) assert(usage);
1255
1256 state->regs[state->nregs].id = offset;
1257 state->regs[state->nregs].block = NULL;
1258 state->regs[state->nregs].value = value;
1259 state->regs[state->nregs].bo = bo;
1260 state->regs[state->nregs].bo_usage = usage;
1261
1262 state->nregs++;
1263 assert(state->nregs < R600_BLOCK_MAX_REG);
1264 }
1265
1266 uint32_t r600_translate_stencil_op(int s_op)
1267 {
1268 switch (s_op) {
1269 case PIPE_STENCIL_OP_KEEP:
1270 return V_028800_STENCIL_KEEP;
1271 case PIPE_STENCIL_OP_ZERO:
1272 return V_028800_STENCIL_ZERO;
1273 case PIPE_STENCIL_OP_REPLACE:
1274 return V_028800_STENCIL_REPLACE;
1275 case PIPE_STENCIL_OP_INCR:
1276 return V_028800_STENCIL_INCR;
1277 case PIPE_STENCIL_OP_DECR:
1278 return V_028800_STENCIL_DECR;
1279 case PIPE_STENCIL_OP_INCR_WRAP:
1280 return V_028800_STENCIL_INCR_WRAP;
1281 case PIPE_STENCIL_OP_DECR_WRAP:
1282 return V_028800_STENCIL_DECR_WRAP;
1283 case PIPE_STENCIL_OP_INVERT:
1284 return V_028800_STENCIL_INVERT;
1285 default:
1286 R600_ERR("Unknown stencil op %d", s_op);
1287 assert(0);
1288 break;
1289 }
1290 return 0;
1291 }
1292
1293 uint32_t r600_translate_fill(uint32_t func)
1294 {
1295 switch(func) {
1296 case PIPE_POLYGON_MODE_FILL:
1297 return 2;
1298 case PIPE_POLYGON_MODE_LINE:
1299 return 1;
1300 case PIPE_POLYGON_MODE_POINT:
1301 return 0;
1302 default:
1303 assert(0);
1304 return 0;
1305 }
1306 }
1307
1308 unsigned r600_tex_wrap(unsigned wrap)
1309 {
1310 switch (wrap) {
1311 default:
1312 case PIPE_TEX_WRAP_REPEAT:
1313 return V_03C000_SQ_TEX_WRAP;
1314 case PIPE_TEX_WRAP_CLAMP:
1315 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1316 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1317 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1318 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1319 return V_03C000_SQ_TEX_CLAMP_BORDER;
1320 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1321 return V_03C000_SQ_TEX_MIRROR;
1322 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1323 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1324 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1325 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1326 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1327 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1328 }
1329 }
1330
1331 unsigned r600_tex_filter(unsigned filter)
1332 {
1333 switch (filter) {
1334 default:
1335 case PIPE_TEX_FILTER_NEAREST:
1336 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1337 case PIPE_TEX_FILTER_LINEAR:
1338 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1339 }
1340 }
1341
1342 unsigned r600_tex_mipfilter(unsigned filter)
1343 {
1344 switch (filter) {
1345 case PIPE_TEX_MIPFILTER_NEAREST:
1346 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1347 case PIPE_TEX_MIPFILTER_LINEAR:
1348 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1349 default:
1350 case PIPE_TEX_MIPFILTER_NONE:
1351 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1352 }
1353 }
1354
1355 unsigned r600_tex_compare(unsigned compare)
1356 {
1357 switch (compare) {
1358 default:
1359 case PIPE_FUNC_NEVER:
1360 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1361 case PIPE_FUNC_LESS:
1362 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1363 case PIPE_FUNC_EQUAL:
1364 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1365 case PIPE_FUNC_LEQUAL:
1366 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1367 case PIPE_FUNC_GREATER:
1368 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1369 case PIPE_FUNC_NOTEQUAL:
1370 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1371 case PIPE_FUNC_GEQUAL:
1372 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1373 case PIPE_FUNC_ALWAYS:
1374 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1375 }
1376 }