2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
97 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
98 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
100 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
101 PIPE_BARRIER_SHADER_BUFFER
|
102 PIPE_BARRIER_TEXTURE
|
104 PIPE_BARRIER_STREAMOUT_BUFFER
|
105 PIPE_BARRIER_GLOBAL_BUFFER
)) {
106 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
|
107 R600_CONTEXT_INV_TEX_CACHE
;
110 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
112 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV
;
114 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
117 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
119 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
121 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
122 R600_CONTEXT_FLUSH_AND_INV_CB
|
123 R600_CONTEXT_FLUSH_AND_INV
|
124 R600_CONTEXT_WAIT_3D_IDLE
;
125 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
128 static unsigned r600_conv_pipe_prim(unsigned prim
)
130 static const unsigned prim_conv
[] = {
131 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
132 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
133 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
134 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
135 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
136 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
138 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
139 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
140 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
141 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
145 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
146 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
148 assert(prim
< ARRAY_SIZE(prim_conv
));
149 return prim_conv
[prim
];
152 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
154 static const int prim_conv
[] = {
155 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
156 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
157 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
158 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
159 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
160 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
161 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
162 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
163 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
164 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
165 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
166 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
167 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
168 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
169 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
170 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
172 assert(mode
< ARRAY_SIZE(prim_conv
));
174 return prim_conv
[mode
];
177 /* common state between evergreen and r600 */
179 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
180 struct r600_blend_state
*blend
, bool blend_disable
)
182 unsigned color_control
;
183 bool update_cb
= false;
185 rctx
->alpha_to_one
= blend
->alpha_to_one
;
186 rctx
->dual_src_blend
= blend
->dual_src_blend
;
188 if (!blend_disable
) {
189 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
190 color_control
= blend
->cb_color_control
;
192 /* Blending is disabled. */
193 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
194 color_control
= blend
->cb_color_control_no_blend
;
197 /* Update derived states. */
198 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
199 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
202 if (rctx
->b
.chip_class
<= R700
&&
203 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
204 rctx
->cb_misc_state
.cb_color_control
= color_control
;
207 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
208 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
212 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
214 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
215 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
216 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
220 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
222 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
223 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
226 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
230 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
233 static void r600_set_blend_color(struct pipe_context
*ctx
,
234 const struct pipe_blend_color
*state
)
236 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
238 rctx
->blend_color
.state
= *state
;
239 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
242 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
244 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
245 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
247 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
248 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
249 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
250 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
251 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
254 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
256 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
257 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
259 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
260 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
261 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
262 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
263 if (a
->last_draw_was_indirect
) {
264 a
->last_draw_was_indirect
= false;
265 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
269 static void r600_set_clip_state(struct pipe_context
*ctx
,
270 const struct pipe_clip_state
*state
)
272 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
274 rctx
->clip_state
.state
= *state
;
275 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
276 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
279 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
280 const struct r600_stencil_ref
*state
)
282 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
284 rctx
->stencil_ref
.state
= *state
;
285 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
288 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
290 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
291 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
293 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
294 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
295 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
296 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
297 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
298 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
299 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
300 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
301 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
304 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
305 const struct pipe_stencil_ref
*state
)
307 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
308 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
309 struct r600_stencil_ref ref
;
311 rctx
->stencil_ref
.pipe_state
= *state
;
316 ref
.ref_value
[0] = state
->ref_value
[0];
317 ref
.ref_value
[1] = state
->ref_value
[1];
318 ref
.valuemask
[0] = dsa
->valuemask
[0];
319 ref
.valuemask
[1] = dsa
->valuemask
[1];
320 ref
.writemask
[0] = dsa
->writemask
[0];
321 ref
.writemask
[1] = dsa
->writemask
[1];
323 r600_set_stencil_ref(ctx
, &ref
);
326 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
328 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
329 struct r600_dsa_state
*dsa
= state
;
330 struct r600_stencil_ref ref
;
333 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
337 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
339 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
340 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
341 ref
.valuemask
[0] = dsa
->valuemask
[0];
342 ref
.valuemask
[1] = dsa
->valuemask
[1];
343 ref
.writemask
[0] = dsa
->writemask
[0];
344 ref
.writemask
[1] = dsa
->writemask
[1];
345 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
346 rctx
->zwritemask
= dsa
->zwritemask
;
347 if (rctx
->b
.chip_class
>= EVERGREEN
) {
348 /* work around some issue when not writing to zbuffer
349 * we are having lockup on evergreen so do not enable
350 * hyperz when not writing zbuffer
352 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
356 r600_set_stencil_ref(ctx
, &ref
);
358 /* Update alphatest state. */
359 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
360 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
361 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
362 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
363 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
367 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
369 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
370 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
375 rctx
->rasterizer
= rs
;
377 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
379 if (rs
->offset_enable
&&
380 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
381 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
382 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
383 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
384 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
385 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
386 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
389 /* Update clip_misc_state. */
390 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
391 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
392 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
393 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
394 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
397 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
399 /* Re-emit PA_SC_LINE_STIPPLE. */
400 rctx
->last_primitive_type
= -1;
403 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
405 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
407 r600_release_command_buffer(&rs
->buffer
);
411 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
412 struct pipe_sampler_view
*state
)
414 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
416 if (view
->tex_resource
->gpu_address
&&
417 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
418 LIST_DELINIT(&view
->list
);
420 pipe_resource_reference(&state
->texture
, NULL
);
424 void r600_sampler_states_dirty(struct r600_context
*rctx
,
425 struct r600_sampler_states
*state
)
427 if (state
->dirty_mask
) {
428 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
429 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
432 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
433 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
434 r600_mark_atom_dirty(rctx
, &state
->atom
);
438 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
439 enum pipe_shader_type shader
,
441 unsigned count
, void **states
)
443 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
444 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
445 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
446 int seamless_cube_map
= -1;
448 /* This sets 1-bit for states with index >= count. */
449 uint32_t disable_mask
= ~((1ull << count
) - 1);
450 /* These are the new states set by this function. */
451 uint32_t new_mask
= 0;
453 assert(start
== 0); /* XXX fix below */
460 for (i
= 0; i
< count
; i
++) {
461 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
463 if (rstate
== dst
->states
.states
[i
]) {
468 if (rstate
->border_color_use
) {
469 dst
->states
.has_bordercolor_mask
|= 1 << i
;
471 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
473 seamless_cube_map
= rstate
->seamless_cube_map
;
477 disable_mask
|= 1 << i
;
481 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
482 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
484 dst
->states
.enabled_mask
&= ~disable_mask
;
485 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
486 dst
->states
.enabled_mask
|= new_mask
;
487 dst
->states
.dirty_mask
|= new_mask
;
488 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
490 r600_sampler_states_dirty(rctx
, &dst
->states
);
492 /* Seamless cubemap state. */
493 if (rctx
->b
.chip_class
<= R700
&&
494 seamless_cube_map
!= -1 &&
495 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
496 /* change in TA_CNTL_AUX need a pipeline flush */
497 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
498 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
499 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
503 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
508 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
510 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
511 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
513 if (rctx
->blend_state
.cso
== state
) {
514 ctx
->bind_blend_state(ctx
, NULL
);
517 r600_release_command_buffer(&blend
->buffer
);
518 r600_release_command_buffer(&blend
->buffer_no_blend
);
522 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
524 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
525 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
527 if (rctx
->dsa_state
.cso
== state
) {
528 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
531 r600_release_command_buffer(&dsa
->buffer
);
535 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
537 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
539 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
542 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
544 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
545 r600_resource_reference(&shader
->buffer
, NULL
);
549 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
551 if (rctx
->vertex_buffer_state
.dirty_mask
) {
552 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
553 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
554 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
558 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
559 unsigned start_slot
, unsigned count
,
560 const struct pipe_vertex_buffer
*input
)
562 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
563 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
564 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
566 uint32_t disable_mask
= 0;
567 /* These are the new buffers set by this function. */
568 uint32_t new_buffer_mask
= 0;
570 /* Set vertex buffers. */
572 for (i
= 0; i
< count
; i
++) {
573 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
574 if (input
[i
].buffer
.resource
) {
575 vb
[i
].stride
= input
[i
].stride
;
576 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
577 pipe_resource_reference(&vb
[i
].buffer
.resource
, input
[i
].buffer
.resource
);
578 new_buffer_mask
|= 1 << i
;
579 r600_context_add_resource_size(ctx
, input
[i
].buffer
.resource
);
581 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
582 disable_mask
|= 1 << i
;
587 for (i
= 0; i
< count
; i
++) {
588 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
590 disable_mask
= ((1ull << count
) - 1);
593 disable_mask
<<= start_slot
;
594 new_buffer_mask
<<= start_slot
;
596 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
597 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
598 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
599 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
601 r600_vertex_buffers_dirty(rctx
);
604 void r600_sampler_views_dirty(struct r600_context
*rctx
,
605 struct r600_samplerview_state
*state
)
607 if (state
->dirty_mask
) {
608 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
609 util_bitcount(state
->dirty_mask
);
610 r600_mark_atom_dirty(rctx
, &state
->atom
);
614 static void r600_set_sampler_views(struct pipe_context
*pipe
,
615 enum pipe_shader_type shader
,
616 unsigned start
, unsigned count
,
617 struct pipe_sampler_view
**views
)
619 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
620 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
621 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
622 uint32_t dirty_sampler_states_mask
= 0;
624 /* This sets 1-bit for textures with index >= count. */
625 uint32_t disable_mask
= ~((1ull << count
) - 1);
626 /* These are the new textures set by this function. */
627 uint32_t new_mask
= 0;
629 /* Set textures with index >= count to NULL. */
630 uint32_t remaining_mask
;
632 assert(start
== 0); /* XXX fix below */
639 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
641 while (remaining_mask
) {
642 i
= u_bit_scan(&remaining_mask
);
643 assert(dst
->views
.views
[i
]);
645 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
648 for (i
= 0; i
< count
; i
++) {
649 if (rviews
[i
] == dst
->views
.views
[i
]) {
654 struct r600_texture
*rtex
=
655 (struct r600_texture
*)rviews
[i
]->base
.texture
;
656 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
658 if (!is_buffer
&& rtex
->db_compatible
) {
659 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
661 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
664 /* Track compressed colorbuffers. */
665 if (!is_buffer
&& rtex
->cmask
.size
) {
666 dst
->views
.compressed_colortex_mask
|= 1 << i
;
668 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
671 /* Changing from array to non-arrays textures and vice versa requires
672 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
673 if (rctx
->b
.chip_class
<= R700
&&
674 (dst
->states
.enabled_mask
& (1 << i
)) &&
675 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
676 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
677 dirty_sampler_states_mask
|= 1 << i
;
680 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
682 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
684 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
685 disable_mask
|= 1 << i
;
689 dst
->views
.enabled_mask
&= ~disable_mask
;
690 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
691 dst
->views
.enabled_mask
|= new_mask
;
692 dst
->views
.dirty_mask
|= new_mask
;
693 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
694 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
695 dst
->views
.dirty_buffer_constants
= TRUE
;
696 r600_sampler_views_dirty(rctx
, &dst
->views
);
698 if (dirty_sampler_states_mask
) {
699 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
700 r600_sampler_states_dirty(rctx
, &dst
->states
);
704 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
706 uint32_t mask
= views
->enabled_mask
;
709 unsigned i
= u_bit_scan(&mask
);
710 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
712 if (res
&& res
->target
!= PIPE_BUFFER
) {
713 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
715 if (rtex
->cmask
.size
) {
716 views
->compressed_colortex_mask
|= 1 << i
;
718 views
->compressed_colortex_mask
&= ~(1 << i
);
724 static int r600_get_hw_atomic_count(const struct pipe_context
*ctx
,
725 enum pipe_shader_type shader
)
727 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
730 case PIPE_SHADER_FRAGMENT
:
731 case PIPE_SHADER_COMPUTE
:
734 case PIPE_SHADER_VERTEX
:
735 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
737 case PIPE_SHADER_GEOMETRY
:
738 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
739 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
741 case PIPE_SHADER_TESS_EVAL
:
742 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
743 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
744 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0);
746 case PIPE_SHADER_TESS_CTRL
:
747 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
748 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
749 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0) +
750 rctx
->tes_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
756 /* Compute the key for the hw shader variant */
757 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
758 const struct r600_pipe_shader_selector
*sel
,
759 union r600_shader_key
*key
)
761 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
762 memset(key
, 0, sizeof(*key
));
765 case PIPE_SHADER_VERTEX
: {
766 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
768 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
770 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
771 key
->vs
.as_gs_a
= true;
772 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
774 key
->vs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_VERTEX
);
777 case PIPE_SHADER_GEOMETRY
:
778 key
->gs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_GEOMETRY
);
779 key
->gs
.tri_strip_adj_fix
= rctx
->gs_tri_strip_adj_fix
;
781 case PIPE_SHADER_FRAGMENT
: {
782 key
->ps
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_FRAGMENT
);
783 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
784 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
785 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
786 !rctx
->framebuffer
.cb0_is_integer
;
787 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
788 /* Dual-source blending only makes sense with nr_cbufs == 1. */
789 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
790 key
->ps
.nr_cbufs
= 2;
793 case PIPE_SHADER_TESS_EVAL
:
794 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
795 key
->tes
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_EVAL
);
797 case PIPE_SHADER_TESS_CTRL
:
798 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
799 key
->tcs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_CTRL
);
806 /* Select the hw shader variant depending on the current state.
807 * (*dirty) is set to 1 if current variant was changed */
808 static int r600_shader_select(struct pipe_context
*ctx
,
809 struct r600_pipe_shader_selector
* sel
,
812 union r600_shader_key key
;
813 struct r600_pipe_shader
* shader
= NULL
;
816 r600_shader_selector_key(ctx
, sel
, &key
);
818 /* Check if we don't need to change anything.
819 * This path is also used for most shaders that don't need multiple
820 * variants, it will cost just a computation of the key and this
822 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
826 /* lookup if we have other variants in the list */
827 if (sel
->num_shaders
> 1) {
828 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
830 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
836 p
->next_variant
= c
->next_variant
;
841 if (unlikely(!shader
)) {
842 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
843 shader
->selector
= sel
;
845 r
= r600_pipe_shader_create(ctx
, shader
, key
);
847 R600_ERR("Failed to build shader variant (type=%u) %d\n",
854 /* We don't know the value of nr_ps_max_color_exports until we built
855 * at least one variant, so we may need to recompute the key after
856 * building first variant. */
857 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
858 sel
->num_shaders
== 0) {
859 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
860 r600_shader_selector_key(ctx
, sel
, &key
);
863 memcpy(&shader
->key
, &key
, sizeof(key
));
870 shader
->next_variant
= sel
->current
;
871 sel
->current
= shader
;
876 static void *r600_create_shader_state(struct pipe_context
*ctx
,
877 const struct pipe_shader_state
*state
,
878 unsigned pipe_shader_type
)
880 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
883 sel
->type
= pipe_shader_type
;
884 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
885 sel
->so
= state
->stream_output
;
886 tgsi_scan_shader(state
->tokens
, &sel
->info
);
888 switch (pipe_shader_type
) {
889 case PIPE_SHADER_GEOMETRY
:
890 sel
->gs_output_prim
=
891 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
892 sel
->gs_max_out_vertices
=
893 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
894 sel
->gs_num_invocations
=
895 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
897 case PIPE_SHADER_VERTEX
:
898 case PIPE_SHADER_TESS_CTRL
:
899 sel
->lds_patch_outputs_written_mask
= 0;
900 sel
->lds_outputs_written_mask
= 0;
902 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
903 unsigned name
= sel
->info
.output_semantic_name
[i
];
904 unsigned index
= sel
->info
.output_semantic_index
[i
];
907 case TGSI_SEMANTIC_TESSINNER
:
908 case TGSI_SEMANTIC_TESSOUTER
:
909 case TGSI_SEMANTIC_PATCH
:
910 sel
->lds_patch_outputs_written_mask
|=
911 1ull << r600_get_lds_unique_index(name
, index
);
914 sel
->lds_outputs_written_mask
|=
915 1ull << r600_get_lds_unique_index(name
, index
);
926 static void *r600_create_ps_state(struct pipe_context
*ctx
,
927 const struct pipe_shader_state
*state
)
929 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
932 static void *r600_create_vs_state(struct pipe_context
*ctx
,
933 const struct pipe_shader_state
*state
)
935 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
938 static void *r600_create_gs_state(struct pipe_context
*ctx
,
939 const struct pipe_shader_state
*state
)
941 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
944 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
945 const struct pipe_shader_state
*state
)
947 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
950 static void *r600_create_tes_state(struct pipe_context
*ctx
,
951 const struct pipe_shader_state
*state
)
953 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
956 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
958 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
961 state
= rctx
->dummy_pixel_shader
;
963 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
966 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
969 return &rctx
->gs_shader
->info
;
970 else if (rctx
->tes_shader
)
971 return &rctx
->tes_shader
->info
;
972 else if (rctx
->vs_shader
)
973 return &rctx
->vs_shader
->info
;
978 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
980 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
982 if (!state
|| rctx
->vs_shader
== state
)
985 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
986 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
987 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
990 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
992 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
994 if (state
== rctx
->gs_shader
)
997 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
998 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1002 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
1005 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1007 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1009 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
1012 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1014 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1016 if (state
== rctx
->tes_shader
)
1019 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
1020 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1024 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
1027 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
1028 struct r600_pipe_shader_selector
*sel
)
1030 struct r600_pipe_shader
*p
= sel
->current
, *c
;
1032 c
= p
->next_variant
;
1033 r600_pipe_shader_destroy(ctx
, p
);
1043 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
1045 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1046 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1048 if (rctx
->ps_shader
== sel
) {
1049 rctx
->ps_shader
= NULL
;
1052 r600_delete_shader_selector(ctx
, sel
);
1055 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1057 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1058 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1060 if (rctx
->vs_shader
== sel
) {
1061 rctx
->vs_shader
= NULL
;
1064 r600_delete_shader_selector(ctx
, sel
);
1068 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1070 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1071 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1073 if (rctx
->gs_shader
== sel
) {
1074 rctx
->gs_shader
= NULL
;
1077 r600_delete_shader_selector(ctx
, sel
);
1080 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1082 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1083 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1085 if (rctx
->tcs_shader
== sel
) {
1086 rctx
->tcs_shader
= NULL
;
1089 r600_delete_shader_selector(ctx
, sel
);
1092 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1094 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1095 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1097 if (rctx
->tes_shader
== sel
) {
1098 rctx
->tes_shader
= NULL
;
1101 r600_delete_shader_selector(ctx
, sel
);
1104 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1106 if (state
->dirty_mask
) {
1107 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1108 : util_bitcount(state
->dirty_mask
)*19;
1109 r600_mark_atom_dirty(rctx
, &state
->atom
);
1113 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1114 enum pipe_shader_type shader
, uint index
,
1115 const struct pipe_constant_buffer
*input
)
1117 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1118 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1119 struct pipe_constant_buffer
*cb
;
1122 /* Note that the state tracker can unbind constant buffers by
1123 * passing NULL here.
1125 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1126 state
->enabled_mask
&= ~(1 << index
);
1127 state
->dirty_mask
&= ~(1 << index
);
1128 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1132 cb
= &state
->cb
[index
];
1133 cb
->buffer_size
= input
->buffer_size
;
1135 ptr
= input
->user_buffer
;
1138 /* Upload the user buffer. */
1139 if (R600_BIG_ENDIAN
) {
1141 unsigned i
, size
= input
->buffer_size
;
1143 if (!(tmpPtr
= malloc(size
))) {
1144 R600_ERR("Failed to allocate BE swap buffer.\n");
1148 for (i
= 0; i
< size
/ 4; ++i
) {
1149 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1152 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1153 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1156 u_upload_data(ctx
->stream_uploader
, 0,
1157 input
->buffer_size
, 256, ptr
,
1158 &cb
->buffer_offset
, &cb
->buffer
);
1160 /* account it in gtt */
1161 rctx
->b
.gtt
+= input
->buffer_size
;
1163 /* Setup the hw buffer. */
1164 cb
->buffer_offset
= input
->buffer_offset
;
1165 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1166 r600_context_add_resource_size(ctx
, input
->buffer
);
1169 state
->enabled_mask
|= 1 << index
;
1170 state
->dirty_mask
|= 1 << index
;
1171 r600_constant_buffers_dirty(rctx
, state
);
1174 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1176 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1178 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1181 rctx
->sample_mask
.sample_mask
= sample_mask
;
1182 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1185 static void r600_update_driver_const_buffers(struct r600_context
*rctx
)
1189 struct pipe_constant_buffer cb
;
1190 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
1191 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1192 if (!info
->vs_ucp_dirty
&&
1193 !info
->texture_const_dirty
&&
1194 !info
->ps_sample_pos_dirty
)
1197 ptr
= info
->constants
;
1198 size
= info
->alloc_size
;
1199 if (info
->vs_ucp_dirty
) {
1200 assert(sh
== PIPE_SHADER_VERTEX
);
1202 ptr
= rctx
->clip_state
.state
.ucp
;
1203 size
= R600_UCP_SIZE
;
1205 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1207 info
->vs_ucp_dirty
= false;
1210 if (info
->ps_sample_pos_dirty
) {
1211 assert(sh
== PIPE_SHADER_FRAGMENT
);
1213 ptr
= rctx
->sample_positions
;
1214 size
= R600_UCP_SIZE
;
1216 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1218 info
->ps_sample_pos_dirty
= false;
1221 if (info
->texture_const_dirty
) {
1224 if (sh
== PIPE_SHADER_VERTEX
)
1225 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1226 if (sh
== PIPE_SHADER_FRAGMENT
)
1227 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1229 info
->texture_const_dirty
= false;
1232 cb
.user_buffer
= ptr
;
1233 cb
.buffer_offset
= 0;
1234 cb
.buffer_size
= size
;
1235 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1236 pipe_resource_reference(&cb
.buffer
, NULL
);
1240 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1241 int array_size
, uint32_t *base_offset
)
1243 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1244 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1245 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1246 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1248 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1249 info
->texture_const_dirty
= true;
1250 *base_offset
= R600_UCP_SIZE
;
1251 return info
->constants
;
1254 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1255 * doesn't require full swizzles it does need masking and setting alpha
1256 * to one, so we setup a set of 5 constants with the masks + alpha value
1257 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1258 * then OR the alpha with the value given here.
1259 * We use a 6th constant to store the txq buffer size in
1260 * we use 7th slot for number of cube layers in a cube map array.
1262 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1264 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1266 uint32_t array_size
;
1268 uint32_t *constants
;
1269 uint32_t base_offset
;
1270 if (!samplers
->views
.dirty_buffer_constants
)
1273 samplers
->views
.dirty_buffer_constants
= FALSE
;
1275 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1276 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1278 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1280 for (i
= 0; i
< bits
; i
++) {
1281 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1282 int offset
= (base_offset
/ 4) + i
* 8;
1283 const struct util_format_description
*desc
;
1284 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1286 for (j
= 0; j
< 4; j
++)
1287 if (j
< desc
->nr_channels
)
1288 constants
[offset
+j
] = 0xffffffff;
1290 constants
[offset
+j
] = 0x0;
1291 if (desc
->nr_channels
< 4) {
1292 if (desc
->channel
[0].pure_integer
)
1293 constants
[offset
+4] = 1;
1295 constants
[offset
+4] = fui(1.0);
1297 constants
[offset
+ 4] = 0;
1299 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1300 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1306 /* On evergreen we store two values
1307 * 1. buffer size for TXQ
1308 * 2. number of cube layers in a cube map array.
1310 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1312 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1314 uint32_t array_size
;
1316 uint32_t *constants
;
1317 uint32_t base_offset
;
1318 if (!samplers
->views
.dirty_buffer_constants
)
1321 samplers
->views
.dirty_buffer_constants
= FALSE
;
1323 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1324 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1326 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1329 for (i
= 0; i
< bits
; i
++) {
1330 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1331 uint32_t offset
= (base_offset
/ 4) + i
* 2;
1332 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1333 constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1338 /* set sample xy locations as array of fragment shader constants */
1339 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1342 struct pipe_context
*ctx
= &rctx
->b
.b
;
1344 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1345 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1347 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1348 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1349 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1350 /* Also fill in center-zeroed positions used for interpolateAtSample */
1351 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1352 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1355 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1358 static void update_shader_atom(struct pipe_context
*ctx
,
1359 struct r600_shader_state
*state
,
1360 struct r600_pipe_shader
*shader
)
1362 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1364 state
->shader
= shader
;
1366 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1367 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1369 state
->atom
.num_dw
= 0;
1371 r600_mark_atom_dirty(rctx
, &state
->atom
);
1374 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1376 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1377 rctx
->shader_stages
.geom_enable
= enable
;
1378 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1381 if (rctx
->gs_rings
.enable
!= enable
) {
1382 rctx
->gs_rings
.enable
= enable
;
1383 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1385 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1386 unsigned size
= 0x1C000;
1387 rctx
->gs_rings
.esgs_ring
.buffer
=
1388 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1389 PIPE_USAGE_DEFAULT
, size
);
1390 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1394 rctx
->gs_rings
.gsvs_ring
.buffer
=
1395 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1396 PIPE_USAGE_DEFAULT
, size
);
1397 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1401 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1402 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1403 if (rctx
->tes_shader
) {
1404 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1405 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1407 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1408 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1411 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1412 R600_GS_RING_CONST_BUFFER
, NULL
);
1413 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1414 R600_GS_RING_CONST_BUFFER
, NULL
);
1415 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1416 R600_GS_RING_CONST_BUFFER
, NULL
);
1421 static void r600_update_clip_state(struct r600_context
*rctx
,
1422 struct r600_pipe_shader
*current
)
1424 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1425 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1426 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1427 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1428 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1429 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1430 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1431 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1432 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1436 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1438 struct ureg_src const0
, const1
;
1439 struct ureg_dst tessouter
, tessinner
;
1440 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1443 return; /* if we get here, we're screwed */
1445 assert(!rctx
->fixed_func_tcs_shader
);
1447 ureg_DECL_constant2D(ureg
, 0, 3, R600_LDS_INFO_CONST_BUFFER
);
1448 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 2),
1449 R600_LDS_INFO_CONST_BUFFER
);
1450 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 3),
1451 R600_LDS_INFO_CONST_BUFFER
);
1453 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1454 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1456 ureg_MOV(ureg
, tessouter
, const0
);
1457 ureg_MOV(ureg
, tessinner
, const1
);
1460 rctx
->fixed_func_tcs_shader
=
1461 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1464 static void r600_update_compressed_resource_state(struct r600_context
*rctx
)
1469 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1470 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1471 rctx
->b
.last_compressed_colortex_counter
= counter
;
1473 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1474 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1478 /* Decompress textures if needed. */
1479 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1480 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1481 if (views
->compressed_depthtex_mask
) {
1482 r600_decompress_depth_textures(rctx
, views
);
1484 if (views
->compressed_colortex_mask
) {
1485 r600_decompress_color_textures(rctx
, views
);
1490 #define SELECT_SHADER_OR_FAIL(x) do { \
1491 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1492 if (unlikely(!rctx->x##_shader->current)) \
1496 #define UPDATE_SHADER(hw, sw) do { \
1497 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1498 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1501 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1502 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1503 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1504 clip_so_current = rctx->sw##_shader->current; \
1508 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1509 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1510 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1511 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1512 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1516 #define SET_NULL_SHADER(hw) do { \
1517 if (rctx->hw_shader_stages[(hw)].shader) \
1518 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1521 static bool r600_update_derived_state(struct r600_context
*rctx
)
1523 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1524 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1525 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1527 bool need_buf_const
;
1528 struct r600_pipe_shader
*clip_so_current
= NULL
;
1530 if (!rctx
->blitter
->running
)
1531 r600_update_compressed_resource_state(rctx
);
1533 SELECT_SHADER_OR_FAIL(ps
);
1535 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1537 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1539 if (rctx
->gs_shader
)
1540 SELECT_SHADER_OR_FAIL(gs
);
1543 if (rctx
->tcs_shader
) {
1544 SELECT_SHADER_OR_FAIL(tcs
);
1546 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1547 } else if (rctx
->tes_shader
) {
1548 if (!rctx
->fixed_func_tcs_shader
) {
1549 r600_generate_fixed_func_tcs(rctx
);
1550 if (!rctx
->fixed_func_tcs_shader
)
1554 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1556 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1558 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1560 if (rctx
->tes_shader
) {
1561 SELECT_SHADER_OR_FAIL(tes
);
1564 SELECT_SHADER_OR_FAIL(vs
);
1566 if (rctx
->gs_shader
) {
1567 if (!rctx
->shader_stages
.geom_enable
) {
1568 rctx
->shader_stages
.geom_enable
= true;
1569 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1572 /* gs_shader provides GS and VS (copy shader) */
1573 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1575 /* vs_shader is used as ES */
1577 if (rctx
->tes_shader
) {
1578 /* VS goes to LS, TES goes to ES */
1579 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1580 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1582 /* vs_shader is used as ES */
1583 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1584 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1587 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1588 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1589 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1590 rctx
->shader_stages
.geom_enable
= false;
1591 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1594 if (rctx
->tes_shader
) {
1595 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1596 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1597 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1599 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1600 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1604 /* Update clip misc state. */
1605 if (clip_so_current
) {
1606 r600_update_clip_state(rctx
, clip_so_current
);
1607 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1610 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1611 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1612 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1614 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1615 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1616 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1619 if (rctx
->b
.chip_class
<= R700
) {
1620 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1622 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1623 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1624 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1628 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1629 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1630 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1632 if (rctx
->b
.chip_class
>= EVERGREEN
)
1633 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1635 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1638 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1640 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1642 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1643 evergreen_update_db_shader_control(rctx
);
1645 r600_update_db_shader_control(rctx
);
1648 /* on R600 we stuff masks + txq info into one constant buffer */
1649 /* on evergreen we only need a txq info one */
1650 if (rctx
->ps_shader
) {
1651 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1652 if (need_buf_const
) {
1653 if (rctx
->b
.chip_class
< EVERGREEN
)
1654 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1656 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1660 if (rctx
->vs_shader
) {
1661 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1662 if (need_buf_const
) {
1663 if (rctx
->b
.chip_class
< EVERGREEN
)
1664 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1666 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1670 if (rctx
->gs_shader
) {
1671 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1672 if (need_buf_const
) {
1673 if (rctx
->b
.chip_class
< EVERGREEN
)
1674 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1676 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1680 r600_update_driver_const_buffers(rctx
);
1682 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1683 if (!r600_adjust_gprs(rctx
)) {
1684 /* discard rendering */
1689 if (rctx
->b
.chip_class
== EVERGREEN
) {
1690 if (!evergreen_adjust_gprs(rctx
)) {
1691 /* discard rendering */
1696 blend_disable
= (rctx
->dual_src_blend
&&
1697 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1699 if (blend_disable
!= rctx
->force_blend_disable
) {
1700 rctx
->force_blend_disable
= blend_disable
;
1701 r600_bind_blend_state_internal(rctx
,
1702 rctx
->blend_state
.cso
,
1709 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1711 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1712 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1714 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1715 state
->pa_cl_clip_cntl
|
1716 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1717 S_028810_CLIP_DISABLE(state
->clip_disable
));
1718 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1719 state
->pa_cl_vs_out_cntl
|
1720 (state
->clip_plane_enable
& state
->clip_dist_write
));
1721 /* reuse needs to be set off if we write oViewport */
1722 if (rctx
->b
.chip_class
>= EVERGREEN
)
1723 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1724 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1727 /* rast_prim is the primitive type after GS. */
1728 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
1730 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1731 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
1733 /* Skip this if not rendering lines. */
1734 if (rast_prim
!= PIPE_PRIM_LINES
&&
1735 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
1736 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
1737 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
1738 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
1741 if (rast_prim
== rctx
->last_rast_prim
)
1744 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1745 * reset the stipple pattern at each packet (line strips, line loops).
1747 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1748 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
1749 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1750 rctx
->last_rast_prim
= rast_prim
;
1753 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1755 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1756 struct pipe_resource
*indexbuf
= info
->has_user_indices
? NULL
: info
->index
.resource
;
1757 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1758 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
1759 bool has_user_indices
= info
->has_user_indices
;
1761 unsigned num_patches
, dirty_tex_counter
, index_offset
= 0;
1762 unsigned index_size
= info
->index_size
;
1764 struct r600_shader_atomic combined_atomics
[8];
1765 uint8_t atomic_used_mask
;
1767 if (!info
->indirect
&& !info
->count
&& (index_size
|| !info
->count_from_stream_output
)) {
1771 if (unlikely(!rctx
->vs_shader
)) {
1775 if (unlikely(!rctx
->ps_shader
&&
1776 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
1781 /* make sure that the gfx ring is only one active */
1782 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
1783 rctx
->b
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1786 /* Re-emit the framebuffer state if needed. */
1787 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
1788 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
1789 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1790 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1791 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
1794 if (rctx
->gs_shader
) {
1795 /* Determine whether the GS triangle strip adjacency fix should
1796 * be applied. Rotate every other triangle if
1797 * - triangle strips with adjacency are fed to the GS and
1798 * - primitive restart is disabled (the rotation doesn't help
1799 * when the restart occurs after an odd number of triangles).
1801 bool gs_tri_strip_adj_fix
=
1802 !rctx
->tes_shader
&&
1803 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1804 !info
->primitive_restart
;
1805 if (gs_tri_strip_adj_fix
!= rctx
->gs_tri_strip_adj_fix
)
1806 rctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1808 if (!r600_update_derived_state(rctx
)) {
1809 /* useless to render because current rendering command
1815 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
1816 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
1819 if (rctx
->b
.chip_class
>= EVERGREEN
)
1820 evergreen_emit_atomic_buffer_setup(rctx
, combined_atomics
, &atomic_used_mask
);
1823 index_offset
+= info
->start
* index_size
;
1825 /* Translate 8-bit indices to 16-bit. */
1826 if (unlikely(index_size
== 1)) {
1827 struct pipe_resource
*out_buffer
= NULL
;
1828 unsigned out_offset
;
1830 unsigned start
, count
;
1832 if (likely(!info
->indirect
)) {
1834 count
= info
->count
;
1837 /* Have to get start/count from indirect buffer, slow path ahead... */
1838 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
->buffer
;
1839 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1840 PIPE_TRANSFER_READ
);
1842 data
+= info
->indirect
->offset
/ sizeof(unsigned);
1843 start
= data
[2] * index_size
;
1852 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
1853 256, &out_offset
, &out_buffer
, &ptr
);
1857 util_shorten_ubyte_elts_to_userptr(
1858 &rctx
->b
.b
, info
, 0, 0, index_offset
, count
, ptr
);
1860 indexbuf
= out_buffer
;
1861 index_offset
= out_offset
;
1863 has_user_indices
= false;
1866 /* Upload the index buffer.
1867 * The upload is skipped for small index counts on little-endian machines
1868 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1869 * Indirect draws never use immediate indices.
1870 * Note: Instanced rendering in combination with immediate indices hangs. */
1871 if (has_user_indices
&& (R600_BIG_ENDIAN
|| info
->indirect
||
1872 info
->instance_count
> 1 ||
1873 info
->count
*index_size
> 20)) {
1875 u_upload_data(ctx
->stream_uploader
, 0,
1876 info
->count
* index_size
, 256,
1877 info
->index
.user
, &index_offset
, &indexbuf
);
1878 has_user_indices
= false;
1880 index_bias
= info
->index_bias
;
1882 index_bias
= info
->start
;
1885 /* Set the index offset and primitive restart. */
1886 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
1887 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
1888 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
1889 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
1890 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
1891 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
1892 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
1893 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1896 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1897 if (rctx
->b
.chip_class
== R600
) {
1898 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1899 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1902 if (rctx
->b
.chip_class
>= EVERGREEN
)
1903 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
1906 r600_need_cs_space(rctx
, has_user_indices
? 5 : 0, TRUE
);
1907 r600_flush_emit(rctx
);
1909 mask
= rctx
->dirty_atoms
;
1911 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
1914 if (rctx
->b
.chip_class
== CAYMAN
) {
1915 /* Copied from radeonsi. */
1916 unsigned primgroup_size
= 128; /* recommended without a GS */
1917 bool ia_switch_on_eop
= false;
1918 bool partial_vs_wave
= false;
1920 if (rctx
->gs_shader
)
1921 primgroup_size
= 64; /* recommended with a GS */
1923 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1924 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1925 ia_switch_on_eop
= true;
1928 if (r600_get_strmout_en(&rctx
->b
))
1929 partial_vs_wave
= true;
1931 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1932 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1933 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1934 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1937 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1938 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
1941 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
1942 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
1945 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1946 * even though it should have no effect on those. */
1947 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1948 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1949 unsigned prim
= info
->mode
;
1951 if (rctx
->gs_shader
) {
1952 prim
= rctx
->gs_shader
->gs_output_prim
;
1954 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1956 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1957 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1958 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
1959 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1961 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1964 /* Update start instance. */
1965 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
1966 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
1967 rctx
->last_start_instance
= info
->start_instance
;
1970 /* Update the primitive type. */
1971 if (rctx
->last_primitive_type
!= info
->mode
) {
1972 r600_emit_rasterizer_prim_state(rctx
);
1973 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1974 r600_conv_pipe_prim(info
->mode
));
1976 rctx
->last_primitive_type
= info
->mode
;
1980 if (likely(!info
->indirect
)) {
1981 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
1982 radeon_emit(cs
, info
->instance_count
);
1984 uint64_t va
= r600_resource(info
->indirect
->buffer
)->gpu_address
;
1985 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1987 // Invalidate so non-indirect draw calls reset this state
1988 rctx
->vgt_state
.last_draw_was_indirect
= true;
1989 rctx
->last_start_instance
= -1;
1991 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
1992 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
1993 radeon_emit(cs
, va
);
1994 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1996 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1997 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1998 (struct r600_resource
*)info
->indirect
->buffer
,
2000 RADEON_PRIO_DRAW_INDIRECT
));
2004 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2005 radeon_emit(cs
, index_size
== 4 ?
2006 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
2007 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
2009 if (has_user_indices
) {
2010 unsigned size_bytes
= info
->count
*index_size
;
2011 unsigned size_dw
= align(size_bytes
, 4) / 4;
2012 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
2013 radeon_emit(cs
, info
->count
);
2014 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
2015 radeon_emit_array(cs
, info
->index
.user
, size_dw
);
2017 uint64_t va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
2019 if (likely(!info
->indirect
)) {
2020 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
2021 radeon_emit(cs
, va
);
2022 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2023 radeon_emit(cs
, info
->count
);
2024 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2025 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2026 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2027 (struct r600_resource
*)indexbuf
,
2029 RADEON_PRIO_INDEX_BUFFER
));
2032 uint32_t max_size
= (indexbuf
->width0
- index_offset
) / index_size
;
2034 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
2035 radeon_emit(cs
, va
);
2036 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2038 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2039 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2040 (struct r600_resource
*)indexbuf
,
2042 RADEON_PRIO_INDEX_BUFFER
));
2044 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2045 radeon_emit(cs
, max_size
);
2047 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
2048 radeon_emit(cs
, info
->indirect
->offset
);
2049 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2053 if (unlikely(info
->count_from_stream_output
)) {
2054 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
2055 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
2057 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
2059 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
2060 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
2061 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
2062 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
2063 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
2064 radeon_emit(cs
, 0); /* unused */
2066 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2067 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2068 t
->buf_filled_size
, RADEON_USAGE_READ
,
2069 RADEON_PRIO_SO_FILLED_SIZE
));
2072 if (likely(!info
->indirect
)) {
2073 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
2074 radeon_emit(cs
, info
->count
);
2077 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
2078 radeon_emit(cs
, info
->indirect
->offset
);
2080 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2081 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2084 /* SMX returns CONTEXT_DONE too early workaround */
2085 if (rctx
->b
.family
== CHIP_R600
||
2086 rctx
->b
.family
== CHIP_RV610
||
2087 rctx
->b
.family
== CHIP_RV630
||
2088 rctx
->b
.family
== CHIP_RV635
) {
2089 /* if we have gs shader or streamout
2090 we need to do a wait idle after every draw */
2091 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2092 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2096 /* ES ring rolling over at EOP - workaround */
2097 if (rctx
->b
.chip_class
== R600
) {
2098 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2099 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2103 if (rctx
->b
.chip_class
>= EVERGREEN
)
2104 evergreen_emit_atomic_buffer_save(rctx
, combined_atomics
, &atomic_used_mask
);
2106 if (rctx
->trace_buf
)
2107 eg_trace_emit(rctx
);
2109 if (rctx
->framebuffer
.do_update_surf_dirtiness
) {
2110 /* Set the depth buffer as dirty. */
2111 if (rctx
->framebuffer
.state
.zsbuf
) {
2112 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2113 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2115 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2117 if (rtex
->surface
.has_stencil
)
2118 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2120 if (rctx
->framebuffer
.compressed_cb_mask
) {
2121 struct pipe_surface
*surf
;
2122 struct r600_texture
*rtex
;
2123 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2126 unsigned i
= u_bit_scan(&mask
);
2127 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2128 rtex
= (struct r600_texture
*)surf
->texture
;
2130 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2134 rctx
->framebuffer
.do_update_surf_dirtiness
= false;
2137 if (index_size
&& indexbuf
!= info
->index
.resource
)
2138 pipe_resource_reference(&indexbuf
, NULL
);
2139 rctx
->b
.num_draw_calls
++;
2142 uint32_t r600_translate_stencil_op(int s_op
)
2145 case PIPE_STENCIL_OP_KEEP
:
2146 return V_028800_STENCIL_KEEP
;
2147 case PIPE_STENCIL_OP_ZERO
:
2148 return V_028800_STENCIL_ZERO
;
2149 case PIPE_STENCIL_OP_REPLACE
:
2150 return V_028800_STENCIL_REPLACE
;
2151 case PIPE_STENCIL_OP_INCR
:
2152 return V_028800_STENCIL_INCR
;
2153 case PIPE_STENCIL_OP_DECR
:
2154 return V_028800_STENCIL_DECR
;
2155 case PIPE_STENCIL_OP_INCR_WRAP
:
2156 return V_028800_STENCIL_INCR_WRAP
;
2157 case PIPE_STENCIL_OP_DECR_WRAP
:
2158 return V_028800_STENCIL_DECR_WRAP
;
2159 case PIPE_STENCIL_OP_INVERT
:
2160 return V_028800_STENCIL_INVERT
;
2162 R600_ERR("Unknown stencil op %d", s_op
);
2169 uint32_t r600_translate_fill(uint32_t func
)
2172 case PIPE_POLYGON_MODE_FILL
:
2174 case PIPE_POLYGON_MODE_LINE
:
2176 case PIPE_POLYGON_MODE_POINT
:
2184 unsigned r600_tex_wrap(unsigned wrap
)
2188 case PIPE_TEX_WRAP_REPEAT
:
2189 return V_03C000_SQ_TEX_WRAP
;
2190 case PIPE_TEX_WRAP_CLAMP
:
2191 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2192 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2193 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2194 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2195 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2196 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2197 return V_03C000_SQ_TEX_MIRROR
;
2198 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2199 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2200 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2201 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2202 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2203 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2207 unsigned r600_tex_mipfilter(unsigned filter
)
2210 case PIPE_TEX_MIPFILTER_NEAREST
:
2211 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2212 case PIPE_TEX_MIPFILTER_LINEAR
:
2213 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2215 case PIPE_TEX_MIPFILTER_NONE
:
2216 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2220 unsigned r600_tex_compare(unsigned compare
)
2224 case PIPE_FUNC_NEVER
:
2225 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2226 case PIPE_FUNC_LESS
:
2227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2228 case PIPE_FUNC_EQUAL
:
2229 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2230 case PIPE_FUNC_LEQUAL
:
2231 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2232 case PIPE_FUNC_GREATER
:
2233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2234 case PIPE_FUNC_NOTEQUAL
:
2235 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2236 case PIPE_FUNC_GEQUAL
:
2237 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2238 case PIPE_FUNC_ALWAYS
:
2239 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2243 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2245 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2246 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2248 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2249 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2252 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2254 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2255 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2257 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2258 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2259 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2260 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2261 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2264 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2267 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2268 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2273 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2274 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2275 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2276 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2279 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2280 const unsigned char *swizzle_view
,
2284 unsigned char swizzle
[4];
2285 unsigned result
= 0;
2286 const uint32_t tex_swizzle_shift
[4] = {
2289 const uint32_t vtx_swizzle_shift
[4] = {
2292 const uint32_t swizzle_bit
[4] = {
2295 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2298 swizzle_shift
= vtx_swizzle_shift
;
2301 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2303 memcpy(swizzle
, swizzle_format
, 4);
2307 for (i
= 0; i
< 4; i
++) {
2308 switch (swizzle
[i
]) {
2309 case PIPE_SWIZZLE_Y
:
2310 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2312 case PIPE_SWIZZLE_Z
:
2313 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2315 case PIPE_SWIZZLE_W
:
2316 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2318 case PIPE_SWIZZLE_0
:
2319 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2321 case PIPE_SWIZZLE_1
:
2322 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2324 default: /* PIPE_SWIZZLE_X */
2325 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2331 /* texture format translate */
2332 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2333 enum pipe_format format
,
2334 const unsigned char *swizzle_view
,
2335 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2336 bool do_endian_swap
)
2338 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2339 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2340 const struct util_format_description
*desc
;
2341 boolean uniform
= TRUE
;
2342 bool is_srgb_valid
= FALSE
;
2343 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2344 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2345 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2346 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2347 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2350 const uint32_t sign_bit
[4] = {
2351 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2352 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2353 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2354 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2357 /* Need to replace the specified texture formats in case of big-endian.
2358 * These formats are formats that have channels with number of bits
2359 * not divisible by 8.
2360 * Mesa conversion functions don't swap bits for those formats, and because
2361 * we transmit this over a serial bus to the GPU (PCIe), the
2362 * bit-endianess is important!!!
2363 * In case we have an "opposite" format, just use that for the swizzling
2364 * information. If we don't have such an "opposite" format, we need
2365 * to use a fixed swizzle info instead (see below)
2367 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2368 format
= PIPE_FORMAT_A4R4_UNORM
;
2370 desc
= util_format_description(format
);
2374 /* Depth and stencil swizzling is handled separately. */
2375 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2376 /* Need to check for specific texture formats that don't have
2377 * an "opposite" format we can use. For those formats, we directly
2378 * specify the swizzling, which is the LE swizzling as defined in
2381 if (do_endian_swap
) {
2382 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2383 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2384 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2385 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2386 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2387 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2389 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2391 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2395 /* Colorspace (return non-RGB formats directly). */
2396 switch (desc
->colorspace
) {
2397 /* Depth stencil formats */
2398 case UTIL_FORMAT_COLORSPACE_ZS
:
2400 /* Depth sampler formats. */
2401 case PIPE_FORMAT_Z16_UNORM
:
2402 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2405 case PIPE_FORMAT_Z24X8_UNORM
:
2406 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2407 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2410 case PIPE_FORMAT_X8Z24_UNORM
:
2411 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2412 if (rscreen
->b
.chip_class
< EVERGREEN
)
2414 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2417 case PIPE_FORMAT_Z32_FLOAT
:
2418 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2419 result
= FMT_32_FLOAT
;
2421 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2422 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2423 result
= FMT_X24_8_32_FLOAT
;
2425 /* Stencil sampler formats. */
2426 case PIPE_FORMAT_S8_UINT
:
2427 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2428 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2431 case PIPE_FORMAT_X24S8_UINT
:
2432 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2433 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2436 case PIPE_FORMAT_S8X24_UINT
:
2437 if (rscreen
->b
.chip_class
< EVERGREEN
)
2439 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2440 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2443 case PIPE_FORMAT_X32_S8X24_UINT
:
2444 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2445 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2446 result
= FMT_X24_8_32_FLOAT
;
2452 case UTIL_FORMAT_COLORSPACE_YUV
:
2453 yuv_format
|= (1 << 30);
2455 case PIPE_FORMAT_UYVY
:
2456 case PIPE_FORMAT_YUYV
:
2460 goto out_unknown
; /* XXX */
2462 case UTIL_FORMAT_COLORSPACE_SRGB
:
2463 word4
|= S_038010_FORCE_DEGAMMA(1);
2470 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2472 case PIPE_FORMAT_RGTC1_SNORM
:
2473 case PIPE_FORMAT_LATC1_SNORM
:
2474 word4
|= sign_bit
[0];
2475 case PIPE_FORMAT_RGTC1_UNORM
:
2476 case PIPE_FORMAT_LATC1_UNORM
:
2479 case PIPE_FORMAT_RGTC2_SNORM
:
2480 case PIPE_FORMAT_LATC2_SNORM
:
2481 word4
|= sign_bit
[0] | sign_bit
[1];
2482 case PIPE_FORMAT_RGTC2_UNORM
:
2483 case PIPE_FORMAT_LATC2_UNORM
:
2491 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2493 case PIPE_FORMAT_DXT1_RGB
:
2494 case PIPE_FORMAT_DXT1_RGBA
:
2495 case PIPE_FORMAT_DXT1_SRGB
:
2496 case PIPE_FORMAT_DXT1_SRGBA
:
2498 is_srgb_valid
= TRUE
;
2500 case PIPE_FORMAT_DXT3_RGBA
:
2501 case PIPE_FORMAT_DXT3_SRGBA
:
2503 is_srgb_valid
= TRUE
;
2505 case PIPE_FORMAT_DXT5_RGBA
:
2506 case PIPE_FORMAT_DXT5_SRGBA
:
2508 is_srgb_valid
= TRUE
;
2515 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2516 if (rscreen
->b
.chip_class
< EVERGREEN
)
2520 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2521 case PIPE_FORMAT_BPTC_SRGBA
:
2523 is_srgb_valid
= TRUE
;
2525 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2526 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2528 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2536 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2538 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2539 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2542 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2543 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2551 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2552 result
= FMT_5_9_9_9_SHAREDEXP
;
2554 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2555 result
= FMT_10_11_11_FLOAT
;
2560 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2561 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2562 word4
|= sign_bit
[i
];
2566 /* R8G8Bx_SNORM - XXX CxV8U8 */
2568 /* See whether the components are of the same size. */
2569 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2570 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2573 /* Non-uniform formats. */
2575 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2576 desc
->channel
[0].pure_integer
)
2577 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2578 switch(desc
->nr_channels
) {
2580 if (desc
->channel
[0].size
== 5 &&
2581 desc
->channel
[1].size
== 6 &&
2582 desc
->channel
[2].size
== 5) {
2588 if (desc
->channel
[0].size
== 5 &&
2589 desc
->channel
[1].size
== 5 &&
2590 desc
->channel
[2].size
== 5 &&
2591 desc
->channel
[3].size
== 1) {
2592 result
= FMT_1_5_5_5
;
2595 if (desc
->channel
[0].size
== 10 &&
2596 desc
->channel
[1].size
== 10 &&
2597 desc
->channel
[2].size
== 10 &&
2598 desc
->channel
[3].size
== 2) {
2599 result
= FMT_2_10_10_10
;
2607 /* Find the first non-VOID channel. */
2608 for (i
= 0; i
< 4; i
++) {
2609 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2617 /* uniform formats */
2618 switch (desc
->channel
[i
].type
) {
2619 case UTIL_FORMAT_TYPE_UNSIGNED
:
2620 case UTIL_FORMAT_TYPE_SIGNED
:
2622 if (!desc
->channel
[i
].normalized
&&
2623 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2627 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2628 desc
->channel
[i
].pure_integer
)
2629 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2631 switch (desc
->channel
[i
].size
) {
2633 switch (desc
->nr_channels
) {
2638 result
= FMT_4_4_4_4
;
2643 switch (desc
->nr_channels
) {
2651 result
= FMT_8_8_8_8
;
2652 is_srgb_valid
= TRUE
;
2657 switch (desc
->nr_channels
) {
2665 result
= FMT_16_16_16_16
;
2670 switch (desc
->nr_channels
) {
2678 result
= FMT_32_32_32_32
;
2684 case UTIL_FORMAT_TYPE_FLOAT
:
2685 switch (desc
->channel
[i
].size
) {
2687 switch (desc
->nr_channels
) {
2689 result
= FMT_16_FLOAT
;
2692 result
= FMT_16_16_FLOAT
;
2695 result
= FMT_16_16_16_16_FLOAT
;
2700 switch (desc
->nr_channels
) {
2702 result
= FMT_32_FLOAT
;
2705 result
= FMT_32_32_FLOAT
;
2708 result
= FMT_32_32_32_32_FLOAT
;
2717 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2722 *yuv_format_p
= yuv_format
;
2725 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2729 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
2730 bool do_endian_swap
)
2732 const struct util_format_description
*desc
= util_format_description(format
);
2733 int channel
= util_format_get_first_non_void_channel(format
);
2738 #define HAS_SIZE(x,y,z,w) \
2739 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2740 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2742 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2743 return V_0280A0_COLOR_10_11_11_FLOAT
;
2745 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2749 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2751 switch (desc
->nr_channels
) {
2753 switch (desc
->channel
[0].size
) {
2755 return V_0280A0_COLOR_8
;
2758 return V_0280A0_COLOR_16_FLOAT
;
2760 return V_0280A0_COLOR_16
;
2763 return V_0280A0_COLOR_32_FLOAT
;
2765 return V_0280A0_COLOR_32
;
2769 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2770 switch (desc
->channel
[0].size
) {
2773 return V_0280A0_COLOR_4_4
;
2775 return ~0U; /* removed on Evergreen */
2777 return V_0280A0_COLOR_8_8
;
2780 return V_0280A0_COLOR_16_16_FLOAT
;
2782 return V_0280A0_COLOR_16_16
;
2785 return V_0280A0_COLOR_32_32_FLOAT
;
2787 return V_0280A0_COLOR_32_32
;
2789 } else if (HAS_SIZE(8,24,0,0)) {
2790 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
2791 } else if (HAS_SIZE(24,8,0,0)) {
2792 return V_0280A0_COLOR_8_24
;
2796 if (HAS_SIZE(5,6,5,0)) {
2797 return V_0280A0_COLOR_5_6_5
;
2798 } else if (HAS_SIZE(32,8,24,0)) {
2799 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2803 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2804 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2805 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2806 switch (desc
->channel
[0].size
) {
2808 return V_0280A0_COLOR_4_4_4_4
;
2810 return V_0280A0_COLOR_8_8_8_8
;
2813 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2815 return V_0280A0_COLOR_16_16_16_16
;
2818 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2820 return V_0280A0_COLOR_32_32_32_32
;
2822 } else if (HAS_SIZE(5,5,5,1)) {
2823 return V_0280A0_COLOR_1_5_5_5
;
2824 } else if (HAS_SIZE(10,10,10,2)) {
2825 return V_0280A0_COLOR_2_10_10_10
;
2832 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
2834 if (R600_BIG_ENDIAN
) {
2835 switch(colorformat
) {
2836 /* 8-bit buffers. */
2837 case V_0280A0_COLOR_4_4
:
2838 case V_0280A0_COLOR_8
:
2841 /* 16-bit buffers. */
2842 case V_0280A0_COLOR_8_8
:
2844 * No need to do endian swaps on array formats,
2845 * as mesa<-->pipe formats conversion take into account
2850 case V_0280A0_COLOR_5_6_5
:
2851 case V_0280A0_COLOR_1_5_5_5
:
2852 case V_0280A0_COLOR_4_4_4_4
:
2853 case V_0280A0_COLOR_16
:
2854 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
2856 /* 32-bit buffers. */
2857 case V_0280A0_COLOR_8_8_8_8
:
2859 * No need to do endian swaps on array formats,
2860 * as mesa<-->pipe formats conversion take into account
2865 case V_0280A0_COLOR_2_10_10_10
:
2866 case V_0280A0_COLOR_8_24
:
2867 case V_0280A0_COLOR_24_8
:
2868 case V_0280A0_COLOR_32_FLOAT
:
2869 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
2871 case V_0280A0_COLOR_16_16_FLOAT
:
2872 case V_0280A0_COLOR_16_16
:
2873 return ENDIAN_8IN16
;
2875 /* 64-bit buffers. */
2876 case V_0280A0_COLOR_16_16_16_16
:
2877 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2878 return ENDIAN_8IN16
;
2880 case V_0280A0_COLOR_32_32_FLOAT
:
2881 case V_0280A0_COLOR_32_32
:
2882 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2883 return ENDIAN_8IN32
;
2885 /* 128-bit buffers. */
2886 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2887 case V_0280A0_COLOR_32_32_32_32
:
2888 return ENDIAN_8IN32
;
2890 return ENDIAN_NONE
; /* Unsupported. */
2897 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2899 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2900 struct r600_resource
*rbuffer
= r600_resource(buf
);
2901 unsigned i
, shader
, mask
;
2902 struct r600_pipe_sampler_view
*view
;
2904 /* Reallocate the buffer in the same pipe_resource. */
2905 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
2907 /* We changed the buffer, now we need to bind it where the old one was bound. */
2908 /* Vertex buffers. */
2909 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2911 i
= u_bit_scan(&mask
);
2912 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
.resource
== &rbuffer
->b
.b
) {
2913 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2914 r600_vertex_buffers_dirty(rctx
);
2917 /* Streamout buffers. */
2918 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2919 if (rctx
->b
.streamout
.targets
[i
] &&
2920 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2921 if (rctx
->b
.streamout
.begin_emitted
) {
2922 r600_emit_streamout_end(&rctx
->b
);
2924 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2925 r600_streamout_buffers_dirty(&rctx
->b
);
2929 /* Constant buffers. */
2930 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2931 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2933 uint32_t mask
= state
->enabled_mask
;
2936 unsigned i
= u_bit_scan(&mask
);
2937 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2939 state
->dirty_mask
|= 1 << i
;
2943 r600_constant_buffers_dirty(rctx
, state
);
2947 /* Texture buffer objects - update the virtual addresses in descriptors. */
2948 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
2949 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2950 uint64_t offset
= view
->base
.u
.buf
.offset
;
2951 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2953 view
->tex_resource_words
[0] = va
;
2954 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2955 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2958 /* Texture buffer objects - make bindings dirty if needed. */
2959 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2960 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2962 uint32_t mask
= state
->enabled_mask
;
2965 unsigned i
= u_bit_scan(&mask
);
2966 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2968 state
->dirty_mask
|= 1 << i
;
2972 r600_sampler_views_dirty(rctx
, state
);
2977 static void r600_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
2979 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2981 /* Pipeline stat & streamout queries. */
2983 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
2984 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
2986 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
2987 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
2990 /* Occlusion queries. */
2991 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
2992 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
2993 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2997 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2998 bool include_draw_vbo
)
3000 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
3003 /* keep this at the end of this file, please */
3004 void r600_init_common_state_functions(struct r600_context
*rctx
)
3006 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
3007 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
3008 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
3009 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
3010 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
3011 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
3012 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
3013 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
3014 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
3015 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
3016 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
3017 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
3018 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
3019 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
3020 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
3021 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
3022 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
3023 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
3024 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
3025 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
3026 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
3027 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
3028 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
3029 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
3030 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
3031 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
3032 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
3033 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
3034 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
3035 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
3036 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
3037 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
3038 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
3039 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
3040 rctx
->b
.b
.memory_barrier
= r600_memory_barrier
;
3041 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
3042 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
3043 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
3044 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
3045 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
3046 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;