2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
98 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
99 R600_CONTEXT_FLUSH_AND_INV_CB
|
100 R600_CONTEXT_FLUSH_AND_INV
|
101 R600_CONTEXT_WAIT_3D_IDLE
;
104 static unsigned r600_conv_pipe_prim(unsigned prim
)
106 static const unsigned prim_conv
[] = {
107 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
108 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
109 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
110 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
111 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
112 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
113 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
114 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
115 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
116 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
117 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
118 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
119 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
120 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
121 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
122 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
124 assert(prim
< ARRAY_SIZE(prim_conv
));
125 return prim_conv
[prim
];
128 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
130 static const int prim_conv
[] = {
131 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
132 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
133 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
134 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
135 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
136 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
138 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
139 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
140 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
141 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
145 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
146 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
148 assert(mode
< ARRAY_SIZE(prim_conv
));
150 return prim_conv
[mode
];
153 /* common state between evergreen and r600 */
155 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
156 struct r600_blend_state
*blend
, bool blend_disable
)
158 unsigned color_control
;
159 bool update_cb
= false;
161 rctx
->alpha_to_one
= blend
->alpha_to_one
;
162 rctx
->dual_src_blend
= blend
->dual_src_blend
;
164 if (!blend_disable
) {
165 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
166 color_control
= blend
->cb_color_control
;
168 /* Blending is disabled. */
169 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
170 color_control
= blend
->cb_color_control_no_blend
;
173 /* Update derived states. */
174 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
175 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
178 if (rctx
->b
.chip_class
<= R700
&&
179 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
180 rctx
->cb_misc_state
.cb_color_control
= color_control
;
183 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
184 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
188 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
190 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
191 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
192 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
196 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
198 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
199 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
202 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
206 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
209 static void r600_set_blend_color(struct pipe_context
*ctx
,
210 const struct pipe_blend_color
*state
)
212 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
214 rctx
->blend_color
.state
= *state
;
215 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
218 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
220 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
221 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
223 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
224 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
225 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
226 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
227 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
230 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
232 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
233 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
235 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
236 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
237 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
238 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
239 if (a
->last_draw_was_indirect
) {
240 a
->last_draw_was_indirect
= false;
241 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
245 static void r600_set_clip_state(struct pipe_context
*ctx
,
246 const struct pipe_clip_state
*state
)
248 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
250 rctx
->clip_state
.state
= *state
;
251 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
252 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
255 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
256 const struct r600_stencil_ref
*state
)
258 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
260 rctx
->stencil_ref
.state
= *state
;
261 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
264 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
266 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
267 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
269 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
270 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
271 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
272 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
273 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
274 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
275 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
276 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
277 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
280 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
281 const struct pipe_stencil_ref
*state
)
283 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
284 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
285 struct r600_stencil_ref ref
;
287 rctx
->stencil_ref
.pipe_state
= *state
;
292 ref
.ref_value
[0] = state
->ref_value
[0];
293 ref
.ref_value
[1] = state
->ref_value
[1];
294 ref
.valuemask
[0] = dsa
->valuemask
[0];
295 ref
.valuemask
[1] = dsa
->valuemask
[1];
296 ref
.writemask
[0] = dsa
->writemask
[0];
297 ref
.writemask
[1] = dsa
->writemask
[1];
299 r600_set_stencil_ref(ctx
, &ref
);
302 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
304 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
305 struct r600_dsa_state
*dsa
= state
;
306 struct r600_stencil_ref ref
;
309 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
313 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
315 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
316 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
317 ref
.valuemask
[0] = dsa
->valuemask
[0];
318 ref
.valuemask
[1] = dsa
->valuemask
[1];
319 ref
.writemask
[0] = dsa
->writemask
[0];
320 ref
.writemask
[1] = dsa
->writemask
[1];
321 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
322 rctx
->zwritemask
= dsa
->zwritemask
;
323 if (rctx
->b
.chip_class
>= EVERGREEN
) {
324 /* work around some issue when not writing to zbuffer
325 * we are having lockup on evergreen so do not enable
326 * hyperz when not writing zbuffer
328 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
332 r600_set_stencil_ref(ctx
, &ref
);
334 /* Update alphatest state. */
335 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
336 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
337 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
338 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
339 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
343 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
345 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
346 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
351 rctx
->rasterizer
= rs
;
353 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
355 if (rs
->offset_enable
&&
356 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
357 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
358 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
359 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
360 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
361 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
362 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
365 /* Update clip_misc_state. */
366 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
367 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
368 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
369 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
370 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
373 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
375 /* Re-emit PA_SC_LINE_STIPPLE. */
376 rctx
->last_primitive_type
= -1;
379 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
381 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
383 r600_release_command_buffer(&rs
->buffer
);
387 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
388 struct pipe_sampler_view
*state
)
390 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
392 if (view
->tex_resource
->gpu_address
&&
393 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
394 LIST_DELINIT(&view
->list
);
396 pipe_resource_reference(&state
->texture
, NULL
);
400 void r600_sampler_states_dirty(struct r600_context
*rctx
,
401 struct r600_sampler_states
*state
)
403 if (state
->dirty_mask
) {
404 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
405 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
408 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
409 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
410 r600_mark_atom_dirty(rctx
, &state
->atom
);
414 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
415 enum pipe_shader_type shader
,
417 unsigned count
, void **states
)
419 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
420 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
421 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
422 int seamless_cube_map
= -1;
424 /* This sets 1-bit for states with index >= count. */
425 uint32_t disable_mask
= ~((1ull << count
) - 1);
426 /* These are the new states set by this function. */
427 uint32_t new_mask
= 0;
429 assert(start
== 0); /* XXX fix below */
436 for (i
= 0; i
< count
; i
++) {
437 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
439 if (rstate
== dst
->states
.states
[i
]) {
444 if (rstate
->border_color_use
) {
445 dst
->states
.has_bordercolor_mask
|= 1 << i
;
447 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
449 seamless_cube_map
= rstate
->seamless_cube_map
;
453 disable_mask
|= 1 << i
;
457 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
458 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
460 dst
->states
.enabled_mask
&= ~disable_mask
;
461 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
462 dst
->states
.enabled_mask
|= new_mask
;
463 dst
->states
.dirty_mask
|= new_mask
;
464 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
466 r600_sampler_states_dirty(rctx
, &dst
->states
);
468 /* Seamless cubemap state. */
469 if (rctx
->b
.chip_class
<= R700
&&
470 seamless_cube_map
!= -1 &&
471 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
472 /* change in TA_CNTL_AUX need a pipeline flush */
473 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
474 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
475 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
479 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
484 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
486 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
487 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
489 if (rctx
->blend_state
.cso
== state
) {
490 ctx
->bind_blend_state(ctx
, NULL
);
493 r600_release_command_buffer(&blend
->buffer
);
494 r600_release_command_buffer(&blend
->buffer_no_blend
);
498 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
500 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
501 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
503 if (rctx
->dsa_state
.cso
== state
) {
504 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
507 r600_release_command_buffer(&dsa
->buffer
);
511 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
513 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
515 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
518 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
520 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
521 r600_resource_reference(&shader
->buffer
, NULL
);
525 static void r600_set_index_buffer(struct pipe_context
*ctx
,
526 const struct pipe_index_buffer
*ib
)
528 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
531 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
532 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
533 r600_context_add_resource_size(ctx
, ib
->buffer
);
535 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
539 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
541 if (rctx
->vertex_buffer_state
.dirty_mask
) {
542 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
543 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
544 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
548 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
549 unsigned start_slot
, unsigned count
,
550 const struct pipe_vertex_buffer
*input
)
552 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
553 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
554 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
556 uint32_t disable_mask
= 0;
557 /* These are the new buffers set by this function. */
558 uint32_t new_buffer_mask
= 0;
560 /* Set vertex buffers. */
562 for (i
= 0; i
< count
; i
++) {
563 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
564 if (input
[i
].buffer
) {
565 vb
[i
].stride
= input
[i
].stride
;
566 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
567 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
568 new_buffer_mask
|= 1 << i
;
569 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
571 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
572 disable_mask
|= 1 << i
;
577 for (i
= 0; i
< count
; i
++) {
578 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
580 disable_mask
= ((1ull << count
) - 1);
583 disable_mask
<<= start_slot
;
584 new_buffer_mask
<<= start_slot
;
586 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
587 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
588 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
589 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
591 r600_vertex_buffers_dirty(rctx
);
594 void r600_sampler_views_dirty(struct r600_context
*rctx
,
595 struct r600_samplerview_state
*state
)
597 if (state
->dirty_mask
) {
598 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
599 util_bitcount(state
->dirty_mask
);
600 r600_mark_atom_dirty(rctx
, &state
->atom
);
604 static void r600_set_sampler_views(struct pipe_context
*pipe
,
605 enum pipe_shader_type shader
,
606 unsigned start
, unsigned count
,
607 struct pipe_sampler_view
**views
)
609 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
610 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
611 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
612 uint32_t dirty_sampler_states_mask
= 0;
614 /* This sets 1-bit for textures with index >= count. */
615 uint32_t disable_mask
= ~((1ull << count
) - 1);
616 /* These are the new textures set by this function. */
617 uint32_t new_mask
= 0;
619 /* Set textures with index >= count to NULL. */
620 uint32_t remaining_mask
;
622 assert(start
== 0); /* XXX fix below */
629 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
631 while (remaining_mask
) {
632 i
= u_bit_scan(&remaining_mask
);
633 assert(dst
->views
.views
[i
]);
635 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
638 for (i
= 0; i
< count
; i
++) {
639 if (rviews
[i
] == dst
->views
.views
[i
]) {
644 struct r600_texture
*rtex
=
645 (struct r600_texture
*)rviews
[i
]->base
.texture
;
646 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
648 if (!is_buffer
&& rtex
->db_compatible
) {
649 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
651 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
654 /* Track compressed colorbuffers. */
655 if (!is_buffer
&& rtex
->cmask
.size
) {
656 dst
->views
.compressed_colortex_mask
|= 1 << i
;
658 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
661 /* Changing from array to non-arrays textures and vice versa requires
662 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
663 if (rctx
->b
.chip_class
<= R700
&&
664 (dst
->states
.enabled_mask
& (1 << i
)) &&
665 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
666 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
667 dirty_sampler_states_mask
|= 1 << i
;
670 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
672 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
674 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
675 disable_mask
|= 1 << i
;
679 dst
->views
.enabled_mask
&= ~disable_mask
;
680 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
681 dst
->views
.enabled_mask
|= new_mask
;
682 dst
->views
.dirty_mask
|= new_mask
;
683 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
684 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
685 dst
->views
.dirty_buffer_constants
= TRUE
;
686 r600_sampler_views_dirty(rctx
, &dst
->views
);
688 if (dirty_sampler_states_mask
) {
689 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
690 r600_sampler_states_dirty(rctx
, &dst
->states
);
694 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
696 uint32_t mask
= views
->enabled_mask
;
699 unsigned i
= u_bit_scan(&mask
);
700 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
702 if (res
&& res
->target
!= PIPE_BUFFER
) {
703 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
705 if (rtex
->cmask
.size
) {
706 views
->compressed_colortex_mask
|= 1 << i
;
708 views
->compressed_colortex_mask
&= ~(1 << i
);
714 /* Compute the key for the hw shader variant */
715 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
716 const struct r600_pipe_shader_selector
*sel
,
717 union r600_shader_key
*key
)
719 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
720 memset(key
, 0, sizeof(*key
));
723 case PIPE_SHADER_VERTEX
: {
724 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
726 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
728 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
729 key
->vs
.as_gs_a
= true;
730 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
734 case PIPE_SHADER_GEOMETRY
:
736 case PIPE_SHADER_FRAGMENT
: {
737 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
738 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
739 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
740 !rctx
->framebuffer
.cb0_is_integer
;
741 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
742 /* Dual-source blending only makes sense with nr_cbufs == 1. */
743 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
744 key
->ps
.nr_cbufs
= 2;
747 case PIPE_SHADER_TESS_EVAL
:
748 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
750 case PIPE_SHADER_TESS_CTRL
:
751 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
758 /* Select the hw shader variant depending on the current state.
759 * (*dirty) is set to 1 if current variant was changed */
760 static int r600_shader_select(struct pipe_context
*ctx
,
761 struct r600_pipe_shader_selector
* sel
,
764 union r600_shader_key key
;
765 struct r600_pipe_shader
* shader
= NULL
;
768 r600_shader_selector_key(ctx
, sel
, &key
);
770 /* Check if we don't need to change anything.
771 * This path is also used for most shaders that don't need multiple
772 * variants, it will cost just a computation of the key and this
774 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
778 /* lookup if we have other variants in the list */
779 if (sel
->num_shaders
> 1) {
780 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
782 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
788 p
->next_variant
= c
->next_variant
;
793 if (unlikely(!shader
)) {
794 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
795 shader
->selector
= sel
;
797 r
= r600_pipe_shader_create(ctx
, shader
, key
);
799 R600_ERR("Failed to build shader variant (type=%u) %d\n",
806 /* We don't know the value of nr_ps_max_color_exports until we built
807 * at least one variant, so we may need to recompute the key after
808 * building first variant. */
809 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
810 sel
->num_shaders
== 0) {
811 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
812 r600_shader_selector_key(ctx
, sel
, &key
);
815 memcpy(&shader
->key
, &key
, sizeof(key
));
822 shader
->next_variant
= sel
->current
;
823 sel
->current
= shader
;
828 static void *r600_create_shader_state(struct pipe_context
*ctx
,
829 const struct pipe_shader_state
*state
,
830 unsigned pipe_shader_type
)
832 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
835 sel
->type
= pipe_shader_type
;
836 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
837 sel
->so
= state
->stream_output
;
838 tgsi_scan_shader(state
->tokens
, &sel
->info
);
840 switch (pipe_shader_type
) {
841 case PIPE_SHADER_GEOMETRY
:
842 sel
->gs_output_prim
=
843 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
844 sel
->gs_max_out_vertices
=
845 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
846 sel
->gs_num_invocations
=
847 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
849 case PIPE_SHADER_VERTEX
:
850 case PIPE_SHADER_TESS_CTRL
:
851 sel
->lds_patch_outputs_written_mask
= 0;
852 sel
->lds_outputs_written_mask
= 0;
854 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
855 unsigned name
= sel
->info
.output_semantic_name
[i
];
856 unsigned index
= sel
->info
.output_semantic_index
[i
];
859 case TGSI_SEMANTIC_TESSINNER
:
860 case TGSI_SEMANTIC_TESSOUTER
:
861 case TGSI_SEMANTIC_PATCH
:
862 sel
->lds_patch_outputs_written_mask
|=
863 1llu << r600_get_lds_unique_index(name
, index
);
866 sel
->lds_outputs_written_mask
|=
867 1llu << r600_get_lds_unique_index(name
, index
);
878 static void *r600_create_ps_state(struct pipe_context
*ctx
,
879 const struct pipe_shader_state
*state
)
881 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
884 static void *r600_create_vs_state(struct pipe_context
*ctx
,
885 const struct pipe_shader_state
*state
)
887 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
890 static void *r600_create_gs_state(struct pipe_context
*ctx
,
891 const struct pipe_shader_state
*state
)
893 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
896 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
897 const struct pipe_shader_state
*state
)
899 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
902 static void *r600_create_tes_state(struct pipe_context
*ctx
,
903 const struct pipe_shader_state
*state
)
905 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
908 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
910 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
913 state
= rctx
->dummy_pixel_shader
;
915 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
918 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
921 return &rctx
->gs_shader
->info
;
922 else if (rctx
->tes_shader
)
923 return &rctx
->tes_shader
->info
;
924 else if (rctx
->vs_shader
)
925 return &rctx
->vs_shader
->info
;
930 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
932 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
934 if (!state
|| rctx
->vs_shader
== state
)
937 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
938 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
939 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
942 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
944 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
946 if (state
== rctx
->gs_shader
)
949 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
950 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
954 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
957 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
959 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
961 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
964 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
966 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
968 if (state
== rctx
->tes_shader
)
971 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
972 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
976 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
979 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
980 struct r600_pipe_shader_selector
*sel
)
982 struct r600_pipe_shader
*p
= sel
->current
, *c
;
985 r600_pipe_shader_destroy(ctx
, p
);
995 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
997 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
998 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1000 if (rctx
->ps_shader
== sel
) {
1001 rctx
->ps_shader
= NULL
;
1004 r600_delete_shader_selector(ctx
, sel
);
1007 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1009 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1010 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1012 if (rctx
->vs_shader
== sel
) {
1013 rctx
->vs_shader
= NULL
;
1016 r600_delete_shader_selector(ctx
, sel
);
1020 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1022 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1023 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1025 if (rctx
->gs_shader
== sel
) {
1026 rctx
->gs_shader
= NULL
;
1029 r600_delete_shader_selector(ctx
, sel
);
1032 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1034 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1035 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1037 if (rctx
->tcs_shader
== sel
) {
1038 rctx
->tcs_shader
= NULL
;
1041 r600_delete_shader_selector(ctx
, sel
);
1044 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1046 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1047 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1049 if (rctx
->tes_shader
== sel
) {
1050 rctx
->tes_shader
= NULL
;
1053 r600_delete_shader_selector(ctx
, sel
);
1056 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1058 if (state
->dirty_mask
) {
1059 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1060 : util_bitcount(state
->dirty_mask
)*19;
1061 r600_mark_atom_dirty(rctx
, &state
->atom
);
1065 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1066 enum pipe_shader_type shader
, uint index
,
1067 const struct pipe_constant_buffer
*input
)
1069 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1070 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1071 struct pipe_constant_buffer
*cb
;
1074 /* Note that the state tracker can unbind constant buffers by
1075 * passing NULL here.
1077 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1078 state
->enabled_mask
&= ~(1 << index
);
1079 state
->dirty_mask
&= ~(1 << index
);
1080 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1084 cb
= &state
->cb
[index
];
1085 cb
->buffer_size
= input
->buffer_size
;
1087 ptr
= input
->user_buffer
;
1090 /* Upload the user buffer. */
1091 if (R600_BIG_ENDIAN
) {
1093 unsigned i
, size
= input
->buffer_size
;
1095 if (!(tmpPtr
= malloc(size
))) {
1096 R600_ERR("Failed to allocate BE swap buffer.\n");
1100 for (i
= 0; i
< size
/ 4; ++i
) {
1101 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1104 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1105 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1108 u_upload_data(ctx
->stream_uploader
, 0,
1109 input
->buffer_size
, 256, ptr
,
1110 &cb
->buffer_offset
, &cb
->buffer
);
1112 /* account it in gtt */
1113 rctx
->b
.gtt
+= input
->buffer_size
;
1115 /* Setup the hw buffer. */
1116 cb
->buffer_offset
= input
->buffer_offset
;
1117 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1118 r600_context_add_resource_size(ctx
, input
->buffer
);
1121 state
->enabled_mask
|= 1 << index
;
1122 state
->dirty_mask
|= 1 << index
;
1123 r600_constant_buffers_dirty(rctx
, state
);
1126 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1128 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1130 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1133 rctx
->sample_mask
.sample_mask
= sample_mask
;
1134 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1137 static void r600_update_driver_const_buffers(struct r600_context
*rctx
)
1141 struct pipe_constant_buffer cb
;
1142 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
1143 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1144 if (!info
->vs_ucp_dirty
&&
1145 !info
->texture_const_dirty
&&
1146 !info
->ps_sample_pos_dirty
)
1149 ptr
= info
->constants
;
1150 size
= info
->alloc_size
;
1151 if (info
->vs_ucp_dirty
) {
1152 assert(sh
== PIPE_SHADER_VERTEX
);
1154 ptr
= rctx
->clip_state
.state
.ucp
;
1155 size
= R600_UCP_SIZE
;
1157 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1159 info
->vs_ucp_dirty
= false;
1162 if (info
->ps_sample_pos_dirty
) {
1163 assert(sh
== PIPE_SHADER_FRAGMENT
);
1165 ptr
= rctx
->sample_positions
;
1166 size
= R600_UCP_SIZE
;
1168 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1170 info
->ps_sample_pos_dirty
= false;
1173 if (info
->texture_const_dirty
) {
1176 if (sh
== PIPE_SHADER_VERTEX
)
1177 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1178 if (sh
== PIPE_SHADER_FRAGMENT
)
1179 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1181 info
->texture_const_dirty
= false;
1184 cb
.user_buffer
= ptr
;
1185 cb
.buffer_offset
= 0;
1186 cb
.buffer_size
= size
;
1187 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1188 pipe_resource_reference(&cb
.buffer
, NULL
);
1192 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1193 int array_size
, uint32_t *base_offset
)
1195 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1196 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1197 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1198 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1200 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1201 info
->texture_const_dirty
= true;
1202 *base_offset
= R600_UCP_SIZE
;
1203 return info
->constants
;
1206 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1207 * doesn't require full swizzles it does need masking and setting alpha
1208 * to one, so we setup a set of 5 constants with the masks + alpha value
1209 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1210 * then OR the alpha with the value given here.
1211 * We use a 6th constant to store the txq buffer size in
1212 * we use 7th slot for number of cube layers in a cube map array.
1214 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1216 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1218 uint32_t array_size
;
1220 uint32_t *constants
;
1221 uint32_t base_offset
;
1222 if (!samplers
->views
.dirty_buffer_constants
)
1225 samplers
->views
.dirty_buffer_constants
= FALSE
;
1227 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1228 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1230 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1232 for (i
= 0; i
< bits
; i
++) {
1233 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1234 int offset
= (base_offset
/ 4) + i
* 8;
1235 const struct util_format_description
*desc
;
1236 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1238 for (j
= 0; j
< 4; j
++)
1239 if (j
< desc
->nr_channels
)
1240 constants
[offset
+j
] = 0xffffffff;
1242 constants
[offset
+j
] = 0x0;
1243 if (desc
->nr_channels
< 4) {
1244 if (desc
->channel
[0].pure_integer
)
1245 constants
[offset
+4] = 1;
1247 constants
[offset
+4] = fui(1.0);
1249 constants
[offset
+ 4] = 0;
1251 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1252 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1258 /* On evergreen we store two values
1259 * 1. buffer size for TXQ
1260 * 2. number of cube layers in a cube map array.
1262 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1264 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1266 uint32_t array_size
;
1268 uint32_t *constants
;
1269 uint32_t base_offset
;
1270 if (!samplers
->views
.dirty_buffer_constants
)
1273 samplers
->views
.dirty_buffer_constants
= FALSE
;
1275 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1276 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1278 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1281 for (i
= 0; i
< bits
; i
++) {
1282 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1283 uint32_t offset
= (base_offset
/ 4) + i
* 2;
1284 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1285 constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1290 /* set sample xy locations as array of fragment shader constants */
1291 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1294 struct pipe_context
*ctx
= &rctx
->b
.b
;
1296 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1297 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1299 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1300 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1301 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1302 /* Also fill in center-zeroed positions used for interpolateAtSample */
1303 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1304 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1307 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1310 static void update_shader_atom(struct pipe_context
*ctx
,
1311 struct r600_shader_state
*state
,
1312 struct r600_pipe_shader
*shader
)
1314 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1316 state
->shader
= shader
;
1318 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1319 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1321 state
->atom
.num_dw
= 0;
1323 r600_mark_atom_dirty(rctx
, &state
->atom
);
1326 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1328 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1329 rctx
->shader_stages
.geom_enable
= enable
;
1330 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1333 if (rctx
->gs_rings
.enable
!= enable
) {
1334 rctx
->gs_rings
.enable
= enable
;
1335 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1337 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1338 unsigned size
= 0x1C000;
1339 rctx
->gs_rings
.esgs_ring
.buffer
=
1340 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1341 PIPE_USAGE_DEFAULT
, size
);
1342 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1346 rctx
->gs_rings
.gsvs_ring
.buffer
=
1347 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1348 PIPE_USAGE_DEFAULT
, size
);
1349 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1353 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1354 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1355 if (rctx
->tes_shader
) {
1356 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1357 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1359 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1360 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1363 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1364 R600_GS_RING_CONST_BUFFER
, NULL
);
1365 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1366 R600_GS_RING_CONST_BUFFER
, NULL
);
1367 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1368 R600_GS_RING_CONST_BUFFER
, NULL
);
1373 static void r600_update_clip_state(struct r600_context
*rctx
,
1374 struct r600_pipe_shader
*current
)
1376 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1377 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1378 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1379 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1380 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1381 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1382 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1383 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1384 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1388 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1390 struct ureg_src const0
, const1
;
1391 struct ureg_dst tessouter
, tessinner
;
1392 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1395 return; /* if we get here, we're screwed */
1397 assert(!rctx
->fixed_func_tcs_shader
);
1399 ureg_DECL_constant2D(ureg
, 0, 3, R600_LDS_INFO_CONST_BUFFER
);
1400 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 2),
1401 R600_LDS_INFO_CONST_BUFFER
);
1402 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 3),
1403 R600_LDS_INFO_CONST_BUFFER
);
1405 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1406 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1408 ureg_MOV(ureg
, tessouter
, const0
);
1409 ureg_MOV(ureg
, tessinner
, const1
);
1412 rctx
->fixed_func_tcs_shader
=
1413 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1416 #define SELECT_SHADER_OR_FAIL(x) do { \
1417 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1418 if (unlikely(!rctx->x##_shader->current)) \
1422 #define UPDATE_SHADER(hw, sw) do { \
1423 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1424 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1427 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1428 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1429 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1430 clip_so_current = rctx->sw##_shader->current; \
1434 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1435 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1436 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1437 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1438 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1442 #define SET_NULL_SHADER(hw) do { \
1443 if (rctx->hw_shader_stages[(hw)].shader) \
1444 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1447 static bool r600_update_derived_state(struct r600_context
*rctx
)
1449 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1450 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1451 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1453 bool need_buf_const
;
1454 struct r600_pipe_shader
*clip_so_current
= NULL
;
1456 if (!rctx
->blitter
->running
) {
1460 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1461 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1462 rctx
->b
.last_compressed_colortex_counter
= counter
;
1464 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1465 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1469 /* Decompress textures if needed. */
1470 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1471 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1472 if (views
->compressed_depthtex_mask
) {
1473 r600_decompress_depth_textures(rctx
, views
);
1475 if (views
->compressed_colortex_mask
) {
1476 r600_decompress_color_textures(rctx
, views
);
1481 SELECT_SHADER_OR_FAIL(ps
);
1483 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1485 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1487 if (rctx
->gs_shader
)
1488 SELECT_SHADER_OR_FAIL(gs
);
1491 if (rctx
->tcs_shader
) {
1492 SELECT_SHADER_OR_FAIL(tcs
);
1494 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1495 } else if (rctx
->tes_shader
) {
1496 if (!rctx
->fixed_func_tcs_shader
) {
1497 r600_generate_fixed_func_tcs(rctx
);
1498 if (!rctx
->fixed_func_tcs_shader
)
1502 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1504 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1506 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1508 if (rctx
->tes_shader
) {
1509 SELECT_SHADER_OR_FAIL(tes
);
1512 SELECT_SHADER_OR_FAIL(vs
);
1514 if (rctx
->gs_shader
) {
1515 if (!rctx
->shader_stages
.geom_enable
) {
1516 rctx
->shader_stages
.geom_enable
= true;
1517 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1520 /* gs_shader provides GS and VS (copy shader) */
1521 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1523 /* vs_shader is used as ES */
1525 if (rctx
->tes_shader
) {
1526 /* VS goes to LS, TES goes to ES */
1527 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1528 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1530 /* vs_shader is used as ES */
1531 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1532 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1535 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1536 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1537 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1538 rctx
->shader_stages
.geom_enable
= false;
1539 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1542 if (rctx
->tes_shader
) {
1543 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1544 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1545 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1547 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1548 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1552 /* Update clip misc state. */
1553 if (clip_so_current
) {
1554 r600_update_clip_state(rctx
, clip_so_current
);
1555 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1558 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1559 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1560 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1562 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1563 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1564 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1567 if (rctx
->b
.chip_class
<= R700
) {
1568 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1570 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1571 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1572 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1576 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1577 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1578 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1580 if (rctx
->b
.chip_class
>= EVERGREEN
)
1581 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1583 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1586 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1588 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1590 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1591 evergreen_update_db_shader_control(rctx
);
1593 r600_update_db_shader_control(rctx
);
1596 /* on R600 we stuff masks + txq info into one constant buffer */
1597 /* on evergreen we only need a txq info one */
1598 if (rctx
->ps_shader
) {
1599 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1600 if (need_buf_const
) {
1601 if (rctx
->b
.chip_class
< EVERGREEN
)
1602 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1604 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1608 if (rctx
->vs_shader
) {
1609 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1610 if (need_buf_const
) {
1611 if (rctx
->b
.chip_class
< EVERGREEN
)
1612 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1614 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1618 if (rctx
->gs_shader
) {
1619 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1620 if (need_buf_const
) {
1621 if (rctx
->b
.chip_class
< EVERGREEN
)
1622 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1624 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1628 r600_update_driver_const_buffers(rctx
);
1630 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1631 if (!r600_adjust_gprs(rctx
)) {
1632 /* discard rendering */
1637 if (rctx
->b
.chip_class
== EVERGREEN
) {
1638 if (!evergreen_adjust_gprs(rctx
)) {
1639 /* discard rendering */
1644 blend_disable
= (rctx
->dual_src_blend
&&
1645 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1647 if (blend_disable
!= rctx
->force_blend_disable
) {
1648 rctx
->force_blend_disable
= blend_disable
;
1649 r600_bind_blend_state_internal(rctx
,
1650 rctx
->blend_state
.cso
,
1657 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1659 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1660 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1662 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1663 state
->pa_cl_clip_cntl
|
1664 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1665 S_028810_CLIP_DISABLE(state
->clip_disable
));
1666 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1667 state
->pa_cl_vs_out_cntl
|
1668 (state
->clip_plane_enable
& state
->clip_dist_write
));
1669 /* reuse needs to be set off if we write oViewport */
1670 if (rctx
->b
.chip_class
>= EVERGREEN
)
1671 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1672 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1675 /* rast_prim is the primitive type after GS. */
1676 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
1678 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1679 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
1681 /* Skip this if not rendering lines. */
1682 if (rast_prim
!= PIPE_PRIM_LINES
&&
1683 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
1684 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
1685 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
1686 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
1689 if (rast_prim
== rctx
->last_rast_prim
)
1692 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1693 * reset the stipple pattern at each packet (line strips, line loops).
1695 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1696 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
1697 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1698 rctx
->last_rast_prim
= rast_prim
;
1701 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1703 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1704 struct pipe_index_buffer ib
= {};
1705 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1706 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
1708 unsigned num_patches
, dirty_tex_counter
;
1711 if (!info
->indirect
&& !info
->count
&& (info
->indexed
|| !info
->count_from_stream_output
)) {
1715 if (unlikely(!rctx
->vs_shader
)) {
1719 if (unlikely(!rctx
->ps_shader
&&
1720 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
1725 /* make sure that the gfx ring is only one active */
1726 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
1727 rctx
->b
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1730 /* Re-emit the framebuffer state if needed. */
1731 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
1732 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
1733 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1734 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1737 if (!r600_update_derived_state(rctx
)) {
1738 /* useless to render because current rendering command
1744 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
1745 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
1748 if (info
->indexed
) {
1749 /* Initialize the index buffer struct. */
1750 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1751 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1752 ib
.index_size
= rctx
->index_buffer
.index_size
;
1753 ib
.offset
= rctx
->index_buffer
.offset
;
1754 if (!info
->indirect
) {
1755 ib
.offset
+= info
->start
* ib
.index_size
;
1758 /* Translate 8-bit indices to 16-bit. */
1759 if (unlikely(ib
.index_size
== 1)) {
1760 struct pipe_resource
*out_buffer
= NULL
;
1761 unsigned out_offset
;
1763 unsigned start
, count
;
1765 if (likely(!info
->indirect
)) {
1767 count
= info
->count
;
1770 /* Have to get start/count from indirect buffer, slow path ahead... */
1771 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
;
1772 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1773 PIPE_TRANSFER_READ
);
1775 data
+= info
->indirect_offset
/ sizeof(unsigned);
1776 start
= data
[2] * ib
.index_size
;
1785 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
1786 256, &out_offset
, &out_buffer
, &ptr
);
1787 if (unlikely(!ptr
)) {
1788 pipe_resource_reference(&ib
.buffer
, NULL
);
1792 util_shorten_ubyte_elts_to_userptr(
1793 &rctx
->b
.b
, &ib
, 0, 0, ib
.offset
+ start
, count
, ptr
);
1795 pipe_resource_reference(&ib
.buffer
, NULL
);
1796 ib
.user_buffer
= NULL
;
1797 ib
.buffer
= out_buffer
;
1798 ib
.offset
= out_offset
;
1802 /* Upload the index buffer.
1803 * The upload is skipped for small index counts on little-endian machines
1804 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1805 * Indirect draws never use immediate indices.
1806 * Note: Instanced rendering in combination with immediate indices hangs. */
1807 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
->indirect
||
1808 info
->instance_count
> 1 ||
1809 info
->count
*ib
.index_size
> 20)) {
1810 u_upload_data(ctx
->stream_uploader
, 0,
1811 info
->count
* ib
.index_size
, 256,
1812 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1813 ib
.user_buffer
= NULL
;
1815 index_bias
= info
->index_bias
;
1817 index_bias
= info
->start
;
1820 /* Set the index offset and primitive restart. */
1821 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
1822 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
1823 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
1824 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
1825 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
1826 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
1827 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
1828 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1831 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1832 if (rctx
->b
.chip_class
== R600
) {
1833 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1834 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1837 if (rctx
->b
.chip_class
>= EVERGREEN
)
1838 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
1841 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1842 r600_flush_emit(rctx
);
1844 mask
= rctx
->dirty_atoms
;
1846 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
1849 if (rctx
->b
.chip_class
== CAYMAN
) {
1850 /* Copied from radeonsi. */
1851 unsigned primgroup_size
= 128; /* recommended without a GS */
1852 bool ia_switch_on_eop
= false;
1853 bool partial_vs_wave
= false;
1855 if (rctx
->gs_shader
)
1856 primgroup_size
= 64; /* recommended with a GS */
1858 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1859 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1860 ia_switch_on_eop
= true;
1863 if (r600_get_strmout_en(&rctx
->b
))
1864 partial_vs_wave
= true;
1866 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1867 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1868 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1869 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1872 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1873 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
1876 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
1877 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
1880 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1881 * even though it should have no effect on those. */
1882 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1883 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1884 unsigned prim
= info
->mode
;
1886 if (rctx
->gs_shader
) {
1887 prim
= rctx
->gs_shader
->gs_output_prim
;
1889 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1891 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1892 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1893 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
1894 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1896 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1899 /* Update start instance. */
1900 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
1901 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
1902 rctx
->last_start_instance
= info
->start_instance
;
1905 /* Update the primitive type. */
1906 if (rctx
->last_primitive_type
!= info
->mode
) {
1907 r600_emit_rasterizer_prim_state(rctx
);
1908 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1909 r600_conv_pipe_prim(info
->mode
));
1911 rctx
->last_primitive_type
= info
->mode
;
1915 if (likely(!info
->indirect
)) {
1916 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
1917 radeon_emit(cs
, info
->instance_count
);
1919 uint64_t va
= r600_resource(info
->indirect
)->gpu_address
;
1920 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1922 // Invalidate so non-indirect draw calls reset this state
1923 rctx
->vgt_state
.last_draw_was_indirect
= true;
1924 rctx
->last_start_instance
= -1;
1926 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
1927 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
1928 radeon_emit(cs
, va
);
1929 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1931 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1932 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1933 (struct r600_resource
*)info
->indirect
,
1935 RADEON_PRIO_DRAW_INDIRECT
));
1938 if (info
->indexed
) {
1939 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1940 radeon_emit(cs
, ib
.index_size
== 4 ?
1941 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1942 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
1944 if (ib
.user_buffer
) {
1945 unsigned size_bytes
= info
->count
*ib
.index_size
;
1946 unsigned size_dw
= align(size_bytes
, 4) / 4;
1947 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
1948 radeon_emit(cs
, info
->count
);
1949 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
1950 radeon_emit_array(cs
, ib
.user_buffer
, size_dw
);
1952 uint64_t va
= r600_resource(ib
.buffer
)->gpu_address
+ ib
.offset
;
1954 if (likely(!info
->indirect
)) {
1955 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
1956 radeon_emit(cs
, va
);
1957 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1958 radeon_emit(cs
, info
->count
);
1959 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1960 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1961 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1962 (struct r600_resource
*)ib
.buffer
,
1964 RADEON_PRIO_INDEX_BUFFER
));
1967 uint32_t max_size
= (ib
.buffer
->width0
- ib
.offset
) / ib
.index_size
;
1969 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
1970 radeon_emit(cs
, va
);
1971 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1973 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1974 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1975 (struct r600_resource
*)ib
.buffer
,
1977 RADEON_PRIO_INDEX_BUFFER
));
1979 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1980 radeon_emit(cs
, max_size
);
1982 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
1983 radeon_emit(cs
, info
->indirect_offset
);
1984 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1988 if (unlikely(info
->count_from_stream_output
)) {
1989 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
1990 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1992 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1994 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
1995 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
1996 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
1997 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
1998 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
1999 radeon_emit(cs
, 0); /* unused */
2001 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2002 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2003 t
->buf_filled_size
, RADEON_USAGE_READ
,
2004 RADEON_PRIO_SO_FILLED_SIZE
));
2007 if (likely(!info
->indirect
)) {
2008 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
2009 radeon_emit(cs
, info
->count
);
2012 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
2013 radeon_emit(cs
, info
->indirect_offset
);
2015 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2016 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2019 /* SMX returns CONTEXT_DONE too early workaround */
2020 if (rctx
->b
.family
== CHIP_R600
||
2021 rctx
->b
.family
== CHIP_RV610
||
2022 rctx
->b
.family
== CHIP_RV630
||
2023 rctx
->b
.family
== CHIP_RV635
) {
2024 /* if we have gs shader or streamout
2025 we need to do a wait idle after every draw */
2026 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2027 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2031 /* ES ring rolling over at EOP - workaround */
2032 if (rctx
->b
.chip_class
== R600
) {
2033 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2034 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2037 /* Set the depth buffer as dirty. */
2038 if (rctx
->framebuffer
.state
.zsbuf
) {
2039 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2040 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2042 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2044 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2045 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2047 if (rctx
->framebuffer
.compressed_cb_mask
) {
2048 struct pipe_surface
*surf
;
2049 struct r600_texture
*rtex
;
2050 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2053 unsigned i
= u_bit_scan(&mask
);
2054 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2055 rtex
= (struct r600_texture
*)surf
->texture
;
2057 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2062 pipe_resource_reference(&ib
.buffer
, NULL
);
2063 rctx
->b
.num_draw_calls
++;
2066 uint32_t r600_translate_stencil_op(int s_op
)
2069 case PIPE_STENCIL_OP_KEEP
:
2070 return V_028800_STENCIL_KEEP
;
2071 case PIPE_STENCIL_OP_ZERO
:
2072 return V_028800_STENCIL_ZERO
;
2073 case PIPE_STENCIL_OP_REPLACE
:
2074 return V_028800_STENCIL_REPLACE
;
2075 case PIPE_STENCIL_OP_INCR
:
2076 return V_028800_STENCIL_INCR
;
2077 case PIPE_STENCIL_OP_DECR
:
2078 return V_028800_STENCIL_DECR
;
2079 case PIPE_STENCIL_OP_INCR_WRAP
:
2080 return V_028800_STENCIL_INCR_WRAP
;
2081 case PIPE_STENCIL_OP_DECR_WRAP
:
2082 return V_028800_STENCIL_DECR_WRAP
;
2083 case PIPE_STENCIL_OP_INVERT
:
2084 return V_028800_STENCIL_INVERT
;
2086 R600_ERR("Unknown stencil op %d", s_op
);
2093 uint32_t r600_translate_fill(uint32_t func
)
2096 case PIPE_POLYGON_MODE_FILL
:
2098 case PIPE_POLYGON_MODE_LINE
:
2100 case PIPE_POLYGON_MODE_POINT
:
2108 unsigned r600_tex_wrap(unsigned wrap
)
2112 case PIPE_TEX_WRAP_REPEAT
:
2113 return V_03C000_SQ_TEX_WRAP
;
2114 case PIPE_TEX_WRAP_CLAMP
:
2115 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2116 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2117 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2118 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2119 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2120 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2121 return V_03C000_SQ_TEX_MIRROR
;
2122 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2123 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2124 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2125 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2126 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2127 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2131 unsigned r600_tex_mipfilter(unsigned filter
)
2134 case PIPE_TEX_MIPFILTER_NEAREST
:
2135 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2136 case PIPE_TEX_MIPFILTER_LINEAR
:
2137 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2139 case PIPE_TEX_MIPFILTER_NONE
:
2140 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2144 unsigned r600_tex_compare(unsigned compare
)
2148 case PIPE_FUNC_NEVER
:
2149 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2150 case PIPE_FUNC_LESS
:
2151 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2152 case PIPE_FUNC_EQUAL
:
2153 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2154 case PIPE_FUNC_LEQUAL
:
2155 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2156 case PIPE_FUNC_GREATER
:
2157 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2158 case PIPE_FUNC_NOTEQUAL
:
2159 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2160 case PIPE_FUNC_GEQUAL
:
2161 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2162 case PIPE_FUNC_ALWAYS
:
2163 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2167 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2169 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2170 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2172 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2173 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2176 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2178 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2179 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2181 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2182 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2183 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2184 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2185 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2188 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2191 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2192 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2197 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2198 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2199 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2200 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2203 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2204 const unsigned char *swizzle_view
,
2208 unsigned char swizzle
[4];
2209 unsigned result
= 0;
2210 const uint32_t tex_swizzle_shift
[4] = {
2213 const uint32_t vtx_swizzle_shift
[4] = {
2216 const uint32_t swizzle_bit
[4] = {
2219 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2222 swizzle_shift
= vtx_swizzle_shift
;
2225 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2227 memcpy(swizzle
, swizzle_format
, 4);
2231 for (i
= 0; i
< 4; i
++) {
2232 switch (swizzle
[i
]) {
2233 case PIPE_SWIZZLE_Y
:
2234 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2236 case PIPE_SWIZZLE_Z
:
2237 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2239 case PIPE_SWIZZLE_W
:
2240 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2242 case PIPE_SWIZZLE_0
:
2243 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2245 case PIPE_SWIZZLE_1
:
2246 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2248 default: /* PIPE_SWIZZLE_X */
2249 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2255 /* texture format translate */
2256 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2257 enum pipe_format format
,
2258 const unsigned char *swizzle_view
,
2259 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2260 bool do_endian_swap
)
2262 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2263 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2264 const struct util_format_description
*desc
;
2265 boolean uniform
= TRUE
;
2266 bool is_srgb_valid
= FALSE
;
2267 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2268 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2269 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2270 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2271 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2274 const uint32_t sign_bit
[4] = {
2275 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2276 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2277 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2278 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2281 /* Need to replace the specified texture formats in case of big-endian.
2282 * These formats are formats that have channels with number of bits
2283 * not divisible by 8.
2284 * Mesa conversion functions don't swap bits for those formats, and because
2285 * we transmit this over a serial bus to the GPU (PCIe), the
2286 * bit-endianess is important!!!
2287 * In case we have an "opposite" format, just use that for the swizzling
2288 * information. If we don't have such an "opposite" format, we need
2289 * to use a fixed swizzle info instead (see below)
2291 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2292 format
= PIPE_FORMAT_A4R4_UNORM
;
2294 desc
= util_format_description(format
);
2296 /* Depth and stencil swizzling is handled separately. */
2297 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2298 /* Need to check for specific texture formats that don't have
2299 * an "opposite" format we can use. For those formats, we directly
2300 * specify the swizzling, which is the LE swizzling as defined in
2303 if (do_endian_swap
) {
2304 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2305 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2306 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2307 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2308 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2309 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2311 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2313 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2317 /* Colorspace (return non-RGB formats directly). */
2318 switch (desc
->colorspace
) {
2319 /* Depth stencil formats */
2320 case UTIL_FORMAT_COLORSPACE_ZS
:
2322 /* Depth sampler formats. */
2323 case PIPE_FORMAT_Z16_UNORM
:
2324 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2327 case PIPE_FORMAT_Z24X8_UNORM
:
2328 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2329 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2332 case PIPE_FORMAT_X8Z24_UNORM
:
2333 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2334 if (rscreen
->b
.chip_class
< EVERGREEN
)
2336 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2339 case PIPE_FORMAT_Z32_FLOAT
:
2340 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2341 result
= FMT_32_FLOAT
;
2343 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2344 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2345 result
= FMT_X24_8_32_FLOAT
;
2347 /* Stencil sampler formats. */
2348 case PIPE_FORMAT_S8_UINT
:
2349 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2350 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2353 case PIPE_FORMAT_X24S8_UINT
:
2354 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2355 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2358 case PIPE_FORMAT_S8X24_UINT
:
2359 if (rscreen
->b
.chip_class
< EVERGREEN
)
2361 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2362 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2365 case PIPE_FORMAT_X32_S8X24_UINT
:
2366 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2367 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2368 result
= FMT_X24_8_32_FLOAT
;
2374 case UTIL_FORMAT_COLORSPACE_YUV
:
2375 yuv_format
|= (1 << 30);
2377 case PIPE_FORMAT_UYVY
:
2378 case PIPE_FORMAT_YUYV
:
2382 goto out_unknown
; /* XXX */
2384 case UTIL_FORMAT_COLORSPACE_SRGB
:
2385 word4
|= S_038010_FORCE_DEGAMMA(1);
2392 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2394 case PIPE_FORMAT_RGTC1_SNORM
:
2395 case PIPE_FORMAT_LATC1_SNORM
:
2396 word4
|= sign_bit
[0];
2397 case PIPE_FORMAT_RGTC1_UNORM
:
2398 case PIPE_FORMAT_LATC1_UNORM
:
2401 case PIPE_FORMAT_RGTC2_SNORM
:
2402 case PIPE_FORMAT_LATC2_SNORM
:
2403 word4
|= sign_bit
[0] | sign_bit
[1];
2404 case PIPE_FORMAT_RGTC2_UNORM
:
2405 case PIPE_FORMAT_LATC2_UNORM
:
2413 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2414 if (!util_format_s3tc_enabled
) {
2419 case PIPE_FORMAT_DXT1_RGB
:
2420 case PIPE_FORMAT_DXT1_RGBA
:
2421 case PIPE_FORMAT_DXT1_SRGB
:
2422 case PIPE_FORMAT_DXT1_SRGBA
:
2424 is_srgb_valid
= TRUE
;
2426 case PIPE_FORMAT_DXT3_RGBA
:
2427 case PIPE_FORMAT_DXT3_SRGBA
:
2429 is_srgb_valid
= TRUE
;
2431 case PIPE_FORMAT_DXT5_RGBA
:
2432 case PIPE_FORMAT_DXT5_SRGBA
:
2434 is_srgb_valid
= TRUE
;
2441 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2442 if (rscreen
->b
.chip_class
< EVERGREEN
)
2446 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2447 case PIPE_FORMAT_BPTC_SRGBA
:
2449 is_srgb_valid
= TRUE
;
2451 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2452 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2454 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2462 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2464 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2465 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2468 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2469 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2477 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2478 result
= FMT_5_9_9_9_SHAREDEXP
;
2480 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2481 result
= FMT_10_11_11_FLOAT
;
2486 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2487 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2488 word4
|= sign_bit
[i
];
2492 /* R8G8Bx_SNORM - XXX CxV8U8 */
2494 /* See whether the components are of the same size. */
2495 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2496 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2499 /* Non-uniform formats. */
2501 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2502 desc
->channel
[0].pure_integer
)
2503 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2504 switch(desc
->nr_channels
) {
2506 if (desc
->channel
[0].size
== 5 &&
2507 desc
->channel
[1].size
== 6 &&
2508 desc
->channel
[2].size
== 5) {
2514 if (desc
->channel
[0].size
== 5 &&
2515 desc
->channel
[1].size
== 5 &&
2516 desc
->channel
[2].size
== 5 &&
2517 desc
->channel
[3].size
== 1) {
2518 result
= FMT_1_5_5_5
;
2521 if (desc
->channel
[0].size
== 10 &&
2522 desc
->channel
[1].size
== 10 &&
2523 desc
->channel
[2].size
== 10 &&
2524 desc
->channel
[3].size
== 2) {
2525 result
= FMT_2_10_10_10
;
2533 /* Find the first non-VOID channel. */
2534 for (i
= 0; i
< 4; i
++) {
2535 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2543 /* uniform formats */
2544 switch (desc
->channel
[i
].type
) {
2545 case UTIL_FORMAT_TYPE_UNSIGNED
:
2546 case UTIL_FORMAT_TYPE_SIGNED
:
2548 if (!desc
->channel
[i
].normalized
&&
2549 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2553 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2554 desc
->channel
[i
].pure_integer
)
2555 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2557 switch (desc
->channel
[i
].size
) {
2559 switch (desc
->nr_channels
) {
2564 result
= FMT_4_4_4_4
;
2569 switch (desc
->nr_channels
) {
2577 result
= FMT_8_8_8_8
;
2578 is_srgb_valid
= TRUE
;
2583 switch (desc
->nr_channels
) {
2591 result
= FMT_16_16_16_16
;
2596 switch (desc
->nr_channels
) {
2604 result
= FMT_32_32_32_32
;
2610 case UTIL_FORMAT_TYPE_FLOAT
:
2611 switch (desc
->channel
[i
].size
) {
2613 switch (desc
->nr_channels
) {
2615 result
= FMT_16_FLOAT
;
2618 result
= FMT_16_16_FLOAT
;
2621 result
= FMT_16_16_16_16_FLOAT
;
2626 switch (desc
->nr_channels
) {
2628 result
= FMT_32_FLOAT
;
2631 result
= FMT_32_32_FLOAT
;
2634 result
= FMT_32_32_32_32_FLOAT
;
2643 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2648 *yuv_format_p
= yuv_format
;
2651 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2655 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
2656 bool do_endian_swap
)
2658 const struct util_format_description
*desc
= util_format_description(format
);
2659 int channel
= util_format_get_first_non_void_channel(format
);
2662 #define HAS_SIZE(x,y,z,w) \
2663 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2664 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2666 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2667 return V_0280A0_COLOR_10_11_11_FLOAT
;
2669 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2673 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2675 switch (desc
->nr_channels
) {
2677 switch (desc
->channel
[0].size
) {
2679 return V_0280A0_COLOR_8
;
2682 return V_0280A0_COLOR_16_FLOAT
;
2684 return V_0280A0_COLOR_16
;
2687 return V_0280A0_COLOR_32_FLOAT
;
2689 return V_0280A0_COLOR_32
;
2693 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2694 switch (desc
->channel
[0].size
) {
2697 return V_0280A0_COLOR_4_4
;
2699 return ~0U; /* removed on Evergreen */
2701 return V_0280A0_COLOR_8_8
;
2704 return V_0280A0_COLOR_16_16_FLOAT
;
2706 return V_0280A0_COLOR_16_16
;
2709 return V_0280A0_COLOR_32_32_FLOAT
;
2711 return V_0280A0_COLOR_32_32
;
2713 } else if (HAS_SIZE(8,24,0,0)) {
2714 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
2715 } else if (HAS_SIZE(24,8,0,0)) {
2716 return V_0280A0_COLOR_8_24
;
2720 if (HAS_SIZE(5,6,5,0)) {
2721 return V_0280A0_COLOR_5_6_5
;
2722 } else if (HAS_SIZE(32,8,24,0)) {
2723 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2727 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2728 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2729 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2730 switch (desc
->channel
[0].size
) {
2732 return V_0280A0_COLOR_4_4_4_4
;
2734 return V_0280A0_COLOR_8_8_8_8
;
2737 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2739 return V_0280A0_COLOR_16_16_16_16
;
2742 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2744 return V_0280A0_COLOR_32_32_32_32
;
2746 } else if (HAS_SIZE(5,5,5,1)) {
2747 return V_0280A0_COLOR_1_5_5_5
;
2748 } else if (HAS_SIZE(10,10,10,2)) {
2749 return V_0280A0_COLOR_2_10_10_10
;
2756 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
2758 if (R600_BIG_ENDIAN
) {
2759 switch(colorformat
) {
2760 /* 8-bit buffers. */
2761 case V_0280A0_COLOR_4_4
:
2762 case V_0280A0_COLOR_8
:
2765 /* 16-bit buffers. */
2766 case V_0280A0_COLOR_8_8
:
2768 * No need to do endian swaps on array formats,
2769 * as mesa<-->pipe formats conversion take into account
2774 case V_0280A0_COLOR_5_6_5
:
2775 case V_0280A0_COLOR_1_5_5_5
:
2776 case V_0280A0_COLOR_4_4_4_4
:
2777 case V_0280A0_COLOR_16
:
2778 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
2780 /* 32-bit buffers. */
2781 case V_0280A0_COLOR_8_8_8_8
:
2783 * No need to do endian swaps on array formats,
2784 * as mesa<-->pipe formats conversion take into account
2789 case V_0280A0_COLOR_2_10_10_10
:
2790 case V_0280A0_COLOR_8_24
:
2791 case V_0280A0_COLOR_24_8
:
2792 case V_0280A0_COLOR_32_FLOAT
:
2793 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
2795 case V_0280A0_COLOR_16_16_FLOAT
:
2796 case V_0280A0_COLOR_16_16
:
2797 return ENDIAN_8IN16
;
2799 /* 64-bit buffers. */
2800 case V_0280A0_COLOR_16_16_16_16
:
2801 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2802 return ENDIAN_8IN16
;
2804 case V_0280A0_COLOR_32_32_FLOAT
:
2805 case V_0280A0_COLOR_32_32
:
2806 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2807 return ENDIAN_8IN32
;
2809 /* 128-bit buffers. */
2810 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2811 case V_0280A0_COLOR_32_32_32_32
:
2812 return ENDIAN_8IN32
;
2814 return ENDIAN_NONE
; /* Unsupported. */
2821 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2823 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2824 struct r600_resource
*rbuffer
= r600_resource(buf
);
2825 unsigned i
, shader
, mask
;
2826 struct r600_pipe_sampler_view
*view
;
2828 /* Reallocate the buffer in the same pipe_resource. */
2829 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
2831 /* We changed the buffer, now we need to bind it where the old one was bound. */
2832 /* Vertex buffers. */
2833 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2835 i
= u_bit_scan(&mask
);
2836 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2837 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2838 r600_vertex_buffers_dirty(rctx
);
2841 /* Streamout buffers. */
2842 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2843 if (rctx
->b
.streamout
.targets
[i
] &&
2844 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2845 if (rctx
->b
.streamout
.begin_emitted
) {
2846 r600_emit_streamout_end(&rctx
->b
);
2848 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2849 r600_streamout_buffers_dirty(&rctx
->b
);
2853 /* Constant buffers. */
2854 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2855 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2857 uint32_t mask
= state
->enabled_mask
;
2860 unsigned i
= u_bit_scan(&mask
);
2861 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2863 state
->dirty_mask
|= 1 << i
;
2867 r600_constant_buffers_dirty(rctx
, state
);
2871 /* Texture buffer objects - update the virtual addresses in descriptors. */
2872 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
2873 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2874 uint64_t offset
= view
->base
.u
.buf
.offset
;
2875 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2877 view
->tex_resource_words
[0] = va
;
2878 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2879 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2882 /* Texture buffer objects - make bindings dirty if needed. */
2883 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2884 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2886 uint32_t mask
= state
->enabled_mask
;
2889 unsigned i
= u_bit_scan(&mask
);
2890 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2892 state
->dirty_mask
|= 1 << i
;
2896 r600_sampler_views_dirty(rctx
, state
);
2901 static void r600_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
2903 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2905 /* Pipeline stat & streamout queries. */
2907 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
2908 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
2910 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
2911 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
2914 /* Occlusion queries. */
2915 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
2916 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
2917 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2921 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2923 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2925 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2928 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2929 bool include_draw_vbo
)
2931 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2934 /* keep this at the end of this file, please */
2935 void r600_init_common_state_functions(struct r600_context
*rctx
)
2937 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2938 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2939 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2940 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
2941 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
2942 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2943 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2944 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2945 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2946 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2947 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2948 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2949 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2950 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2951 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
2952 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
2953 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2954 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2955 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2956 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2957 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2958 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2959 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2960 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2961 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
2962 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
2963 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2964 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2965 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2966 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2967 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2968 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2969 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2970 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2971 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2972 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2973 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2974 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
2975 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2976 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2977 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2978 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;