2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
39 struct radeon_winsys_cs
*cs
= rctx
->cs
;
40 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
42 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
43 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
44 cs
->cdw
+= cb
->atom
.num_dw
;
47 void r600_init_command_buffer(struct r600_context
*rctx
, struct r600_command_buffer
*cb
, unsigned id
, unsigned num_dw
)
49 r600_init_atom(rctx
, &cb
->atom
, id
, r600_emit_command_buffer
, 0);
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 void r600_init_atom(struct r600_context
*rctx
,
60 struct r600_atom
*atom
,
62 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
65 assert(id
< R600_NUM_ATOMS
);
66 assert(rctx
->atoms
[id
] == NULL
);
67 rctx
->atoms
[id
] = atom
;
70 atom
->num_dw
= num_dw
;
74 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
76 struct radeon_winsys_cs
*cs
= rctx
->cs
;
77 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
78 unsigned alpha_ref
= a
->sx_alpha_ref
;
80 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
84 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
85 a
->sx_alpha_test_control
|
86 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
87 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
90 static void r600_texture_barrier(struct pipe_context
*ctx
)
92 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
94 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_TEX_FLUSH
;
97 if (rctx
->chip_class
== R600
) {
98 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
102 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
104 static const int prim_conv
[] = {
105 V_008958_DI_PT_POINTLIST
,
106 V_008958_DI_PT_LINELIST
,
107 V_008958_DI_PT_LINELOOP
,
108 V_008958_DI_PT_LINESTRIP
,
109 V_008958_DI_PT_TRILIST
,
110 V_008958_DI_PT_TRISTRIP
,
111 V_008958_DI_PT_TRIFAN
,
112 V_008958_DI_PT_QUADLIST
,
113 V_008958_DI_PT_QUADSTRIP
,
114 V_008958_DI_PT_POLYGON
,
119 V_008958_DI_PT_RECTLIST
122 *prim
= prim_conv
[pprim
];
124 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
130 /* common state between evergreen and r600 */
132 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
133 struct r600_pipe_blend
*blend
)
135 struct r600_pipe_state
*rstate
;
136 bool update_cb
= false;
138 rstate
= &blend
->rstate
;
139 rctx
->states
[rstate
->id
] = rstate
;
140 r600_context_pipe_state_set(rctx
, rstate
);
142 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
143 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
146 if (rctx
->chip_class
<= R700
&&
147 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
148 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
151 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
152 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
156 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
160 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
169 rctx
->alpha_to_one
= blend
->alpha_to_one
;
170 rctx
->dual_src_blend
= blend
->dual_src_blend
;
172 if (!rctx
->blend_override
)
173 r600_bind_blend_state_internal(rctx
, blend
);
176 static void r600_set_blend_color(struct pipe_context
*ctx
,
177 const struct pipe_blend_color
*state
)
179 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
181 rctx
->blend_color
.state
= *state
;
182 r600_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
185 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
187 struct radeon_winsys_cs
*cs
= rctx
->cs
;
188 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
190 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
191 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
192 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
193 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
194 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
197 static void r600_set_clip_state(struct pipe_context
*ctx
,
198 const struct pipe_clip_state
*state
)
200 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
201 struct pipe_constant_buffer cb
;
203 rctx
->clip_state
.state
= *state
;
204 r600_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
207 cb
.user_buffer
= state
->ucp
;
208 cb
.buffer_offset
= 0;
209 cb
.buffer_size
= 4*4*8;
210 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
211 pipe_resource_reference(&cb
.buffer
, NULL
);
214 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
215 const struct r600_stencil_ref
*state
)
217 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
219 rctx
->stencil_ref
.state
= *state
;
220 r600_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
223 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
225 struct radeon_winsys_cs
*cs
= rctx
->cs
;
226 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
228 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
229 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
230 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
231 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
232 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
233 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
234 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
235 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
236 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
239 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
240 const struct pipe_stencil_ref
*state
)
242 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
243 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
244 struct r600_stencil_ref ref
;
246 rctx
->stencil_ref
.pipe_state
= *state
;
251 ref
.ref_value
[0] = state
->ref_value
[0];
252 ref
.ref_value
[1] = state
->ref_value
[1];
253 ref
.valuemask
[0] = dsa
->valuemask
[0];
254 ref
.valuemask
[1] = dsa
->valuemask
[1];
255 ref
.writemask
[0] = dsa
->writemask
[0];
256 ref
.writemask
[1] = dsa
->writemask
[1];
258 r600_set_stencil_ref(ctx
, &ref
);
261 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
263 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
264 struct r600_pipe_dsa
*dsa
= state
;
265 struct r600_pipe_state
*rstate
;
266 struct r600_stencil_ref ref
;
270 rstate
= &dsa
->rstate
;
271 rctx
->states
[rstate
->id
] = rstate
;
272 r600_context_pipe_state_set(rctx
, rstate
);
274 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
275 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
276 ref
.valuemask
[0] = dsa
->valuemask
[0];
277 ref
.valuemask
[1] = dsa
->valuemask
[1];
278 ref
.writemask
[0] = dsa
->writemask
[0];
279 ref
.writemask
[1] = dsa
->writemask
[1];
281 r600_set_stencil_ref(ctx
, &ref
);
283 /* Update alphatest state. */
284 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
285 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
286 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
287 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
288 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
292 void r600_set_max_scissor(struct r600_context
*rctx
)
294 /* Set a scissor state such that it doesn't do anything. */
295 struct pipe_scissor_state scissor
;
301 r600_set_scissor_state(rctx
, &scissor
);
304 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
306 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
307 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
312 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
313 rctx
->two_side
= rs
->two_side
;
314 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
315 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
316 rctx
->multisample_enable
= rs
->multisample_enable
;
318 rctx
->rasterizer
= rs
;
320 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
321 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
323 if (rctx
->chip_class
>= EVERGREEN
) {
324 evergreen_polygon_offset_update(rctx
);
326 r600_polygon_offset_update(rctx
);
329 /* Workaround for a missing scissor enable on r600. */
330 if (rctx
->chip_class
== R600
) {
331 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
332 rctx
->scissor_enable
= rs
->scissor_enable
;
334 if (rs
->scissor_enable
) {
335 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
337 r600_set_max_scissor(rctx
);
343 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
345 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
346 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
348 if (rctx
->rasterizer
== rs
) {
349 rctx
->rasterizer
= NULL
;
351 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
352 rctx
->states
[rs
->rstate
.id
] = NULL
;
357 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
358 struct pipe_sampler_view
*state
)
360 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
362 pipe_resource_reference(&state
->texture
, NULL
);
366 void r600_sampler_states_dirty(struct r600_context
*rctx
,
367 struct r600_sampler_states
*state
)
369 if (state
->dirty_mask
) {
370 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
371 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
374 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
375 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
376 r600_atom_dirty(rctx
, &state
->atom
);
380 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
383 unsigned count
, void **states
)
385 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
386 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
387 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
388 int seamless_cube_map
= -1;
390 /* This sets 1-bit for states with index >= count. */
391 uint32_t disable_mask
= ~((1ull << count
) - 1);
392 /* These are the new states set by this function. */
393 uint32_t new_mask
= 0;
395 assert(start
== 0); /* XXX fix below */
397 for (i
= 0; i
< count
; i
++) {
398 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
400 if (rstate
== dst
->states
.states
[i
]) {
405 if (rstate
->border_color_use
) {
406 dst
->states
.has_bordercolor_mask
|= 1 << i
;
408 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
410 seamless_cube_map
= rstate
->seamless_cube_map
;
414 disable_mask
|= 1 << i
;
418 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
419 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
421 dst
->states
.enabled_mask
&= ~disable_mask
;
422 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
423 dst
->states
.enabled_mask
|= new_mask
;
424 dst
->states
.dirty_mask
|= new_mask
;
425 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
427 r600_sampler_states_dirty(rctx
, &dst
->states
);
429 /* Seamless cubemap state. */
430 if (rctx
->chip_class
<= R700
&&
431 seamless_cube_map
!= -1 &&
432 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
433 /* change in TA_CNTL_AUX need a pipeline flush */
434 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
435 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
436 r600_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
440 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
442 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
445 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
447 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
450 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
455 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
457 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
458 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
460 if (rctx
->states
[rstate
->id
] == rstate
) {
461 rctx
->states
[rstate
->id
] = NULL
;
463 for (int i
= 0; i
< rstate
->nregs
; i
++) {
464 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
469 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
471 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
472 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
474 rctx
->vertex_elements
= v
;
476 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
477 r600_context_pipe_state_set(rctx
, &v
->rstate
);
481 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
483 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
484 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
486 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
487 rctx
->states
[v
->rstate
.id
] = NULL
;
489 if (rctx
->vertex_elements
== state
)
490 rctx
->vertex_elements
= NULL
;
492 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
496 static void r600_set_index_buffer(struct pipe_context
*ctx
,
497 const struct pipe_index_buffer
*ib
)
499 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
502 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
503 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
505 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
509 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
511 if (rctx
->vertex_buffer_state
.dirty_mask
) {
512 rctx
->flags
|= rctx
->has_vertex_cache
? R600_CONTEXT_VTX_FLUSH
: R600_CONTEXT_TEX_FLUSH
;
513 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
514 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
515 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
519 static void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
520 const struct pipe_vertex_buffer
*input
)
522 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
523 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
524 struct pipe_vertex_buffer
*vb
= state
->vb
;
526 /* This sets 1-bit for buffers with index >= count. */
527 uint32_t disable_mask
= ~((1ull << count
) - 1);
528 /* These are the new buffers set by this function. */
529 uint32_t new_buffer_mask
= 0;
531 /* Set buffers with index >= count to NULL. */
532 uint32_t remaining_buffers_mask
=
533 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
535 while (remaining_buffers_mask
) {
536 i
= u_bit_scan(&remaining_buffers_mask
);
537 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
540 /* Set vertex buffers. */
541 for (i
= 0; i
< count
; i
++) {
542 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
543 if (input
[i
].buffer
) {
544 vb
[i
].stride
= input
[i
].stride
;
545 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
546 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
547 new_buffer_mask
|= 1 << i
;
549 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
550 disable_mask
|= 1 << i
;
555 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
556 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
557 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
558 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
560 r600_vertex_buffers_dirty(rctx
);
563 void r600_sampler_views_dirty(struct r600_context
*rctx
,
564 struct r600_samplerview_state
*state
)
566 if (state
->dirty_mask
) {
567 rctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
568 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
569 util_bitcount(state
->dirty_mask
);
570 r600_atom_dirty(rctx
, &state
->atom
);
574 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
575 unsigned start
, unsigned count
,
576 struct pipe_sampler_view
**views
)
578 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
579 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
580 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
581 uint32_t dirty_sampler_states_mask
= 0;
583 /* This sets 1-bit for textures with index >= count. */
584 uint32_t disable_mask
= ~((1ull << count
) - 1);
585 /* These are the new textures set by this function. */
586 uint32_t new_mask
= 0;
588 /* Set textures with index >= count to NULL. */
589 uint32_t remaining_mask
;
591 assert(start
== 0); /* XXX fix below */
593 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
595 while (remaining_mask
) {
596 i
= u_bit_scan(&remaining_mask
);
597 assert(dst
->views
.views
[i
]);
599 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
602 for (i
= 0; i
< count
; i
++) {
603 if (rviews
[i
] == dst
->views
.views
[i
]) {
608 struct r600_texture
*rtex
=
609 (struct r600_texture
*)rviews
[i
]->base
.texture
;
611 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
612 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
614 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
617 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
618 if (rctx
->chip_class
!= CAYMAN
&& rtex
->cmask_size
&& rtex
->fmask_size
) {
619 dst
->views
.compressed_colortex_mask
|= 1 << i
;
621 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
624 /* Changing from array to non-arrays textures and vice versa requires
625 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
626 if (rctx
->chip_class
<= R700
&&
627 (dst
->states
.enabled_mask
& (1 << i
)) &&
628 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
629 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
630 dirty_sampler_states_mask
|= 1 << i
;
633 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
636 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
637 disable_mask
|= 1 << i
;
641 dst
->views
.enabled_mask
&= ~disable_mask
;
642 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
643 dst
->views
.enabled_mask
|= new_mask
;
644 dst
->views
.dirty_mask
|= new_mask
;
645 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
646 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
648 r600_sampler_views_dirty(rctx
, &dst
->views
);
650 if (dirty_sampler_states_mask
) {
651 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
652 r600_sampler_states_dirty(rctx
, &dst
->states
);
656 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
657 struct pipe_sampler_view
**views
)
659 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
662 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
663 struct pipe_sampler_view
**views
)
665 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
668 static void r600_set_viewport_state(struct pipe_context
*ctx
,
669 const struct pipe_viewport_state
*state
)
671 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
673 rctx
->viewport
.state
= *state
;
674 r600_atom_dirty(rctx
, &rctx
->viewport
.atom
);
677 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
679 struct radeon_winsys_cs
*cs
= rctx
->cs
;
680 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
682 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
683 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
684 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
685 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
686 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
687 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
688 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
691 static void *r600_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
692 const struct pipe_vertex_element
*elements
)
694 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
695 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
702 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
704 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
712 /* Compute the key for the hw shader variant */
713 static INLINE
unsigned r600_shader_selector_key(struct pipe_context
* ctx
,
714 struct r600_pipe_shader_selector
* sel
)
716 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
719 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
720 key
= rctx
->two_side
|
721 ((rctx
->alpha_to_one
&& rctx
->multisample_enable
&& !rctx
->cb0_is_integer
) << 1) |
722 (MIN2(sel
->nr_ps_max_color_exports
, rctx
->nr_cbufs
+ rctx
->dual_src_blend
) << 2);
729 /* Select the hw shader variant depending on the current state.
730 * (*dirty) is set to 1 if current variant was changed */
731 static int r600_shader_select(struct pipe_context
*ctx
,
732 struct r600_pipe_shader_selector
* sel
,
736 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
737 struct r600_pipe_shader
* shader
= NULL
;
740 key
= r600_shader_selector_key(ctx
, sel
);
742 /* Check if we don't need to change anything.
743 * This path is also used for most shaders that don't need multiple
744 * variants, it will cost just a computation of the key and this
746 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
750 /* lookup if we have other variants in the list */
751 if (sel
->num_shaders
> 1) {
752 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
754 while (c
&& c
->key
!= key
) {
760 p
->next_variant
= c
->next_variant
;
765 if (unlikely(!shader
)) {
766 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
767 shader
->selector
= sel
;
769 r
= r600_pipe_shader_create(ctx
, shader
);
771 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
777 /* We don't know the value of nr_ps_max_color_exports until we built
778 * at least one variant, so we may need to recompute the key after
779 * building first variant. */
780 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
781 sel
->num_shaders
== 0) {
782 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
783 key
= r600_shader_selector_key(ctx
, sel
);
793 shader
->next_variant
= sel
->current
;
794 sel
->current
= shader
;
796 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
797 r600_adjust_gprs(rctx
);
800 if (rctx
->ps_shader
&&
801 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
802 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
803 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
808 static void *r600_create_shader_state(struct pipe_context
*ctx
,
809 const struct pipe_shader_state
*state
,
810 unsigned pipe_shader_type
)
812 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
815 sel
->type
= pipe_shader_type
;
816 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
817 sel
->so
= state
->stream_output
;
819 r
= r600_shader_select(ctx
, sel
, NULL
);
826 static void *r600_create_ps_state(struct pipe_context
*ctx
,
827 const struct pipe_shader_state
*state
)
829 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
832 static void *r600_create_vs_state(struct pipe_context
*ctx
,
833 const struct pipe_shader_state
*state
)
835 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
838 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
840 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
843 state
= rctx
->dummy_pixel_shader
;
845 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
846 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
848 if (rctx
->chip_class
<= R700
) {
849 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
851 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
852 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
853 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
857 r600_adjust_gprs(rctx
);
860 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
861 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
862 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
866 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
868 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
870 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
872 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
874 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
875 r600_adjust_gprs(rctx
);
879 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
880 struct r600_pipe_shader_selector
*sel
)
882 struct r600_pipe_shader
*p
= sel
->current
, *c
;
885 r600_pipe_shader_destroy(ctx
, p
);
895 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
897 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
898 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
900 if (rctx
->ps_shader
== sel
) {
901 rctx
->ps_shader
= NULL
;
904 r600_delete_shader_selector(ctx
, sel
);
907 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
909 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
910 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
912 if (rctx
->vs_shader
== sel
) {
913 rctx
->vs_shader
= NULL
;
916 r600_delete_shader_selector(ctx
, sel
);
919 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
921 if (state
->dirty_mask
) {
922 rctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
923 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
924 : util_bitcount(state
->dirty_mask
)*19;
925 r600_atom_dirty(rctx
, &state
->atom
);
929 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
930 struct pipe_constant_buffer
*input
)
932 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
933 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
934 struct pipe_constant_buffer
*cb
;
937 /* Note that the state tracker can unbind constant buffers by
940 if (unlikely(!input
)) {
941 state
->enabled_mask
&= ~(1 << index
);
942 state
->dirty_mask
&= ~(1 << index
);
943 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
947 cb
= &state
->cb
[index
];
948 cb
->buffer_size
= input
->buffer_size
;
950 ptr
= input
->user_buffer
;
953 /* Upload the user buffer. */
954 if (R600_BIG_ENDIAN
) {
956 unsigned i
, size
= input
->buffer_size
;
958 if (!(tmpPtr
= malloc(size
))) {
959 R600_ERR("Failed to allocate BE swap buffer.\n");
963 for (i
= 0; i
< size
/ 4; ++i
) {
964 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
967 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
970 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
973 /* Setup the hw buffer. */
974 cb
->buffer_offset
= input
->buffer_offset
;
975 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
978 state
->enabled_mask
|= 1 << index
;
979 state
->dirty_mask
|= 1 << index
;
980 r600_constant_buffers_dirty(rctx
, state
);
983 static struct pipe_stream_output_target
*
984 r600_create_so_target(struct pipe_context
*ctx
,
985 struct pipe_resource
*buffer
,
986 unsigned buffer_offset
,
987 unsigned buffer_size
)
989 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
990 struct r600_so_target
*t
;
993 t
= CALLOC_STRUCT(r600_so_target
);
998 t
->b
.reference
.count
= 1;
1000 pipe_resource_reference(&t
->b
.buffer
, buffer
);
1001 t
->b
.buffer_offset
= buffer_offset
;
1002 t
->b
.buffer_size
= buffer_size
;
1004 t
->filled_size
= (struct r600_resource
*)
1005 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
1006 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
1007 memset(ptr
, 0, t
->filled_size
->buf
->size
);
1008 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
1013 static void r600_so_target_destroy(struct pipe_context
*ctx
,
1014 struct pipe_stream_output_target
*target
)
1016 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
1017 pipe_resource_reference(&t
->b
.buffer
, NULL
);
1018 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
1022 static void r600_set_so_targets(struct pipe_context
*ctx
,
1023 unsigned num_targets
,
1024 struct pipe_stream_output_target
**targets
,
1025 unsigned append_bitmask
)
1027 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1030 /* Stop streamout. */
1031 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
1032 r600_context_streamout_end(rctx
);
1035 /* Set the new targets. */
1036 for (i
= 0; i
< num_targets
; i
++) {
1037 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
1039 for (; i
< rctx
->num_so_targets
; i
++) {
1040 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
1043 rctx
->num_so_targets
= num_targets
;
1044 rctx
->streamout_start
= num_targets
!= 0;
1045 rctx
->streamout_append_bitmask
= append_bitmask
;
1048 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1050 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1052 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1055 rctx
->sample_mask
.sample_mask
= sample_mask
;
1056 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1059 static void r600_update_derived_state(struct r600_context
*rctx
)
1061 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1062 unsigned ps_dirty
= 0, blend_override
;
1064 if (!rctx
->blitter
->running
) {
1067 /* Decompress textures if needed. */
1068 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1069 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1070 if (views
->compressed_depthtex_mask
) {
1071 r600_decompress_depth_textures(rctx
, views
);
1073 if (views
->compressed_colortex_mask
) {
1074 r600_decompress_color_textures(rctx
, views
);
1079 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1081 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
1082 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
1083 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1085 if (rctx
->chip_class
>= EVERGREEN
)
1086 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1088 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1094 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1096 blend_override
= (rctx
->dual_src_blend
&&
1097 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1099 if (blend_override
!= rctx
->blend_override
) {
1100 rctx
->blend_override
= blend_override
;
1101 r600_bind_blend_state_internal(rctx
,
1102 blend_override
? rctx
->no_blend
: rctx
->blend
);
1105 if (rctx
->chip_class
>= EVERGREEN
) {
1106 evergreen_update_dual_export_state(rctx
);
1108 r600_update_dual_export_state(rctx
);
1112 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1114 static const int prim_conv
[] = {
1115 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1116 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1117 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1118 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1119 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1120 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1121 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1122 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1123 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1124 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1125 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1126 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1127 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1128 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1129 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1131 assert(mode
< Elements(prim_conv
));
1133 return prim_conv
[mode
];
1136 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1138 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1139 struct pipe_draw_info info
= *dinfo
;
1140 struct pipe_index_buffer ib
= {};
1141 unsigned prim
, ls_mask
= 0, i
;
1142 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1143 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1147 if ((!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) ||
1148 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
1153 if (!rctx
->vs_shader
) {
1158 r600_update_derived_state(rctx
);
1161 /* Initialize the index buffer struct. */
1162 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1163 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1164 ib
.index_size
= rctx
->index_buffer
.index_size
;
1165 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1167 /* Translate or upload, if needed. */
1168 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1170 ptr
= (uint8_t*)ib
.user_buffer
;
1171 if (!ib
.buffer
&& ptr
) {
1172 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1173 ptr
, &ib
.offset
, &ib
.buffer
);
1176 info
.index_bias
= info
.start
;
1179 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
1180 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
1181 rctx
->vgt
.nregs
= 0;
1182 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
1183 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0);
1184 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
);
1185 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
);
1186 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
);
1187 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1188 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A0C_PA_SC_LINE_STIPPLE
, 0);
1189 r600_pipe_state_add_reg(&rctx
->vgt
, R_02881C_PA_CL_VS_OUT_CNTL
, 0);
1190 r600_pipe_state_add_reg(&rctx
->vgt
, R_028810_PA_CL_CLIP_CNTL
, 0);
1193 rctx
->vgt
.nregs
= 0;
1194 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
1195 r600_pipe_state_mod_reg(&rctx
->vgt
, r600_conv_prim_to_gs_out(info
.mode
));
1196 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
1197 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
1198 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
1199 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
1201 if (prim
== V_008958_DI_PT_LINELIST
)
1203 else if (prim
== V_008958_DI_PT_LINESTRIP
||
1204 prim
== V_008958_DI_PT_LINELOOP
)
1206 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
1207 r600_pipe_state_mod_reg(&rctx
->vgt
,
1208 rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
|
1209 (rctx
->rasterizer
->clip_plane_enable
& rctx
->vs_shader
->current
->shader
.clip_dist_write
));
1210 r600_pipe_state_mod_reg(&rctx
->vgt
,
1211 rctx
->pa_cl_clip_cntl
|
1212 (rctx
->vs_shader
->current
->shader
.clip_dist_write
||
1213 rctx
->vs_shader
->current
->shader
.vs_prohibit_ucps
?
1214 0 : rctx
->rasterizer
->clip_plane_enable
& 0x3F));
1216 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
1218 /* Enable stream out if needed. */
1219 if (rctx
->streamout_start
) {
1220 r600_context_streamout_begin(rctx
);
1221 rctx
->streamout_start
= FALSE
;
1224 /* Emit states (the function expects that we emit at most 17 dwords here). */
1225 r600_need_cs_space(rctx
, 0, TRUE
);
1226 r600_flush_emit(rctx
);
1228 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1229 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1232 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1234 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1235 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1237 rctx
->pm4_dirty_cdwords
= 0;
1240 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1241 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1243 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1244 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1245 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1246 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1248 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1250 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1251 cs
->buf
[cs
->cdw
++] = va
;
1252 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1253 cs
->buf
[cs
->cdw
++] = info
.count
;
1254 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1255 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1256 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1258 if (info
.count_from_stream_output
) {
1259 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1260 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1262 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1264 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1265 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1266 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1267 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1268 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1269 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1271 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1272 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1275 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1276 cs
->buf
[cs
->cdw
++] = info
.count
;
1277 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1278 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1281 /* Set the depth buffer as dirty. */
1282 if (rctx
->framebuffer
.zsbuf
) {
1283 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
1284 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1286 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1288 if (rctx
->compressed_cb_mask
) {
1289 struct pipe_surface
*surf
;
1290 struct r600_texture
*rtex
;
1291 unsigned mask
= rctx
->compressed_cb_mask
;
1294 unsigned i
= u_bit_scan(&mask
);
1295 surf
= rctx
->framebuffer
.cbufs
[i
];
1296 rtex
= (struct r600_texture
*)surf
->texture
;
1298 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1303 pipe_resource_reference(&ib
.buffer
, NULL
);
1306 void r600_draw_rectangle(struct blitter_context
*blitter
,
1307 unsigned x1
, unsigned y1
, unsigned x2
, unsigned y2
, float depth
,
1308 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1310 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1311 struct pipe_viewport_state viewport
;
1312 struct pipe_resource
*buf
= NULL
;
1313 unsigned offset
= 0;
1316 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1317 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1321 /* Some operations (like color resolve on r6xx) don't work
1322 * with the conventional primitive types.
1323 * One that works is PT_RECTLIST, which we use here. */
1325 /* setup viewport */
1326 viewport
.scale
[0] = 1.0f
;
1327 viewport
.scale
[1] = 1.0f
;
1328 viewport
.scale
[2] = 1.0f
;
1329 viewport
.scale
[3] = 1.0f
;
1330 viewport
.translate
[0] = 0.0f
;
1331 viewport
.translate
[1] = 0.0f
;
1332 viewport
.translate
[2] = 0.0f
;
1333 viewport
.translate
[3] = 0.0f
;
1334 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1336 /* Upload vertices. The hw rectangle has only 3 vertices,
1337 * I guess the 4th one is derived from the first 3.
1338 * The vertex specification should match u_blitter's vertex element state. */
1339 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1356 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1357 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1358 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1362 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, offset
,
1363 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1364 pipe_resource_reference(&buf
, NULL
);
1367 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1368 struct r600_pipe_state
*state
,
1369 uint32_t offset
, uint32_t value
,
1370 uint32_t range_id
, uint32_t block_id
,
1371 struct r600_resource
*bo
,
1372 enum radeon_bo_usage usage
)
1375 struct r600_range
*range
;
1376 struct r600_block
*block
;
1378 if (bo
) assert(usage
);
1380 range
= &ctx
->range
[range_id
];
1381 block
= range
->blocks
[block_id
];
1382 state
->regs
[state
->nregs
].block
= block
;
1383 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1385 state
->regs
[state
->nregs
].value
= value
;
1386 state
->regs
[state
->nregs
].bo
= bo
;
1387 state
->regs
[state
->nregs
].bo_usage
= usage
;
1390 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1393 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1394 struct r600_pipe_state
*state
,
1395 uint32_t offset
, uint32_t value
,
1396 uint32_t range_id
, uint32_t block_id
)
1398 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1399 range_id
, block_id
, NULL
, 0);
1402 uint32_t r600_translate_stencil_op(int s_op
)
1405 case PIPE_STENCIL_OP_KEEP
:
1406 return V_028800_STENCIL_KEEP
;
1407 case PIPE_STENCIL_OP_ZERO
:
1408 return V_028800_STENCIL_ZERO
;
1409 case PIPE_STENCIL_OP_REPLACE
:
1410 return V_028800_STENCIL_REPLACE
;
1411 case PIPE_STENCIL_OP_INCR
:
1412 return V_028800_STENCIL_INCR
;
1413 case PIPE_STENCIL_OP_DECR
:
1414 return V_028800_STENCIL_DECR
;
1415 case PIPE_STENCIL_OP_INCR_WRAP
:
1416 return V_028800_STENCIL_INCR_WRAP
;
1417 case PIPE_STENCIL_OP_DECR_WRAP
:
1418 return V_028800_STENCIL_DECR_WRAP
;
1419 case PIPE_STENCIL_OP_INVERT
:
1420 return V_028800_STENCIL_INVERT
;
1422 R600_ERR("Unknown stencil op %d", s_op
);
1429 uint32_t r600_translate_fill(uint32_t func
)
1432 case PIPE_POLYGON_MODE_FILL
:
1434 case PIPE_POLYGON_MODE_LINE
:
1436 case PIPE_POLYGON_MODE_POINT
:
1444 unsigned r600_tex_wrap(unsigned wrap
)
1448 case PIPE_TEX_WRAP_REPEAT
:
1449 return V_03C000_SQ_TEX_WRAP
;
1450 case PIPE_TEX_WRAP_CLAMP
:
1451 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1452 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1453 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1454 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1455 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1456 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1457 return V_03C000_SQ_TEX_MIRROR
;
1458 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1459 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1460 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1461 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1462 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1463 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1467 unsigned r600_tex_filter(unsigned filter
)
1471 case PIPE_TEX_FILTER_NEAREST
:
1472 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1473 case PIPE_TEX_FILTER_LINEAR
:
1474 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1478 unsigned r600_tex_mipfilter(unsigned filter
)
1481 case PIPE_TEX_MIPFILTER_NEAREST
:
1482 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1483 case PIPE_TEX_MIPFILTER_LINEAR
:
1484 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1486 case PIPE_TEX_MIPFILTER_NONE
:
1487 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1491 unsigned r600_tex_compare(unsigned compare
)
1495 case PIPE_FUNC_NEVER
:
1496 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1497 case PIPE_FUNC_LESS
:
1498 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1499 case PIPE_FUNC_EQUAL
:
1500 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1501 case PIPE_FUNC_LEQUAL
:
1502 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1503 case PIPE_FUNC_GREATER
:
1504 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1505 case PIPE_FUNC_NOTEQUAL
:
1506 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1507 case PIPE_FUNC_GEQUAL
:
1508 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1509 case PIPE_FUNC_ALWAYS
:
1510 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1514 /* keep this at the end of this file, please */
1515 void r600_init_common_state_functions(struct r600_context
*rctx
)
1517 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1518 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1519 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1520 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1521 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1522 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1523 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1524 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1525 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1526 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1527 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1528 rctx
->context
.delete_blend_state
= r600_delete_state
;
1529 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1530 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1531 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1532 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1533 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1534 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1535 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1536 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1537 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1538 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1539 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1540 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1541 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1542 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1543 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1544 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1545 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1546 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1547 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1548 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1549 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1550 rctx
->context
.draw_vbo
= r600_draw_vbo
;