2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
98 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
99 R600_CONTEXT_FLUSH_AND_INV_CB
|
100 R600_CONTEXT_FLUSH_AND_INV
|
101 R600_CONTEXT_WAIT_3D_IDLE
;
102 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
105 static unsigned r600_conv_pipe_prim(unsigned prim
)
107 static const unsigned prim_conv
[] = {
108 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
109 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
110 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
111 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
112 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
113 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
114 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
115 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
116 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
117 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
118 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
119 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
120 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
121 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
122 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
123 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
125 assert(prim
< ARRAY_SIZE(prim_conv
));
126 return prim_conv
[prim
];
129 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
131 static const int prim_conv
[] = {
132 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
133 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
134 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
135 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
136 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
138 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
139 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
140 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
141 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
142 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
143 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
144 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
145 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
146 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
147 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
149 assert(mode
< ARRAY_SIZE(prim_conv
));
151 return prim_conv
[mode
];
154 /* common state between evergreen and r600 */
156 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
157 struct r600_blend_state
*blend
, bool blend_disable
)
159 unsigned color_control
;
160 bool update_cb
= false;
162 rctx
->alpha_to_one
= blend
->alpha_to_one
;
163 rctx
->dual_src_blend
= blend
->dual_src_blend
;
165 if (!blend_disable
) {
166 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
167 color_control
= blend
->cb_color_control
;
169 /* Blending is disabled. */
170 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
171 color_control
= blend
->cb_color_control_no_blend
;
174 /* Update derived states. */
175 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
176 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
179 if (rctx
->b
.chip_class
<= R700
&&
180 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
181 rctx
->cb_misc_state
.cb_color_control
= color_control
;
184 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
185 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
189 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
191 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
192 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
193 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
197 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
199 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
200 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
203 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
207 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
210 static void r600_set_blend_color(struct pipe_context
*ctx
,
211 const struct pipe_blend_color
*state
)
213 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
215 rctx
->blend_color
.state
= *state
;
216 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
219 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
221 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
222 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
224 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
225 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
226 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
227 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
228 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
231 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
233 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
234 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
236 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
237 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
238 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
239 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
240 if (a
->last_draw_was_indirect
) {
241 a
->last_draw_was_indirect
= false;
242 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
246 static void r600_set_clip_state(struct pipe_context
*ctx
,
247 const struct pipe_clip_state
*state
)
249 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
251 rctx
->clip_state
.state
= *state
;
252 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
253 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
256 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
257 const struct r600_stencil_ref
*state
)
259 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
261 rctx
->stencil_ref
.state
= *state
;
262 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
265 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
267 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
268 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
270 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
271 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
272 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
273 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
274 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
275 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
276 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
277 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
278 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
281 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
282 const struct pipe_stencil_ref
*state
)
284 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
285 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
286 struct r600_stencil_ref ref
;
288 rctx
->stencil_ref
.pipe_state
= *state
;
293 ref
.ref_value
[0] = state
->ref_value
[0];
294 ref
.ref_value
[1] = state
->ref_value
[1];
295 ref
.valuemask
[0] = dsa
->valuemask
[0];
296 ref
.valuemask
[1] = dsa
->valuemask
[1];
297 ref
.writemask
[0] = dsa
->writemask
[0];
298 ref
.writemask
[1] = dsa
->writemask
[1];
300 r600_set_stencil_ref(ctx
, &ref
);
303 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
305 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
306 struct r600_dsa_state
*dsa
= state
;
307 struct r600_stencil_ref ref
;
310 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
314 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
316 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
317 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
318 ref
.valuemask
[0] = dsa
->valuemask
[0];
319 ref
.valuemask
[1] = dsa
->valuemask
[1];
320 ref
.writemask
[0] = dsa
->writemask
[0];
321 ref
.writemask
[1] = dsa
->writemask
[1];
322 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
323 rctx
->zwritemask
= dsa
->zwritemask
;
324 if (rctx
->b
.chip_class
>= EVERGREEN
) {
325 /* work around some issue when not writing to zbuffer
326 * we are having lockup on evergreen so do not enable
327 * hyperz when not writing zbuffer
329 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
333 r600_set_stencil_ref(ctx
, &ref
);
335 /* Update alphatest state. */
336 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
337 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
338 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
339 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
340 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
344 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
346 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
347 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
352 rctx
->rasterizer
= rs
;
354 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
356 if (rs
->offset_enable
&&
357 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
358 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
359 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
360 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
361 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
362 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
363 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
366 /* Update clip_misc_state. */
367 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
368 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
369 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
370 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
371 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
374 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
376 /* Re-emit PA_SC_LINE_STIPPLE. */
377 rctx
->last_primitive_type
= -1;
380 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
382 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
384 r600_release_command_buffer(&rs
->buffer
);
388 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
389 struct pipe_sampler_view
*state
)
391 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
393 if (view
->tex_resource
->gpu_address
&&
394 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
395 LIST_DELINIT(&view
->list
);
397 pipe_resource_reference(&state
->texture
, NULL
);
401 void r600_sampler_states_dirty(struct r600_context
*rctx
,
402 struct r600_sampler_states
*state
)
404 if (state
->dirty_mask
) {
405 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
406 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
409 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
410 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
411 r600_mark_atom_dirty(rctx
, &state
->atom
);
415 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
416 enum pipe_shader_type shader
,
418 unsigned count
, void **states
)
420 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
421 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
422 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
423 int seamless_cube_map
= -1;
425 /* This sets 1-bit for states with index >= count. */
426 uint32_t disable_mask
= ~((1ull << count
) - 1);
427 /* These are the new states set by this function. */
428 uint32_t new_mask
= 0;
430 assert(start
== 0); /* XXX fix below */
437 for (i
= 0; i
< count
; i
++) {
438 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
440 if (rstate
== dst
->states
.states
[i
]) {
445 if (rstate
->border_color_use
) {
446 dst
->states
.has_bordercolor_mask
|= 1 << i
;
448 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
450 seamless_cube_map
= rstate
->seamless_cube_map
;
454 disable_mask
|= 1 << i
;
458 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
459 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
461 dst
->states
.enabled_mask
&= ~disable_mask
;
462 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
463 dst
->states
.enabled_mask
|= new_mask
;
464 dst
->states
.dirty_mask
|= new_mask
;
465 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
467 r600_sampler_states_dirty(rctx
, &dst
->states
);
469 /* Seamless cubemap state. */
470 if (rctx
->b
.chip_class
<= R700
&&
471 seamless_cube_map
!= -1 &&
472 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
473 /* change in TA_CNTL_AUX need a pipeline flush */
474 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
475 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
476 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
480 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
485 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
487 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
488 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
490 if (rctx
->blend_state
.cso
== state
) {
491 ctx
->bind_blend_state(ctx
, NULL
);
494 r600_release_command_buffer(&blend
->buffer
);
495 r600_release_command_buffer(&blend
->buffer_no_blend
);
499 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
501 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
502 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
504 if (rctx
->dsa_state
.cso
== state
) {
505 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
508 r600_release_command_buffer(&dsa
->buffer
);
512 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
514 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
516 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
519 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
521 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
522 r600_resource_reference(&shader
->buffer
, NULL
);
526 static void r600_set_index_buffer(struct pipe_context
*ctx
,
527 const struct pipe_index_buffer
*ib
)
529 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
532 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
533 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
534 r600_context_add_resource_size(ctx
, ib
->buffer
);
536 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
540 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
542 if (rctx
->vertex_buffer_state
.dirty_mask
) {
543 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
544 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
545 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
549 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
550 unsigned start_slot
, unsigned count
,
551 const struct pipe_vertex_buffer
*input
)
553 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
554 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
555 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
557 uint32_t disable_mask
= 0;
558 /* These are the new buffers set by this function. */
559 uint32_t new_buffer_mask
= 0;
561 /* Set vertex buffers. */
563 for (i
= 0; i
< count
; i
++) {
564 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
565 if (input
[i
].buffer
) {
566 vb
[i
].stride
= input
[i
].stride
;
567 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
568 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
569 new_buffer_mask
|= 1 << i
;
570 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
572 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
573 disable_mask
|= 1 << i
;
578 for (i
= 0; i
< count
; i
++) {
579 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
581 disable_mask
= ((1ull << count
) - 1);
584 disable_mask
<<= start_slot
;
585 new_buffer_mask
<<= start_slot
;
587 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
588 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
589 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
590 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
592 r600_vertex_buffers_dirty(rctx
);
595 void r600_sampler_views_dirty(struct r600_context
*rctx
,
596 struct r600_samplerview_state
*state
)
598 if (state
->dirty_mask
) {
599 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
600 util_bitcount(state
->dirty_mask
);
601 r600_mark_atom_dirty(rctx
, &state
->atom
);
605 static void r600_set_sampler_views(struct pipe_context
*pipe
,
606 enum pipe_shader_type shader
,
607 unsigned start
, unsigned count
,
608 struct pipe_sampler_view
**views
)
610 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
611 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
612 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
613 uint32_t dirty_sampler_states_mask
= 0;
615 /* This sets 1-bit for textures with index >= count. */
616 uint32_t disable_mask
= ~((1ull << count
) - 1);
617 /* These are the new textures set by this function. */
618 uint32_t new_mask
= 0;
620 /* Set textures with index >= count to NULL. */
621 uint32_t remaining_mask
;
623 assert(start
== 0); /* XXX fix below */
630 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
632 while (remaining_mask
) {
633 i
= u_bit_scan(&remaining_mask
);
634 assert(dst
->views
.views
[i
]);
636 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
639 for (i
= 0; i
< count
; i
++) {
640 if (rviews
[i
] == dst
->views
.views
[i
]) {
645 struct r600_texture
*rtex
=
646 (struct r600_texture
*)rviews
[i
]->base
.texture
;
647 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
649 if (!is_buffer
&& rtex
->db_compatible
) {
650 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
652 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
655 /* Track compressed colorbuffers. */
656 if (!is_buffer
&& rtex
->cmask
.size
) {
657 dst
->views
.compressed_colortex_mask
|= 1 << i
;
659 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
662 /* Changing from array to non-arrays textures and vice versa requires
663 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
664 if (rctx
->b
.chip_class
<= R700
&&
665 (dst
->states
.enabled_mask
& (1 << i
)) &&
666 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
667 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
668 dirty_sampler_states_mask
|= 1 << i
;
671 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
673 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
675 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
676 disable_mask
|= 1 << i
;
680 dst
->views
.enabled_mask
&= ~disable_mask
;
681 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
682 dst
->views
.enabled_mask
|= new_mask
;
683 dst
->views
.dirty_mask
|= new_mask
;
684 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
685 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
686 dst
->views
.dirty_buffer_constants
= TRUE
;
687 r600_sampler_views_dirty(rctx
, &dst
->views
);
689 if (dirty_sampler_states_mask
) {
690 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
691 r600_sampler_states_dirty(rctx
, &dst
->states
);
695 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
697 uint32_t mask
= views
->enabled_mask
;
700 unsigned i
= u_bit_scan(&mask
);
701 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
703 if (res
&& res
->target
!= PIPE_BUFFER
) {
704 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
706 if (rtex
->cmask
.size
) {
707 views
->compressed_colortex_mask
|= 1 << i
;
709 views
->compressed_colortex_mask
&= ~(1 << i
);
715 /* Compute the key for the hw shader variant */
716 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
717 const struct r600_pipe_shader_selector
*sel
,
718 union r600_shader_key
*key
)
720 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
721 memset(key
, 0, sizeof(*key
));
724 case PIPE_SHADER_VERTEX
: {
725 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
727 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
729 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
730 key
->vs
.as_gs_a
= true;
731 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
735 case PIPE_SHADER_GEOMETRY
:
737 case PIPE_SHADER_FRAGMENT
: {
738 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
739 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
740 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
741 !rctx
->framebuffer
.cb0_is_integer
;
742 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
743 /* Dual-source blending only makes sense with nr_cbufs == 1. */
744 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
745 key
->ps
.nr_cbufs
= 2;
748 case PIPE_SHADER_TESS_EVAL
:
749 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
751 case PIPE_SHADER_TESS_CTRL
:
752 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
759 /* Select the hw shader variant depending on the current state.
760 * (*dirty) is set to 1 if current variant was changed */
761 static int r600_shader_select(struct pipe_context
*ctx
,
762 struct r600_pipe_shader_selector
* sel
,
765 union r600_shader_key key
;
766 struct r600_pipe_shader
* shader
= NULL
;
769 r600_shader_selector_key(ctx
, sel
, &key
);
771 /* Check if we don't need to change anything.
772 * This path is also used for most shaders that don't need multiple
773 * variants, it will cost just a computation of the key and this
775 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
779 /* lookup if we have other variants in the list */
780 if (sel
->num_shaders
> 1) {
781 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
783 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
789 p
->next_variant
= c
->next_variant
;
794 if (unlikely(!shader
)) {
795 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
796 shader
->selector
= sel
;
798 r
= r600_pipe_shader_create(ctx
, shader
, key
);
800 R600_ERR("Failed to build shader variant (type=%u) %d\n",
807 /* We don't know the value of nr_ps_max_color_exports until we built
808 * at least one variant, so we may need to recompute the key after
809 * building first variant. */
810 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
811 sel
->num_shaders
== 0) {
812 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
813 r600_shader_selector_key(ctx
, sel
, &key
);
816 memcpy(&shader
->key
, &key
, sizeof(key
));
823 shader
->next_variant
= sel
->current
;
824 sel
->current
= shader
;
829 static void *r600_create_shader_state(struct pipe_context
*ctx
,
830 const struct pipe_shader_state
*state
,
831 unsigned pipe_shader_type
)
833 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
836 sel
->type
= pipe_shader_type
;
837 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
838 sel
->so
= state
->stream_output
;
839 tgsi_scan_shader(state
->tokens
, &sel
->info
);
841 switch (pipe_shader_type
) {
842 case PIPE_SHADER_GEOMETRY
:
843 sel
->gs_output_prim
=
844 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
845 sel
->gs_max_out_vertices
=
846 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
847 sel
->gs_num_invocations
=
848 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
850 case PIPE_SHADER_VERTEX
:
851 case PIPE_SHADER_TESS_CTRL
:
852 sel
->lds_patch_outputs_written_mask
= 0;
853 sel
->lds_outputs_written_mask
= 0;
855 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
856 unsigned name
= sel
->info
.output_semantic_name
[i
];
857 unsigned index
= sel
->info
.output_semantic_index
[i
];
860 case TGSI_SEMANTIC_TESSINNER
:
861 case TGSI_SEMANTIC_TESSOUTER
:
862 case TGSI_SEMANTIC_PATCH
:
863 sel
->lds_patch_outputs_written_mask
|=
864 1llu << r600_get_lds_unique_index(name
, index
);
867 sel
->lds_outputs_written_mask
|=
868 1llu << r600_get_lds_unique_index(name
, index
);
879 static void *r600_create_ps_state(struct pipe_context
*ctx
,
880 const struct pipe_shader_state
*state
)
882 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
885 static void *r600_create_vs_state(struct pipe_context
*ctx
,
886 const struct pipe_shader_state
*state
)
888 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
891 static void *r600_create_gs_state(struct pipe_context
*ctx
,
892 const struct pipe_shader_state
*state
)
894 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
897 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
898 const struct pipe_shader_state
*state
)
900 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
903 static void *r600_create_tes_state(struct pipe_context
*ctx
,
904 const struct pipe_shader_state
*state
)
906 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
909 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
911 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
914 state
= rctx
->dummy_pixel_shader
;
916 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
919 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
922 return &rctx
->gs_shader
->info
;
923 else if (rctx
->tes_shader
)
924 return &rctx
->tes_shader
->info
;
925 else if (rctx
->vs_shader
)
926 return &rctx
->vs_shader
->info
;
931 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
933 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
935 if (!state
|| rctx
->vs_shader
== state
)
938 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
939 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
940 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
943 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
945 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
947 if (state
== rctx
->gs_shader
)
950 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
951 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
955 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
958 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
960 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
962 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
965 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
967 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
969 if (state
== rctx
->tes_shader
)
972 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
973 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
977 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
980 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
981 struct r600_pipe_shader_selector
*sel
)
983 struct r600_pipe_shader
*p
= sel
->current
, *c
;
986 r600_pipe_shader_destroy(ctx
, p
);
996 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
998 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
999 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1001 if (rctx
->ps_shader
== sel
) {
1002 rctx
->ps_shader
= NULL
;
1005 r600_delete_shader_selector(ctx
, sel
);
1008 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1010 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1011 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1013 if (rctx
->vs_shader
== sel
) {
1014 rctx
->vs_shader
= NULL
;
1017 r600_delete_shader_selector(ctx
, sel
);
1021 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1023 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1024 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1026 if (rctx
->gs_shader
== sel
) {
1027 rctx
->gs_shader
= NULL
;
1030 r600_delete_shader_selector(ctx
, sel
);
1033 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1035 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1036 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1038 if (rctx
->tcs_shader
== sel
) {
1039 rctx
->tcs_shader
= NULL
;
1042 r600_delete_shader_selector(ctx
, sel
);
1045 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1047 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1048 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1050 if (rctx
->tes_shader
== sel
) {
1051 rctx
->tes_shader
= NULL
;
1054 r600_delete_shader_selector(ctx
, sel
);
1057 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1059 if (state
->dirty_mask
) {
1060 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1061 : util_bitcount(state
->dirty_mask
)*19;
1062 r600_mark_atom_dirty(rctx
, &state
->atom
);
1066 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1067 enum pipe_shader_type shader
, uint index
,
1068 const struct pipe_constant_buffer
*input
)
1070 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1071 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1072 struct pipe_constant_buffer
*cb
;
1075 /* Note that the state tracker can unbind constant buffers by
1076 * passing NULL here.
1078 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1079 state
->enabled_mask
&= ~(1 << index
);
1080 state
->dirty_mask
&= ~(1 << index
);
1081 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1085 cb
= &state
->cb
[index
];
1086 cb
->buffer_size
= input
->buffer_size
;
1088 ptr
= input
->user_buffer
;
1091 /* Upload the user buffer. */
1092 if (R600_BIG_ENDIAN
) {
1094 unsigned i
, size
= input
->buffer_size
;
1096 if (!(tmpPtr
= malloc(size
))) {
1097 R600_ERR("Failed to allocate BE swap buffer.\n");
1101 for (i
= 0; i
< size
/ 4; ++i
) {
1102 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1105 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1106 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1109 u_upload_data(ctx
->stream_uploader
, 0,
1110 input
->buffer_size
, 256, ptr
,
1111 &cb
->buffer_offset
, &cb
->buffer
);
1113 /* account it in gtt */
1114 rctx
->b
.gtt
+= input
->buffer_size
;
1116 /* Setup the hw buffer. */
1117 cb
->buffer_offset
= input
->buffer_offset
;
1118 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1119 r600_context_add_resource_size(ctx
, input
->buffer
);
1122 state
->enabled_mask
|= 1 << index
;
1123 state
->dirty_mask
|= 1 << index
;
1124 r600_constant_buffers_dirty(rctx
, state
);
1127 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1129 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1131 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1134 rctx
->sample_mask
.sample_mask
= sample_mask
;
1135 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1138 static void r600_update_driver_const_buffers(struct r600_context
*rctx
)
1142 struct pipe_constant_buffer cb
;
1143 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
1144 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1145 if (!info
->vs_ucp_dirty
&&
1146 !info
->texture_const_dirty
&&
1147 !info
->ps_sample_pos_dirty
)
1150 ptr
= info
->constants
;
1151 size
= info
->alloc_size
;
1152 if (info
->vs_ucp_dirty
) {
1153 assert(sh
== PIPE_SHADER_VERTEX
);
1155 ptr
= rctx
->clip_state
.state
.ucp
;
1156 size
= R600_UCP_SIZE
;
1158 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1160 info
->vs_ucp_dirty
= false;
1163 if (info
->ps_sample_pos_dirty
) {
1164 assert(sh
== PIPE_SHADER_FRAGMENT
);
1166 ptr
= rctx
->sample_positions
;
1167 size
= R600_UCP_SIZE
;
1169 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1171 info
->ps_sample_pos_dirty
= false;
1174 if (info
->texture_const_dirty
) {
1177 if (sh
== PIPE_SHADER_VERTEX
)
1178 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1179 if (sh
== PIPE_SHADER_FRAGMENT
)
1180 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1182 info
->texture_const_dirty
= false;
1185 cb
.user_buffer
= ptr
;
1186 cb
.buffer_offset
= 0;
1187 cb
.buffer_size
= size
;
1188 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1189 pipe_resource_reference(&cb
.buffer
, NULL
);
1193 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1194 int array_size
, uint32_t *base_offset
)
1196 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1197 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1198 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1199 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1201 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1202 info
->texture_const_dirty
= true;
1203 *base_offset
= R600_UCP_SIZE
;
1204 return info
->constants
;
1207 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1208 * doesn't require full swizzles it does need masking and setting alpha
1209 * to one, so we setup a set of 5 constants with the masks + alpha value
1210 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1211 * then OR the alpha with the value given here.
1212 * We use a 6th constant to store the txq buffer size in
1213 * we use 7th slot for number of cube layers in a cube map array.
1215 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1217 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1219 uint32_t array_size
;
1221 uint32_t *constants
;
1222 uint32_t base_offset
;
1223 if (!samplers
->views
.dirty_buffer_constants
)
1226 samplers
->views
.dirty_buffer_constants
= FALSE
;
1228 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1229 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1231 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1233 for (i
= 0; i
< bits
; i
++) {
1234 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1235 int offset
= (base_offset
/ 4) + i
* 8;
1236 const struct util_format_description
*desc
;
1237 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1239 for (j
= 0; j
< 4; j
++)
1240 if (j
< desc
->nr_channels
)
1241 constants
[offset
+j
] = 0xffffffff;
1243 constants
[offset
+j
] = 0x0;
1244 if (desc
->nr_channels
< 4) {
1245 if (desc
->channel
[0].pure_integer
)
1246 constants
[offset
+4] = 1;
1248 constants
[offset
+4] = fui(1.0);
1250 constants
[offset
+ 4] = 0;
1252 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1253 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1259 /* On evergreen we store two values
1260 * 1. buffer size for TXQ
1261 * 2. number of cube layers in a cube map array.
1263 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1265 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1267 uint32_t array_size
;
1269 uint32_t *constants
;
1270 uint32_t base_offset
;
1271 if (!samplers
->views
.dirty_buffer_constants
)
1274 samplers
->views
.dirty_buffer_constants
= FALSE
;
1276 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1277 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1279 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1282 for (i
= 0; i
< bits
; i
++) {
1283 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1284 uint32_t offset
= (base_offset
/ 4) + i
* 2;
1285 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1286 constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1291 /* set sample xy locations as array of fragment shader constants */
1292 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1295 struct pipe_context
*ctx
= &rctx
->b
.b
;
1297 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1298 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1300 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1301 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1302 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1303 /* Also fill in center-zeroed positions used for interpolateAtSample */
1304 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1305 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1308 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1311 static void update_shader_atom(struct pipe_context
*ctx
,
1312 struct r600_shader_state
*state
,
1313 struct r600_pipe_shader
*shader
)
1315 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1317 state
->shader
= shader
;
1319 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1320 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1322 state
->atom
.num_dw
= 0;
1324 r600_mark_atom_dirty(rctx
, &state
->atom
);
1327 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1329 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1330 rctx
->shader_stages
.geom_enable
= enable
;
1331 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1334 if (rctx
->gs_rings
.enable
!= enable
) {
1335 rctx
->gs_rings
.enable
= enable
;
1336 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1338 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1339 unsigned size
= 0x1C000;
1340 rctx
->gs_rings
.esgs_ring
.buffer
=
1341 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1342 PIPE_USAGE_DEFAULT
, size
);
1343 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1347 rctx
->gs_rings
.gsvs_ring
.buffer
=
1348 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1349 PIPE_USAGE_DEFAULT
, size
);
1350 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1354 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1355 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1356 if (rctx
->tes_shader
) {
1357 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1358 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1360 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1361 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1364 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1365 R600_GS_RING_CONST_BUFFER
, NULL
);
1366 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1367 R600_GS_RING_CONST_BUFFER
, NULL
);
1368 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1369 R600_GS_RING_CONST_BUFFER
, NULL
);
1374 static void r600_update_clip_state(struct r600_context
*rctx
,
1375 struct r600_pipe_shader
*current
)
1377 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1378 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1379 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1380 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1381 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1382 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1383 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1384 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1385 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1389 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1391 struct ureg_src const0
, const1
;
1392 struct ureg_dst tessouter
, tessinner
;
1393 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1396 return; /* if we get here, we're screwed */
1398 assert(!rctx
->fixed_func_tcs_shader
);
1400 ureg_DECL_constant2D(ureg
, 0, 3, R600_LDS_INFO_CONST_BUFFER
);
1401 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 2),
1402 R600_LDS_INFO_CONST_BUFFER
);
1403 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 3),
1404 R600_LDS_INFO_CONST_BUFFER
);
1406 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1407 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1409 ureg_MOV(ureg
, tessouter
, const0
);
1410 ureg_MOV(ureg
, tessinner
, const1
);
1413 rctx
->fixed_func_tcs_shader
=
1414 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1417 #define SELECT_SHADER_OR_FAIL(x) do { \
1418 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1419 if (unlikely(!rctx->x##_shader->current)) \
1423 #define UPDATE_SHADER(hw, sw) do { \
1424 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1425 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1428 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1429 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1430 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1431 clip_so_current = rctx->sw##_shader->current; \
1435 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1436 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1437 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1438 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1439 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1443 #define SET_NULL_SHADER(hw) do { \
1444 if (rctx->hw_shader_stages[(hw)].shader) \
1445 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1448 static bool r600_update_derived_state(struct r600_context
*rctx
)
1450 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1451 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1452 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1454 bool need_buf_const
;
1455 struct r600_pipe_shader
*clip_so_current
= NULL
;
1457 if (!rctx
->blitter
->running
) {
1461 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1462 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1463 rctx
->b
.last_compressed_colortex_counter
= counter
;
1465 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1466 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1470 /* Decompress textures if needed. */
1471 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1472 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1473 if (views
->compressed_depthtex_mask
) {
1474 r600_decompress_depth_textures(rctx
, views
);
1476 if (views
->compressed_colortex_mask
) {
1477 r600_decompress_color_textures(rctx
, views
);
1482 SELECT_SHADER_OR_FAIL(ps
);
1484 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1486 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1488 if (rctx
->gs_shader
)
1489 SELECT_SHADER_OR_FAIL(gs
);
1492 if (rctx
->tcs_shader
) {
1493 SELECT_SHADER_OR_FAIL(tcs
);
1495 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1496 } else if (rctx
->tes_shader
) {
1497 if (!rctx
->fixed_func_tcs_shader
) {
1498 r600_generate_fixed_func_tcs(rctx
);
1499 if (!rctx
->fixed_func_tcs_shader
)
1503 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1505 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1507 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1509 if (rctx
->tes_shader
) {
1510 SELECT_SHADER_OR_FAIL(tes
);
1513 SELECT_SHADER_OR_FAIL(vs
);
1515 if (rctx
->gs_shader
) {
1516 if (!rctx
->shader_stages
.geom_enable
) {
1517 rctx
->shader_stages
.geom_enable
= true;
1518 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1521 /* gs_shader provides GS and VS (copy shader) */
1522 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1524 /* vs_shader is used as ES */
1526 if (rctx
->tes_shader
) {
1527 /* VS goes to LS, TES goes to ES */
1528 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1529 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1531 /* vs_shader is used as ES */
1532 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1533 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1536 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1537 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1538 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1539 rctx
->shader_stages
.geom_enable
= false;
1540 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1543 if (rctx
->tes_shader
) {
1544 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1545 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1546 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1548 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1549 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1553 /* Update clip misc state. */
1554 if (clip_so_current
) {
1555 r600_update_clip_state(rctx
, clip_so_current
);
1556 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1559 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1560 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1561 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1563 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1564 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1565 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1568 if (rctx
->b
.chip_class
<= R700
) {
1569 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1571 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1572 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1573 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1577 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1578 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1579 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1581 if (rctx
->b
.chip_class
>= EVERGREEN
)
1582 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1584 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1587 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1589 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1591 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1592 evergreen_update_db_shader_control(rctx
);
1594 r600_update_db_shader_control(rctx
);
1597 /* on R600 we stuff masks + txq info into one constant buffer */
1598 /* on evergreen we only need a txq info one */
1599 if (rctx
->ps_shader
) {
1600 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1601 if (need_buf_const
) {
1602 if (rctx
->b
.chip_class
< EVERGREEN
)
1603 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1605 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1609 if (rctx
->vs_shader
) {
1610 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1611 if (need_buf_const
) {
1612 if (rctx
->b
.chip_class
< EVERGREEN
)
1613 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1615 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1619 if (rctx
->gs_shader
) {
1620 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1621 if (need_buf_const
) {
1622 if (rctx
->b
.chip_class
< EVERGREEN
)
1623 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1625 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1629 r600_update_driver_const_buffers(rctx
);
1631 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1632 if (!r600_adjust_gprs(rctx
)) {
1633 /* discard rendering */
1638 if (rctx
->b
.chip_class
== EVERGREEN
) {
1639 if (!evergreen_adjust_gprs(rctx
)) {
1640 /* discard rendering */
1645 blend_disable
= (rctx
->dual_src_blend
&&
1646 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1648 if (blend_disable
!= rctx
->force_blend_disable
) {
1649 rctx
->force_blend_disable
= blend_disable
;
1650 r600_bind_blend_state_internal(rctx
,
1651 rctx
->blend_state
.cso
,
1658 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1660 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1661 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1663 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1664 state
->pa_cl_clip_cntl
|
1665 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1666 S_028810_CLIP_DISABLE(state
->clip_disable
));
1667 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1668 state
->pa_cl_vs_out_cntl
|
1669 (state
->clip_plane_enable
& state
->clip_dist_write
));
1670 /* reuse needs to be set off if we write oViewport */
1671 if (rctx
->b
.chip_class
>= EVERGREEN
)
1672 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1673 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1676 /* rast_prim is the primitive type after GS. */
1677 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
1679 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1680 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
1682 /* Skip this if not rendering lines. */
1683 if (rast_prim
!= PIPE_PRIM_LINES
&&
1684 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
1685 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
1686 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
1687 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
1690 if (rast_prim
== rctx
->last_rast_prim
)
1693 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1694 * reset the stipple pattern at each packet (line strips, line loops).
1696 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1697 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
1698 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1699 rctx
->last_rast_prim
= rast_prim
;
1702 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1704 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1705 struct pipe_index_buffer ib
= {};
1706 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1707 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
1709 unsigned num_patches
, dirty_tex_counter
;
1712 if (!info
->indirect
&& !info
->count
&& (info
->indexed
|| !info
->count_from_stream_output
)) {
1716 if (unlikely(!rctx
->vs_shader
)) {
1720 if (unlikely(!rctx
->ps_shader
&&
1721 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
1726 /* make sure that the gfx ring is only one active */
1727 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
1728 rctx
->b
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1731 /* Re-emit the framebuffer state if needed. */
1732 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
1733 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
1734 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1735 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1736 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
1739 if (!r600_update_derived_state(rctx
)) {
1740 /* useless to render because current rendering command
1746 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
1747 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
1750 if (info
->indexed
) {
1751 /* Initialize the index buffer struct. */
1752 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1753 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1754 ib
.index_size
= rctx
->index_buffer
.index_size
;
1755 ib
.offset
= rctx
->index_buffer
.offset
;
1756 if (!info
->indirect
) {
1757 ib
.offset
+= info
->start
* ib
.index_size
;
1760 /* Translate 8-bit indices to 16-bit. */
1761 if (unlikely(ib
.index_size
== 1)) {
1762 struct pipe_resource
*out_buffer
= NULL
;
1763 unsigned out_offset
;
1765 unsigned start
, count
;
1767 if (likely(!info
->indirect
)) {
1769 count
= info
->count
;
1772 /* Have to get start/count from indirect buffer, slow path ahead... */
1773 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
;
1774 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1775 PIPE_TRANSFER_READ
);
1777 data
+= info
->indirect_offset
/ sizeof(unsigned);
1778 start
= data
[2] * ib
.index_size
;
1787 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
1788 256, &out_offset
, &out_buffer
, &ptr
);
1789 if (unlikely(!ptr
)) {
1790 pipe_resource_reference(&ib
.buffer
, NULL
);
1794 util_shorten_ubyte_elts_to_userptr(
1795 &rctx
->b
.b
, &ib
, 0, 0, ib
.offset
+ start
, count
, ptr
);
1797 pipe_resource_reference(&ib
.buffer
, NULL
);
1798 ib
.user_buffer
= NULL
;
1799 ib
.buffer
= out_buffer
;
1800 ib
.offset
= out_offset
;
1804 /* Upload the index buffer.
1805 * The upload is skipped for small index counts on little-endian machines
1806 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1807 * Indirect draws never use immediate indices.
1808 * Note: Instanced rendering in combination with immediate indices hangs. */
1809 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
->indirect
||
1810 info
->instance_count
> 1 ||
1811 info
->count
*ib
.index_size
> 20)) {
1812 u_upload_data(ctx
->stream_uploader
, 0,
1813 info
->count
* ib
.index_size
, 256,
1814 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1815 ib
.user_buffer
= NULL
;
1817 index_bias
= info
->index_bias
;
1819 index_bias
= info
->start
;
1822 /* Set the index offset and primitive restart. */
1823 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
1824 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
1825 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
1826 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
1827 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
1828 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
1829 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
1830 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1833 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1834 if (rctx
->b
.chip_class
== R600
) {
1835 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1836 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1839 if (rctx
->b
.chip_class
>= EVERGREEN
)
1840 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
1843 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1844 r600_flush_emit(rctx
);
1846 mask
= rctx
->dirty_atoms
;
1848 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
1851 if (rctx
->b
.chip_class
== CAYMAN
) {
1852 /* Copied from radeonsi. */
1853 unsigned primgroup_size
= 128; /* recommended without a GS */
1854 bool ia_switch_on_eop
= false;
1855 bool partial_vs_wave
= false;
1857 if (rctx
->gs_shader
)
1858 primgroup_size
= 64; /* recommended with a GS */
1860 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1861 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1862 ia_switch_on_eop
= true;
1865 if (r600_get_strmout_en(&rctx
->b
))
1866 partial_vs_wave
= true;
1868 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1869 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1870 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1871 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1874 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1875 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
1878 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
1879 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
1882 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1883 * even though it should have no effect on those. */
1884 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1885 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1886 unsigned prim
= info
->mode
;
1888 if (rctx
->gs_shader
) {
1889 prim
= rctx
->gs_shader
->gs_output_prim
;
1891 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1893 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1894 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1895 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
1896 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1898 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1901 /* Update start instance. */
1902 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
1903 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
1904 rctx
->last_start_instance
= info
->start_instance
;
1907 /* Update the primitive type. */
1908 if (rctx
->last_primitive_type
!= info
->mode
) {
1909 r600_emit_rasterizer_prim_state(rctx
);
1910 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1911 r600_conv_pipe_prim(info
->mode
));
1913 rctx
->last_primitive_type
= info
->mode
;
1917 if (likely(!info
->indirect
)) {
1918 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
1919 radeon_emit(cs
, info
->instance_count
);
1921 uint64_t va
= r600_resource(info
->indirect
)->gpu_address
;
1922 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1924 // Invalidate so non-indirect draw calls reset this state
1925 rctx
->vgt_state
.last_draw_was_indirect
= true;
1926 rctx
->last_start_instance
= -1;
1928 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
1929 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
1930 radeon_emit(cs
, va
);
1931 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1933 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1934 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1935 (struct r600_resource
*)info
->indirect
,
1937 RADEON_PRIO_DRAW_INDIRECT
));
1940 if (info
->indexed
) {
1941 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
1942 radeon_emit(cs
, ib
.index_size
== 4 ?
1943 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1944 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
1946 if (ib
.user_buffer
) {
1947 unsigned size_bytes
= info
->count
*ib
.index_size
;
1948 unsigned size_dw
= align(size_bytes
, 4) / 4;
1949 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
1950 radeon_emit(cs
, info
->count
);
1951 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
1952 radeon_emit_array(cs
, ib
.user_buffer
, size_dw
);
1954 uint64_t va
= r600_resource(ib
.buffer
)->gpu_address
+ ib
.offset
;
1956 if (likely(!info
->indirect
)) {
1957 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
1958 radeon_emit(cs
, va
);
1959 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1960 radeon_emit(cs
, info
->count
);
1961 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1962 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1963 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1964 (struct r600_resource
*)ib
.buffer
,
1966 RADEON_PRIO_INDEX_BUFFER
));
1969 uint32_t max_size
= (ib
.buffer
->width0
- ib
.offset
) / ib
.index_size
;
1971 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
1972 radeon_emit(cs
, va
);
1973 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
1975 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1976 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
1977 (struct r600_resource
*)ib
.buffer
,
1979 RADEON_PRIO_INDEX_BUFFER
));
1981 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
1982 radeon_emit(cs
, max_size
);
1984 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
1985 radeon_emit(cs
, info
->indirect_offset
);
1986 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
1990 if (unlikely(info
->count_from_stream_output
)) {
1991 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
1992 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1994 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1996 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
1997 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
1998 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
1999 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
2000 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
2001 radeon_emit(cs
, 0); /* unused */
2003 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2004 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2005 t
->buf_filled_size
, RADEON_USAGE_READ
,
2006 RADEON_PRIO_SO_FILLED_SIZE
));
2009 if (likely(!info
->indirect
)) {
2010 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
2011 radeon_emit(cs
, info
->count
);
2014 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
2015 radeon_emit(cs
, info
->indirect_offset
);
2017 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2018 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2021 /* SMX returns CONTEXT_DONE too early workaround */
2022 if (rctx
->b
.family
== CHIP_R600
||
2023 rctx
->b
.family
== CHIP_RV610
||
2024 rctx
->b
.family
== CHIP_RV630
||
2025 rctx
->b
.family
== CHIP_RV635
) {
2026 /* if we have gs shader or streamout
2027 we need to do a wait idle after every draw */
2028 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2029 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2033 /* ES ring rolling over at EOP - workaround */
2034 if (rctx
->b
.chip_class
== R600
) {
2035 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2036 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2039 if (rctx
->framebuffer
.do_update_surf_dirtiness
) {
2040 /* Set the depth buffer as dirty. */
2041 if (rctx
->framebuffer
.state
.zsbuf
) {
2042 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2043 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2045 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2047 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2048 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2050 if (rctx
->framebuffer
.compressed_cb_mask
) {
2051 struct pipe_surface
*surf
;
2052 struct r600_texture
*rtex
;
2053 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2056 unsigned i
= u_bit_scan(&mask
);
2057 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2058 rtex
= (struct r600_texture
*)surf
->texture
;
2060 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2064 rctx
->framebuffer
.do_update_surf_dirtiness
= false;
2067 pipe_resource_reference(&ib
.buffer
, NULL
);
2068 rctx
->b
.num_draw_calls
++;
2071 uint32_t r600_translate_stencil_op(int s_op
)
2074 case PIPE_STENCIL_OP_KEEP
:
2075 return V_028800_STENCIL_KEEP
;
2076 case PIPE_STENCIL_OP_ZERO
:
2077 return V_028800_STENCIL_ZERO
;
2078 case PIPE_STENCIL_OP_REPLACE
:
2079 return V_028800_STENCIL_REPLACE
;
2080 case PIPE_STENCIL_OP_INCR
:
2081 return V_028800_STENCIL_INCR
;
2082 case PIPE_STENCIL_OP_DECR
:
2083 return V_028800_STENCIL_DECR
;
2084 case PIPE_STENCIL_OP_INCR_WRAP
:
2085 return V_028800_STENCIL_INCR_WRAP
;
2086 case PIPE_STENCIL_OP_DECR_WRAP
:
2087 return V_028800_STENCIL_DECR_WRAP
;
2088 case PIPE_STENCIL_OP_INVERT
:
2089 return V_028800_STENCIL_INVERT
;
2091 R600_ERR("Unknown stencil op %d", s_op
);
2098 uint32_t r600_translate_fill(uint32_t func
)
2101 case PIPE_POLYGON_MODE_FILL
:
2103 case PIPE_POLYGON_MODE_LINE
:
2105 case PIPE_POLYGON_MODE_POINT
:
2113 unsigned r600_tex_wrap(unsigned wrap
)
2117 case PIPE_TEX_WRAP_REPEAT
:
2118 return V_03C000_SQ_TEX_WRAP
;
2119 case PIPE_TEX_WRAP_CLAMP
:
2120 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2121 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2122 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2123 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2124 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2125 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2126 return V_03C000_SQ_TEX_MIRROR
;
2127 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2128 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2129 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2130 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2131 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2132 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2136 unsigned r600_tex_mipfilter(unsigned filter
)
2139 case PIPE_TEX_MIPFILTER_NEAREST
:
2140 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2141 case PIPE_TEX_MIPFILTER_LINEAR
:
2142 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2144 case PIPE_TEX_MIPFILTER_NONE
:
2145 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2149 unsigned r600_tex_compare(unsigned compare
)
2153 case PIPE_FUNC_NEVER
:
2154 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2155 case PIPE_FUNC_LESS
:
2156 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2157 case PIPE_FUNC_EQUAL
:
2158 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2159 case PIPE_FUNC_LEQUAL
:
2160 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2161 case PIPE_FUNC_GREATER
:
2162 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2163 case PIPE_FUNC_NOTEQUAL
:
2164 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2165 case PIPE_FUNC_GEQUAL
:
2166 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2167 case PIPE_FUNC_ALWAYS
:
2168 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2172 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2174 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2175 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2177 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2178 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2181 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2183 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2184 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2186 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2187 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2188 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2189 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2190 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2193 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2196 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2197 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2202 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2203 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2204 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2205 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2208 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2209 const unsigned char *swizzle_view
,
2213 unsigned char swizzle
[4];
2214 unsigned result
= 0;
2215 const uint32_t tex_swizzle_shift
[4] = {
2218 const uint32_t vtx_swizzle_shift
[4] = {
2221 const uint32_t swizzle_bit
[4] = {
2224 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2227 swizzle_shift
= vtx_swizzle_shift
;
2230 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2232 memcpy(swizzle
, swizzle_format
, 4);
2236 for (i
= 0; i
< 4; i
++) {
2237 switch (swizzle
[i
]) {
2238 case PIPE_SWIZZLE_Y
:
2239 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2241 case PIPE_SWIZZLE_Z
:
2242 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2244 case PIPE_SWIZZLE_W
:
2245 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2247 case PIPE_SWIZZLE_0
:
2248 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2250 case PIPE_SWIZZLE_1
:
2251 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2253 default: /* PIPE_SWIZZLE_X */
2254 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2260 /* texture format translate */
2261 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2262 enum pipe_format format
,
2263 const unsigned char *swizzle_view
,
2264 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2265 bool do_endian_swap
)
2267 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2268 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2269 const struct util_format_description
*desc
;
2270 boolean uniform
= TRUE
;
2271 bool is_srgb_valid
= FALSE
;
2272 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2273 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2274 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2275 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2276 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2279 const uint32_t sign_bit
[4] = {
2280 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2281 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2282 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2283 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2286 /* Need to replace the specified texture formats in case of big-endian.
2287 * These formats are formats that have channels with number of bits
2288 * not divisible by 8.
2289 * Mesa conversion functions don't swap bits for those formats, and because
2290 * we transmit this over a serial bus to the GPU (PCIe), the
2291 * bit-endianess is important!!!
2292 * In case we have an "opposite" format, just use that for the swizzling
2293 * information. If we don't have such an "opposite" format, we need
2294 * to use a fixed swizzle info instead (see below)
2296 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2297 format
= PIPE_FORMAT_A4R4_UNORM
;
2299 desc
= util_format_description(format
);
2301 /* Depth and stencil swizzling is handled separately. */
2302 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2303 /* Need to check for specific texture formats that don't have
2304 * an "opposite" format we can use. For those formats, we directly
2305 * specify the swizzling, which is the LE swizzling as defined in
2308 if (do_endian_swap
) {
2309 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2310 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2311 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2312 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2313 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2314 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2316 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2318 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2322 /* Colorspace (return non-RGB formats directly). */
2323 switch (desc
->colorspace
) {
2324 /* Depth stencil formats */
2325 case UTIL_FORMAT_COLORSPACE_ZS
:
2327 /* Depth sampler formats. */
2328 case PIPE_FORMAT_Z16_UNORM
:
2329 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2332 case PIPE_FORMAT_Z24X8_UNORM
:
2333 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2334 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2337 case PIPE_FORMAT_X8Z24_UNORM
:
2338 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2339 if (rscreen
->b
.chip_class
< EVERGREEN
)
2341 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2344 case PIPE_FORMAT_Z32_FLOAT
:
2345 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2346 result
= FMT_32_FLOAT
;
2348 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2349 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2350 result
= FMT_X24_8_32_FLOAT
;
2352 /* Stencil sampler formats. */
2353 case PIPE_FORMAT_S8_UINT
:
2354 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2355 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2358 case PIPE_FORMAT_X24S8_UINT
:
2359 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2360 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2363 case PIPE_FORMAT_S8X24_UINT
:
2364 if (rscreen
->b
.chip_class
< EVERGREEN
)
2366 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2367 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2370 case PIPE_FORMAT_X32_S8X24_UINT
:
2371 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2372 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2373 result
= FMT_X24_8_32_FLOAT
;
2379 case UTIL_FORMAT_COLORSPACE_YUV
:
2380 yuv_format
|= (1 << 30);
2382 case PIPE_FORMAT_UYVY
:
2383 case PIPE_FORMAT_YUYV
:
2387 goto out_unknown
; /* XXX */
2389 case UTIL_FORMAT_COLORSPACE_SRGB
:
2390 word4
|= S_038010_FORCE_DEGAMMA(1);
2397 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2399 case PIPE_FORMAT_RGTC1_SNORM
:
2400 case PIPE_FORMAT_LATC1_SNORM
:
2401 word4
|= sign_bit
[0];
2402 case PIPE_FORMAT_RGTC1_UNORM
:
2403 case PIPE_FORMAT_LATC1_UNORM
:
2406 case PIPE_FORMAT_RGTC2_SNORM
:
2407 case PIPE_FORMAT_LATC2_SNORM
:
2408 word4
|= sign_bit
[0] | sign_bit
[1];
2409 case PIPE_FORMAT_RGTC2_UNORM
:
2410 case PIPE_FORMAT_LATC2_UNORM
:
2418 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2419 if (!util_format_s3tc_enabled
) {
2424 case PIPE_FORMAT_DXT1_RGB
:
2425 case PIPE_FORMAT_DXT1_RGBA
:
2426 case PIPE_FORMAT_DXT1_SRGB
:
2427 case PIPE_FORMAT_DXT1_SRGBA
:
2429 is_srgb_valid
= TRUE
;
2431 case PIPE_FORMAT_DXT3_RGBA
:
2432 case PIPE_FORMAT_DXT3_SRGBA
:
2434 is_srgb_valid
= TRUE
;
2436 case PIPE_FORMAT_DXT5_RGBA
:
2437 case PIPE_FORMAT_DXT5_SRGBA
:
2439 is_srgb_valid
= TRUE
;
2446 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2447 if (rscreen
->b
.chip_class
< EVERGREEN
)
2451 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2452 case PIPE_FORMAT_BPTC_SRGBA
:
2454 is_srgb_valid
= TRUE
;
2456 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2457 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2459 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2467 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2469 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2470 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2473 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2474 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2482 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2483 result
= FMT_5_9_9_9_SHAREDEXP
;
2485 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2486 result
= FMT_10_11_11_FLOAT
;
2491 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2492 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2493 word4
|= sign_bit
[i
];
2497 /* R8G8Bx_SNORM - XXX CxV8U8 */
2499 /* See whether the components are of the same size. */
2500 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2501 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2504 /* Non-uniform formats. */
2506 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2507 desc
->channel
[0].pure_integer
)
2508 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2509 switch(desc
->nr_channels
) {
2511 if (desc
->channel
[0].size
== 5 &&
2512 desc
->channel
[1].size
== 6 &&
2513 desc
->channel
[2].size
== 5) {
2519 if (desc
->channel
[0].size
== 5 &&
2520 desc
->channel
[1].size
== 5 &&
2521 desc
->channel
[2].size
== 5 &&
2522 desc
->channel
[3].size
== 1) {
2523 result
= FMT_1_5_5_5
;
2526 if (desc
->channel
[0].size
== 10 &&
2527 desc
->channel
[1].size
== 10 &&
2528 desc
->channel
[2].size
== 10 &&
2529 desc
->channel
[3].size
== 2) {
2530 result
= FMT_2_10_10_10
;
2538 /* Find the first non-VOID channel. */
2539 for (i
= 0; i
< 4; i
++) {
2540 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2548 /* uniform formats */
2549 switch (desc
->channel
[i
].type
) {
2550 case UTIL_FORMAT_TYPE_UNSIGNED
:
2551 case UTIL_FORMAT_TYPE_SIGNED
:
2553 if (!desc
->channel
[i
].normalized
&&
2554 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2558 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2559 desc
->channel
[i
].pure_integer
)
2560 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2562 switch (desc
->channel
[i
].size
) {
2564 switch (desc
->nr_channels
) {
2569 result
= FMT_4_4_4_4
;
2574 switch (desc
->nr_channels
) {
2582 result
= FMT_8_8_8_8
;
2583 is_srgb_valid
= TRUE
;
2588 switch (desc
->nr_channels
) {
2596 result
= FMT_16_16_16_16
;
2601 switch (desc
->nr_channels
) {
2609 result
= FMT_32_32_32_32
;
2615 case UTIL_FORMAT_TYPE_FLOAT
:
2616 switch (desc
->channel
[i
].size
) {
2618 switch (desc
->nr_channels
) {
2620 result
= FMT_16_FLOAT
;
2623 result
= FMT_16_16_FLOAT
;
2626 result
= FMT_16_16_16_16_FLOAT
;
2631 switch (desc
->nr_channels
) {
2633 result
= FMT_32_FLOAT
;
2636 result
= FMT_32_32_FLOAT
;
2639 result
= FMT_32_32_32_32_FLOAT
;
2648 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2653 *yuv_format_p
= yuv_format
;
2656 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2660 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
2661 bool do_endian_swap
)
2663 const struct util_format_description
*desc
= util_format_description(format
);
2664 int channel
= util_format_get_first_non_void_channel(format
);
2667 #define HAS_SIZE(x,y,z,w) \
2668 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2669 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2671 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2672 return V_0280A0_COLOR_10_11_11_FLOAT
;
2674 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2678 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2680 switch (desc
->nr_channels
) {
2682 switch (desc
->channel
[0].size
) {
2684 return V_0280A0_COLOR_8
;
2687 return V_0280A0_COLOR_16_FLOAT
;
2689 return V_0280A0_COLOR_16
;
2692 return V_0280A0_COLOR_32_FLOAT
;
2694 return V_0280A0_COLOR_32
;
2698 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2699 switch (desc
->channel
[0].size
) {
2702 return V_0280A0_COLOR_4_4
;
2704 return ~0U; /* removed on Evergreen */
2706 return V_0280A0_COLOR_8_8
;
2709 return V_0280A0_COLOR_16_16_FLOAT
;
2711 return V_0280A0_COLOR_16_16
;
2714 return V_0280A0_COLOR_32_32_FLOAT
;
2716 return V_0280A0_COLOR_32_32
;
2718 } else if (HAS_SIZE(8,24,0,0)) {
2719 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
2720 } else if (HAS_SIZE(24,8,0,0)) {
2721 return V_0280A0_COLOR_8_24
;
2725 if (HAS_SIZE(5,6,5,0)) {
2726 return V_0280A0_COLOR_5_6_5
;
2727 } else if (HAS_SIZE(32,8,24,0)) {
2728 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2732 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2733 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2734 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2735 switch (desc
->channel
[0].size
) {
2737 return V_0280A0_COLOR_4_4_4_4
;
2739 return V_0280A0_COLOR_8_8_8_8
;
2742 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2744 return V_0280A0_COLOR_16_16_16_16
;
2747 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2749 return V_0280A0_COLOR_32_32_32_32
;
2751 } else if (HAS_SIZE(5,5,5,1)) {
2752 return V_0280A0_COLOR_1_5_5_5
;
2753 } else if (HAS_SIZE(10,10,10,2)) {
2754 return V_0280A0_COLOR_2_10_10_10
;
2761 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
2763 if (R600_BIG_ENDIAN
) {
2764 switch(colorformat
) {
2765 /* 8-bit buffers. */
2766 case V_0280A0_COLOR_4_4
:
2767 case V_0280A0_COLOR_8
:
2770 /* 16-bit buffers. */
2771 case V_0280A0_COLOR_8_8
:
2773 * No need to do endian swaps on array formats,
2774 * as mesa<-->pipe formats conversion take into account
2779 case V_0280A0_COLOR_5_6_5
:
2780 case V_0280A0_COLOR_1_5_5_5
:
2781 case V_0280A0_COLOR_4_4_4_4
:
2782 case V_0280A0_COLOR_16
:
2783 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
2785 /* 32-bit buffers. */
2786 case V_0280A0_COLOR_8_8_8_8
:
2788 * No need to do endian swaps on array formats,
2789 * as mesa<-->pipe formats conversion take into account
2794 case V_0280A0_COLOR_2_10_10_10
:
2795 case V_0280A0_COLOR_8_24
:
2796 case V_0280A0_COLOR_24_8
:
2797 case V_0280A0_COLOR_32_FLOAT
:
2798 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
2800 case V_0280A0_COLOR_16_16_FLOAT
:
2801 case V_0280A0_COLOR_16_16
:
2802 return ENDIAN_8IN16
;
2804 /* 64-bit buffers. */
2805 case V_0280A0_COLOR_16_16_16_16
:
2806 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2807 return ENDIAN_8IN16
;
2809 case V_0280A0_COLOR_32_32_FLOAT
:
2810 case V_0280A0_COLOR_32_32
:
2811 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2812 return ENDIAN_8IN32
;
2814 /* 128-bit buffers. */
2815 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2816 case V_0280A0_COLOR_32_32_32_32
:
2817 return ENDIAN_8IN32
;
2819 return ENDIAN_NONE
; /* Unsupported. */
2826 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2828 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2829 struct r600_resource
*rbuffer
= r600_resource(buf
);
2830 unsigned i
, shader
, mask
;
2831 struct r600_pipe_sampler_view
*view
;
2833 /* Reallocate the buffer in the same pipe_resource. */
2834 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
2836 /* We changed the buffer, now we need to bind it where the old one was bound. */
2837 /* Vertex buffers. */
2838 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2840 i
= u_bit_scan(&mask
);
2841 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2842 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2843 r600_vertex_buffers_dirty(rctx
);
2846 /* Streamout buffers. */
2847 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2848 if (rctx
->b
.streamout
.targets
[i
] &&
2849 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2850 if (rctx
->b
.streamout
.begin_emitted
) {
2851 r600_emit_streamout_end(&rctx
->b
);
2853 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2854 r600_streamout_buffers_dirty(&rctx
->b
);
2858 /* Constant buffers. */
2859 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2860 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2862 uint32_t mask
= state
->enabled_mask
;
2865 unsigned i
= u_bit_scan(&mask
);
2866 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2868 state
->dirty_mask
|= 1 << i
;
2872 r600_constant_buffers_dirty(rctx
, state
);
2876 /* Texture buffer objects - update the virtual addresses in descriptors. */
2877 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
2878 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2879 uint64_t offset
= view
->base
.u
.buf
.offset
;
2880 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2882 view
->tex_resource_words
[0] = va
;
2883 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2884 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2887 /* Texture buffer objects - make bindings dirty if needed. */
2888 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2889 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2891 uint32_t mask
= state
->enabled_mask
;
2894 unsigned i
= u_bit_scan(&mask
);
2895 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2897 state
->dirty_mask
|= 1 << i
;
2901 r600_sampler_views_dirty(rctx
, state
);
2906 static void r600_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
2908 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2910 /* Pipeline stat & streamout queries. */
2912 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
2913 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
2915 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
2916 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
2919 /* Occlusion queries. */
2920 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
2921 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
2922 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2926 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2928 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2930 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2933 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2934 bool include_draw_vbo
)
2936 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2939 /* keep this at the end of this file, please */
2940 void r600_init_common_state_functions(struct r600_context
*rctx
)
2942 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2943 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2944 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2945 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
2946 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
2947 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2948 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2949 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2950 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2951 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2952 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2953 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2954 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2955 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2956 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
2957 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
2958 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2959 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2960 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2961 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2962 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2963 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2964 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2965 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2966 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
2967 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
2968 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2969 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2970 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2971 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2972 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2973 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2974 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2975 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2976 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2977 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2978 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2979 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
2980 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2981 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2982 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2983 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;