src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "r600_formats.h"
  28 #include "r600d.h"
  29
  30 #include "util/u_blitter.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include <byteswap.h>
  34
  35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
  36 {
  37         struct radeon_winsys_cs *cs = rctx->cs;
  38         struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
  39
  40         assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
  41         memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
  42         cs->cdw += cb->atom.num_dw;
  43 }
  44
  45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
  46 {
  47         cb->atom.emit = r600_emit_command_buffer;
  48         cb->atom.num_dw = 0;
  49         cb->atom.flags = flags;
  50         cb->buf = CALLOC(1, 4 * num_dw);
  51         cb->max_num_dw = num_dw;
  52 }
  53
  54 void r600_release_command_buffer(struct r600_command_buffer *cb)
  55 {
  56         FREE(cb->buf);
  57 }
  58
  59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  60 {
  61         struct radeon_winsys_cs *cs = rctx->cs;
  62         struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
  63
  64         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  65         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  66         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  67         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  68         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  69
  70         a->flush_flags = 0;
  71 }
  72
  73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  74 {
  75         struct radeon_winsys_cs *cs = rctx->cs;
  76         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  77         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  78 }
  79
  80 void r600_init_atom(struct r600_atom *atom,
  81                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  82                     unsigned num_dw, enum r600_atom_flags flags)
  83 {
  84         atom->emit = emit;
  85         atom->num_dw = num_dw;
  86         atom->flags = flags;
  87 }
  88
  89 void r600_init_common_atoms(struct r600_context *rctx)
  90 {
  91         r600_init_atom(&rctx->surface_sync_cmd.atom,    r600_emit_surface_sync,         5, EMIT_EARLY);
  92         r600_init_atom(&rctx->r6xx_flush_and_inv_cmd,   r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  93 }
  94
  95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  96 {
  97         unsigned flags = 0;
  98
  99         if (rctx->framebuffer.nr_cbufs) {
 100                 flags |= S_0085F0_CB_ACTION_ENA(1) |
 101                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
 102         }
 103
 104         /* Workaround for broken flushing on some R6xx chipsets. */
 105         if (rctx->family == CHIP_RV670 ||
 106             rctx->family == CHIP_RS780 ||
 107             rctx->family == CHIP_RS880) {
 108                 flags |=  S_0085F0_CB1_DEST_BASE_ENA(1) |
 109                           S_0085F0_DEST_BASE_0_ENA(1);
 110         }
 111         return flags;
 112 }
 113
 114 void r600_texture_barrier(struct pipe_context *ctx)
 115 {
 116         struct r600_context *rctx = (struct r600_context *)ctx;
 117
 118         rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
 119         r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
 120 }
 121
 122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 123 {
 124         static const int prim_conv[] = {
 125                 V_008958_DI_PT_POINTLIST,
 126                 V_008958_DI_PT_LINELIST,
 127                 V_008958_DI_PT_LINELOOP,
 128                 V_008958_DI_PT_LINESTRIP,
 129                 V_008958_DI_PT_TRILIST,
 130                 V_008958_DI_PT_TRISTRIP,
 131                 V_008958_DI_PT_TRIFAN,
 132                 V_008958_DI_PT_QUADLIST,
 133                 V_008958_DI_PT_QUADSTRIP,
 134                 V_008958_DI_PT_POLYGON,
 135                 -1,
 136                 -1,
 137                 -1,
 138                 -1
 139         };
 140
 141         *prim = prim_conv[pprim];
 142         if (*prim == -1) {
 143                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 144                 return false;
 145         }
 146         return true;
 147 }
 148
 149 /* common state between evergreen and r600 */
 150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 151 {
 152         struct r600_context *rctx = (struct r600_context *)ctx;
 153         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 154         struct r600_pipe_state *rstate;
 155
 156         if (state == NULL)
 157                 return;
 158         rstate = &blend->rstate;
 159         rctx->states[rstate->id] = rstate;
 160         rctx->cb_target_mask = blend->cb_target_mask;
 161         /* Replace every bit except MULTIWRITE_ENABLE. */
 162         rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
 163         rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
 164         rctx->dual_src_blend = blend->dual_src_blend;
 165         r600_context_pipe_state_set(rctx, rstate);
 166 }
 167
 168 void r600_set_blend_color(struct pipe_context *ctx,
 169                           const struct pipe_blend_color *state)
 170 {
 171         struct r600_context *rctx = (struct r600_context *)ctx;
 172         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 173
 174         if (rstate == NULL)
 175                 return;
 176
 177         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 178         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
 179         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
 180         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
 181         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
 182
 183         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 184         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 185         r600_context_pipe_state_set(rctx, rstate);
 186 }
 187
 188 static void r600_set_stencil_ref(struct pipe_context *ctx,
 189                                  const struct r600_stencil_ref *state)
 190 {
 191         struct r600_context *rctx = (struct r600_context *)ctx;
 192         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 193
 194         if (rstate == NULL)
 195                 return;
 196
 197         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 198         r600_pipe_state_add_reg(rstate,
 199                                 R_028430_DB_STENCILREFMASK,
 200                                 S_028430_STENCILREF(state->ref_value[0]) |
 201                                 S_028430_STENCILMASK(state->valuemask[0]) |
 202                                 S_028430_STENCILWRITEMASK(state->writemask[0]));
 203         r600_pipe_state_add_reg(rstate,
 204                                 R_028434_DB_STENCILREFMASK_BF,
 205                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 206                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 207                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
 208
 209         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 210         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 211         r600_context_pipe_state_set(rctx, rstate);
 212 }
 213
 214 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 215                                const struct pipe_stencil_ref *state)
 216 {
 217         struct r600_context *rctx = (struct r600_context *)ctx;
 218         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 219         struct r600_stencil_ref ref;
 220
 221         rctx->stencil_ref = *state;
 222
 223         if (!dsa)
 224                 return;
 225
 226         ref.ref_value[0] = state->ref_value[0];
 227         ref.ref_value[1] = state->ref_value[1];
 228         ref.valuemask[0] = dsa->valuemask[0];
 229         ref.valuemask[1] = dsa->valuemask[1];
 230         ref.writemask[0] = dsa->writemask[0];
 231         ref.writemask[1] = dsa->writemask[1];
 232
 233         r600_set_stencil_ref(ctx, &ref);
 234 }
 235
 236 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 237 {
 238         struct r600_context *rctx = (struct r600_context *)ctx;
 239         struct r600_pipe_dsa *dsa = state;
 240         struct r600_pipe_state *rstate;
 241         struct r600_stencil_ref ref;
 242
 243         if (state == NULL)
 244                 return;
 245         rstate = &dsa->rstate;
 246         rctx->states[rstate->id] = rstate;
 247         rctx->sx_alpha_test_control &= ~0xff;
 248         rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
 249         rctx->alpha_ref = dsa->alpha_ref;
 250         rctx->alpha_ref_dirty = true;
 251         r600_context_pipe_state_set(rctx, rstate);
 252
 253         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 254         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 255         ref.valuemask[0] = dsa->valuemask[0];
 256         ref.valuemask[1] = dsa->valuemask[1];
 257         ref.writemask[0] = dsa->writemask[0];
 258         ref.writemask[1] = dsa->writemask[1];
 259
 260         r600_set_stencil_ref(ctx, &ref);
 261
 262         if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
 263                 rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
 264                 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
 265         }
 266 }
 267
 268 void r600_set_max_scissor(struct r600_context *rctx)
 269 {
 270         /* Set a scissor state such that it doesn't do anything. */
 271         struct pipe_scissor_state scissor;
 272         scissor.minx = 0;
 273         scissor.miny = 0;
 274         scissor.maxx = 8192;
 275         scissor.maxy = 8192;
 276
 277         r600_set_scissor_state(rctx, &scissor);
 278 }
 279
 280 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 281 {
 282         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 283         struct r600_context *rctx = (struct r600_context *)ctx;
 284
 285         if (state == NULL)
 286                 return;
 287
 288         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 289         rctx->two_side = rs->two_side;
 290         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 291         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 292
 293         rctx->rasterizer = rs;
 294
 295         rctx->states[rs->rstate.id] = &rs->rstate;
 296         r600_context_pipe_state_set(rctx, &rs->rstate);
 297
 298         if (rctx->chip_class >= EVERGREEN) {
 299                 evergreen_polygon_offset_update(rctx);
 300         } else {
 301                 r600_polygon_offset_update(rctx);
 302         }
 303
 304         /* Workaround for a missing scissor enable on r600. */
 305         if (rctx->chip_class == R600) {
 306                 if (rs->scissor_enable != rctx->scissor_enable) {
 307                         rctx->scissor_enable = rs->scissor_enable;
 308
 309                         if (rs->scissor_enable) {
 310                                 r600_set_scissor_state(rctx, &rctx->scissor_state);
 311                         } else {
 312                                 r600_set_max_scissor(rctx);
 313                         }
 314                 }
 315         }
 316 }
 317
 318 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 319 {
 320         struct r600_context *rctx = (struct r600_context *)ctx;
 321         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 322
 323         if (rctx->rasterizer == rs) {
 324                 rctx->rasterizer = NULL;
 325         }
 326         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 327                 rctx->states[rs->rstate.id] = NULL;
 328         }
 329         free(rs);
 330 }
 331
 332 void r600_sampler_view_destroy(struct pipe_context *ctx,
 333                                struct pipe_sampler_view *state)
 334 {
 335         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 336
 337         pipe_resource_reference(&state->texture, NULL);
 338         FREE(resource);
 339 }
 340
 341 void r600_delete_state(struct pipe_context *ctx, void *state)
 342 {
 343         struct r600_context *rctx = (struct r600_context *)ctx;
 344         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 345
 346         if (rctx->states[rstate->id] == rstate) {
 347                 rctx->states[rstate->id] = NULL;
 348         }
 349         for (int i = 0; i < rstate->nregs; i++) {
 350                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 351         }
 352         free(rstate);
 353 }
 354
 355 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 356 {
 357         struct r600_context *rctx = (struct r600_context *)ctx;
 358         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 359
 360         rctx->vertex_elements = v;
 361         if (v) {
 362                 r600_inval_shader_cache(rctx);
 363
 364                 rctx->states[v->rstate.id] = &v->rstate;
 365                 r600_context_pipe_state_set(rctx, &v->rstate);
 366         }
 367 }
 368
 369 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 370 {
 371         struct r600_context *rctx = (struct r600_context *)ctx;
 372         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 373
 374         if (rctx->states[v->rstate.id] == &v->rstate) {
 375                 rctx->states[v->rstate.id] = NULL;
 376         }
 377         if (rctx->vertex_elements == state)
 378                 rctx->vertex_elements = NULL;
 379
 380         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 381         FREE(state);
 382 }
 383
 384 void r600_set_index_buffer(struct pipe_context *ctx,
 385                            const struct pipe_index_buffer *ib)
 386 {
 387         struct r600_context *rctx = (struct r600_context *)ctx;
 388
 389         if (ib) {
 390                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 391                 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
 392         } else {
 393                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 394         }
 395 }
 396
 397 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 398                              const struct pipe_vertex_buffer *buffers)
 399 {
 400         struct r600_context *rctx = (struct r600_context *)ctx;
 401
 402         util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
 403
 404         r600_inval_vertex_cache(rctx);
 405         rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
 406                                            rctx->nr_vertex_buffers;
 407         r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
 408 }
 409
 410 void *r600_create_vertex_elements(struct pipe_context *ctx,
 411                                   unsigned count,
 412                                   const struct pipe_vertex_element *elements)
 413 {
 414         struct r600_context *rctx = (struct r600_context *)ctx;
 415         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 416
 417         assert(count < 32);
 418         if (!v)
 419                 return NULL;
 420
 421         v->count = count;
 422         memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
 423
 424         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 425                 FREE(v);
 426                 return NULL;
 427         }
 428
 429         return v;
 430 }
 431
 432 /* Compute the key for the hw shader variant */
 433 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
 434                 struct r600_pipe_shader_selector * sel)
 435 {
 436         struct r600_context *rctx = (struct r600_context *)ctx;
 437         unsigned key;
 438
 439         if (sel->type == PIPE_SHADER_FRAGMENT) {
 440                 key = rctx->two_side;
 441                 if (sel->eg_fs_write_all)
 442                         key |= rctx->nr_cbufs << 1;
 443         } else
 444                 key = 0;
 445
 446         return key;
 447 }
 448
 449 /* Select the hw shader variant depending on the current state.
 450  * (*dirty) is set to 1 if current variant was changed */
 451 static int r600_shader_select(struct pipe_context *ctx,
 452         struct r600_pipe_shader_selector* sel,
 453         unsigned *dirty)
 454 {
 455         unsigned key;
 456         struct r600_context *rctx = (struct r600_context *)ctx;
 457         struct r600_pipe_shader * shader = NULL;
 458         int r;
 459
 460         key = r600_shader_selector_key(ctx, sel);
 461
 462         /* Check if we don't need to change anything.
 463          * This path is also used for most shaders that don't need multiple
 464          * variants, it will cost just a computation of the key and this
 465          * test. */
 466         if (likely(sel->current && sel->current->key == key)) {
 467                 return 0;
 468         }
 469
 470         /* lookup if we have other variants in the list */
 471         if (sel->num_shaders > 1) {
 472                 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
 473
 474                 while (c && c->key != key) {
 475                         p = c;
 476                         c = c->next_variant;
 477                 }
 478
 479                 if (c) {
 480                         p->next_variant = c->next_variant;
 481                         shader = c;
 482                 }
 483         }
 484
 485         if (unlikely(!shader)) {
 486                 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
 487                 shader->selector = sel;
 488
 489                 r = r600_pipe_shader_create(ctx, shader);
 490                 if (unlikely(r)) {
 491                         R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
 492                                         sel->type, key, r);
 493                         sel->current = NULL;
 494                         return r;
 495                 }
 496
 497                 /* We don't know the value of eg_fs_write_all property until we built
 498                  * at least one variant, so we may need to recompute the key (include
 499                  * rctx->nr_cbufs) after building first variant. */
 500                 if (sel->type == PIPE_SHADER_FRAGMENT &&
 501                                 sel->num_shaders == 0 &&
 502                                 rctx->chip_class >= EVERGREEN &&
 503                                 shader->shader.fs_write_all) {
 504                         sel->eg_fs_write_all = 1;
 505                         key = r600_shader_selector_key(ctx, sel);
 506                 }
 507
 508                 shader->key = key;
 509                 sel->num_shaders++;
 510         }
 511
 512         if (dirty)
 513                 *dirty = 1;
 514
 515         shader->next_variant = sel->current;
 516         sel->current = shader;
 517
 518         /* Moved from r600_bind_ps_shader, different shader variants
 519          * may use different number of GPRs, so we need to update it. */
 520         /* FIXME: we never did it after rebuilding the shaders, is it required? */
 521         if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
 522                 r600_adjust_gprs(rctx);
 523         }
 524
 525         return 0;
 526 }
 527
 528 static void *r600_create_shader_state(struct pipe_context *ctx,
 529                                const struct pipe_shader_state *state,
 530                                unsigned pipe_shader_type)
 531 {
 532         struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
 533         int r;
 534
 535         sel->type = pipe_shader_type;
 536         sel->tokens = tgsi_dup_tokens(state->tokens);
 537         sel->so = state->stream_output;
 538
 539         r = r600_shader_select(ctx, sel, NULL);
 540         if (r)
 541             return NULL;
 542
 543         return sel;
 544 }
 545
 546 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 547                 const struct pipe_shader_state *state)
 548 {
 549         return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
 550 }
 551
 552 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 553                 const struct pipe_shader_state *state)
 554 {
 555         return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
 556 }
 557
 558 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 559 {
 560         struct r600_context *rctx = (struct r600_context *)ctx;
 561
 562         if (!state)
 563                 state = rctx->dummy_pixel_shader;
 564
 565         rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
 566         r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
 567
 568         rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
 569         rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->current->shader.fs_write_all);
 570
 571         if (rctx->chip_class < EVERGREEN && rctx->vs_shader) {
 572                 r600_adjust_gprs(rctx);
 573         }
 574 }
 575
 576 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 577 {
 578         struct r600_context *rctx = (struct r600_context *)ctx;
 579
 580         rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
 581         if (state) {
 582                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
 583
 584                 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
 585                         r600_adjust_gprs(rctx);
 586         }
 587 }
 588
 589 static void r600_delete_shader_selector(struct pipe_context *ctx,
 590                 struct r600_pipe_shader_selector *sel)
 591 {
 592         struct r600_pipe_shader *p = sel->current, *c;
 593         while (p) {
 594                 c = p->next_variant;
 595                 r600_pipe_shader_destroy(ctx, p);
 596                 free(p);
 597                 p = c;
 598         }
 599
 600         free(sel->tokens);
 601         free(sel);
 602 }
 603
 604
 605 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 606 {
 607         struct r600_context *rctx = (struct r600_context *)ctx;
 608         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 609
 610         if (rctx->ps_shader == sel) {
 611                 rctx->ps_shader = NULL;
 612         }
 613
 614         r600_delete_shader_selector(ctx, sel);
 615 }
 616
 617 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 618 {
 619         struct r600_context *rctx = (struct r600_context *)ctx;
 620         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 621
 622         if (rctx->vs_shader == sel) {
 623                 rctx->vs_shader = NULL;
 624         }
 625
 626         r600_delete_shader_selector(ctx, sel);
 627 }
 628
 629 static void r600_update_alpha_ref(struct r600_context *rctx)
 630 {
 631         unsigned alpha_ref;
 632         struct r600_pipe_state rstate;
 633
 634         alpha_ref = rctx->alpha_ref;
 635         rstate.nregs = 0;
 636         if (rctx->export_16bpc)
 637                 alpha_ref &= ~0x1FFF;
 638         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
 639
 640         r600_context_pipe_state_set(rctx, &rstate);
 641         rctx->alpha_ref_dirty = false;
 642 }
 643
 644 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 645 {
 646         r600_inval_shader_cache(rctx);
 647         state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 648                                                            : util_bitcount(state->dirty_mask)*19;
 649         r600_atom_dirty(rctx, &state->atom);
 650 }
 651
 652 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 653                               struct pipe_constant_buffer *input)
 654 {
 655         struct r600_context *rctx = (struct r600_context *)ctx;
 656         struct r600_constbuf_state *state;
 657         struct pipe_constant_buffer *cb;
 658         const uint8_t *ptr;
 659
 660         switch (shader) {
 661         case PIPE_SHADER_VERTEX:
 662                 state = &rctx->vs_constbuf_state;
 663                 break;
 664         case PIPE_SHADER_FRAGMENT:
 665                 state = &rctx->ps_constbuf_state;
 666                 break;
 667         default:
 668                 return;
 669         }
 670
 671         /* Note that the state tracker can unbind constant buffers by
 672          * passing NULL here.
 673          */
 674         if (unlikely(!input)) {
 675                 state->enabled_mask &= ~(1 << index);
 676                 state->dirty_mask &= ~(1 << index);
 677                 pipe_resource_reference(&state->cb[index].buffer, NULL);
 678                 return;
 679         }
 680
 681         cb = &state->cb[index];
 682         cb->buffer_size = input->buffer_size;
 683
 684         ptr = input->user_buffer;
 685
 686         if (ptr) {
 687                 /* Upload the user buffer. */
 688                 if (R600_BIG_ENDIAN) {
 689                         uint32_t *tmpPtr;
 690                         unsigned i, size = input->buffer_size;
 691
 692                         if (!(tmpPtr = malloc(size))) {
 693                                 R600_ERR("Failed to allocate BE swap buffer.\n");
 694                                 return;
 695                         }
 696
 697                         for (i = 0; i < size / 4; ++i) {
 698                                 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
 699                         }
 700
 701                         u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
 702                         free(tmpPtr);
 703                 } else {
 704                         u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 705                 }
 706         } else {
 707                 /* Setup the hw buffer. */
 708                 cb->buffer_offset = input->buffer_offset;
 709                 pipe_resource_reference(&cb->buffer, input->buffer);
 710         }
 711
 712         state->enabled_mask |= 1 << index;
 713         state->dirty_mask |= 1 << index;
 714         r600_constant_buffers_dirty(rctx, state);
 715 }
 716
 717 struct pipe_stream_output_target *
 718 r600_create_so_target(struct pipe_context *ctx,
 719                       struct pipe_resource *buffer,
 720                       unsigned buffer_offset,
 721                       unsigned buffer_size)
 722 {
 723         struct r600_context *rctx = (struct r600_context *)ctx;
 724         struct r600_so_target *t;
 725         void *ptr;
 726
 727         t = CALLOC_STRUCT(r600_so_target);
 728         if (!t) {
 729                 return NULL;
 730         }
 731
 732         t->b.reference.count = 1;
 733         t->b.context = ctx;
 734         pipe_resource_reference(&t->b.buffer, buffer);
 735         t->b.buffer_offset = buffer_offset;
 736         t->b.buffer_size = buffer_size;
 737
 738         t->filled_size = (struct r600_resource*)
 739                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 740         ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
 741         memset(ptr, 0, t->filled_size->buf->size);
 742         rctx->ws->buffer_unmap(t->filled_size->cs_buf);
 743
 744         return &t->b;
 745 }
 746
 747 void r600_so_target_destroy(struct pipe_context *ctx,
 748                             struct pipe_stream_output_target *target)
 749 {
 750         struct r600_so_target *t = (struct r600_so_target*)target;
 751         pipe_resource_reference(&t->b.buffer, NULL);
 752         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 753         FREE(t);
 754 }
 755
 756 void r600_set_so_targets(struct pipe_context *ctx,
 757                          unsigned num_targets,
 758                          struct pipe_stream_output_target **targets,
 759                          unsigned append_bitmask)
 760 {
 761         struct r600_context *rctx = (struct r600_context *)ctx;
 762         unsigned i;
 763
 764         /* Stop streamout. */
 765         if (rctx->num_so_targets && !rctx->streamout_start) {
 766                 r600_context_streamout_end(rctx);
 767         }
 768
 769         /* Set the new targets. */
 770         for (i = 0; i < num_targets; i++) {
 771                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 772         }
 773         for (; i < rctx->num_so_targets; i++) {
 774                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 775         }
 776
 777         rctx->num_so_targets = num_targets;
 778         rctx->streamout_start = num_targets != 0;
 779         rctx->streamout_append_bitmask = append_bitmask;
 780 }
 781
 782 static void r600_update_derived_state(struct r600_context *rctx)
 783 {
 784         struct pipe_context * ctx = (struct pipe_context*)rctx;
 785         unsigned ps_dirty = 0;
 786
 787         if (!rctx->blitter->running) {
 788                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 789                         r600_flush_depth_textures(rctx);
 790         }
 791
 792         if (rctx->chip_class < EVERGREEN) {
 793                 r600_update_sampler_states(rctx);
 794         }
 795
 796         r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
 797
 798         if (rctx->alpha_ref_dirty) {
 799                 r600_update_alpha_ref(rctx);
 800         }
 801
 802         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 803                 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 804                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
 805
 806                 if (rctx->chip_class >= EVERGREEN)
 807                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
 808                 else
 809                         r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
 810
 811                 ps_dirty = 1;
 812         }
 813
 814         if (ps_dirty)
 815                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
 816
 817         if (rctx->dual_src_blend)
 818                 rctx->cb_shader_mask = rctx->ps_shader->current->ps_cb_shader_mask | rctx->fb_cb_shader_mask;
 819         else
 820                 rctx->cb_shader_mask = rctx->fb_cb_shader_mask;
 821 }
 822
 823 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
 824 {
 825         static const int prim_conv[] = {
 826                 V_028A6C_OUTPRIM_TYPE_POINTLIST,
 827                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 828                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 829                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 830                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 831                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 832                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 833                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 834                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 835                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 836                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 837                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 838                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 839                 V_028A6C_OUTPRIM_TYPE_TRISTRIP
 840         };
 841         assert(mode < Elements(prim_conv));
 842
 843         return prim_conv[mode];
 844 }
 845
 846 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 847 {
 848         struct r600_context *rctx = (struct r600_context *)ctx;
 849         struct pipe_draw_info info = *dinfo;
 850         struct pipe_index_buffer ib = {};
 851         unsigned prim, mask, ls_mask = 0;
 852         struct r600_block *dirty_block = NULL, *next_block = NULL;
 853         struct r600_atom *state = NULL, *next_state = NULL;
 854         struct radeon_winsys_cs *cs = rctx->cs;
 855         uint64_t va;
 856         uint8_t *ptr;
 857
 858         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 859             !r600_conv_pipe_prim(info.mode, &prim)) {
 860                 assert(0);
 861                 return;
 862         }
 863
 864         if (!rctx->vs_shader) {
 865                 assert(0);
 866                 return;
 867         }
 868
 869         r600_update_derived_state(rctx);
 870
 871         if (info.indexed) {
 872                 /* Initialize the index buffer struct. */
 873                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
 874                 ib.user_buffer = rctx->index_buffer.user_buffer;
 875                 ib.index_size = rctx->index_buffer.index_size;
 876                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
 877
 878                 /* Translate or upload, if needed. */
 879                 r600_translate_index_buffer(rctx, &ib, info.count);
 880
 881                 ptr = (uint8_t*)ib.user_buffer;
 882                 if (!ib.buffer && ptr) {
 883                         u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
 884                                       ptr, &ib.offset, &ib.buffer);
 885                 }
 886         } else {
 887                 info.index_bias = info.start;
 888                 if (info.count_from_stream_output) {
 889                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 890                 }
 891         }
 892
 893         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 894
 895         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 896                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 897                 rctx->vgt.nregs = 0;
 898                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
 899                 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
 900                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask);
 901                 r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0);
 902                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
 903                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
 904                 r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
 905                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
 906                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
 907                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
 908                 if (rctx->chip_class <= R700)
 909                         r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
 910                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
 911                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
 912         }
 913
 914         rctx->vgt.nregs = 0;
 915         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 916         r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
 917         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 918         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
 919         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 920         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 921         r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
 922         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 923         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 924
 925         if (prim == V_008958_DI_PT_LINELIST)
 926                 ls_mask = 1;
 927         else if (prim == V_008958_DI_PT_LINESTRIP)
 928                 ls_mask = 2;
 929         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 930         if (rctx->chip_class <= R700)
 931                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 932         r600_pipe_state_mod_reg(&rctx->vgt,
 933                                 rctx->vs_shader->current->pa_cl_vs_out_cntl |
 934                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
 935         r600_pipe_state_mod_reg(&rctx->vgt,
 936                                 rctx->pa_cl_clip_cntl |
 937                                 (rctx->vs_shader->current->shader.clip_dist_write ||
 938                                  rctx->vs_shader->current->shader.vs_prohibit_ucps ?
 939                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F));
 940
 941         r600_context_pipe_state_set(rctx, &rctx->vgt);
 942
 943         /* Emit states (the function expects that we emit at most 17 dwords here). */
 944         r600_need_cs_space(rctx, 0, TRUE);
 945
 946         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 947                 r600_emit_atom(rctx, state);
 948         }
 949         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 950                 r600_context_block_emit_dirty(rctx, dirty_block);
 951         }
 952         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
 953                 r600_context_block_resource_emit_dirty(rctx, dirty_block);
 954         }
 955         rctx->pm4_dirty_cdwords = 0;
 956
 957         /* Enable stream out if needed. */
 958         if (rctx->streamout_start) {
 959                 r600_context_streamout_begin(rctx);
 960                 rctx->streamout_start = FALSE;
 961         }
 962
 963         /* draw packet */
 964         cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
 965         cs->buf[cs->cdw++] = ib.index_size == 4 ?
 966                                 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
 967                                 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
 968         cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
 969         cs->buf[cs->cdw++] = info.instance_count;
 970         if (info.indexed) {
 971                 va = r600_resource_va(ctx->screen, ib.buffer);
 972                 va += ib.offset;
 973                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
 974                 cs->buf[cs->cdw++] = va;
 975                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
 976                 cs->buf[cs->cdw++] = info.count;
 977                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
 978                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
 979                 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
 980         } else {
 981                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
 982                 cs->buf[cs->cdw++] = info.count;
 983                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
 984                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
 985         }
 986
 987         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 988
 989         if (rctx->framebuffer.zsbuf)
 990         {
 991                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 992                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 993         }
 994
 995         pipe_resource_reference(&ib.buffer, NULL);
 996 }
 997
 998 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
 999                                  struct r600_pipe_state *state,
1000                                  uint32_t offset, uint32_t value,
1001                                  uint32_t range_id, uint32_t block_id,
1002                                  struct r600_resource *bo,
1003                                  enum radeon_bo_usage usage)
1004
1005 {
1006         struct r600_range *range;
1007         struct r600_block *block;
1008
1009         if (bo) assert(usage);
1010
1011         range = &ctx->range[range_id];
1012         block = range->blocks[block_id];
1013         state->regs[state->nregs].block = block;
1014         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1015
1016         state->regs[state->nregs].value = value;
1017         state->regs[state->nregs].bo = bo;
1018         state->regs[state->nregs].bo_usage = usage;
1019
1020         state->nregs++;
1021         assert(state->nregs < R600_BLOCK_MAX_REG);
1022 }
1023
1024 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1025                               struct r600_pipe_state *state,
1026                               uint32_t offset, uint32_t value,
1027                               uint32_t range_id, uint32_t block_id)
1028 {
1029         _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1030                                     range_id, block_id, NULL, 0);
1031 }
1032
1033 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
1034                                      uint32_t offset, uint32_t value,
1035                                      struct r600_resource *bo,
1036                                      enum radeon_bo_usage usage)
1037 {
1038         if (bo) assert(usage);
1039
1040         state->regs[state->nregs].id = offset;
1041         state->regs[state->nregs].block = NULL;
1042         state->regs[state->nregs].value = value;
1043         state->regs[state->nregs].bo = bo;
1044         state->regs[state->nregs].bo_usage = usage;
1045
1046         state->nregs++;
1047         assert(state->nregs < R600_BLOCK_MAX_REG);
1048 }
1049
1050 uint32_t r600_translate_stencil_op(int s_op)
1051 {
1052         switch (s_op) {
1053         case PIPE_STENCIL_OP_KEEP:
1054                 return V_028800_STENCIL_KEEP;
1055         case PIPE_STENCIL_OP_ZERO:
1056                 return V_028800_STENCIL_ZERO;
1057         case PIPE_STENCIL_OP_REPLACE:
1058                 return V_028800_STENCIL_REPLACE;
1059         case PIPE_STENCIL_OP_INCR:
1060                 return V_028800_STENCIL_INCR;
1061         case PIPE_STENCIL_OP_DECR:
1062                 return V_028800_STENCIL_DECR;
1063         case PIPE_STENCIL_OP_INCR_WRAP:
1064                 return V_028800_STENCIL_INCR_WRAP;
1065         case PIPE_STENCIL_OP_DECR_WRAP:
1066                 return V_028800_STENCIL_DECR_WRAP;
1067         case PIPE_STENCIL_OP_INVERT:
1068                 return V_028800_STENCIL_INVERT;
1069         default:
1070                 R600_ERR("Unknown stencil op %d", s_op);
1071                 assert(0);
1072                 break;
1073         }
1074         return 0;
1075 }
1076
1077 uint32_t r600_translate_fill(uint32_t func)
1078 {
1079         switch(func) {
1080         case PIPE_POLYGON_MODE_FILL:
1081                 return 2;
1082         case PIPE_POLYGON_MODE_LINE:
1083                 return 1;
1084         case PIPE_POLYGON_MODE_POINT:
1085                 return 0;
1086         default:
1087                 assert(0);
1088                 return 0;
1089         }
1090 }
1091
1092 unsigned r600_tex_wrap(unsigned wrap)
1093 {
1094         switch (wrap) {
1095         default:
1096         case PIPE_TEX_WRAP_REPEAT:
1097                 return V_03C000_SQ_TEX_WRAP;
1098         case PIPE_TEX_WRAP_CLAMP:
1099                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1100         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1101                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1102         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1103                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1104         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1105                 return V_03C000_SQ_TEX_MIRROR;
1106         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1107                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1108         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1109                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1110         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1111                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1112         }
1113 }
1114
1115 unsigned r600_tex_filter(unsigned filter)
1116 {
1117         switch (filter) {
1118         default:
1119         case PIPE_TEX_FILTER_NEAREST:
1120                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1121         case PIPE_TEX_FILTER_LINEAR:
1122                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1123         }
1124 }
1125
1126 unsigned r600_tex_mipfilter(unsigned filter)
1127 {
1128         switch (filter) {
1129         case PIPE_TEX_MIPFILTER_NEAREST:
1130                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1131         case PIPE_TEX_MIPFILTER_LINEAR:
1132                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1133         default:
1134         case PIPE_TEX_MIPFILTER_NONE:
1135                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1136         }
1137 }
1138
1139 unsigned r600_tex_compare(unsigned compare)
1140 {
1141         switch (compare) {
1142         default:
1143         case PIPE_FUNC_NEVER:
1144                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1145         case PIPE_FUNC_LESS:
1146                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1147         case PIPE_FUNC_EQUAL:
1148                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1149         case PIPE_FUNC_LEQUAL:
1150                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1151         case PIPE_FUNC_GREATER:
1152                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1153         case PIPE_FUNC_NOTEQUAL:
1154                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1155         case PIPE_FUNC_GEQUAL:
1156                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1157         case PIPE_FUNC_ALWAYS:
1158                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1159         }
1160 }