2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
38 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
41 cb
->buf
= CALLOC(1, 4 * num_dw
);
42 cb
->max_num_dw
= num_dw
;
45 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
50 void r600_init_atom(struct r600_context
*rctx
,
51 struct r600_atom
*atom
,
53 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
59 atom
->emit
= (void*)emit
;
60 atom
->num_dw
= num_dw
;
64 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
66 r600_emit_command_buffer(rctx
->b
.rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
69 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
71 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
72 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
73 unsigned alpha_ref
= a
->sx_alpha_ref
;
75 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
79 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
80 a
->sx_alpha_test_control
|
81 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
82 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
85 static void r600_texture_barrier(struct pipe_context
*ctx
)
87 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
89 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
90 R600_CONTEXT_FLUSH_AND_INV_CB
|
91 R600_CONTEXT_FLUSH_AND_INV
|
92 R600_CONTEXT_WAIT_3D_IDLE
;
95 static unsigned r600_conv_pipe_prim(unsigned prim
)
97 static const unsigned prim_conv
[] = {
98 V_008958_DI_PT_POINTLIST
,
99 V_008958_DI_PT_LINELIST
,
100 V_008958_DI_PT_LINELOOP
,
101 V_008958_DI_PT_LINESTRIP
,
102 V_008958_DI_PT_TRILIST
,
103 V_008958_DI_PT_TRISTRIP
,
104 V_008958_DI_PT_TRIFAN
,
105 V_008958_DI_PT_QUADLIST
,
106 V_008958_DI_PT_QUADSTRIP
,
107 V_008958_DI_PT_POLYGON
,
108 V_008958_DI_PT_LINELIST_ADJ
,
109 V_008958_DI_PT_LINESTRIP_ADJ
,
110 V_008958_DI_PT_TRILIST_ADJ
,
111 V_008958_DI_PT_TRISTRIP_ADJ
,
112 V_008958_DI_PT_RECTLIST
114 return prim_conv
[prim
];
117 /* common state between evergreen and r600 */
119 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
120 struct r600_blend_state
*blend
, bool blend_disable
)
122 unsigned color_control
;
123 bool update_cb
= false;
125 rctx
->alpha_to_one
= blend
->alpha_to_one
;
126 rctx
->dual_src_blend
= blend
->dual_src_blend
;
128 if (!blend_disable
) {
129 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
130 color_control
= blend
->cb_color_control
;
132 /* Blending is disabled. */
133 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
134 color_control
= blend
->cb_color_control_no_blend
;
137 /* Update derived states. */
138 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
139 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
142 if (rctx
->b
.chip_class
<= R700
&&
143 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
144 rctx
->cb_misc_state
.cb_color_control
= color_control
;
147 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
148 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
152 rctx
->cb_misc_state
.atom
.dirty
= true;
156 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
158 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
159 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
162 r600_set_cso_state_with_cb(&rctx
->blend_state
, NULL
, NULL
);
166 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
169 static void r600_set_blend_color(struct pipe_context
*ctx
,
170 const struct pipe_blend_color
*state
)
172 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
174 rctx
->blend_color
.state
= *state
;
175 rctx
->blend_color
.atom
.dirty
= true;
178 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
180 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
181 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
183 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
184 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
185 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
186 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
187 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
190 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
192 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
193 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
195 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
196 r600_write_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
197 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
198 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
201 static void r600_set_clip_state(struct pipe_context
*ctx
,
202 const struct pipe_clip_state
*state
)
204 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
205 struct pipe_constant_buffer cb
;
207 rctx
->clip_state
.state
= *state
;
208 rctx
->clip_state
.atom
.dirty
= true;
211 cb
.user_buffer
= state
->ucp
;
212 cb
.buffer_offset
= 0;
213 cb
.buffer_size
= 4*4*8;
214 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
215 pipe_resource_reference(&cb
.buffer
, NULL
);
218 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
219 const struct r600_stencil_ref
*state
)
221 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
223 rctx
->stencil_ref
.state
= *state
;
224 rctx
->stencil_ref
.atom
.dirty
= true;
227 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
229 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
230 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
232 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
233 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
234 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
235 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
236 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
237 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
238 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
239 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
240 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
243 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
244 const struct pipe_stencil_ref
*state
)
246 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
247 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
248 struct r600_stencil_ref ref
;
250 rctx
->stencil_ref
.pipe_state
= *state
;
255 ref
.ref_value
[0] = state
->ref_value
[0];
256 ref
.ref_value
[1] = state
->ref_value
[1];
257 ref
.valuemask
[0] = dsa
->valuemask
[0];
258 ref
.valuemask
[1] = dsa
->valuemask
[1];
259 ref
.writemask
[0] = dsa
->writemask
[0];
260 ref
.writemask
[1] = dsa
->writemask
[1];
262 r600_set_stencil_ref(ctx
, &ref
);
265 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
267 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
268 struct r600_dsa_state
*dsa
= state
;
269 struct r600_stencil_ref ref
;
272 r600_set_cso_state_with_cb(&rctx
->dsa_state
, NULL
, NULL
);
276 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
278 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
279 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
280 ref
.valuemask
[0] = dsa
->valuemask
[0];
281 ref
.valuemask
[1] = dsa
->valuemask
[1];
282 ref
.writemask
[0] = dsa
->writemask
[0];
283 ref
.writemask
[1] = dsa
->writemask
[1];
284 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
285 rctx
->zwritemask
= dsa
->zwritemask
;
286 if (rctx
->b
.chip_class
>= EVERGREEN
) {
287 /* work around some issue when not writting to zbuffer
288 * we are having lockup on evergreen so do not enable
289 * hyperz when not writting zbuffer
291 rctx
->db_misc_state
.atom
.dirty
= true;
295 r600_set_stencil_ref(ctx
, &ref
);
297 /* Update alphatest state. */
298 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
299 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
300 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
301 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
302 rctx
->alphatest_state
.atom
.dirty
= true;
306 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
308 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
309 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
314 rctx
->rasterizer
= rs
;
316 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
318 if (rs
->offset_enable
&&
319 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
320 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
321 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
322 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
323 rctx
->poly_offset_state
.atom
.dirty
= true;
326 /* Update clip_misc_state. */
327 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
328 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
329 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
330 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
331 rctx
->clip_misc_state
.atom
.dirty
= true;
334 /* Workaround for a missing scissor enable on r600. */
335 if (rctx
->b
.chip_class
== R600
&&
336 rs
->scissor_enable
!= rctx
->scissor
[0].enable
) {
337 rctx
->scissor
[0].enable
= rs
->scissor_enable
;
338 rctx
->scissor
[0].atom
.dirty
= true;
341 /* Re-emit PA_SC_LINE_STIPPLE. */
342 rctx
->last_primitive_type
= -1;
345 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
347 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
349 r600_release_command_buffer(&rs
->buffer
);
353 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
354 struct pipe_sampler_view
*state
)
356 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
358 if (view
->tex_resource
->gpu_address
&&
359 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
360 LIST_DELINIT(&view
->list
);
362 pipe_resource_reference(&state
->texture
, NULL
);
366 void r600_sampler_states_dirty(struct r600_context
*rctx
,
367 struct r600_sampler_states
*state
)
369 if (state
->dirty_mask
) {
370 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
371 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
374 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
375 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
376 state
->atom
.dirty
= true;
380 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
383 unsigned count
, void **states
)
385 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
386 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
387 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
388 int seamless_cube_map
= -1;
390 /* This sets 1-bit for states with index >= count. */
391 uint32_t disable_mask
= ~((1ull << count
) - 1);
392 /* These are the new states set by this function. */
393 uint32_t new_mask
= 0;
395 assert(start
== 0); /* XXX fix below */
397 if (shader
!= PIPE_SHADER_VERTEX
&&
398 shader
!= PIPE_SHADER_FRAGMENT
) {
402 for (i
= 0; i
< count
; i
++) {
403 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
405 if (rstate
== dst
->states
.states
[i
]) {
410 if (rstate
->border_color_use
) {
411 dst
->states
.has_bordercolor_mask
|= 1 << i
;
413 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
415 seamless_cube_map
= rstate
->seamless_cube_map
;
419 disable_mask
|= 1 << i
;
423 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
424 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
426 dst
->states
.enabled_mask
&= ~disable_mask
;
427 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
428 dst
->states
.enabled_mask
|= new_mask
;
429 dst
->states
.dirty_mask
|= new_mask
;
430 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
432 r600_sampler_states_dirty(rctx
, &dst
->states
);
434 /* Seamless cubemap state. */
435 if (rctx
->b
.chip_class
<= R700
&&
436 seamless_cube_map
!= -1 &&
437 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
438 /* change in TA_CNTL_AUX need a pipeline flush */
439 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
440 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
441 rctx
->seamless_cube_map
.atom
.dirty
= true;
445 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
450 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
452 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
453 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
455 if (rctx
->blend_state
.cso
== state
) {
456 ctx
->bind_blend_state(ctx
, NULL
);
459 r600_release_command_buffer(&blend
->buffer
);
460 r600_release_command_buffer(&blend
->buffer_no_blend
);
464 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
466 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
467 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
469 if (rctx
->dsa_state
.cso
== state
) {
470 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
473 r600_release_command_buffer(&dsa
->buffer
);
477 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
479 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
481 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
484 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
486 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
487 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
491 static void r600_set_index_buffer(struct pipe_context
*ctx
,
492 const struct pipe_index_buffer
*ib
)
494 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
497 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
498 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
499 r600_context_add_resource_size(ctx
, ib
->buffer
);
501 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
505 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
507 if (rctx
->vertex_buffer_state
.dirty_mask
) {
508 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
;
509 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
510 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
511 rctx
->vertex_buffer_state
.atom
.dirty
= true;
515 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
516 unsigned start_slot
, unsigned count
,
517 const struct pipe_vertex_buffer
*input
)
519 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
520 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
521 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
523 uint32_t disable_mask
= 0;
524 /* These are the new buffers set by this function. */
525 uint32_t new_buffer_mask
= 0;
527 /* Set vertex buffers. */
529 for (i
= 0; i
< count
; i
++) {
530 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
531 if (input
[i
].buffer
) {
532 vb
[i
].stride
= input
[i
].stride
;
533 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
534 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
535 new_buffer_mask
|= 1 << i
;
536 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
538 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
539 disable_mask
|= 1 << i
;
544 for (i
= 0; i
< count
; i
++) {
545 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
547 disable_mask
= ((1ull << count
) - 1);
550 disable_mask
<<= start_slot
;
551 new_buffer_mask
<<= start_slot
;
553 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
554 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
555 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
556 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
558 r600_vertex_buffers_dirty(rctx
);
561 void r600_sampler_views_dirty(struct r600_context
*rctx
,
562 struct r600_samplerview_state
*state
)
564 if (state
->dirty_mask
) {
565 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
566 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
567 util_bitcount(state
->dirty_mask
);
568 state
->atom
.dirty
= true;
572 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
573 unsigned start
, unsigned count
,
574 struct pipe_sampler_view
**views
)
576 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
577 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
578 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
579 uint32_t dirty_sampler_states_mask
= 0;
581 /* This sets 1-bit for textures with index >= count. */
582 uint32_t disable_mask
= ~((1ull << count
) - 1);
583 /* These are the new textures set by this function. */
584 uint32_t new_mask
= 0;
586 /* Set textures with index >= count to NULL. */
587 uint32_t remaining_mask
;
589 assert(start
== 0); /* XXX fix below */
591 if (shader
== PIPE_SHADER_COMPUTE
) {
592 evergreen_set_cs_sampler_view(pipe
, start
, count
, views
);
596 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
598 while (remaining_mask
) {
599 i
= u_bit_scan(&remaining_mask
);
600 assert(dst
->views
.views
[i
]);
602 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
605 for (i
= 0; i
< count
; i
++) {
606 if (rviews
[i
] == dst
->views
.views
[i
]) {
611 struct r600_texture
*rtex
=
612 (struct r600_texture
*)rviews
[i
]->base
.texture
;
614 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
615 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
616 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
618 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
621 /* Track compressed colorbuffers. */
622 if (rtex
->cmask
.size
) {
623 dst
->views
.compressed_colortex_mask
|= 1 << i
;
625 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
628 /* Changing from array to non-arrays textures and vice versa requires
629 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
630 if (rctx
->b
.chip_class
<= R700
&&
631 (dst
->states
.enabled_mask
& (1 << i
)) &&
632 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
633 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
634 dirty_sampler_states_mask
|= 1 << i
;
637 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
639 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
641 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
642 disable_mask
|= 1 << i
;
646 dst
->views
.enabled_mask
&= ~disable_mask
;
647 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
648 dst
->views
.enabled_mask
|= new_mask
;
649 dst
->views
.dirty_mask
|= new_mask
;
650 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
651 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
652 dst
->views
.dirty_txq_constants
= TRUE
;
653 dst
->views
.dirty_buffer_constants
= TRUE
;
654 r600_sampler_views_dirty(rctx
, &dst
->views
);
656 if (dirty_sampler_states_mask
) {
657 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
658 r600_sampler_states_dirty(rctx
, &dst
->states
);
662 static void r600_set_viewport_states(struct pipe_context
*ctx
,
664 unsigned num_viewports
,
665 const struct pipe_viewport_state
*state
)
667 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
670 for (i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
671 rctx
->viewport
[i
].state
= state
[i
- start_slot
];
672 rctx
->viewport
[i
].atom
.dirty
= true;
676 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
678 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
679 struct r600_viewport_state
*rstate
= (struct r600_viewport_state
*)atom
;
680 struct pipe_viewport_state
*state
= &rstate
->state
;
681 int offset
= rstate
->idx
* 6 * 4;
683 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
+ offset
, 6);
684 radeon_emit(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
685 radeon_emit(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
686 radeon_emit(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
687 radeon_emit(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
688 radeon_emit(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
689 radeon_emit(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
692 /* Compute the key for the hw shader variant */
693 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
694 struct r600_pipe_shader_selector
* sel
)
696 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
697 struct r600_shader_key key
;
698 memset(&key
, 0, sizeof(key
));
700 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
701 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
702 key
.alpha_to_one
= rctx
->alpha_to_one
&&
703 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
704 !rctx
->framebuffer
.cb0_is_integer
;
705 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
706 /* Dual-source blending only makes sense with nr_cbufs == 1. */
707 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
709 } else if (sel
->type
== PIPE_SHADER_VERTEX
) {
710 key
.vs_as_es
= (rctx
->gs_shader
!= NULL
);
715 /* Select the hw shader variant depending on the current state.
716 * (*dirty) is set to 1 if current variant was changed */
717 static int r600_shader_select(struct pipe_context
*ctx
,
718 struct r600_pipe_shader_selector
* sel
,
721 struct r600_shader_key key
;
722 struct r600_pipe_shader
* shader
= NULL
;
725 memset(&key
, 0, sizeof(key
));
726 key
= r600_shader_selector_key(ctx
, sel
);
728 /* Check if we don't need to change anything.
729 * This path is also used for most shaders that don't need multiple
730 * variants, it will cost just a computation of the key and this
732 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
736 /* lookup if we have other variants in the list */
737 if (sel
->num_shaders
> 1) {
738 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
740 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
746 p
->next_variant
= c
->next_variant
;
751 if (unlikely(!shader
)) {
752 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
753 shader
->selector
= sel
;
755 r
= r600_pipe_shader_create(ctx
, shader
, key
);
757 R600_ERR("Failed to build shader variant (type=%u) %d\n",
764 /* We don't know the value of nr_ps_max_color_exports until we built
765 * at least one variant, so we may need to recompute the key after
766 * building first variant. */
767 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
768 sel
->num_shaders
== 0) {
769 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
770 key
= r600_shader_selector_key(ctx
, sel
);
773 memcpy(&shader
->key
, &key
, sizeof(key
));
780 shader
->next_variant
= sel
->current
;
781 sel
->current
= shader
;
786 static void *r600_create_shader_state(struct pipe_context
*ctx
,
787 const struct pipe_shader_state
*state
,
788 unsigned pipe_shader_type
)
790 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
792 sel
->type
= pipe_shader_type
;
793 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
794 sel
->so
= state
->stream_output
;
798 static void *r600_create_ps_state(struct pipe_context
*ctx
,
799 const struct pipe_shader_state
*state
)
801 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
804 static void *r600_create_vs_state(struct pipe_context
*ctx
,
805 const struct pipe_shader_state
*state
)
807 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
810 static void *r600_create_gs_state(struct pipe_context
*ctx
,
811 const struct pipe_shader_state
*state
)
813 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
816 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
818 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
821 state
= rctx
->dummy_pixel_shader
;
823 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
826 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
828 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
833 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
834 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
837 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
839 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
841 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
845 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
848 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
849 struct r600_pipe_shader_selector
*sel
)
851 struct r600_pipe_shader
*p
= sel
->current
, *c
;
854 r600_pipe_shader_destroy(ctx
, p
);
864 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
866 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
867 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
869 if (rctx
->ps_shader
== sel
) {
870 rctx
->ps_shader
= NULL
;
873 r600_delete_shader_selector(ctx
, sel
);
876 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
878 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
879 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
881 if (rctx
->vs_shader
== sel
) {
882 rctx
->vs_shader
= NULL
;
885 r600_delete_shader_selector(ctx
, sel
);
889 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
891 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
892 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
894 if (rctx
->gs_shader
== sel
) {
895 rctx
->gs_shader
= NULL
;
898 r600_delete_shader_selector(ctx
, sel
);
902 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
904 if (state
->dirty_mask
) {
905 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
906 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
907 : util_bitcount(state
->dirty_mask
)*19;
908 state
->atom
.dirty
= true;
912 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
913 struct pipe_constant_buffer
*input
)
915 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
916 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
917 struct pipe_constant_buffer
*cb
;
920 /* Note that the state tracker can unbind constant buffers by
923 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
924 state
->enabled_mask
&= ~(1 << index
);
925 state
->dirty_mask
&= ~(1 << index
);
926 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
930 cb
= &state
->cb
[index
];
931 cb
->buffer_size
= input
->buffer_size
;
933 ptr
= input
->user_buffer
;
936 /* Upload the user buffer. */
937 if (R600_BIG_ENDIAN
) {
939 unsigned i
, size
= input
->buffer_size
;
941 if (!(tmpPtr
= malloc(size
))) {
942 R600_ERR("Failed to allocate BE swap buffer.\n");
946 for (i
= 0; i
< size
/ 4; ++i
) {
947 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
950 u_upload_data(rctx
->b
.uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
953 u_upload_data(rctx
->b
.uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
955 /* account it in gtt */
956 rctx
->b
.gtt
+= input
->buffer_size
;
958 /* Setup the hw buffer. */
959 cb
->buffer_offset
= input
->buffer_offset
;
960 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
961 r600_context_add_resource_size(ctx
, input
->buffer
);
964 state
->enabled_mask
|= 1 << index
;
965 state
->dirty_mask
|= 1 << index
;
966 r600_constant_buffers_dirty(rctx
, state
);
969 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
971 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
973 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
976 rctx
->sample_mask
.sample_mask
= sample_mask
;
977 rctx
->sample_mask
.atom
.dirty
= true;
981 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
982 * doesn't require full swizzles it does need masking and setting alpha
983 * to one, so we setup a set of 5 constants with the masks + alpha value
984 * then in the shader, we AND the 4 components with 0xffffffff or 0,
985 * then OR the alpha with the value given here.
986 * We use a 6th constant to store the txq buffer size in
988 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
990 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
993 struct pipe_constant_buffer cb
;
996 if (!samplers
->views
.dirty_buffer_constants
)
999 samplers
->views
.dirty_buffer_constants
= FALSE
;
1001 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1002 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1003 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1004 memset(samplers
->buffer_constants
, 0, array_size
);
1005 for (i
= 0; i
< bits
; i
++) {
1006 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1008 const struct util_format_description
*desc
;
1009 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1011 for (j
= 0; j
< 4; j
++)
1012 if (j
< desc
->nr_channels
)
1013 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1015 samplers
->buffer_constants
[offset
+j
] = 0x0;
1016 if (desc
->nr_channels
< 4) {
1017 if (desc
->channel
[0].pure_integer
)
1018 samplers
->buffer_constants
[offset
+4] = 1;
1020 samplers
->buffer_constants
[offset
+4] = 0x3f800000;
1022 samplers
->buffer_constants
[offset
+ 4] = 0;
1024 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1029 cb
.user_buffer
= samplers
->buffer_constants
;
1030 cb
.buffer_offset
= 0;
1031 cb
.buffer_size
= array_size
;
1032 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1033 pipe_resource_reference(&cb
.buffer
, NULL
);
1036 /* On evergreen we only need to store the buffer size for TXQ */
1037 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1039 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1041 uint32_t array_size
;
1042 struct pipe_constant_buffer cb
;
1045 if (!samplers
->views
.dirty_buffer_constants
)
1048 samplers
->views
.dirty_buffer_constants
= FALSE
;
1050 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1051 array_size
= bits
* sizeof(uint32_t) * 4;
1052 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1053 memset(samplers
->buffer_constants
, 0, array_size
);
1054 for (i
= 0; i
< bits
; i
++)
1055 if (samplers
->views
.enabled_mask
& (1 << i
))
1056 samplers
->buffer_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1059 cb
.user_buffer
= samplers
->buffer_constants
;
1060 cb
.buffer_offset
= 0;
1061 cb
.buffer_size
= array_size
;
1062 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1063 pipe_resource_reference(&cb
.buffer
, NULL
);
1066 static void r600_setup_txq_cube_array_constants(struct r600_context
*rctx
, int shader_type
)
1068 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1070 uint32_t array_size
;
1071 struct pipe_constant_buffer cb
;
1074 if (!samplers
->views
.dirty_txq_constants
)
1077 samplers
->views
.dirty_txq_constants
= FALSE
;
1079 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1080 array_size
= bits
* sizeof(uint32_t) * 4;
1081 samplers
->txq_constants
= realloc(samplers
->txq_constants
, array_size
);
1082 memset(samplers
->txq_constants
, 0, array_size
);
1083 for (i
= 0; i
< bits
; i
++)
1084 if (samplers
->views
.enabled_mask
& (1 << i
))
1085 samplers
->txq_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1088 cb
.user_buffer
= samplers
->txq_constants
;
1089 cb
.buffer_offset
= 0;
1090 cb
.buffer_size
= array_size
;
1091 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_TXQ_CONST_BUFFER
, &cb
);
1092 pipe_resource_reference(&cb
.buffer
, NULL
);
1095 /* set sample xy locations as array of fragment shader constants */
1096 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1098 struct pipe_constant_buffer constbuf
= {0};
1099 float values
[4*16] = {0.0f
};
1101 struct pipe_context
*ctx
= &rctx
->b
.b
;
1103 assert(rctx
->framebuffer
.nr_samples
<= Elements(values
)/4);
1104 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1105 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &values
[4*i
]);
1108 constbuf
.user_buffer
= values
;
1109 constbuf
.buffer_size
= rctx
->framebuffer
.nr_samples
* 4 * 4;
1110 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_FRAGMENT
,
1111 R600_SAMPLE_POSITIONS_CONST_BUFFER
, &constbuf
);
1112 pipe_resource_reference(&constbuf
.buffer
, NULL
);
1115 static void update_shader_atom(struct pipe_context
*ctx
,
1116 struct r600_shader_state
*state
,
1117 struct r600_pipe_shader
*shader
)
1119 state
->shader
= shader
;
1121 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1122 state
->atom
.dirty
= true;
1123 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1125 state
->atom
.num_dw
= 0;
1126 state
->atom
.dirty
= false;
1130 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1132 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1133 rctx
->shader_stages
.geom_enable
= enable
;
1134 rctx
->shader_stages
.atom
.dirty
= true;
1137 if (rctx
->gs_rings
.enable
!= enable
) {
1138 rctx
->gs_rings
.enable
= enable
;
1139 rctx
->gs_rings
.atom
.dirty
= true;
1141 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1142 unsigned size
= 0x1C000;
1143 rctx
->gs_rings
.esgs_ring
.buffer
=
1144 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1145 PIPE_USAGE_DEFAULT
, size
);
1146 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1150 rctx
->gs_rings
.gsvs_ring
.buffer
=
1151 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1152 PIPE_USAGE_DEFAULT
, size
);
1153 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1157 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1158 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1159 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1160 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1162 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1163 R600_GS_RING_CONST_BUFFER
, NULL
);
1164 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1165 R600_GS_RING_CONST_BUFFER
, NULL
);
1170 static bool r600_update_derived_state(struct r600_context
*rctx
)
1172 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1173 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1176 if (!rctx
->blitter
->running
) {
1179 /* Decompress textures if needed. */
1180 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1181 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1182 if (views
->compressed_depthtex_mask
) {
1183 r600_decompress_depth_textures(rctx
, views
);
1185 if (views
->compressed_colortex_mask
) {
1186 r600_decompress_color_textures(rctx
, views
);
1191 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1193 if (rctx
->gs_shader
) {
1194 r600_shader_select(ctx
, rctx
->gs_shader
, &gs_dirty
);
1195 if (unlikely(!rctx
->gs_shader
->current
))
1198 if (!rctx
->shader_stages
.geom_enable
) {
1199 rctx
->shader_stages
.geom_enable
= true;
1200 rctx
->shader_stages
.atom
.dirty
= true;
1203 /* gs_shader provides GS and VS (copy shader) */
1204 if (unlikely(rctx
->geometry_shader
.shader
!= rctx
->gs_shader
->current
)) {
1205 update_shader_atom(ctx
, &rctx
->geometry_shader
, rctx
->gs_shader
->current
);
1206 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->gs_shader
->current
->gs_copy_shader
);
1207 /* Update clip misc state. */
1208 if (rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1209 rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1210 rctx
->clip_misc_state
.clip_disable
!= rctx
->gs_shader
->current
->shader
.vs_position_window_space
) {
1211 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
;
1212 rctx
->clip_misc_state
.clip_dist_write
= rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
;
1213 rctx
->clip_misc_state
.clip_disable
= rctx
->gs_shader
->current
->shader
.vs_position_window_space
;
1214 rctx
->clip_misc_state
.atom
.dirty
= true;
1218 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1219 if (unlikely(!rctx
->vs_shader
->current
))
1222 /* vs_shader is used as ES */
1223 if (unlikely(vs_dirty
|| rctx
->export_shader
.shader
!= rctx
->vs_shader
->current
)) {
1224 update_shader_atom(ctx
, &rctx
->export_shader
, rctx
->vs_shader
->current
);
1227 if (unlikely(rctx
->geometry_shader
.shader
)) {
1228 update_shader_atom(ctx
, &rctx
->geometry_shader
, NULL
);
1229 update_shader_atom(ctx
, &rctx
->export_shader
, NULL
);
1230 rctx
->shader_stages
.geom_enable
= false;
1231 rctx
->shader_stages
.atom
.dirty
= true;
1234 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1235 if (unlikely(!rctx
->vs_shader
->current
))
1238 if (unlikely(vs_dirty
|| rctx
->vertex_shader
.shader
!= rctx
->vs_shader
->current
)) {
1239 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->vs_shader
->current
);
1241 /* Update clip misc state. */
1242 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1243 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1244 rctx
->clip_misc_state
.clip_disable
!= rctx
->vs_shader
->current
->shader
.vs_position_window_space
) {
1245 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
1246 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
1247 rctx
->clip_misc_state
.clip_disable
= rctx
->vs_shader
->current
->shader
.vs_position_window_space
;
1248 rctx
->clip_misc_state
.atom
.dirty
= true;
1253 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1254 if (unlikely(!rctx
->ps_shader
->current
))
1257 if (unlikely(ps_dirty
|| rctx
->pixel_shader
.shader
!= rctx
->ps_shader
->current
||
1258 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1259 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1261 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1262 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1263 rctx
->cb_misc_state
.atom
.dirty
= true;
1266 if (rctx
->b
.chip_class
<= R700
) {
1267 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1269 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1270 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1271 rctx
->cb_misc_state
.atom
.dirty
= true;
1275 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1276 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1277 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1279 if (rctx
->b
.chip_class
>= EVERGREEN
)
1280 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1282 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1285 update_shader_atom(ctx
, &rctx
->pixel_shader
, rctx
->ps_shader
->current
);
1288 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1289 evergreen_update_db_shader_control(rctx
);
1291 r600_update_db_shader_control(rctx
);
1294 /* on R600 we stuff masks + txq info into one constant buffer */
1295 /* on evergreen we only need a txq info one */
1296 if (rctx
->b
.chip_class
< EVERGREEN
) {
1297 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1298 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1299 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1300 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1301 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.uses_tex_buffers
)
1302 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1304 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1305 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1306 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1307 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1308 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.uses_tex_buffers
)
1309 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1313 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1314 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1315 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1316 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_VERTEX
);
1317 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1318 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1320 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1321 if (!r600_adjust_gprs(rctx
)) {
1322 /* discard rendering */
1327 blend_disable
= (rctx
->dual_src_blend
&&
1328 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1330 if (blend_disable
!= rctx
->force_blend_disable
) {
1331 rctx
->force_blend_disable
= blend_disable
;
1332 r600_bind_blend_state_internal(rctx
,
1333 rctx
->blend_state
.cso
,
1340 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1342 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1343 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1345 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1346 state
->pa_cl_clip_cntl
|
1347 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1348 S_028810_CLIP_DISABLE(state
->clip_disable
));
1349 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1350 state
->pa_cl_vs_out_cntl
|
1351 (state
->clip_plane_enable
& state
->clip_dist_write
));
1354 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1356 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1357 struct pipe_draw_info info
= *dinfo
;
1358 struct pipe_index_buffer ib
= {};
1360 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1362 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1366 if (!rctx
->vs_shader
|| !rctx
->ps_shader
) {
1371 /* make sure that the gfx ring is only one active */
1372 if (rctx
->b
.rings
.dma
.cs
&& rctx
->b
.rings
.dma
.cs
->cdw
) {
1373 rctx
->b
.rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1376 if (!r600_update_derived_state(rctx
)) {
1377 /* useless to render because current rendering command
1384 /* Initialize the index buffer struct. */
1385 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1386 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1387 ib
.index_size
= rctx
->index_buffer
.index_size
;
1388 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1390 /* Translate 8-bit indices to 16-bit. */
1391 if (ib
.index_size
== 1) {
1392 struct pipe_resource
*out_buffer
= NULL
;
1393 unsigned out_offset
;
1396 u_upload_alloc(rctx
->b
.uploader
, 0, info
.count
* 2,
1397 &out_offset
, &out_buffer
, &ptr
);
1399 util_shorten_ubyte_elts_to_userptr(
1400 &rctx
->b
.b
, &ib
, 0, ib
.offset
, info
.count
, ptr
);
1402 pipe_resource_reference(&ib
.buffer
, NULL
);
1403 ib
.user_buffer
= NULL
;
1404 ib
.buffer
= out_buffer
;
1405 ib
.offset
= out_offset
;
1409 /* Upload the index buffer.
1410 * The upload is skipped for small index counts on little-endian machines
1411 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1412 * Note: Instanced rendering in combination with immediate indices hangs. */
1413 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.instance_count
> 1 ||
1414 info
.count
*ib
.index_size
> 20)) {
1415 u_upload_data(rctx
->b
.uploader
, 0, info
.count
* ib
.index_size
,
1416 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1417 ib
.user_buffer
= NULL
;
1420 info
.index_bias
= info
.start
;
1423 /* Set the index offset and primitive restart. */
1424 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1425 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1426 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
) {
1427 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1428 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1429 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1430 rctx
->vgt_state
.atom
.dirty
= true;
1433 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1434 if (rctx
->b
.chip_class
== R600
) {
1435 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1436 rctx
->cb_misc_state
.atom
.dirty
= true;
1440 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1441 r600_flush_emit(rctx
);
1443 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1444 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1447 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1450 if (rctx
->b
.chip_class
== CAYMAN
) {
1451 /* Copied from radeonsi. */
1452 unsigned primgroup_size
= 128; /* recommended without a GS */
1453 bool ia_switch_on_eop
= false;
1454 bool partial_vs_wave
= false;
1456 if (rctx
->gs_shader
)
1457 primgroup_size
= 64; /* recommended with a GS */
1459 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1460 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1461 ia_switch_on_eop
= true;
1464 if (rctx
->b
.streamout
.streamout_enabled
||
1465 rctx
->b
.streamout
.prims_gen_query_enabled
)
1466 partial_vs_wave
= true;
1468 r600_write_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1469 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1470 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1471 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1474 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1475 * even though it should have no effect on those. */
1476 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1477 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1478 unsigned prim
= info
.mode
;
1480 if (rctx
->gs_shader
) {
1481 prim
= rctx
->gs_shader
->current
->shader
.gs_output_prim
;
1483 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1485 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1486 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1487 info
.mode
== R600_PRIM_RECTANGLE_LIST
) {
1488 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1490 r600_write_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1493 /* Update start instance. */
1494 if (rctx
->last_start_instance
!= info
.start_instance
) {
1495 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1496 rctx
->last_start_instance
= info
.start_instance
;
1499 /* Update the primitive type. */
1500 if (rctx
->last_primitive_type
!= info
.mode
) {
1501 unsigned ls_mask
= 0;
1503 if (info
.mode
== PIPE_PRIM_LINES
)
1505 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1506 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1509 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1510 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1511 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1512 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1513 r600_conv_pipe_prim(info
.mode
));
1515 rctx
->last_primitive_type
= info
.mode
;
1519 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->b
.predicate_drawing
);
1520 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1522 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->b
.predicate_drawing
);
1523 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1524 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1525 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1527 if (ib
.user_buffer
) {
1528 unsigned size_bytes
= info
.count
*ib
.index_size
;
1529 unsigned size_dw
= align(size_bytes
, 4) / 4;
1530 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->b
.predicate_drawing
);
1531 cs
->buf
[cs
->cdw
++] = info
.count
;
1532 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1533 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1536 uint64_t va
= r600_resource(ib
.buffer
)->gpu_address
+ ib
.offset
;
1537 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->b
.predicate_drawing
);
1538 cs
->buf
[cs
->cdw
++] = va
;
1539 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1540 cs
->buf
[cs
->cdw
++] = info
.count
;
1541 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1542 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1543 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1544 (struct r600_resource
*)ib
.buffer
,
1545 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
1548 if (info
.count_from_stream_output
) {
1549 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1550 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1552 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1554 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1555 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1556 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1557 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1558 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1559 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1561 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1562 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1563 t
->buf_filled_size
, RADEON_USAGE_READ
,
1567 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->b
.predicate_drawing
);
1568 cs
->buf
[cs
->cdw
++] = info
.count
;
1569 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1570 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1573 if (rctx
->screen
->b
.trace_bo
) {
1574 r600_trace_emit(rctx
);
1577 /* Set the depth buffer as dirty. */
1578 if (rctx
->framebuffer
.state
.zsbuf
) {
1579 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1580 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1582 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1584 if (rctx
->framebuffer
.compressed_cb_mask
) {
1585 struct pipe_surface
*surf
;
1586 struct r600_texture
*rtex
;
1587 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1590 unsigned i
= u_bit_scan(&mask
);
1591 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1592 rtex
= (struct r600_texture
*)surf
->texture
;
1594 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1599 pipe_resource_reference(&ib
.buffer
, NULL
);
1600 rctx
->b
.num_draw_calls
++;
1603 uint32_t r600_translate_stencil_op(int s_op
)
1606 case PIPE_STENCIL_OP_KEEP
:
1607 return V_028800_STENCIL_KEEP
;
1608 case PIPE_STENCIL_OP_ZERO
:
1609 return V_028800_STENCIL_ZERO
;
1610 case PIPE_STENCIL_OP_REPLACE
:
1611 return V_028800_STENCIL_REPLACE
;
1612 case PIPE_STENCIL_OP_INCR
:
1613 return V_028800_STENCIL_INCR
;
1614 case PIPE_STENCIL_OP_DECR
:
1615 return V_028800_STENCIL_DECR
;
1616 case PIPE_STENCIL_OP_INCR_WRAP
:
1617 return V_028800_STENCIL_INCR_WRAP
;
1618 case PIPE_STENCIL_OP_DECR_WRAP
:
1619 return V_028800_STENCIL_DECR_WRAP
;
1620 case PIPE_STENCIL_OP_INVERT
:
1621 return V_028800_STENCIL_INVERT
;
1623 R600_ERR("Unknown stencil op %d", s_op
);
1630 uint32_t r600_translate_fill(uint32_t func
)
1633 case PIPE_POLYGON_MODE_FILL
:
1635 case PIPE_POLYGON_MODE_LINE
:
1637 case PIPE_POLYGON_MODE_POINT
:
1645 unsigned r600_tex_wrap(unsigned wrap
)
1649 case PIPE_TEX_WRAP_REPEAT
:
1650 return V_03C000_SQ_TEX_WRAP
;
1651 case PIPE_TEX_WRAP_CLAMP
:
1652 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1653 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1654 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1655 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1656 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1657 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1658 return V_03C000_SQ_TEX_MIRROR
;
1659 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1660 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1661 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1662 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1663 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1664 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1668 unsigned r600_tex_filter(unsigned filter
)
1672 case PIPE_TEX_FILTER_NEAREST
:
1673 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1674 case PIPE_TEX_FILTER_LINEAR
:
1675 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1679 unsigned r600_tex_mipfilter(unsigned filter
)
1682 case PIPE_TEX_MIPFILTER_NEAREST
:
1683 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1684 case PIPE_TEX_MIPFILTER_LINEAR
:
1685 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1687 case PIPE_TEX_MIPFILTER_NONE
:
1688 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1692 unsigned r600_tex_compare(unsigned compare
)
1696 case PIPE_FUNC_NEVER
:
1697 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1698 case PIPE_FUNC_LESS
:
1699 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1700 case PIPE_FUNC_EQUAL
:
1701 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1702 case PIPE_FUNC_LEQUAL
:
1703 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1704 case PIPE_FUNC_GREATER
:
1705 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1706 case PIPE_FUNC_NOTEQUAL
:
1707 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1708 case PIPE_FUNC_GEQUAL
:
1709 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1710 case PIPE_FUNC_ALWAYS
:
1711 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1715 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1717 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1718 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1720 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1721 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1724 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1726 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1727 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1729 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1730 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1731 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1732 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1733 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1736 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1739 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1740 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
1745 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
1746 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1747 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->bo
,
1748 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
1751 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
1752 const unsigned char *swizzle_view
,
1756 unsigned char swizzle
[4];
1757 unsigned result
= 0;
1758 const uint32_t tex_swizzle_shift
[4] = {
1761 const uint32_t vtx_swizzle_shift
[4] = {
1764 const uint32_t swizzle_bit
[4] = {
1767 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
1770 swizzle_shift
= vtx_swizzle_shift
;
1773 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1775 memcpy(swizzle
, swizzle_format
, 4);
1779 for (i
= 0; i
< 4; i
++) {
1780 switch (swizzle
[i
]) {
1781 case UTIL_FORMAT_SWIZZLE_Y
:
1782 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1784 case UTIL_FORMAT_SWIZZLE_Z
:
1785 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1787 case UTIL_FORMAT_SWIZZLE_W
:
1788 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1790 case UTIL_FORMAT_SWIZZLE_0
:
1791 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1793 case UTIL_FORMAT_SWIZZLE_1
:
1794 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1796 default: /* UTIL_FORMAT_SWIZZLE_X */
1797 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1803 /* texture format translate */
1804 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1805 enum pipe_format format
,
1806 const unsigned char *swizzle_view
,
1807 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1809 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1810 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1811 const struct util_format_description
*desc
;
1812 boolean uniform
= TRUE
;
1813 bool enable_s3tc
= rscreen
->b
.info
.drm_minor
>= 9;
1814 bool is_srgb_valid
= FALSE
;
1815 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
1816 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
1819 const uint32_t sign_bit
[4] = {
1820 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1821 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1822 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1823 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1825 desc
= util_format_description(format
);
1827 /* Depth and stencil swizzling is handled separately. */
1828 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
1829 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
1832 /* Colorspace (return non-RGB formats directly). */
1833 switch (desc
->colorspace
) {
1834 /* Depth stencil formats */
1835 case UTIL_FORMAT_COLORSPACE_ZS
:
1837 /* Depth sampler formats. */
1838 case PIPE_FORMAT_Z16_UNORM
:
1839 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1842 case PIPE_FORMAT_Z24X8_UNORM
:
1843 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1844 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1847 case PIPE_FORMAT_X8Z24_UNORM
:
1848 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1849 if (rscreen
->b
.chip_class
< EVERGREEN
)
1851 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1854 case PIPE_FORMAT_Z32_FLOAT
:
1855 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1856 result
= FMT_32_FLOAT
;
1858 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1859 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1860 result
= FMT_X24_8_32_FLOAT
;
1862 /* Stencil sampler formats. */
1863 case PIPE_FORMAT_S8_UINT
:
1864 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1865 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1868 case PIPE_FORMAT_X24S8_UINT
:
1869 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1870 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1873 case PIPE_FORMAT_S8X24_UINT
:
1874 if (rscreen
->b
.chip_class
< EVERGREEN
)
1876 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1877 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1880 case PIPE_FORMAT_X32_S8X24_UINT
:
1881 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1882 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1883 result
= FMT_X24_8_32_FLOAT
;
1889 case UTIL_FORMAT_COLORSPACE_YUV
:
1890 yuv_format
|= (1 << 30);
1892 case PIPE_FORMAT_UYVY
:
1893 case PIPE_FORMAT_YUYV
:
1897 goto out_unknown
; /* XXX */
1899 case UTIL_FORMAT_COLORSPACE_SRGB
:
1900 word4
|= S_038010_FORCE_DEGAMMA(1);
1907 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1912 case PIPE_FORMAT_RGTC1_SNORM
:
1913 case PIPE_FORMAT_LATC1_SNORM
:
1914 word4
|= sign_bit
[0];
1915 case PIPE_FORMAT_RGTC1_UNORM
:
1916 case PIPE_FORMAT_LATC1_UNORM
:
1919 case PIPE_FORMAT_RGTC2_SNORM
:
1920 case PIPE_FORMAT_LATC2_SNORM
:
1921 word4
|= sign_bit
[0] | sign_bit
[1];
1922 case PIPE_FORMAT_RGTC2_UNORM
:
1923 case PIPE_FORMAT_LATC2_UNORM
:
1931 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1936 if (!util_format_s3tc_enabled
) {
1941 case PIPE_FORMAT_DXT1_RGB
:
1942 case PIPE_FORMAT_DXT1_RGBA
:
1943 case PIPE_FORMAT_DXT1_SRGB
:
1944 case PIPE_FORMAT_DXT1_SRGBA
:
1946 is_srgb_valid
= TRUE
;
1948 case PIPE_FORMAT_DXT3_RGBA
:
1949 case PIPE_FORMAT_DXT3_SRGBA
:
1951 is_srgb_valid
= TRUE
;
1953 case PIPE_FORMAT_DXT5_RGBA
:
1954 case PIPE_FORMAT_DXT5_SRGBA
:
1956 is_srgb_valid
= TRUE
;
1963 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1967 if (rscreen
->b
.chip_class
< EVERGREEN
)
1971 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1972 case PIPE_FORMAT_BPTC_SRGBA
:
1974 is_srgb_valid
= TRUE
;
1976 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1977 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
1979 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1987 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1989 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1990 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1993 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1994 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2002 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2003 result
= FMT_5_9_9_9_SHAREDEXP
;
2005 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2006 result
= FMT_10_11_11_FLOAT
;
2011 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2012 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2013 word4
|= sign_bit
[i
];
2017 /* R8G8Bx_SNORM - XXX CxV8U8 */
2019 /* See whether the components are of the same size. */
2020 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2021 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2024 /* Non-uniform formats. */
2026 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2027 desc
->channel
[0].pure_integer
)
2028 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2029 switch(desc
->nr_channels
) {
2031 if (desc
->channel
[0].size
== 5 &&
2032 desc
->channel
[1].size
== 6 &&
2033 desc
->channel
[2].size
== 5) {
2039 if (desc
->channel
[0].size
== 5 &&
2040 desc
->channel
[1].size
== 5 &&
2041 desc
->channel
[2].size
== 5 &&
2042 desc
->channel
[3].size
== 1) {
2043 result
= FMT_1_5_5_5
;
2046 if (desc
->channel
[0].size
== 10 &&
2047 desc
->channel
[1].size
== 10 &&
2048 desc
->channel
[2].size
== 10 &&
2049 desc
->channel
[3].size
== 2) {
2050 result
= FMT_2_10_10_10
;
2058 /* Find the first non-VOID channel. */
2059 for (i
= 0; i
< 4; i
++) {
2060 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2068 /* uniform formats */
2069 switch (desc
->channel
[i
].type
) {
2070 case UTIL_FORMAT_TYPE_UNSIGNED
:
2071 case UTIL_FORMAT_TYPE_SIGNED
:
2073 if (!desc
->channel
[i
].normalized
&&
2074 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2078 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2079 desc
->channel
[i
].pure_integer
)
2080 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2082 switch (desc
->channel
[i
].size
) {
2084 switch (desc
->nr_channels
) {
2089 result
= FMT_4_4_4_4
;
2094 switch (desc
->nr_channels
) {
2102 result
= FMT_8_8_8_8
;
2103 is_srgb_valid
= TRUE
;
2108 switch (desc
->nr_channels
) {
2116 result
= FMT_16_16_16_16
;
2121 switch (desc
->nr_channels
) {
2129 result
= FMT_32_32_32_32
;
2135 case UTIL_FORMAT_TYPE_FLOAT
:
2136 switch (desc
->channel
[i
].size
) {
2138 switch (desc
->nr_channels
) {
2140 result
= FMT_16_FLOAT
;
2143 result
= FMT_16_16_FLOAT
;
2146 result
= FMT_16_16_16_16_FLOAT
;
2151 switch (desc
->nr_channels
) {
2153 result
= FMT_32_FLOAT
;
2156 result
= FMT_32_32_FLOAT
;
2159 result
= FMT_32_32_32_32_FLOAT
;
2168 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2173 *yuv_format_p
= yuv_format
;
2176 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2180 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
)
2182 const struct util_format_description
*desc
= util_format_description(format
);
2183 int channel
= util_format_get_first_non_void_channel(format
);
2186 #define HAS_SIZE(x,y,z,w) \
2187 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2188 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2190 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2191 return V_0280A0_COLOR_10_11_11_FLOAT
;
2193 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2197 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2199 switch (desc
->nr_channels
) {
2201 switch (desc
->channel
[0].size
) {
2203 return V_0280A0_COLOR_8
;
2206 return V_0280A0_COLOR_16_FLOAT
;
2208 return V_0280A0_COLOR_16
;
2211 return V_0280A0_COLOR_32_FLOAT
;
2213 return V_0280A0_COLOR_32
;
2217 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2218 switch (desc
->channel
[0].size
) {
2221 return V_0280A0_COLOR_4_4
;
2223 return ~0U; /* removed on Evergreen */
2225 return V_0280A0_COLOR_8_8
;
2228 return V_0280A0_COLOR_16_16_FLOAT
;
2230 return V_0280A0_COLOR_16_16
;
2233 return V_0280A0_COLOR_32_32_FLOAT
;
2235 return V_0280A0_COLOR_32_32
;
2237 } else if (HAS_SIZE(8,24,0,0)) {
2238 return V_0280A0_COLOR_24_8
;
2239 } else if (HAS_SIZE(24,8,0,0)) {
2240 return V_0280A0_COLOR_8_24
;
2244 if (HAS_SIZE(5,6,5,0)) {
2245 return V_0280A0_COLOR_5_6_5
;
2246 } else if (HAS_SIZE(32,8,24,0)) {
2247 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2251 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2252 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2253 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2254 switch (desc
->channel
[0].size
) {
2256 return V_0280A0_COLOR_4_4_4_4
;
2258 return V_0280A0_COLOR_8_8_8_8
;
2261 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2263 return V_0280A0_COLOR_16_16_16_16
;
2266 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2268 return V_0280A0_COLOR_32_32_32_32
;
2270 } else if (HAS_SIZE(5,5,5,1)) {
2271 return V_0280A0_COLOR_1_5_5_5
;
2272 } else if (HAS_SIZE(10,10,10,2)) {
2273 return V_0280A0_COLOR_2_10_10_10
;
2280 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
2282 if (R600_BIG_ENDIAN
) {
2283 switch(colorformat
) {
2284 /* 8-bit buffers. */
2285 case V_0280A0_COLOR_4_4
:
2286 case V_0280A0_COLOR_8
:
2289 /* 16-bit buffers. */
2290 case V_0280A0_COLOR_5_6_5
:
2291 case V_0280A0_COLOR_1_5_5_5
:
2292 case V_0280A0_COLOR_4_4_4_4
:
2293 case V_0280A0_COLOR_16
:
2294 case V_0280A0_COLOR_8_8
:
2295 return ENDIAN_8IN16
;
2297 /* 32-bit buffers. */
2298 case V_0280A0_COLOR_8_8_8_8
:
2299 case V_0280A0_COLOR_2_10_10_10
:
2300 case V_0280A0_COLOR_8_24
:
2301 case V_0280A0_COLOR_24_8
:
2302 case V_0280A0_COLOR_32_FLOAT
:
2303 case V_0280A0_COLOR_16_16_FLOAT
:
2304 case V_0280A0_COLOR_16_16
:
2305 return ENDIAN_8IN32
;
2307 /* 64-bit buffers. */
2308 case V_0280A0_COLOR_16_16_16_16
:
2309 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2310 return ENDIAN_8IN16
;
2312 case V_0280A0_COLOR_32_32_FLOAT
:
2313 case V_0280A0_COLOR_32_32
:
2314 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2315 return ENDIAN_8IN32
;
2317 /* 128-bit buffers. */
2318 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2319 case V_0280A0_COLOR_32_32_32_32
:
2320 return ENDIAN_8IN32
;
2322 return ENDIAN_NONE
; /* Unsupported. */
2329 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2331 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2332 struct r600_resource
*rbuffer
= r600_resource(buf
);
2333 unsigned i
, shader
, mask
, alignment
= rbuffer
->buf
->alignment
;
2334 struct r600_pipe_sampler_view
*view
;
2336 /* Reallocate the buffer in the same pipe_resource. */
2337 r600_init_resource(&rctx
->screen
->b
, rbuffer
, rbuffer
->b
.b
.width0
,
2340 /* We changed the buffer, now we need to bind it where the old one was bound. */
2341 /* Vertex buffers. */
2342 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2344 i
= u_bit_scan(&mask
);
2345 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2346 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2347 r600_vertex_buffers_dirty(rctx
);
2350 /* Streamout buffers. */
2351 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2352 if (rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2353 if (rctx
->b
.streamout
.begin_emitted
) {
2354 r600_emit_streamout_end(&rctx
->b
);
2356 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2357 r600_streamout_buffers_dirty(&rctx
->b
);
2361 /* Constant buffers. */
2362 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2363 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2365 uint32_t mask
= state
->enabled_mask
;
2368 unsigned i
= u_bit_scan(&mask
);
2369 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2371 state
->dirty_mask
|= 1 << i
;
2375 r600_constant_buffers_dirty(rctx
, state
);
2379 /* Texture buffer objects - update the virtual addresses in descriptors. */
2380 LIST_FOR_EACH_ENTRY(view
, &rctx
->b
.texture_buffers
, list
) {
2381 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2382 unsigned stride
= util_format_get_blocksize(view
->base
.format
);
2383 uint64_t offset
= (uint64_t)view
->base
.u
.buf
.first_element
* stride
;
2384 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2386 view
->tex_resource_words
[0] = va
;
2387 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2388 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2391 /* Texture buffer objects - make bindings dirty if needed. */
2392 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2393 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2395 uint32_t mask
= state
->enabled_mask
;
2398 unsigned i
= u_bit_scan(&mask
);
2399 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2401 state
->dirty_mask
|= 1 << i
;
2405 r600_sampler_views_dirty(rctx
, state
);
2410 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2412 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2414 if (rctx
->db_misc_state
.occlusion_query_enabled
!= enable
) {
2415 rctx
->db_misc_state
.occlusion_query_enabled
= enable
;
2416 rctx
->db_misc_state
.atom
.dirty
= true;
2420 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2421 bool include_draw_vbo
)
2423 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2426 /* keep this at the end of this file, please */
2427 void r600_init_common_state_functions(struct r600_context
*rctx
)
2429 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2430 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2431 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2432 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2433 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2434 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2435 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2436 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2437 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2438 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2439 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2440 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2441 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2442 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2443 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2444 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2445 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2446 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2447 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2448 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2449 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2450 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2451 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2452 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2453 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2454 rctx
->b
.b
.set_viewport_states
= r600_set_viewport_states
;
2455 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2456 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2457 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2458 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2459 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2460 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2461 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2462 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2463 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2464 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;
2467 void r600_trace_emit(struct r600_context
*rctx
)
2469 struct r600_screen
*rscreen
= rctx
->screen
;
2470 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2474 va
= rscreen
->b
.trace_bo
->gpu_address
;
2475 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rscreen
->b
.trace_bo
,
2476 RADEON_USAGE_READWRITE
, RADEON_PRIO_MIN
);
2477 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
2478 radeon_emit(cs
, va
& 0xFFFFFFFFUL
);
2479 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
);
2480 radeon_emit(cs
, cs
->cdw
);
2481 radeon_emit(cs
, rscreen
->b
.cs_count
);
2482 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2483 radeon_emit(cs
, reloc
);