2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
41 #include "nir/nir_to_tgsi_info.h"
42 #include "tgsi/tgsi_from_mesa.h"
44 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
47 cb
->buf
= CALLOC(1, 4 * num_dw
);
48 cb
->max_num_dw
= num_dw
;
51 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
56 void r600_add_atom(struct r600_context
*rctx
,
57 struct r600_atom
*atom
,
60 assert(id
< R600_NUM_ATOMS
);
61 assert(rctx
->atoms
[id
] == NULL
);
62 rctx
->atoms
[id
] = atom
;
66 void r600_init_atom(struct r600_context
*rctx
,
67 struct r600_atom
*atom
,
69 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
72 atom
->emit
= (void*)emit
;
73 atom
->num_dw
= num_dw
;
74 r600_add_atom(rctx
, atom
, id
);
77 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
79 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
82 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
84 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
85 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
86 unsigned alpha_ref
= a
->sx_alpha_ref
;
88 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
92 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
93 a
->sx_alpha_test_control
|
94 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
95 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
98 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
100 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
102 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
105 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
106 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
108 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
109 PIPE_BARRIER_SHADER_BUFFER
|
110 PIPE_BARRIER_TEXTURE
|
112 PIPE_BARRIER_STREAMOUT_BUFFER
|
113 PIPE_BARRIER_GLOBAL_BUFFER
)) {
114 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
|
115 R600_CONTEXT_INV_TEX_CACHE
;
118 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
120 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV
;
122 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
125 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
127 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
129 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
130 R600_CONTEXT_FLUSH_AND_INV_CB
|
131 R600_CONTEXT_FLUSH_AND_INV
|
132 R600_CONTEXT_WAIT_3D_IDLE
;
133 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
136 static unsigned r600_conv_pipe_prim(unsigned prim
)
138 static const unsigned prim_conv
[] = {
139 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
140 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
141 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
142 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
143 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
144 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
145 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
146 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
147 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
148 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
149 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
150 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
151 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
152 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
153 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
154 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
156 assert(prim
< ARRAY_SIZE(prim_conv
));
157 return prim_conv
[prim
];
160 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
162 static const int prim_conv
[] = {
163 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
164 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
165 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
166 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
167 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
168 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
169 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
170 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
171 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
172 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
173 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
174 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
175 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
176 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
177 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
178 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
180 assert(mode
< ARRAY_SIZE(prim_conv
));
182 return prim_conv
[mode
];
185 /* common state between evergreen and r600 */
187 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
188 struct r600_blend_state
*blend
, bool blend_disable
)
190 unsigned color_control
;
191 bool update_cb
= false;
193 rctx
->alpha_to_one
= blend
->alpha_to_one
;
194 rctx
->dual_src_blend
= blend
->dual_src_blend
;
196 if (!blend_disable
) {
197 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
198 color_control
= blend
->cb_color_control
;
200 /* Blending is disabled. */
201 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
202 color_control
= blend
->cb_color_control_no_blend
;
205 /* Update derived states. */
206 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
207 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
210 if (rctx
->b
.chip_class
<= R700
&&
211 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
212 rctx
->cb_misc_state
.cb_color_control
= color_control
;
215 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
216 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
220 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
222 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
223 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
224 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
228 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
230 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
231 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
234 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
238 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
241 static void r600_set_blend_color(struct pipe_context
*ctx
,
242 const struct pipe_blend_color
*state
)
244 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
246 rctx
->blend_color
.state
= *state
;
247 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
250 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
252 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
253 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
255 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
256 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
257 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
258 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
259 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
262 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
264 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
265 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
267 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
268 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
269 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
270 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
271 if (a
->last_draw_was_indirect
) {
272 a
->last_draw_was_indirect
= false;
273 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
277 static void r600_set_clip_state(struct pipe_context
*ctx
,
278 const struct pipe_clip_state
*state
)
280 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
282 rctx
->clip_state
.state
= *state
;
283 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
284 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
287 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
288 const struct r600_stencil_ref
*state
)
290 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
292 rctx
->stencil_ref
.state
= *state
;
293 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
296 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
298 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
299 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
301 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
302 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
303 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
304 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
305 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
306 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
307 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
308 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
309 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
312 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
313 const struct pipe_stencil_ref
*state
)
315 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
316 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
317 struct r600_stencil_ref ref
;
319 rctx
->stencil_ref
.pipe_state
= *state
;
324 ref
.ref_value
[0] = state
->ref_value
[0];
325 ref
.ref_value
[1] = state
->ref_value
[1];
326 ref
.valuemask
[0] = dsa
->valuemask
[0];
327 ref
.valuemask
[1] = dsa
->valuemask
[1];
328 ref
.writemask
[0] = dsa
->writemask
[0];
329 ref
.writemask
[1] = dsa
->writemask
[1];
331 r600_set_stencil_ref(ctx
, &ref
);
334 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
336 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
337 struct r600_dsa_state
*dsa
= state
;
338 struct r600_stencil_ref ref
;
341 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
345 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
347 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
348 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
349 ref
.valuemask
[0] = dsa
->valuemask
[0];
350 ref
.valuemask
[1] = dsa
->valuemask
[1];
351 ref
.writemask
[0] = dsa
->writemask
[0];
352 ref
.writemask
[1] = dsa
->writemask
[1];
353 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
354 rctx
->zwritemask
= dsa
->zwritemask
;
355 if (rctx
->b
.chip_class
>= EVERGREEN
) {
356 /* work around some issue when not writing to zbuffer
357 * we are having lockup on evergreen so do not enable
358 * hyperz when not writing zbuffer
360 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
364 r600_set_stencil_ref(ctx
, &ref
);
366 /* Update alphatest state. */
367 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
368 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
369 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
370 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
371 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
375 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
377 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
378 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
383 rctx
->rasterizer
= rs
;
385 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
387 if (rs
->offset_enable
&&
388 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
389 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
390 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
391 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
392 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
393 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
394 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
397 /* Update clip_misc_state. */
398 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
399 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
400 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
401 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
402 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
405 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
407 /* Re-emit PA_SC_LINE_STIPPLE. */
408 rctx
->last_primitive_type
= -1;
411 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
413 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
415 r600_release_command_buffer(&rs
->buffer
);
419 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
420 struct pipe_sampler_view
*state
)
422 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
424 if (view
->tex_resource
->gpu_address
&&
425 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
426 list_delinit(&view
->list
);
428 pipe_resource_reference(&state
->texture
, NULL
);
432 void r600_sampler_states_dirty(struct r600_context
*rctx
,
433 struct r600_sampler_states
*state
)
435 if (state
->dirty_mask
) {
436 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
437 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
440 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
441 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
442 r600_mark_atom_dirty(rctx
, &state
->atom
);
446 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
447 enum pipe_shader_type shader
,
449 unsigned count
, void **states
)
451 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
452 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
453 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
454 int seamless_cube_map
= -1;
456 /* This sets 1-bit for states with index >= count. */
457 uint32_t disable_mask
= ~((1ull << count
) - 1);
458 /* These are the new states set by this function. */
459 uint32_t new_mask
= 0;
461 assert(start
== 0); /* XXX fix below */
468 for (i
= 0; i
< count
; i
++) {
469 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
471 if (rstate
== dst
->states
.states
[i
]) {
476 if (rstate
->border_color_use
) {
477 dst
->states
.has_bordercolor_mask
|= 1 << i
;
479 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
481 seamless_cube_map
= rstate
->seamless_cube_map
;
485 disable_mask
|= 1 << i
;
489 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
490 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
492 dst
->states
.enabled_mask
&= ~disable_mask
;
493 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
494 dst
->states
.enabled_mask
|= new_mask
;
495 dst
->states
.dirty_mask
|= new_mask
;
496 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
498 r600_sampler_states_dirty(rctx
, &dst
->states
);
500 /* Seamless cubemap state. */
501 if (rctx
->b
.chip_class
<= R700
&&
502 seamless_cube_map
!= -1 &&
503 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
504 /* change in TA_CNTL_AUX need a pipeline flush */
505 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
506 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
507 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
511 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
516 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
518 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
519 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
521 if (rctx
->blend_state
.cso
== state
) {
522 ctx
->bind_blend_state(ctx
, NULL
);
525 r600_release_command_buffer(&blend
->buffer
);
526 r600_release_command_buffer(&blend
->buffer_no_blend
);
530 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
532 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
533 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
535 if (rctx
->dsa_state
.cso
== state
) {
536 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
539 r600_release_command_buffer(&dsa
->buffer
);
543 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
545 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
547 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
550 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
552 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
554 r600_resource_reference(&shader
->buffer
, NULL
);
558 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
560 if (rctx
->vertex_buffer_state
.dirty_mask
) {
561 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
562 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
563 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
567 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
568 unsigned start_slot
, unsigned count
,
569 const struct pipe_vertex_buffer
*input
)
571 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
572 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
573 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
575 uint32_t disable_mask
= 0;
576 /* These are the new buffers set by this function. */
577 uint32_t new_buffer_mask
= 0;
579 /* Set vertex buffers. */
581 for (i
= 0; i
< count
; i
++) {
582 if ((input
[i
].buffer
.resource
!= vb
[i
].buffer
.resource
) ||
583 (vb
[i
].stride
!= input
[i
].stride
) ||
584 (vb
[i
].buffer_offset
!= input
[i
].buffer_offset
) ||
585 (vb
[i
].is_user_buffer
!= input
[i
].is_user_buffer
)) {
586 if (input
[i
].buffer
.resource
) {
587 vb
[i
].stride
= input
[i
].stride
;
588 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
589 pipe_resource_reference(&vb
[i
].buffer
.resource
, input
[i
].buffer
.resource
);
590 new_buffer_mask
|= 1 << i
;
591 r600_context_add_resource_size(ctx
, input
[i
].buffer
.resource
);
593 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
594 disable_mask
|= 1 << i
;
599 for (i
= 0; i
< count
; i
++) {
600 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
602 disable_mask
= ((1ull << count
) - 1);
605 disable_mask
<<= start_slot
;
606 new_buffer_mask
<<= start_slot
;
608 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
609 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
610 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
611 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
613 r600_vertex_buffers_dirty(rctx
);
616 void r600_sampler_views_dirty(struct r600_context
*rctx
,
617 struct r600_samplerview_state
*state
)
619 if (state
->dirty_mask
) {
620 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
621 util_bitcount(state
->dirty_mask
);
622 r600_mark_atom_dirty(rctx
, &state
->atom
);
626 static void r600_set_sampler_views(struct pipe_context
*pipe
,
627 enum pipe_shader_type shader
,
628 unsigned start
, unsigned count
,
629 struct pipe_sampler_view
**views
)
631 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
632 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
633 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
634 uint32_t dirty_sampler_states_mask
= 0;
636 /* This sets 1-bit for textures with index >= count. */
637 uint32_t disable_mask
= ~((1ull << count
) - 1);
638 /* These are the new textures set by this function. */
639 uint32_t new_mask
= 0;
641 /* Set textures with index >= count to NULL. */
642 uint32_t remaining_mask
;
644 assert(start
== 0); /* XXX fix below */
651 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
653 while (remaining_mask
) {
654 i
= u_bit_scan(&remaining_mask
);
655 assert(dst
->views
.views
[i
]);
657 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
660 for (i
= 0; i
< count
; i
++) {
661 if (rviews
[i
] == dst
->views
.views
[i
]) {
666 struct r600_texture
*rtex
=
667 (struct r600_texture
*)rviews
[i
]->base
.texture
;
668 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
670 if (!is_buffer
&& rtex
->db_compatible
) {
671 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
673 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
676 /* Track compressed colorbuffers. */
677 if (!is_buffer
&& rtex
->cmask
.size
) {
678 dst
->views
.compressed_colortex_mask
|= 1 << i
;
680 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
683 /* Changing from array to non-arrays textures and vice versa requires
684 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
685 if (rctx
->b
.chip_class
<= R700
&&
686 (dst
->states
.enabled_mask
& (1 << i
)) &&
687 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
688 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
689 dirty_sampler_states_mask
|= 1 << i
;
692 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
694 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
696 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
697 disable_mask
|= 1 << i
;
701 dst
->views
.enabled_mask
&= ~disable_mask
;
702 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
703 dst
->views
.enabled_mask
|= new_mask
;
704 dst
->views
.dirty_mask
|= new_mask
;
705 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
706 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
707 dst
->views
.dirty_buffer_constants
= TRUE
;
708 r600_sampler_views_dirty(rctx
, &dst
->views
);
710 if (dirty_sampler_states_mask
) {
711 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
712 r600_sampler_states_dirty(rctx
, &dst
->states
);
716 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
718 uint32_t mask
= views
->enabled_mask
;
721 unsigned i
= u_bit_scan(&mask
);
722 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
724 if (res
&& res
->target
!= PIPE_BUFFER
) {
725 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
727 if (rtex
->cmask
.size
) {
728 views
->compressed_colortex_mask
|= 1 << i
;
730 views
->compressed_colortex_mask
&= ~(1 << i
);
736 static int r600_get_hw_atomic_count(const struct pipe_context
*ctx
,
737 enum pipe_shader_type shader
)
739 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
742 case PIPE_SHADER_FRAGMENT
:
743 case PIPE_SHADER_COMPUTE
:
746 case PIPE_SHADER_VERTEX
:
747 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
749 case PIPE_SHADER_GEOMETRY
:
750 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
751 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
753 case PIPE_SHADER_TESS_EVAL
:
754 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
755 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
756 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0);
758 case PIPE_SHADER_TESS_CTRL
:
759 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
760 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
761 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0) +
762 rctx
->tes_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
768 static void r600_update_compressed_colortex_mask_images(struct r600_image_state
*images
)
770 uint32_t mask
= images
->enabled_mask
;
773 unsigned i
= u_bit_scan(&mask
);
774 struct pipe_resource
*res
= images
->views
[i
].base
.resource
;
776 if (res
&& res
->target
!= PIPE_BUFFER
) {
777 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
779 if (rtex
->cmask
.size
) {
780 images
->compressed_colortex_mask
|= 1 << i
;
782 images
->compressed_colortex_mask
&= ~(1 << i
);
788 /* Compute the key for the hw shader variant */
789 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
790 const struct r600_pipe_shader_selector
*sel
,
791 union r600_shader_key
*key
)
793 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
794 memset(key
, 0, sizeof(*key
));
797 case PIPE_SHADER_VERTEX
: {
798 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
800 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
802 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
803 key
->vs
.as_gs_a
= true;
804 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
806 key
->vs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_VERTEX
);
809 case PIPE_SHADER_GEOMETRY
:
810 key
->gs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_GEOMETRY
);
811 key
->gs
.tri_strip_adj_fix
= rctx
->gs_tri_strip_adj_fix
;
813 case PIPE_SHADER_FRAGMENT
: {
814 if (rctx
->ps_shader
->info
.images_declared
)
815 key
->ps
.image_size_const_offset
= util_last_bit(rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.enabled_mask
);
816 key
->ps
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_FRAGMENT
);
817 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
818 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
819 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
820 !rctx
->framebuffer
.cb0_is_integer
;
821 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
822 key
->ps
.apply_sample_id_mask
= (rctx
->ps_iter_samples
> 1) || !rctx
->rasterizer
->multisample_enable
;
823 /* Dual-source blending only makes sense with nr_cbufs == 1. */
824 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
825 key
->ps
.nr_cbufs
= 2;
828 case PIPE_SHADER_TESS_EVAL
:
829 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
830 key
->tes
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_EVAL
);
832 case PIPE_SHADER_TESS_CTRL
:
833 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
834 key
->tcs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_CTRL
);
836 case PIPE_SHADER_COMPUTE
:
843 /* Select the hw shader variant depending on the current state.
844 * (*dirty) is set to 1 if current variant was changed */
845 int r600_shader_select(struct pipe_context
*ctx
,
846 struct r600_pipe_shader_selector
* sel
,
849 union r600_shader_key key
;
850 struct r600_pipe_shader
* shader
= NULL
;
853 r600_shader_selector_key(ctx
, sel
, &key
);
855 /* Check if we don't need to change anything.
856 * This path is also used for most shaders that don't need multiple
857 * variants, it will cost just a computation of the key and this
859 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
863 /* lookup if we have other variants in the list */
864 if (sel
->num_shaders
> 1) {
865 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
867 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
873 p
->next_variant
= c
->next_variant
;
878 if (unlikely(!shader
)) {
879 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
880 shader
->selector
= sel
;
882 r
= r600_pipe_shader_create(ctx
, shader
, key
);
884 R600_ERR("Failed to build shader variant (type=%u) %d\n",
891 /* We don't know the value of nr_ps_max_color_exports until we built
892 * at least one variant, so we may need to recompute the key after
893 * building first variant. */
894 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
895 sel
->num_shaders
== 0) {
896 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
897 r600_shader_selector_key(ctx
, sel
, &key
);
900 memcpy(&shader
->key
, &key
, sizeof(key
));
907 shader
->next_variant
= sel
->current
;
908 sel
->current
= shader
;
913 struct r600_pipe_shader_selector
*r600_create_shader_state_tokens(struct pipe_context
*ctx
,
914 const void *prog
, enum pipe_shader_ir ir
,
915 unsigned pipe_shader_type
)
917 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
919 sel
->type
= pipe_shader_type
;
920 if (ir
== PIPE_SHADER_IR_TGSI
) {
921 sel
->tokens
= tgsi_dup_tokens((const struct tgsi_token
*)prog
);
922 tgsi_scan_shader(sel
->tokens
, &sel
->info
);
923 } else if (ir
== PIPE_SHADER_IR_NIR
){
924 sel
->nir
= nir_shader_clone(NULL
, (const nir_shader
*)prog
);
925 nir_tgsi_scan_shader(sel
->nir
, &sel
->info
, true);
930 static void *r600_create_shader_state(struct pipe_context
*ctx
,
931 const struct pipe_shader_state
*state
,
932 unsigned pipe_shader_type
)
935 struct r600_pipe_shader_selector
*sel
;
937 if (state
->type
== PIPE_SHADER_IR_TGSI
)
938 sel
= r600_create_shader_state_tokens(ctx
, state
->tokens
, state
->type
, pipe_shader_type
);
939 else if (state
->type
== PIPE_SHADER_IR_NIR
) {
940 sel
= r600_create_shader_state_tokens(ctx
, state
->ir
.nir
, state
->type
, pipe_shader_type
);
942 assert(0 && "Unknown shader type\n");
944 sel
->ir_type
= state
->type
;
945 sel
->so
= state
->stream_output
;
947 switch (pipe_shader_type
) {
948 case PIPE_SHADER_GEOMETRY
:
949 sel
->gs_output_prim
=
950 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
951 sel
->gs_max_out_vertices
=
952 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
953 sel
->gs_num_invocations
=
954 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
956 case PIPE_SHADER_VERTEX
:
957 case PIPE_SHADER_TESS_CTRL
:
958 sel
->lds_patch_outputs_written_mask
= 0;
959 sel
->lds_outputs_written_mask
= 0;
961 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
962 unsigned name
= sel
->info
.output_semantic_name
[i
];
963 unsigned index
= sel
->info
.output_semantic_index
[i
];
966 case TGSI_SEMANTIC_TESSINNER
:
967 case TGSI_SEMANTIC_TESSOUTER
:
968 case TGSI_SEMANTIC_PATCH
:
969 sel
->lds_patch_outputs_written_mask
|=
970 1ull << r600_get_lds_unique_index(name
, index
);
973 sel
->lds_outputs_written_mask
|=
974 1ull << r600_get_lds_unique_index(name
, index
);
985 static void *r600_create_ps_state(struct pipe_context
*ctx
,
986 const struct pipe_shader_state
*state
)
988 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
991 static void *r600_create_vs_state(struct pipe_context
*ctx
,
992 const struct pipe_shader_state
*state
)
994 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
997 static void *r600_create_gs_state(struct pipe_context
*ctx
,
998 const struct pipe_shader_state
*state
)
1000 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
1003 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
1004 const struct pipe_shader_state
*state
)
1006 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
1009 static void *r600_create_tes_state(struct pipe_context
*ctx
,
1010 const struct pipe_shader_state
*state
)
1012 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
1015 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
1017 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1020 state
= rctx
->dummy_pixel_shader
;
1022 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
1025 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
1027 if (rctx
->gs_shader
)
1028 return &rctx
->gs_shader
->info
;
1029 else if (rctx
->tes_shader
)
1030 return &rctx
->tes_shader
->info
;
1031 else if (rctx
->vs_shader
)
1032 return &rctx
->vs_shader
->info
;
1037 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1039 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1041 if (!state
|| rctx
->vs_shader
== state
)
1044 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
1045 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1047 if (rctx
->vs_shader
->so
.num_outputs
)
1048 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
1051 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1053 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1055 if (state
== rctx
->gs_shader
)
1058 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
1059 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1064 if (rctx
->gs_shader
->so
.num_outputs
)
1065 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
1068 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1070 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1072 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
1075 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1077 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1079 if (state
== rctx
->tes_shader
)
1082 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
1083 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1088 if (rctx
->tes_shader
->so
.num_outputs
)
1089 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
1092 void r600_delete_shader_selector(struct pipe_context
*ctx
,
1093 struct r600_pipe_shader_selector
*sel
)
1095 struct r600_pipe_shader
*p
= sel
->current
, *c
;
1097 c
= p
->next_variant
;
1098 r600_pipe_shader_destroy(ctx
, p
);
1103 if (sel
->ir_type
== PIPE_SHADER_IR_TGSI
) {
1105 /* We might have converted the TGSI shader to a NIR shader */
1107 ralloc_free(sel
->nir
);
1109 else if (sel
->ir_type
== PIPE_SHADER_IR_NIR
)
1110 ralloc_free(sel
->nir
);
1115 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
1117 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1118 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1120 if (rctx
->ps_shader
== sel
) {
1121 rctx
->ps_shader
= NULL
;
1124 r600_delete_shader_selector(ctx
, sel
);
1127 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1129 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1130 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1132 if (rctx
->vs_shader
== sel
) {
1133 rctx
->vs_shader
= NULL
;
1136 r600_delete_shader_selector(ctx
, sel
);
1140 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1142 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1143 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1145 if (rctx
->gs_shader
== sel
) {
1146 rctx
->gs_shader
= NULL
;
1149 r600_delete_shader_selector(ctx
, sel
);
1152 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1154 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1155 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1157 if (rctx
->tcs_shader
== sel
) {
1158 rctx
->tcs_shader
= NULL
;
1161 r600_delete_shader_selector(ctx
, sel
);
1164 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1166 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1167 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1169 if (rctx
->tes_shader
== sel
) {
1170 rctx
->tes_shader
= NULL
;
1173 r600_delete_shader_selector(ctx
, sel
);
1176 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1178 if (state
->dirty_mask
) {
1179 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1180 : util_bitcount(state
->dirty_mask
)*19;
1181 r600_mark_atom_dirty(rctx
, &state
->atom
);
1185 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1186 enum pipe_shader_type shader
, uint index
,
1187 const struct pipe_constant_buffer
*input
)
1189 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1190 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1191 struct pipe_constant_buffer
*cb
;
1194 /* Note that the gallium frontend can unbind constant buffers by
1195 * passing NULL here.
1197 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1198 state
->enabled_mask
&= ~(1 << index
);
1199 state
->dirty_mask
&= ~(1 << index
);
1200 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1204 cb
= &state
->cb
[index
];
1205 cb
->buffer_size
= input
->buffer_size
;
1207 ptr
= input
->user_buffer
;
1210 /* Upload the user buffer. */
1211 if (R600_BIG_ENDIAN
) {
1213 unsigned i
, size
= input
->buffer_size
;
1215 if (!(tmpPtr
= malloc(size
))) {
1216 R600_ERR("Failed to allocate BE swap buffer.\n");
1220 for (i
= 0; i
< size
/ 4; ++i
) {
1221 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1224 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1225 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1228 u_upload_data(ctx
->stream_uploader
, 0,
1229 input
->buffer_size
, 256, ptr
,
1230 &cb
->buffer_offset
, &cb
->buffer
);
1232 /* account it in gtt */
1233 rctx
->b
.gtt
+= input
->buffer_size
;
1235 /* Setup the hw buffer. */
1236 cb
->buffer_offset
= input
->buffer_offset
;
1237 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1238 r600_context_add_resource_size(ctx
, input
->buffer
);
1241 state
->enabled_mask
|= 1 << index
;
1242 state
->dirty_mask
|= 1 << index
;
1243 r600_constant_buffers_dirty(rctx
, state
);
1246 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1248 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1250 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1253 rctx
->sample_mask
.sample_mask
= sample_mask
;
1254 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1257 void r600_update_driver_const_buffers(struct r600_context
*rctx
, bool compute_only
)
1261 struct pipe_constant_buffer cb
;
1264 start
= compute_only
? PIPE_SHADER_COMPUTE
: 0;
1265 end
= compute_only
? PIPE_SHADER_TYPES
: PIPE_SHADER_COMPUTE
;
1267 for (sh
= start
; sh
< end
; sh
++) {
1268 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1269 if (!info
->vs_ucp_dirty
&&
1270 !info
->texture_const_dirty
&&
1271 !info
->ps_sample_pos_dirty
&&
1272 !info
->tcs_default_levels_dirty
&&
1273 !info
->cs_block_grid_size_dirty
)
1276 ptr
= info
->constants
;
1277 size
= info
->alloc_size
;
1278 if (info
->vs_ucp_dirty
) {
1279 assert(sh
== PIPE_SHADER_VERTEX
);
1281 ptr
= rctx
->clip_state
.state
.ucp
;
1282 size
= R600_UCP_SIZE
;
1284 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1286 info
->vs_ucp_dirty
= false;
1289 else if (info
->ps_sample_pos_dirty
) {
1290 assert(sh
== PIPE_SHADER_FRAGMENT
);
1292 ptr
= rctx
->sample_positions
;
1293 size
= R600_UCP_SIZE
;
1295 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1297 info
->ps_sample_pos_dirty
= false;
1300 else if (info
->cs_block_grid_size_dirty
) {
1301 assert(sh
== PIPE_SHADER_COMPUTE
);
1303 ptr
= rctx
->cs_block_grid_sizes
;
1304 size
= R600_CS_BLOCK_GRID_SIZE
;
1306 memcpy(ptr
, rctx
->cs_block_grid_sizes
, R600_CS_BLOCK_GRID_SIZE
);
1308 info
->cs_block_grid_size_dirty
= false;
1311 else if (info
->tcs_default_levels_dirty
) {
1313 * We'd only really need this for default tcs shader.
1315 assert(sh
== PIPE_SHADER_TESS_CTRL
);
1317 ptr
= rctx
->tess_state
;
1318 size
= R600_TCS_DEFAULT_LEVELS_SIZE
;
1320 memcpy(ptr
, rctx
->tess_state
, R600_TCS_DEFAULT_LEVELS_SIZE
);
1322 info
->tcs_default_levels_dirty
= false;
1325 if (info
->texture_const_dirty
) {
1328 if (sh
== PIPE_SHADER_VERTEX
)
1329 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1330 if (sh
== PIPE_SHADER_FRAGMENT
)
1331 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1332 if (sh
== PIPE_SHADER_COMPUTE
)
1333 memcpy(ptr
, rctx
->cs_block_grid_sizes
, R600_CS_BLOCK_GRID_SIZE
);
1334 if (sh
== PIPE_SHADER_TESS_CTRL
)
1335 memcpy(ptr
, rctx
->tess_state
, R600_TCS_DEFAULT_LEVELS_SIZE
);
1337 info
->texture_const_dirty
= false;
1340 cb
.user_buffer
= ptr
;
1341 cb
.buffer_offset
= 0;
1342 cb
.buffer_size
= size
;
1343 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1344 pipe_resource_reference(&cb
.buffer
, NULL
);
1348 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1349 unsigned array_size
, uint32_t *base_offset
)
1351 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1352 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1353 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1354 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1356 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1357 info
->texture_const_dirty
= true;
1358 *base_offset
= R600_UCP_SIZE
;
1359 return info
->constants
;
1362 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1363 * doesn't require full swizzles it does need masking and setting alpha
1364 * to one, so we setup a set of 5 constants with the masks + alpha value
1365 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1366 * then OR the alpha with the value given here.
1367 * We use a 6th constant to store the txq buffer size in
1368 * we use 7th slot for number of cube layers in a cube map array.
1370 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1372 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1374 uint32_t array_size
;
1376 uint32_t *constants
;
1377 uint32_t base_offset
;
1378 if (!samplers
->views
.dirty_buffer_constants
)
1381 samplers
->views
.dirty_buffer_constants
= FALSE
;
1383 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1384 array_size
= bits
* 8 * sizeof(uint32_t);
1386 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1388 for (i
= 0; i
< bits
; i
++) {
1389 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1390 int offset
= (base_offset
/ 4) + i
* 8;
1391 const struct util_format_description
*desc
;
1392 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1394 for (j
= 0; j
< 4; j
++)
1395 if (j
< desc
->nr_channels
)
1396 constants
[offset
+j
] = 0xffffffff;
1398 constants
[offset
+j
] = 0x0;
1399 if (desc
->nr_channels
< 4) {
1400 if (desc
->channel
[0].pure_integer
)
1401 constants
[offset
+4] = 1;
1403 constants
[offset
+4] = fui(1.0);
1405 constants
[offset
+ 4] = 0;
1407 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.u
.buf
.size
/
1408 util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1409 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1415 /* On evergreen we store one value
1416 * 1. number of cube layers in a cube map array.
1418 void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1420 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1421 struct r600_image_state
*images
= NULL
;
1422 int bits
, sview_bits
, img_bits
;
1423 uint32_t array_size
;
1425 uint32_t *constants
;
1426 uint32_t base_offset
;
1428 if (shader_type
== PIPE_SHADER_FRAGMENT
) {
1429 images
= &rctx
->fragment_images
;
1430 } else if (shader_type
== PIPE_SHADER_COMPUTE
) {
1431 images
= &rctx
->compute_images
;
1434 if (!samplers
->views
.dirty_buffer_constants
&&
1435 !(images
&& images
->dirty_buffer_constants
))
1439 images
->dirty_buffer_constants
= FALSE
;
1440 samplers
->views
.dirty_buffer_constants
= FALSE
;
1442 bits
= sview_bits
= util_last_bit(samplers
->views
.enabled_mask
);
1444 bits
+= util_last_bit(images
->enabled_mask
);
1447 array_size
= bits
* sizeof(uint32_t);
1449 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1452 for (i
= 0; i
< sview_bits
; i
++) {
1453 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1454 uint32_t offset
= (base_offset
/ 4) + i
;
1455 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1459 for (i
= sview_bits
; i
< img_bits
; i
++) {
1460 int idx
= i
- sview_bits
;
1461 if (images
->enabled_mask
& (1 << idx
)) {
1462 uint32_t offset
= (base_offset
/ 4) + i
;
1463 constants
[offset
] = images
->views
[idx
].base
.resource
->array_size
/ 6;
1469 /* set sample xy locations as array of fragment shader constants */
1470 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1472 struct pipe_context
*ctx
= &rctx
->b
.b
;
1474 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1475 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1477 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1478 for (unsigned i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1479 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1480 /* Also fill in center-zeroed positions used for interpolateAtSample */
1481 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1482 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1485 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1488 static void update_shader_atom(struct pipe_context
*ctx
,
1489 struct r600_shader_state
*state
,
1490 struct r600_pipe_shader
*shader
)
1492 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1494 state
->shader
= shader
;
1496 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1497 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1499 state
->atom
.num_dw
= 0;
1501 r600_mark_atom_dirty(rctx
, &state
->atom
);
1504 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1506 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1507 rctx
->shader_stages
.geom_enable
= enable
;
1508 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1511 if (rctx
->gs_rings
.enable
!= enable
) {
1512 rctx
->gs_rings
.enable
= enable
;
1513 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1515 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1516 unsigned size
= 0x1C000;
1517 rctx
->gs_rings
.esgs_ring
.buffer
=
1518 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1519 PIPE_USAGE_DEFAULT
, size
);
1520 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1524 rctx
->gs_rings
.gsvs_ring
.buffer
=
1525 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1526 PIPE_USAGE_DEFAULT
, size
);
1527 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1531 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1532 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1533 if (rctx
->tes_shader
) {
1534 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1535 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1537 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1538 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1541 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1542 R600_GS_RING_CONST_BUFFER
, NULL
);
1543 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1544 R600_GS_RING_CONST_BUFFER
, NULL
);
1545 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1546 R600_GS_RING_CONST_BUFFER
, NULL
);
1551 static void r600_update_clip_state(struct r600_context
*rctx
,
1552 struct r600_pipe_shader
*current
)
1554 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1555 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1556 current
->shader
.cull_dist_write
!= rctx
->clip_misc_state
.cull_dist_write
||
1557 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1558 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1559 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1560 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1561 rctx
->clip_misc_state
.cull_dist_write
= current
->shader
.cull_dist_write
;
1562 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1563 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1564 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1568 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1570 struct ureg_src const0
, const1
;
1571 struct ureg_dst tessouter
, tessinner
;
1572 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1575 return; /* if we get here, we're screwed */
1577 assert(!rctx
->fixed_func_tcs_shader
);
1579 ureg_DECL_constant2D(ureg
, 0, 1, R600_BUFFER_INFO_CONST_BUFFER
);
1580 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 0),
1581 R600_BUFFER_INFO_CONST_BUFFER
);
1582 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 1),
1583 R600_BUFFER_INFO_CONST_BUFFER
);
1585 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1586 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1588 ureg_MOV(ureg
, tessouter
, const0
);
1589 ureg_MOV(ureg
, tessinner
, const1
);
1592 rctx
->fixed_func_tcs_shader
=
1593 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1596 void r600_update_compressed_resource_state(struct r600_context
*rctx
, bool compute_only
)
1601 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1602 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1603 rctx
->b
.last_compressed_colortex_counter
= counter
;
1606 r600_update_compressed_colortex_mask(&rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
);
1608 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1609 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1613 r600_update_compressed_colortex_mask_images(&rctx
->fragment_images
);
1614 r600_update_compressed_colortex_mask_images(&rctx
->compute_images
);
1617 /* Decompress textures if needed. */
1618 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1619 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1622 if (i
!= PIPE_SHADER_COMPUTE
)
1624 if (views
->compressed_depthtex_mask
) {
1625 r600_decompress_depth_textures(rctx
, views
);
1627 if (views
->compressed_colortex_mask
) {
1628 r600_decompress_color_textures(rctx
, views
);
1633 struct r600_image_state
*istate
;
1635 if (!compute_only
) {
1636 istate
= &rctx
->fragment_images
;
1637 if (istate
->compressed_depthtex_mask
)
1638 r600_decompress_depth_images(rctx
, istate
);
1639 if (istate
->compressed_colortex_mask
)
1640 r600_decompress_color_images(rctx
, istate
);
1643 istate
= &rctx
->compute_images
;
1644 if (istate
->compressed_depthtex_mask
)
1645 r600_decompress_depth_images(rctx
, istate
);
1646 if (istate
->compressed_colortex_mask
)
1647 r600_decompress_color_images(rctx
, istate
);
1651 /* update MEM_SCRATCH buffers if needed */
1652 void r600_setup_scratch_area_for_shader(struct r600_context
*rctx
,
1653 struct r600_pipe_shader
*shader
, struct r600_scratch_buffer
*scratch
,
1654 unsigned ring_base_reg
, unsigned item_size_reg
, unsigned ring_size_reg
)
1656 unsigned num_ses
= rctx
->screen
->b
.info
.max_se
;
1657 unsigned num_pipes
= rctx
->screen
->b
.info
.r600_max_quad_pipes
;
1658 unsigned nthreads
= 128;
1660 unsigned itemsize
= shader
->scratch_space_needed
* 4;
1661 unsigned size
= align(itemsize
* nthreads
* num_pipes
* num_ses
* 4, 256);
1663 if (scratch
->dirty
||
1664 unlikely(shader
->scratch_space_needed
!= scratch
->item_size
||
1665 size
> scratch
->size
)) {
1666 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
1668 scratch
->dirty
= false;
1670 if (size
> scratch
->size
) {
1671 // Release prior one if any
1672 if (scratch
->buffer
) {
1673 pipe_resource_reference((struct pipe_resource
**)&scratch
->buffer
, NULL
);
1676 scratch
->buffer
= (struct r600_resource
*)pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1677 PIPE_USAGE_DEFAULT
, size
);
1678 if (scratch
->buffer
) {
1679 scratch
->size
= size
;
1683 scratch
->item_size
= shader
->scratch_space_needed
;
1685 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1686 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1687 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1689 // multi-SE chips need programming per SE
1690 for (unsigned se
= 0; se
< num_ses
; se
++) {
1691 struct r600_resource
*rbuffer
= scratch
->buffer
;
1692 unsigned size_per_se
= size
/ num_ses
;
1694 // Direct to particular SE
1696 radeon_set_config_reg(cs
, EG_0802C_GRBM_GFX_INDEX
,
1697 S_0802C_INSTANCE_INDEX(0) |
1698 S_0802C_SE_INDEX(se
) |
1699 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1700 S_0802C_SE_BROADCAST_WRITES(0));
1703 radeon_set_config_reg(cs
, ring_base_reg
, (rbuffer
->gpu_address
+ size_per_se
* se
) >> 8);
1704 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1705 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1706 RADEON_USAGE_READWRITE
,
1707 RADEON_PRIO_SCRATCH_BUFFER
));
1708 radeon_set_context_reg(cs
, item_size_reg
, itemsize
);
1709 radeon_set_config_reg(cs
, ring_size_reg
, size_per_se
>> 8);
1712 // Restore broadcast mode
1714 radeon_set_config_reg(cs
, EG_0802C_GRBM_GFX_INDEX
,
1715 S_0802C_INSTANCE_INDEX(0) |
1716 S_0802C_SE_INDEX(0) |
1717 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1718 S_0802C_SE_BROADCAST_WRITES(1));
1721 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1722 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1723 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1727 void r600_setup_scratch_buffers(struct r600_context
*rctx
) {
1728 static const struct {
1732 } regs
[R600_NUM_HW_STAGES
] = {
1733 [R600_HW_STAGE_PS
] = { R_008C68_SQ_PSTMP_RING_BASE
, R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, R_008C6C_SQ_PSTMP_RING_SIZE
},
1734 [R600_HW_STAGE_VS
] = { R_008C60_SQ_VSTMP_RING_BASE
, R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, R_008C64_SQ_VSTMP_RING_SIZE
},
1735 [R600_HW_STAGE_GS
] = { R_008C58_SQ_GSTMP_RING_BASE
, R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, R_008C5C_SQ_GSTMP_RING_SIZE
},
1736 [R600_HW_STAGE_ES
] = { R_008C50_SQ_ESTMP_RING_BASE
, R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, R_008C54_SQ_ESTMP_RING_SIZE
}
1739 for (unsigned i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
1740 struct r600_pipe_shader
*stage
= rctx
->hw_shader_stages
[i
].shader
;
1742 if (stage
&& unlikely(stage
->scratch_space_needed
)) {
1743 r600_setup_scratch_area_for_shader(rctx
, stage
,
1744 &rctx
->scratch_buffers
[i
], regs
[i
].ring_base
, regs
[i
].item_size
, regs
[i
].ring_size
);
1749 #define SELECT_SHADER_OR_FAIL(x) do { \
1750 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1751 if (unlikely(!rctx->x##_shader->current)) \
1755 #define UPDATE_SHADER(hw, sw) do { \
1756 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1757 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1760 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1761 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1762 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1763 clip_so_current = rctx->sw##_shader->current; \
1767 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1768 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1769 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1770 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1771 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1775 #define SET_NULL_SHADER(hw) do { \
1776 if (rctx->hw_shader_stages[(hw)].shader) \
1777 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1780 static bool r600_update_derived_state(struct r600_context
*rctx
)
1782 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1783 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1784 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1786 bool need_buf_const
;
1787 struct r600_pipe_shader
*clip_so_current
= NULL
;
1789 if (!rctx
->blitter
->running
)
1790 r600_update_compressed_resource_state(rctx
, false);
1792 SELECT_SHADER_OR_FAIL(ps
);
1794 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1796 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1798 if (rctx
->gs_shader
)
1799 SELECT_SHADER_OR_FAIL(gs
);
1802 if (rctx
->tcs_shader
) {
1803 SELECT_SHADER_OR_FAIL(tcs
);
1805 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1806 } else if (rctx
->tes_shader
) {
1807 if (!rctx
->fixed_func_tcs_shader
) {
1808 r600_generate_fixed_func_tcs(rctx
);
1809 if (!rctx
->fixed_func_tcs_shader
)
1813 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1815 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1817 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1819 if (rctx
->tes_shader
) {
1820 SELECT_SHADER_OR_FAIL(tes
);
1823 SELECT_SHADER_OR_FAIL(vs
);
1825 if (rctx
->gs_shader
) {
1826 if (!rctx
->shader_stages
.geom_enable
) {
1827 rctx
->shader_stages
.geom_enable
= true;
1828 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1831 /* gs_shader provides GS and VS (copy shader) */
1832 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1834 /* vs_shader is used as ES */
1836 if (rctx
->tes_shader
) {
1837 /* VS goes to LS, TES goes to ES */
1838 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1839 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1841 /* vs_shader is used as ES */
1842 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1843 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1846 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1847 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1848 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1849 rctx
->shader_stages
.geom_enable
= false;
1850 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1853 if (rctx
->tes_shader
) {
1854 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1855 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1856 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1858 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1859 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1864 * XXX: I believe there's some fatal flaw in the dirty state logic when
1865 * enabling/disabling tes.
1866 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1867 * it will therefore overwrite the VS slots. If it now gets disabled,
1868 * the VS needs to rebind all buffer/resource/sampler slots - not only
1869 * has TES overwritten the corresponding slots, but when the VS was
1870 * operating as LS the things with correpsonding dirty bits got bound
1871 * to LS slots and won't reflect what is dirty as VS stage even if the
1872 * TES didn't overwrite it. The story for re-enabled TES is similar.
1873 * In any case, we're not allowed to submit any TES state when
1874 * TES is disabled (the gallium frontend may not do this but this looks
1875 * like an optimization to me, not something which can be relied on).
1878 /* Update clip misc state. */
1879 if (clip_so_current
) {
1880 r600_update_clip_state(rctx
, clip_so_current
);
1881 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1884 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1885 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1886 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1888 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
||
1889 rctx
->cb_misc_state
.ps_color_export_mask
!= rctx
->ps_shader
->current
->ps_color_export_mask
) {
1890 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1891 rctx
->cb_misc_state
.ps_color_export_mask
= rctx
->ps_shader
->current
->ps_color_export_mask
;
1892 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1895 if (rctx
->b
.chip_class
<= R700
) {
1896 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1898 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1899 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1900 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1904 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1905 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1906 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1908 if (rctx
->b
.chip_class
>= EVERGREEN
)
1909 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1911 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1914 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1916 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1918 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1919 evergreen_update_db_shader_control(rctx
);
1921 r600_update_db_shader_control(rctx
);
1924 /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */
1925 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1926 evergreen_setup_scratch_buffers(rctx
);
1928 r600_setup_scratch_buffers(rctx
);
1931 /* on R600 we stuff masks + txq info into one constant buffer */
1932 /* on evergreen we only need a txq info one */
1933 if (rctx
->ps_shader
) {
1934 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1935 if (need_buf_const
) {
1936 if (rctx
->b
.chip_class
< EVERGREEN
)
1937 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1939 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1943 if (rctx
->vs_shader
) {
1944 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1945 if (need_buf_const
) {
1946 if (rctx
->b
.chip_class
< EVERGREEN
)
1947 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1949 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1953 if (rctx
->gs_shader
) {
1954 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1955 if (need_buf_const
) {
1956 if (rctx
->b
.chip_class
< EVERGREEN
)
1957 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1959 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1963 if (rctx
->tes_shader
) {
1964 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1965 need_buf_const
= rctx
->tes_shader
->current
->shader
.uses_tex_buffers
||
1966 rctx
->tes_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1967 if (need_buf_const
) {
1968 eg_setup_buffer_constants(rctx
, PIPE_SHADER_TESS_EVAL
);
1970 if (rctx
->tcs_shader
) {
1971 need_buf_const
= rctx
->tcs_shader
->current
->shader
.uses_tex_buffers
||
1972 rctx
->tcs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1973 if (need_buf_const
) {
1974 eg_setup_buffer_constants(rctx
, PIPE_SHADER_TESS_CTRL
);
1979 r600_update_driver_const_buffers(rctx
, false);
1981 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1982 if (!r600_adjust_gprs(rctx
)) {
1983 /* discard rendering */
1988 if (rctx
->b
.chip_class
== EVERGREEN
) {
1989 if (!evergreen_adjust_gprs(rctx
)) {
1990 /* discard rendering */
1995 blend_disable
= (rctx
->dual_src_blend
&&
1996 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1998 if (blend_disable
!= rctx
->force_blend_disable
) {
1999 rctx
->force_blend_disable
= blend_disable
;
2000 r600_bind_blend_state_internal(rctx
,
2001 rctx
->blend_state
.cso
,
2008 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2010 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2011 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
2013 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
2014 state
->pa_cl_clip_cntl
|
2015 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
2016 S_028810_CLIP_DISABLE(state
->clip_disable
));
2017 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
2018 state
->pa_cl_vs_out_cntl
|
2019 (state
->clip_plane_enable
& state
->clip_dist_write
) |
2020 (state
->cull_dist_write
<< 8));
2021 /* reuse needs to be set off if we write oViewport */
2022 if (rctx
->b
.chip_class
>= EVERGREEN
)
2023 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
2024 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
2027 /* rast_prim is the primitive type after GS. */
2028 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
2030 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2031 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
2033 /* Skip this if not rendering lines. */
2034 if (rast_prim
!= PIPE_PRIM_LINES
&&
2035 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
2036 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
2037 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
2038 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
2041 if (rast_prim
== rctx
->last_rast_prim
)
2044 /* For lines, reset the stipple pattern at each primitive. Otherwise,
2045 * reset the stipple pattern at each packet (line strips, line loops).
2047 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
2048 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
2049 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
2050 rctx
->last_rast_prim
= rast_prim
;
2053 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
2055 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2056 struct pipe_resource
*indexbuf
= info
->has_user_indices
? NULL
: info
->index
.resource
;
2057 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2058 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
2059 bool has_user_indices
= info
->has_user_indices
;
2061 unsigned num_patches
, dirty_tex_counter
, index_offset
= 0;
2062 unsigned index_size
= info
->index_size
;
2064 struct r600_shader_atomic combined_atomics
[8];
2065 uint8_t atomic_used_mask
;
2067 if (!info
->indirect
&& !info
->count
&& (index_size
|| !info
->count_from_stream_output
)) {
2071 if (unlikely(!rctx
->vs_shader
)) {
2075 if (unlikely(!rctx
->ps_shader
&&
2076 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
2081 /* make sure that the gfx ring is only one active */
2082 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
2083 rctx
->b
.dma
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
2086 if (rctx
->cmd_buf_is_compute
) {
2087 rctx
->b
.gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
2088 rctx
->cmd_buf_is_compute
= false;
2091 /* Re-emit the framebuffer state if needed. */
2092 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
2093 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
2094 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
2095 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
2096 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
2099 if (rctx
->gs_shader
) {
2100 /* Determine whether the GS triangle strip adjacency fix should
2101 * be applied. Rotate every other triangle if
2102 * - triangle strips with adjacency are fed to the GS and
2103 * - primitive restart is disabled (the rotation doesn't help
2104 * when the restart occurs after an odd number of triangles).
2106 bool gs_tri_strip_adj_fix
=
2107 !rctx
->tes_shader
&&
2108 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
2109 !info
->primitive_restart
;
2110 if (gs_tri_strip_adj_fix
!= rctx
->gs_tri_strip_adj_fix
)
2111 rctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
2113 if (!r600_update_derived_state(rctx
)) {
2114 /* useless to render because current rendering command
2120 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
2121 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
2124 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2125 evergreen_emit_atomic_buffer_setup_count(rctx
, NULL
, combined_atomics
, &atomic_used_mask
);
2129 index_offset
+= info
->start
* index_size
;
2131 /* Translate 8-bit indices to 16-bit. */
2132 if (unlikely(index_size
== 1)) {
2133 struct pipe_resource
*out_buffer
= NULL
;
2134 unsigned out_offset
;
2136 unsigned start
, count
;
2138 if (likely(!info
->indirect
)) {
2140 count
= info
->count
;
2143 /* Have to get start/count from indirect buffer, slow path ahead... */
2144 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
->buffer
;
2145 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
2146 PIPE_TRANSFER_READ
);
2148 data
+= info
->indirect
->offset
/ sizeof(unsigned);
2149 start
= data
[2] * index_size
;
2158 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
2159 256, &out_offset
, &out_buffer
, &ptr
);
2163 util_shorten_ubyte_elts_to_userptr(
2164 &rctx
->b
.b
, info
, 0, 0, index_offset
, count
, ptr
);
2166 indexbuf
= out_buffer
;
2167 index_offset
= out_offset
;
2169 has_user_indices
= false;
2172 /* Upload the index buffer.
2173 * The upload is skipped for small index counts on little-endian machines
2174 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2175 * Indirect draws never use immediate indices.
2176 * Note: Instanced rendering in combination with immediate indices hangs. */
2177 if (has_user_indices
&& (R600_BIG_ENDIAN
|| info
->indirect
||
2178 info
->instance_count
> 1 ||
2179 info
->count
*index_size
> 20)) {
2181 u_upload_data(ctx
->stream_uploader
, 0,
2182 info
->count
* index_size
, 256,
2183 info
->index
.user
, &index_offset
, &indexbuf
);
2184 has_user_indices
= false;
2186 index_bias
= info
->index_bias
;
2188 index_bias
= info
->start
;
2191 /* Set the index offset and primitive restart. */
2192 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
2193 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
2194 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
2195 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
2196 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
2197 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
2198 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
2199 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
2202 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2203 if (rctx
->b
.chip_class
== R600
) {
2204 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
2205 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
2208 if (rctx
->b
.chip_class
>= EVERGREEN
)
2209 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
2212 r600_need_cs_space(rctx
, has_user_indices
? 5 : 0, TRUE
, util_bitcount(atomic_used_mask
));
2213 r600_flush_emit(rctx
);
2215 mask
= rctx
->dirty_atoms
;
2217 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
2220 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2221 evergreen_emit_atomic_buffer_setup(rctx
, false, combined_atomics
, atomic_used_mask
);
2224 if (rctx
->b
.chip_class
== CAYMAN
) {
2225 /* Copied from radeonsi. */
2226 unsigned primgroup_size
= 128; /* recommended without a GS */
2227 bool ia_switch_on_eop
= false;
2228 bool partial_vs_wave
= false;
2230 if (rctx
->gs_shader
)
2231 primgroup_size
= 64; /* recommended with a GS */
2233 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
2234 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
2235 ia_switch_on_eop
= true;
2238 if (r600_get_strmout_en(&rctx
->b
))
2239 partial_vs_wave
= true;
2241 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
2242 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
2243 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
2244 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
2247 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2248 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
2251 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
2252 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
2255 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2256 * even though it should have no effect on those. */
2257 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
2258 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
2259 unsigned prim
= info
->mode
;
2261 if (rctx
->gs_shader
) {
2262 prim
= rctx
->gs_shader
->gs_output_prim
;
2264 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
2266 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
2267 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
2268 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
2269 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
2271 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
2274 /* Update start instance. */
2275 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
2276 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
2277 rctx
->last_start_instance
= info
->start_instance
;
2280 /* Update the primitive type. */
2281 if (rctx
->last_primitive_type
!= info
->mode
) {
2282 r600_emit_rasterizer_prim_state(rctx
);
2283 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
2284 r600_conv_pipe_prim(info
->mode
));
2286 rctx
->last_primitive_type
= info
->mode
;
2290 if (likely(!info
->indirect
)) {
2291 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2292 radeon_emit(cs
, info
->instance_count
);
2294 uint64_t va
= r600_resource(info
->indirect
->buffer
)->gpu_address
;
2295 assert(rctx
->b
.chip_class
>= EVERGREEN
);
2297 // Invalidate so non-indirect draw calls reset this state
2298 rctx
->vgt_state
.last_draw_was_indirect
= true;
2299 rctx
->last_start_instance
= -1;
2301 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
2302 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
2303 radeon_emit(cs
, va
);
2304 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2306 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2307 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2308 (struct r600_resource
*)info
->indirect
->buffer
,
2310 RADEON_PRIO_DRAW_INDIRECT
));
2314 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2315 radeon_emit(cs
, index_size
== 4 ?
2316 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
2317 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
2319 if (has_user_indices
) {
2320 unsigned size_bytes
= info
->count
*index_size
;
2321 unsigned size_dw
= align(size_bytes
, 4) / 4;
2322 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
2323 radeon_emit(cs
, info
->count
);
2324 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
2325 radeon_emit_array(cs
, info
->index
.user
, size_dw
);
2327 uint64_t va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
2329 if (likely(!info
->indirect
)) {
2330 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
2331 radeon_emit(cs
, va
);
2332 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2333 radeon_emit(cs
, info
->count
);
2334 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2335 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2336 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2337 (struct r600_resource
*)indexbuf
,
2339 RADEON_PRIO_INDEX_BUFFER
));
2342 uint32_t max_size
= (indexbuf
->width0
- index_offset
) / index_size
;
2344 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
2345 radeon_emit(cs
, va
);
2346 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2348 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2349 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2350 (struct r600_resource
*)indexbuf
,
2352 RADEON_PRIO_INDEX_BUFFER
));
2354 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2355 radeon_emit(cs
, max_size
);
2357 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
2358 radeon_emit(cs
, info
->indirect
->offset
);
2359 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2363 if (unlikely(info
->count_from_stream_output
)) {
2364 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
2365 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
2367 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
2369 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
2370 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
2371 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
2372 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
2373 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
2374 radeon_emit(cs
, 0); /* unused */
2376 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2377 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2378 t
->buf_filled_size
, RADEON_USAGE_READ
,
2379 RADEON_PRIO_SO_FILLED_SIZE
));
2382 if (likely(!info
->indirect
)) {
2383 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
2384 radeon_emit(cs
, info
->count
);
2387 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
2388 radeon_emit(cs
, info
->indirect
->offset
);
2390 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2391 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2394 /* SMX returns CONTEXT_DONE too early workaround */
2395 if (rctx
->b
.family
== CHIP_R600
||
2396 rctx
->b
.family
== CHIP_RV610
||
2397 rctx
->b
.family
== CHIP_RV630
||
2398 rctx
->b
.family
== CHIP_RV635
) {
2399 /* if we have gs shader or streamout
2400 we need to do a wait idle after every draw */
2401 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2402 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2406 /* ES ring rolling over at EOP - workaround */
2407 if (rctx
->b
.chip_class
== R600
) {
2408 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2409 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2413 if (rctx
->b
.chip_class
>= EVERGREEN
)
2414 evergreen_emit_atomic_buffer_save(rctx
, false, combined_atomics
, &atomic_used_mask
);
2416 if (rctx
->trace_buf
)
2417 eg_trace_emit(rctx
);
2419 if (rctx
->framebuffer
.do_update_surf_dirtiness
) {
2420 /* Set the depth buffer as dirty. */
2421 if (rctx
->framebuffer
.state
.zsbuf
) {
2422 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2423 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2425 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2427 if (rtex
->surface
.has_stencil
)
2428 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2430 if (rctx
->framebuffer
.compressed_cb_mask
) {
2431 struct pipe_surface
*surf
;
2432 struct r600_texture
*rtex
;
2433 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2436 unsigned i
= u_bit_scan(&mask
);
2437 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2438 rtex
= (struct r600_texture
*)surf
->texture
;
2440 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2444 rctx
->framebuffer
.do_update_surf_dirtiness
= false;
2447 if (index_size
&& indexbuf
!= info
->index
.resource
)
2448 pipe_resource_reference(&indexbuf
, NULL
);
2449 rctx
->b
.num_draw_calls
++;
2452 uint32_t r600_translate_stencil_op(int s_op
)
2455 case PIPE_STENCIL_OP_KEEP
:
2456 return V_028800_STENCIL_KEEP
;
2457 case PIPE_STENCIL_OP_ZERO
:
2458 return V_028800_STENCIL_ZERO
;
2459 case PIPE_STENCIL_OP_REPLACE
:
2460 return V_028800_STENCIL_REPLACE
;
2461 case PIPE_STENCIL_OP_INCR
:
2462 return V_028800_STENCIL_INCR
;
2463 case PIPE_STENCIL_OP_DECR
:
2464 return V_028800_STENCIL_DECR
;
2465 case PIPE_STENCIL_OP_INCR_WRAP
:
2466 return V_028800_STENCIL_INCR_WRAP
;
2467 case PIPE_STENCIL_OP_DECR_WRAP
:
2468 return V_028800_STENCIL_DECR_WRAP
;
2469 case PIPE_STENCIL_OP_INVERT
:
2470 return V_028800_STENCIL_INVERT
;
2472 R600_ERR("Unknown stencil op %d", s_op
);
2479 uint32_t r600_translate_fill(uint32_t func
)
2482 case PIPE_POLYGON_MODE_FILL
:
2484 case PIPE_POLYGON_MODE_LINE
:
2486 case PIPE_POLYGON_MODE_POINT
:
2494 unsigned r600_tex_wrap(unsigned wrap
)
2498 case PIPE_TEX_WRAP_REPEAT
:
2499 return V_03C000_SQ_TEX_WRAP
;
2500 case PIPE_TEX_WRAP_CLAMP
:
2501 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2502 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2503 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2504 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2505 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2506 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2507 return V_03C000_SQ_TEX_MIRROR
;
2508 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2509 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2510 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2511 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2512 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2513 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2517 unsigned r600_tex_mipfilter(unsigned filter
)
2520 case PIPE_TEX_MIPFILTER_NEAREST
:
2521 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2522 case PIPE_TEX_MIPFILTER_LINEAR
:
2523 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2525 case PIPE_TEX_MIPFILTER_NONE
:
2526 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2530 unsigned r600_tex_compare(unsigned compare
)
2534 case PIPE_FUNC_NEVER
:
2535 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2536 case PIPE_FUNC_LESS
:
2537 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2538 case PIPE_FUNC_EQUAL
:
2539 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2540 case PIPE_FUNC_LEQUAL
:
2541 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2542 case PIPE_FUNC_GREATER
:
2543 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2544 case PIPE_FUNC_NOTEQUAL
:
2545 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2546 case PIPE_FUNC_GEQUAL
:
2547 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2548 case PIPE_FUNC_ALWAYS
:
2549 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2553 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2555 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2556 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2558 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2559 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2562 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2564 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2565 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2567 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2568 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2569 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2570 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2571 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2574 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2577 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2578 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2583 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2584 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2585 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2586 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2589 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2590 const unsigned char *swizzle_view
,
2594 unsigned char swizzle
[4];
2595 unsigned result
= 0;
2596 const uint32_t tex_swizzle_shift
[4] = {
2599 const uint32_t vtx_swizzle_shift
[4] = {
2602 const uint32_t swizzle_bit
[4] = {
2605 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2608 swizzle_shift
= vtx_swizzle_shift
;
2611 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2613 memcpy(swizzle
, swizzle_format
, 4);
2617 for (i
= 0; i
< 4; i
++) {
2618 switch (swizzle
[i
]) {
2619 case PIPE_SWIZZLE_Y
:
2620 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2622 case PIPE_SWIZZLE_Z
:
2623 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2625 case PIPE_SWIZZLE_W
:
2626 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2628 case PIPE_SWIZZLE_0
:
2629 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2631 case PIPE_SWIZZLE_1
:
2632 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2634 default: /* PIPE_SWIZZLE_X */
2635 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2641 /* texture format translate */
2642 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2643 enum pipe_format format
,
2644 const unsigned char *swizzle_view
,
2645 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2646 bool do_endian_swap
)
2648 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2649 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2650 const struct util_format_description
*desc
;
2651 boolean uniform
= TRUE
;
2652 bool is_srgb_valid
= FALSE
;
2653 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2654 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2655 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2656 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2657 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2660 const uint32_t sign_bit
[4] = {
2661 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2662 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2663 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2664 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2667 /* Need to replace the specified texture formats in case of big-endian.
2668 * These formats are formats that have channels with number of bits
2669 * not divisible by 8.
2670 * Mesa conversion functions don't swap bits for those formats, and because
2671 * we transmit this over a serial bus to the GPU (PCIe), the
2672 * bit-endianess is important!!!
2673 * In case we have an "opposite" format, just use that for the swizzling
2674 * information. If we don't have such an "opposite" format, we need
2675 * to use a fixed swizzle info instead (see below)
2677 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2678 format
= PIPE_FORMAT_A4R4_UNORM
;
2680 desc
= util_format_description(format
);
2684 /* Depth and stencil swizzling is handled separately. */
2685 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2686 /* Need to check for specific texture formats that don't have
2687 * an "opposite" format we can use. For those formats, we directly
2688 * specify the swizzling, which is the LE swizzling as defined in
2691 if (do_endian_swap
) {
2692 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2693 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2694 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2695 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2696 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2697 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2699 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2701 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2705 /* Colorspace (return non-RGB formats directly). */
2706 switch (desc
->colorspace
) {
2707 /* Depth stencil formats */
2708 case UTIL_FORMAT_COLORSPACE_ZS
:
2710 /* Depth sampler formats. */
2711 case PIPE_FORMAT_Z16_UNORM
:
2712 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2715 case PIPE_FORMAT_Z24X8_UNORM
:
2716 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2717 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2720 case PIPE_FORMAT_X8Z24_UNORM
:
2721 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2722 if (rscreen
->b
.chip_class
< EVERGREEN
)
2724 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2727 case PIPE_FORMAT_Z32_FLOAT
:
2728 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2729 result
= FMT_32_FLOAT
;
2731 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2732 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2733 result
= FMT_X24_8_32_FLOAT
;
2735 /* Stencil sampler formats. */
2736 case PIPE_FORMAT_S8_UINT
:
2737 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2738 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2741 case PIPE_FORMAT_X24S8_UINT
:
2742 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2743 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2746 case PIPE_FORMAT_S8X24_UINT
:
2747 if (rscreen
->b
.chip_class
< EVERGREEN
)
2749 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2750 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2753 case PIPE_FORMAT_X32_S8X24_UINT
:
2754 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2755 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2756 result
= FMT_X24_8_32_FLOAT
;
2762 case UTIL_FORMAT_COLORSPACE_YUV
:
2763 yuv_format
|= (1 << 30);
2765 case PIPE_FORMAT_UYVY
:
2766 case PIPE_FORMAT_YUYV
:
2770 goto out_unknown
; /* XXX */
2772 case UTIL_FORMAT_COLORSPACE_SRGB
:
2773 word4
|= S_038010_FORCE_DEGAMMA(1);
2780 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2782 case PIPE_FORMAT_RGTC1_SNORM
:
2783 case PIPE_FORMAT_LATC1_SNORM
:
2784 word4
|= sign_bit
[0];
2786 case PIPE_FORMAT_RGTC1_UNORM
:
2787 case PIPE_FORMAT_LATC1_UNORM
:
2790 case PIPE_FORMAT_RGTC2_SNORM
:
2791 case PIPE_FORMAT_LATC2_SNORM
:
2792 word4
|= sign_bit
[0] | sign_bit
[1];
2794 case PIPE_FORMAT_RGTC2_UNORM
:
2795 case PIPE_FORMAT_LATC2_UNORM
:
2803 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2805 case PIPE_FORMAT_DXT1_RGB
:
2806 case PIPE_FORMAT_DXT1_RGBA
:
2807 case PIPE_FORMAT_DXT1_SRGB
:
2808 case PIPE_FORMAT_DXT1_SRGBA
:
2810 is_srgb_valid
= TRUE
;
2812 case PIPE_FORMAT_DXT3_RGBA
:
2813 case PIPE_FORMAT_DXT3_SRGBA
:
2815 is_srgb_valid
= TRUE
;
2817 case PIPE_FORMAT_DXT5_RGBA
:
2818 case PIPE_FORMAT_DXT5_SRGBA
:
2820 is_srgb_valid
= TRUE
;
2827 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2828 if (rscreen
->b
.chip_class
< EVERGREEN
)
2832 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2833 case PIPE_FORMAT_BPTC_SRGBA
:
2835 is_srgb_valid
= TRUE
;
2837 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2838 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2840 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2848 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2850 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2851 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2854 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2855 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2863 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2864 result
= FMT_5_9_9_9_SHAREDEXP
;
2866 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2867 result
= FMT_10_11_11_FLOAT
;
2872 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2873 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2874 word4
|= sign_bit
[i
];
2878 /* R8G8Bx_SNORM - XXX CxV8U8 */
2880 /* See whether the components are of the same size. */
2881 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2882 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2885 /* Non-uniform formats. */
2887 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2888 desc
->channel
[0].pure_integer
)
2889 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2890 switch(desc
->nr_channels
) {
2892 if (desc
->channel
[0].size
== 5 &&
2893 desc
->channel
[1].size
== 6 &&
2894 desc
->channel
[2].size
== 5) {
2900 if (desc
->channel
[0].size
== 5 &&
2901 desc
->channel
[1].size
== 5 &&
2902 desc
->channel
[2].size
== 5 &&
2903 desc
->channel
[3].size
== 1) {
2904 result
= FMT_1_5_5_5
;
2907 if (desc
->channel
[0].size
== 10 &&
2908 desc
->channel
[1].size
== 10 &&
2909 desc
->channel
[2].size
== 10 &&
2910 desc
->channel
[3].size
== 2) {
2911 result
= FMT_2_10_10_10
;
2919 /* Find the first non-VOID channel. */
2920 for (i
= 0; i
< 4; i
++) {
2921 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2929 /* uniform formats */
2930 switch (desc
->channel
[i
].type
) {
2931 case UTIL_FORMAT_TYPE_UNSIGNED
:
2932 case UTIL_FORMAT_TYPE_SIGNED
:
2934 if (!desc
->channel
[i
].normalized
&&
2935 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2939 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2940 desc
->channel
[i
].pure_integer
)
2941 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2943 switch (desc
->channel
[i
].size
) {
2945 switch (desc
->nr_channels
) {
2950 result
= FMT_4_4_4_4
;
2955 switch (desc
->nr_channels
) {
2958 is_srgb_valid
= TRUE
;
2964 result
= FMT_8_8_8_8
;
2965 is_srgb_valid
= TRUE
;
2970 switch (desc
->nr_channels
) {
2978 result
= FMT_16_16_16_16
;
2983 switch (desc
->nr_channels
) {
2991 result
= FMT_32_32_32_32
;
2997 case UTIL_FORMAT_TYPE_FLOAT
:
2998 switch (desc
->channel
[i
].size
) {
3000 switch (desc
->nr_channels
) {
3002 result
= FMT_16_FLOAT
;
3005 result
= FMT_16_16_FLOAT
;
3008 result
= FMT_16_16_16_16_FLOAT
;
3013 switch (desc
->nr_channels
) {
3015 result
= FMT_32_FLOAT
;
3018 result
= FMT_32_32_FLOAT
;
3021 result
= FMT_32_32_32_32_FLOAT
;
3030 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
3035 *yuv_format_p
= yuv_format
;
3038 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
3042 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
3043 bool do_endian_swap
)
3045 const struct util_format_description
*desc
= util_format_description(format
);
3046 int channel
= util_format_get_first_non_void_channel(format
);
3051 #define HAS_SIZE(x,y,z,w) \
3052 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
3053 desc->channel[2].size == (z) && desc->channel[3].size == (w))
3055 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
3056 return V_0280A0_COLOR_10_11_11_FLOAT
;
3058 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
3062 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
3064 switch (desc
->nr_channels
) {
3066 switch (desc
->channel
[0].size
) {
3068 return V_0280A0_COLOR_8
;
3071 return V_0280A0_COLOR_16_FLOAT
;
3073 return V_0280A0_COLOR_16
;
3076 return V_0280A0_COLOR_32_FLOAT
;
3078 return V_0280A0_COLOR_32
;
3082 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
3083 switch (desc
->channel
[0].size
) {
3086 return V_0280A0_COLOR_4_4
;
3088 return ~0U; /* removed on Evergreen */
3090 return V_0280A0_COLOR_8_8
;
3093 return V_0280A0_COLOR_16_16_FLOAT
;
3095 return V_0280A0_COLOR_16_16
;
3098 return V_0280A0_COLOR_32_32_FLOAT
;
3100 return V_0280A0_COLOR_32_32
;
3102 } else if (HAS_SIZE(8,24,0,0)) {
3103 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
3104 } else if (HAS_SIZE(24,8,0,0)) {
3105 return V_0280A0_COLOR_8_24
;
3109 if (HAS_SIZE(5,6,5,0)) {
3110 return V_0280A0_COLOR_5_6_5
;
3111 } else if (HAS_SIZE(32,8,24,0)) {
3112 return V_0280A0_COLOR_X24_8_32_FLOAT
;
3116 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
3117 desc
->channel
[0].size
== desc
->channel
[2].size
&&
3118 desc
->channel
[0].size
== desc
->channel
[3].size
) {
3119 switch (desc
->channel
[0].size
) {
3121 return V_0280A0_COLOR_4_4_4_4
;
3123 return V_0280A0_COLOR_8_8_8_8
;
3126 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
3128 return V_0280A0_COLOR_16_16_16_16
;
3131 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
3133 return V_0280A0_COLOR_32_32_32_32
;
3135 } else if (HAS_SIZE(5,5,5,1)) {
3136 return V_0280A0_COLOR_1_5_5_5
;
3137 } else if (HAS_SIZE(10,10,10,2)) {
3138 return V_0280A0_COLOR_2_10_10_10
;
3145 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
3147 if (R600_BIG_ENDIAN
) {
3148 switch(colorformat
) {
3149 /* 8-bit buffers. */
3150 case V_0280A0_COLOR_4_4
:
3151 case V_0280A0_COLOR_8
:
3154 /* 16-bit buffers. */
3155 case V_0280A0_COLOR_8_8
:
3157 * No need to do endian swaps on array formats,
3158 * as mesa<-->pipe formats conversion take into account
3163 case V_0280A0_COLOR_5_6_5
:
3164 case V_0280A0_COLOR_1_5_5_5
:
3165 case V_0280A0_COLOR_4_4_4_4
:
3166 case V_0280A0_COLOR_16
:
3167 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
3169 /* 32-bit buffers. */
3170 case V_0280A0_COLOR_8_8_8_8
:
3172 * No need to do endian swaps on array formats,
3173 * as mesa<-->pipe formats conversion take into account
3178 case V_0280A0_COLOR_2_10_10_10
:
3179 case V_0280A0_COLOR_8_24
:
3180 case V_0280A0_COLOR_24_8
:
3181 case V_0280A0_COLOR_32_FLOAT
:
3182 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
3184 case V_0280A0_COLOR_16_16_FLOAT
:
3185 case V_0280A0_COLOR_16_16
:
3186 return ENDIAN_8IN16
;
3188 /* 64-bit buffers. */
3189 case V_0280A0_COLOR_16_16_16_16
:
3190 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
3191 return ENDIAN_8IN16
;
3193 case V_0280A0_COLOR_32_32_FLOAT
:
3194 case V_0280A0_COLOR_32_32
:
3195 case V_0280A0_COLOR_X24_8_32_FLOAT
:
3196 return ENDIAN_8IN32
;
3198 /* 128-bit buffers. */
3199 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
3200 case V_0280A0_COLOR_32_32_32_32
:
3201 return ENDIAN_8IN32
;
3203 return ENDIAN_NONE
; /* Unsupported. */
3210 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
3212 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3213 struct r600_resource
*rbuffer
= r600_resource(buf
);
3214 unsigned i
, shader
, mask
;
3215 struct r600_pipe_sampler_view
*view
;
3217 /* Reallocate the buffer in the same pipe_resource. */
3218 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
3220 /* We changed the buffer, now we need to bind it where the old one was bound. */
3221 /* Vertex buffers. */
3222 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
3224 i
= u_bit_scan(&mask
);
3225 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
.resource
== &rbuffer
->b
.b
) {
3226 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
3227 r600_vertex_buffers_dirty(rctx
);
3230 /* Streamout buffers. */
3231 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
3232 if (rctx
->b
.streamout
.targets
[i
] &&
3233 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
3234 if (rctx
->b
.streamout
.begin_emitted
) {
3235 r600_emit_streamout_end(&rctx
->b
);
3237 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
3238 r600_streamout_buffers_dirty(&rctx
->b
);
3242 /* Constant buffers. */
3243 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3244 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
3246 uint32_t mask
= state
->enabled_mask
;
3249 unsigned i
= u_bit_scan(&mask
);
3250 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
3252 state
->dirty_mask
|= 1 << i
;
3256 r600_constant_buffers_dirty(rctx
, state
);
3260 /* Texture buffer objects - update the virtual addresses in descriptors. */
3261 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
3262 if (view
->base
.texture
== &rbuffer
->b
.b
) {
3263 uint64_t offset
= view
->base
.u
.buf
.offset
;
3264 uint64_t va
= rbuffer
->gpu_address
+ offset
;
3266 view
->tex_resource_words
[0] = va
;
3267 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
3268 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
3271 /* Texture buffer objects - make bindings dirty if needed. */
3272 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3273 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
3275 uint32_t mask
= state
->enabled_mask
;
3278 unsigned i
= u_bit_scan(&mask
);
3279 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
3281 state
->dirty_mask
|= 1 << i
;
3285 r600_sampler_views_dirty(rctx
, state
);
3290 struct r600_image_state
*istate
= &rctx
->fragment_buffers
;
3292 uint32_t mask
= istate
->enabled_mask
;
3295 unsigned i
= u_bit_scan(&mask
);
3296 if (istate
->views
[i
].base
.resource
== &rbuffer
->b
.b
) {
3298 istate
->dirty_mask
|= 1 << i
;
3302 r600_mark_atom_dirty(rctx
, &istate
->atom
);
3308 static void r600_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
3310 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3312 /* Pipeline stat & streamout queries. */
3314 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
3315 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
3317 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
3318 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
3321 /* Occlusion queries. */
3322 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
3323 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
3324 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3328 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3329 bool include_draw_vbo
)
3331 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
, 0);
3334 /* keep this at the end of this file, please */
3335 void r600_init_common_state_functions(struct r600_context
*rctx
)
3337 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
3338 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
3339 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
3340 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
3341 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
3342 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
3343 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
3344 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
3345 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
3346 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
3347 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
3348 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
3349 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
3350 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
3351 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
3352 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
3353 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
3354 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
3355 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
3356 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
3357 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
3358 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
3359 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
3360 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
3361 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
3362 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
3363 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
3364 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
3365 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
3366 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
3367 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
3368 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
3369 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
3370 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
3371 rctx
->b
.b
.memory_barrier
= r600_memory_barrier
;
3372 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
3373 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
3374 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
3376 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
3377 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
3378 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;