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r600: refactor and export some shader selector code for compute
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 assert(!cb->buf);
43 cb->buf = CALLOC(1, 4 * num_dw);
44 cb->max_num_dw = num_dw;
45 }
46
47 void r600_release_command_buffer(struct r600_command_buffer *cb)
48 {
49 FREE(cb->buf);
50 }
51
52 void r600_add_atom(struct r600_context *rctx,
53 struct r600_atom *atom,
54 unsigned id)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->id = id;
60 }
61
62 void r600_init_atom(struct r600_context *rctx,
63 struct r600_atom *atom,
64 unsigned id,
65 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
66 unsigned num_dw)
67 {
68 atom->emit = (void*)emit;
69 atom->num_dw = num_dw;
70 r600_add_atom(rctx, atom, id);
71 }
72
73 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 r600_emit_command_buffer(rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
76 }
77
78 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
79 {
80 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
81 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
82 unsigned alpha_ref = a->sx_alpha_ref;
83
84 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
85 alpha_ref &= ~0x1FFF;
86 }
87
88 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
89 a->sx_alpha_test_control |
90 S_028410_ALPHA_TEST_BYPASS(a->bypass));
91 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
92 }
93
94 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
95 {
96 struct r600_context *rctx = (struct r600_context *)ctx;
97 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
98 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
99
100 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
101 PIPE_BARRIER_SHADER_BUFFER |
102 PIPE_BARRIER_TEXTURE |
103 PIPE_BARRIER_IMAGE |
104 PIPE_BARRIER_STREAMOUT_BUFFER |
105 PIPE_BARRIER_GLOBAL_BUFFER)) {
106 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
107 R600_CONTEXT_INV_TEX_CACHE;
108 }
109
110 if (flags & (PIPE_BARRIER_FRAMEBUFFER|
111 PIPE_BARRIER_IMAGE))
112 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
113
114 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
115 }
116
117 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 struct r600_context *rctx = (struct r600_context *)ctx;
120
121 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
122 R600_CONTEXT_FLUSH_AND_INV_CB |
123 R600_CONTEXT_FLUSH_AND_INV |
124 R600_CONTEXT_WAIT_3D_IDLE;
125 rctx->framebuffer.do_update_surf_dirtiness = true;
126 }
127
128 static unsigned r600_conv_pipe_prim(unsigned prim)
129 {
130 static const unsigned prim_conv[] = {
131 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
132 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
133 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
134 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
135 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
136 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
137 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
138 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
139 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
140 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
141 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
145 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
146 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
147 };
148 assert(prim < ARRAY_SIZE(prim_conv));
149 return prim_conv[prim];
150 }
151
152 unsigned r600_conv_prim_to_gs_out(unsigned mode)
153 {
154 static const int prim_conv[] = {
155 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
156 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
157 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
158 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
159 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
160 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
161 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
162 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
163 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
164 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
165 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
166 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
167 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
168 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
169 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
170 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
171 };
172 assert(mode < ARRAY_SIZE(prim_conv));
173
174 return prim_conv[mode];
175 }
176
177 /* common state between evergreen and r600 */
178
179 static void r600_bind_blend_state_internal(struct r600_context *rctx,
180 struct r600_blend_state *blend, bool blend_disable)
181 {
182 unsigned color_control;
183 bool update_cb = false;
184
185 rctx->alpha_to_one = blend->alpha_to_one;
186 rctx->dual_src_blend = blend->dual_src_blend;
187
188 if (!blend_disable) {
189 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
190 color_control = blend->cb_color_control;
191 } else {
192 /* Blending is disabled. */
193 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
194 color_control = blend->cb_color_control_no_blend;
195 }
196
197 /* Update derived states. */
198 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
199 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
200 update_cb = true;
201 }
202 if (rctx->b.chip_class <= R700 &&
203 rctx->cb_misc_state.cb_color_control != color_control) {
204 rctx->cb_misc_state.cb_color_control = color_control;
205 update_cb = true;
206 }
207 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
208 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
209 update_cb = true;
210 }
211 if (update_cb) {
212 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
213 }
214 if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) {
215 rctx->framebuffer.dual_src_blend = blend->dual_src_blend;
216 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
217 }
218 }
219
220 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
221 {
222 struct r600_context *rctx = (struct r600_context *)ctx;
223 struct r600_blend_state *blend = (struct r600_blend_state *)state;
224
225 if (!blend) {
226 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
227 return;
228 }
229
230 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
231 }
232
233 static void r600_set_blend_color(struct pipe_context *ctx,
234 const struct pipe_blend_color *state)
235 {
236 struct r600_context *rctx = (struct r600_context *)ctx;
237
238 rctx->blend_color.state = *state;
239 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
240 }
241
242 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
243 {
244 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
245 struct pipe_blend_color *state = &rctx->blend_color.state;
246
247 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
248 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
249 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
250 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
251 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
252 }
253
254 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
255 {
256 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
257 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
258
259 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
260 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
261 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
262 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
263 if (a->last_draw_was_indirect) {
264 a->last_draw_was_indirect = false;
265 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
266 }
267 }
268
269 static void r600_set_clip_state(struct pipe_context *ctx,
270 const struct pipe_clip_state *state)
271 {
272 struct r600_context *rctx = (struct r600_context *)ctx;
273
274 rctx->clip_state.state = *state;
275 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
276 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
277 }
278
279 static void r600_set_stencil_ref(struct pipe_context *ctx,
280 const struct r600_stencil_ref *state)
281 {
282 struct r600_context *rctx = (struct r600_context *)ctx;
283
284 rctx->stencil_ref.state = *state;
285 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
286 }
287
288 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
289 {
290 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
291 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
292
293 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
294 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
295 S_028430_STENCILREF(a->state.ref_value[0]) |
296 S_028430_STENCILMASK(a->state.valuemask[0]) |
297 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
298 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
299 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
300 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
301 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
302 }
303
304 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
305 const struct pipe_stencil_ref *state)
306 {
307 struct r600_context *rctx = (struct r600_context *)ctx;
308 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
309 struct r600_stencil_ref ref;
310
311 rctx->stencil_ref.pipe_state = *state;
312
313 if (!dsa)
314 return;
315
316 ref.ref_value[0] = state->ref_value[0];
317 ref.ref_value[1] = state->ref_value[1];
318 ref.valuemask[0] = dsa->valuemask[0];
319 ref.valuemask[1] = dsa->valuemask[1];
320 ref.writemask[0] = dsa->writemask[0];
321 ref.writemask[1] = dsa->writemask[1];
322
323 r600_set_stencil_ref(ctx, &ref);
324 }
325
326 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
327 {
328 struct r600_context *rctx = (struct r600_context *)ctx;
329 struct r600_dsa_state *dsa = state;
330 struct r600_stencil_ref ref;
331
332 if (!state) {
333 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
334 return;
335 }
336
337 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
338
339 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
340 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
341 ref.valuemask[0] = dsa->valuemask[0];
342 ref.valuemask[1] = dsa->valuemask[1];
343 ref.writemask[0] = dsa->writemask[0];
344 ref.writemask[1] = dsa->writemask[1];
345 if (rctx->zwritemask != dsa->zwritemask) {
346 rctx->zwritemask = dsa->zwritemask;
347 if (rctx->b.chip_class >= EVERGREEN) {
348 /* work around some issue when not writing to zbuffer
349 * we are having lockup on evergreen so do not enable
350 * hyperz when not writing zbuffer
351 */
352 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
353 }
354 }
355
356 r600_set_stencil_ref(ctx, &ref);
357
358 /* Update alphatest state. */
359 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
360 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
361 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
362 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
363 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
364 }
365 }
366
367 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
368 {
369 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
370 struct r600_context *rctx = (struct r600_context *)ctx;
371
372 if (!state)
373 return;
374
375 rctx->rasterizer = rs;
376
377 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
378
379 if (rs->offset_enable &&
380 (rs->offset_units != rctx->poly_offset_state.offset_units ||
381 rs->offset_scale != rctx->poly_offset_state.offset_scale ||
382 rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
383 rctx->poly_offset_state.offset_units = rs->offset_units;
384 rctx->poly_offset_state.offset_scale = rs->offset_scale;
385 rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
386 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
387 }
388
389 /* Update clip_misc_state. */
390 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
391 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
392 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
393 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
394 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
395 }
396
397 r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
398
399 /* Re-emit PA_SC_LINE_STIPPLE. */
400 rctx->last_primitive_type = -1;
401 }
402
403 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
404 {
405 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
406
407 r600_release_command_buffer(&rs->buffer);
408 FREE(rs);
409 }
410
411 static void r600_sampler_view_destroy(struct pipe_context *ctx,
412 struct pipe_sampler_view *state)
413 {
414 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
415
416 if (view->tex_resource->gpu_address &&
417 view->tex_resource->b.b.target == PIPE_BUFFER)
418 LIST_DELINIT(&view->list);
419
420 pipe_resource_reference(&state->texture, NULL);
421 FREE(view);
422 }
423
424 void r600_sampler_states_dirty(struct r600_context *rctx,
425 struct r600_sampler_states *state)
426 {
427 if (state->dirty_mask) {
428 if (state->dirty_mask & state->has_bordercolor_mask) {
429 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
430 }
431 state->atom.num_dw =
432 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
433 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
434 r600_mark_atom_dirty(rctx, &state->atom);
435 }
436 }
437
438 static void r600_bind_sampler_states(struct pipe_context *pipe,
439 enum pipe_shader_type shader,
440 unsigned start,
441 unsigned count, void **states)
442 {
443 struct r600_context *rctx = (struct r600_context *)pipe;
444 struct r600_textures_info *dst = &rctx->samplers[shader];
445 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
446 int seamless_cube_map = -1;
447 unsigned i;
448 /* This sets 1-bit for states with index >= count. */
449 uint32_t disable_mask = ~((1ull << count) - 1);
450 /* These are the new states set by this function. */
451 uint32_t new_mask = 0;
452
453 assert(start == 0); /* XXX fix below */
454
455 if (!states) {
456 disable_mask = ~0u;
457 count = 0;
458 }
459
460 for (i = 0; i < count; i++) {
461 struct r600_pipe_sampler_state *rstate = rstates[i];
462
463 if (rstate == dst->states.states[i]) {
464 continue;
465 }
466
467 if (rstate) {
468 if (rstate->border_color_use) {
469 dst->states.has_bordercolor_mask |= 1 << i;
470 } else {
471 dst->states.has_bordercolor_mask &= ~(1 << i);
472 }
473 seamless_cube_map = rstate->seamless_cube_map;
474
475 new_mask |= 1 << i;
476 } else {
477 disable_mask |= 1 << i;
478 }
479 }
480
481 memcpy(dst->states.states, rstates, sizeof(void*) * count);
482 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
483
484 dst->states.enabled_mask &= ~disable_mask;
485 dst->states.dirty_mask &= dst->states.enabled_mask;
486 dst->states.enabled_mask |= new_mask;
487 dst->states.dirty_mask |= new_mask;
488 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
489
490 r600_sampler_states_dirty(rctx, &dst->states);
491
492 /* Seamless cubemap state. */
493 if (rctx->b.chip_class <= R700 &&
494 seamless_cube_map != -1 &&
495 seamless_cube_map != rctx->seamless_cube_map.enabled) {
496 /* change in TA_CNTL_AUX need a pipeline flush */
497 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
498 rctx->seamless_cube_map.enabled = seamless_cube_map;
499 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
500 }
501 }
502
503 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
504 {
505 free(state);
506 }
507
508 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
509 {
510 struct r600_context *rctx = (struct r600_context *)ctx;
511 struct r600_blend_state *blend = (struct r600_blend_state*)state;
512
513 if (rctx->blend_state.cso == state) {
514 ctx->bind_blend_state(ctx, NULL);
515 }
516
517 r600_release_command_buffer(&blend->buffer);
518 r600_release_command_buffer(&blend->buffer_no_blend);
519 FREE(blend);
520 }
521
522 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
523 {
524 struct r600_context *rctx = (struct r600_context *)ctx;
525 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
526
527 if (rctx->dsa_state.cso == state) {
528 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
529 }
530
531 r600_release_command_buffer(&dsa->buffer);
532 free(dsa);
533 }
534
535 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
536 {
537 struct r600_context *rctx = (struct r600_context *)ctx;
538
539 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
540 }
541
542 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
543 {
544 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
545 r600_resource_reference(&shader->buffer, NULL);
546 FREE(shader);
547 }
548
549 void r600_vertex_buffers_dirty(struct r600_context *rctx)
550 {
551 if (rctx->vertex_buffer_state.dirty_mask) {
552 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
553 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
554 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
555 }
556 }
557
558 static void r600_set_vertex_buffers(struct pipe_context *ctx,
559 unsigned start_slot, unsigned count,
560 const struct pipe_vertex_buffer *input)
561 {
562 struct r600_context *rctx = (struct r600_context *)ctx;
563 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
564 struct pipe_vertex_buffer *vb = state->vb + start_slot;
565 unsigned i;
566 uint32_t disable_mask = 0;
567 /* These are the new buffers set by this function. */
568 uint32_t new_buffer_mask = 0;
569
570 /* Set vertex buffers. */
571 if (input) {
572 for (i = 0; i < count; i++) {
573 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
574 if (input[i].buffer.resource) {
575 vb[i].stride = input[i].stride;
576 vb[i].buffer_offset = input[i].buffer_offset;
577 pipe_resource_reference(&vb[i].buffer.resource, input[i].buffer.resource);
578 new_buffer_mask |= 1 << i;
579 r600_context_add_resource_size(ctx, input[i].buffer.resource);
580 } else {
581 pipe_resource_reference(&vb[i].buffer.resource, NULL);
582 disable_mask |= 1 << i;
583 }
584 }
585 }
586 } else {
587 for (i = 0; i < count; i++) {
588 pipe_resource_reference(&vb[i].buffer.resource, NULL);
589 }
590 disable_mask = ((1ull << count) - 1);
591 }
592
593 disable_mask <<= start_slot;
594 new_buffer_mask <<= start_slot;
595
596 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
597 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
598 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
599 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
600
601 r600_vertex_buffers_dirty(rctx);
602 }
603
604 void r600_sampler_views_dirty(struct r600_context *rctx,
605 struct r600_samplerview_state *state)
606 {
607 if (state->dirty_mask) {
608 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
609 util_bitcount(state->dirty_mask);
610 r600_mark_atom_dirty(rctx, &state->atom);
611 }
612 }
613
614 static void r600_set_sampler_views(struct pipe_context *pipe,
615 enum pipe_shader_type shader,
616 unsigned start, unsigned count,
617 struct pipe_sampler_view **views)
618 {
619 struct r600_context *rctx = (struct r600_context *) pipe;
620 struct r600_textures_info *dst = &rctx->samplers[shader];
621 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
622 uint32_t dirty_sampler_states_mask = 0;
623 unsigned i;
624 /* This sets 1-bit for textures with index >= count. */
625 uint32_t disable_mask = ~((1ull << count) - 1);
626 /* These are the new textures set by this function. */
627 uint32_t new_mask = 0;
628
629 /* Set textures with index >= count to NULL. */
630 uint32_t remaining_mask;
631
632 assert(start == 0); /* XXX fix below */
633
634 if (!views) {
635 disable_mask = ~0u;
636 count = 0;
637 }
638
639 remaining_mask = dst->views.enabled_mask & disable_mask;
640
641 while (remaining_mask) {
642 i = u_bit_scan(&remaining_mask);
643 assert(dst->views.views[i]);
644
645 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
646 }
647
648 for (i = 0; i < count; i++) {
649 if (rviews[i] == dst->views.views[i]) {
650 continue;
651 }
652
653 if (rviews[i]) {
654 struct r600_texture *rtex =
655 (struct r600_texture*)rviews[i]->base.texture;
656 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
657
658 if (!is_buffer && rtex->db_compatible) {
659 dst->views.compressed_depthtex_mask |= 1 << i;
660 } else {
661 dst->views.compressed_depthtex_mask &= ~(1 << i);
662 }
663
664 /* Track compressed colorbuffers. */
665 if (!is_buffer && rtex->cmask.size) {
666 dst->views.compressed_colortex_mask |= 1 << i;
667 } else {
668 dst->views.compressed_colortex_mask &= ~(1 << i);
669 }
670
671 /* Changing from array to non-arrays textures and vice versa requires
672 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
673 if (rctx->b.chip_class <= R700 &&
674 (dst->states.enabled_mask & (1 << i)) &&
675 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
676 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
677 dirty_sampler_states_mask |= 1 << i;
678 }
679
680 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
681 new_mask |= 1 << i;
682 r600_context_add_resource_size(pipe, views[i]->texture);
683 } else {
684 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
685 disable_mask |= 1 << i;
686 }
687 }
688
689 dst->views.enabled_mask &= ~disable_mask;
690 dst->views.dirty_mask &= dst->views.enabled_mask;
691 dst->views.enabled_mask |= new_mask;
692 dst->views.dirty_mask |= new_mask;
693 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
694 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
695 dst->views.dirty_buffer_constants = TRUE;
696 r600_sampler_views_dirty(rctx, &dst->views);
697
698 if (dirty_sampler_states_mask) {
699 dst->states.dirty_mask |= dirty_sampler_states_mask;
700 r600_sampler_states_dirty(rctx, &dst->states);
701 }
702 }
703
704 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
705 {
706 uint32_t mask = views->enabled_mask;
707
708 while (mask) {
709 unsigned i = u_bit_scan(&mask);
710 struct pipe_resource *res = views->views[i]->base.texture;
711
712 if (res && res->target != PIPE_BUFFER) {
713 struct r600_texture *rtex = (struct r600_texture *)res;
714
715 if (rtex->cmask.size) {
716 views->compressed_colortex_mask |= 1 << i;
717 } else {
718 views->compressed_colortex_mask &= ~(1 << i);
719 }
720 }
721 }
722 }
723
724 static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
725 enum pipe_shader_type shader)
726 {
727 const struct r600_context *rctx = (struct r600_context *)ctx;
728 int value = 0;
729 switch (shader) {
730 case PIPE_SHADER_FRAGMENT:
731 case PIPE_SHADER_COMPUTE:
732 default:
733 break;
734 case PIPE_SHADER_VERTEX:
735 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
736 break;
737 case PIPE_SHADER_GEOMETRY:
738 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
739 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
740 break;
741 case PIPE_SHADER_TESS_EVAL:
742 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
743 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
744 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0);
745 break;
746 case PIPE_SHADER_TESS_CTRL:
747 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
748 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
749 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0) +
750 rctx->tes_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
751 break;
752 }
753 return value;
754 }
755
756 static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
757 {
758 uint32_t mask = images->enabled_mask;
759
760 while (mask) {
761 unsigned i = u_bit_scan(&mask);
762 struct pipe_resource *res = images->views[i].base.resource;
763
764 if (res && res->target != PIPE_BUFFER) {
765 struct r600_texture *rtex = (struct r600_texture *)res;
766
767 if (rtex->cmask.size) {
768 images->compressed_colortex_mask |= 1 << i;
769 } else {
770 images->compressed_colortex_mask &= ~(1 << i);
771 }
772 }
773 }
774 }
775
776 /* Compute the key for the hw shader variant */
777 static inline void r600_shader_selector_key(const struct pipe_context *ctx,
778 const struct r600_pipe_shader_selector *sel,
779 union r600_shader_key *key)
780 {
781 const struct r600_context *rctx = (struct r600_context *)ctx;
782 memset(key, 0, sizeof(*key));
783
784 switch (sel->type) {
785 case PIPE_SHADER_VERTEX: {
786 key->vs.as_ls = (rctx->tes_shader != NULL);
787 if (!key->vs.as_ls)
788 key->vs.as_es = (rctx->gs_shader != NULL);
789
790 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
791 key->vs.as_gs_a = true;
792 key->vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
793 }
794 key->vs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_VERTEX);
795 break;
796 }
797 case PIPE_SHADER_GEOMETRY:
798 key->gs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_GEOMETRY);
799 key->gs.tri_strip_adj_fix = rctx->gs_tri_strip_adj_fix;
800 break;
801 case PIPE_SHADER_FRAGMENT: {
802 if (rctx->ps_shader->info.images_declared)
803 key->ps.image_size_const_offset = util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask);
804 key->ps.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_FRAGMENT);
805 key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
806 key->ps.alpha_to_one = rctx->alpha_to_one &&
807 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
808 !rctx->framebuffer.cb0_is_integer;
809 key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
810 /* Dual-source blending only makes sense with nr_cbufs == 1. */
811 if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend)
812 key->ps.nr_cbufs = 2;
813 break;
814 }
815 case PIPE_SHADER_TESS_EVAL:
816 key->tes.as_es = (rctx->gs_shader != NULL);
817 key->tes.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_EVAL);
818 break;
819 case PIPE_SHADER_TESS_CTRL:
820 key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
821 key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_CTRL);
822 break;
823 case PIPE_SHADER_COMPUTE:
824 break;
825 default:
826 assert(0);
827 }
828 }
829
830 /* Select the hw shader variant depending on the current state.
831 * (*dirty) is set to 1 if current variant was changed */
832 int r600_shader_select(struct pipe_context *ctx,
833 struct r600_pipe_shader_selector* sel,
834 bool *dirty)
835 {
836 union r600_shader_key key;
837 struct r600_pipe_shader * shader = NULL;
838 int r;
839
840 r600_shader_selector_key(ctx, sel, &key);
841
842 /* Check if we don't need to change anything.
843 * This path is also used for most shaders that don't need multiple
844 * variants, it will cost just a computation of the key and this
845 * test. */
846 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
847 return 0;
848 }
849
850 /* lookup if we have other variants in the list */
851 if (sel->num_shaders > 1) {
852 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
853
854 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
855 p = c;
856 c = c->next_variant;
857 }
858
859 if (c) {
860 p->next_variant = c->next_variant;
861 shader = c;
862 }
863 }
864
865 if (unlikely(!shader)) {
866 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
867 shader->selector = sel;
868
869 r = r600_pipe_shader_create(ctx, shader, key);
870 if (unlikely(r)) {
871 R600_ERR("Failed to build shader variant (type=%u) %d\n",
872 sel->type, r);
873 sel->current = NULL;
874 FREE(shader);
875 return r;
876 }
877
878 /* We don't know the value of nr_ps_max_color_exports until we built
879 * at least one variant, so we may need to recompute the key after
880 * building first variant. */
881 if (sel->type == PIPE_SHADER_FRAGMENT &&
882 sel->num_shaders == 0) {
883 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
884 r600_shader_selector_key(ctx, sel, &key);
885 }
886
887 memcpy(&shader->key, &key, sizeof(key));
888 sel->num_shaders++;
889 }
890
891 if (dirty)
892 *dirty = true;
893
894 shader->next_variant = sel->current;
895 sel->current = shader;
896
897 return 0;
898 }
899
900 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
901 const struct tgsi_token *tokens,
902 unsigned pipe_shader_type)
903 {
904 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
905 int i;
906
907 sel->type = pipe_shader_type;
908 sel->tokens = tgsi_dup_tokens(tokens);
909 tgsi_scan_shader(tokens, &sel->info);
910 return sel;
911 }
912
913 static void *r600_create_shader_state(struct pipe_context *ctx,
914 const struct pipe_shader_state *state,
915 unsigned pipe_shader_type)
916 {
917 int i;
918 struct r600_pipe_shader_selector *sel = r600_create_shader_state_tokens(ctx, state->tokens, pipe_shader_type);
919
920 sel->so = state->stream_output;
921
922 switch (pipe_shader_type) {
923 case PIPE_SHADER_GEOMETRY:
924 sel->gs_output_prim =
925 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
926 sel->gs_max_out_vertices =
927 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
928 sel->gs_num_invocations =
929 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
930 break;
931 case PIPE_SHADER_VERTEX:
932 case PIPE_SHADER_TESS_CTRL:
933 sel->lds_patch_outputs_written_mask = 0;
934 sel->lds_outputs_written_mask = 0;
935
936 for (i = 0; i < sel->info.num_outputs; i++) {
937 unsigned name = sel->info.output_semantic_name[i];
938 unsigned index = sel->info.output_semantic_index[i];
939
940 switch (name) {
941 case TGSI_SEMANTIC_TESSINNER:
942 case TGSI_SEMANTIC_TESSOUTER:
943 case TGSI_SEMANTIC_PATCH:
944 sel->lds_patch_outputs_written_mask |=
945 1ull << r600_get_lds_unique_index(name, index);
946 break;
947 default:
948 sel->lds_outputs_written_mask |=
949 1ull << r600_get_lds_unique_index(name, index);
950 }
951 }
952 break;
953 default:
954 break;
955 }
956
957 return sel;
958 }
959
960 static void *r600_create_ps_state(struct pipe_context *ctx,
961 const struct pipe_shader_state *state)
962 {
963 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
964 }
965
966 static void *r600_create_vs_state(struct pipe_context *ctx,
967 const struct pipe_shader_state *state)
968 {
969 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
970 }
971
972 static void *r600_create_gs_state(struct pipe_context *ctx,
973 const struct pipe_shader_state *state)
974 {
975 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
976 }
977
978 static void *r600_create_tcs_state(struct pipe_context *ctx,
979 const struct pipe_shader_state *state)
980 {
981 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
982 }
983
984 static void *r600_create_tes_state(struct pipe_context *ctx,
985 const struct pipe_shader_state *state)
986 {
987 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
988 }
989
990 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
991 {
992 struct r600_context *rctx = (struct r600_context *)ctx;
993
994 if (!state)
995 state = rctx->dummy_pixel_shader;
996
997 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
998 }
999
1000 static struct tgsi_shader_info *r600_get_vs_info(struct r600_context *rctx)
1001 {
1002 if (rctx->gs_shader)
1003 return &rctx->gs_shader->info;
1004 else if (rctx->tes_shader)
1005 return &rctx->tes_shader->info;
1006 else if (rctx->vs_shader)
1007 return &rctx->vs_shader->info;
1008 else
1009 return NULL;
1010 }
1011
1012 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
1013 {
1014 struct r600_context *rctx = (struct r600_context *)ctx;
1015
1016 if (!state || rctx->vs_shader == state)
1017 return;
1018
1019 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
1020 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1021 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
1022 }
1023
1024 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
1025 {
1026 struct r600_context *rctx = (struct r600_context *)ctx;
1027
1028 if (state == rctx->gs_shader)
1029 return;
1030
1031 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
1032 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1033
1034 if (!state)
1035 return;
1036 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
1037 }
1038
1039 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
1040 {
1041 struct r600_context *rctx = (struct r600_context *)ctx;
1042
1043 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
1044 }
1045
1046 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
1047 {
1048 struct r600_context *rctx = (struct r600_context *)ctx;
1049
1050 if (state == rctx->tes_shader)
1051 return;
1052
1053 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
1054 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1055
1056 if (!state)
1057 return;
1058 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1059 }
1060
1061 void r600_delete_shader_selector(struct pipe_context *ctx,
1062 struct r600_pipe_shader_selector *sel)
1063 {
1064 struct r600_pipe_shader *p = sel->current, *c;
1065 while (p) {
1066 c = p->next_variant;
1067 r600_pipe_shader_destroy(ctx, p);
1068 free(p);
1069 p = c;
1070 }
1071
1072 free(sel->tokens);
1073 free(sel);
1074 }
1075
1076
1077 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1078 {
1079 struct r600_context *rctx = (struct r600_context *)ctx;
1080 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1081
1082 if (rctx->ps_shader == sel) {
1083 rctx->ps_shader = NULL;
1084 }
1085
1086 r600_delete_shader_selector(ctx, sel);
1087 }
1088
1089 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1090 {
1091 struct r600_context *rctx = (struct r600_context *)ctx;
1092 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1093
1094 if (rctx->vs_shader == sel) {
1095 rctx->vs_shader = NULL;
1096 }
1097
1098 r600_delete_shader_selector(ctx, sel);
1099 }
1100
1101
1102 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1103 {
1104 struct r600_context *rctx = (struct r600_context *)ctx;
1105 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1106
1107 if (rctx->gs_shader == sel) {
1108 rctx->gs_shader = NULL;
1109 }
1110
1111 r600_delete_shader_selector(ctx, sel);
1112 }
1113
1114 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1115 {
1116 struct r600_context *rctx = (struct r600_context *)ctx;
1117 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1118
1119 if (rctx->tcs_shader == sel) {
1120 rctx->tcs_shader = NULL;
1121 }
1122
1123 r600_delete_shader_selector(ctx, sel);
1124 }
1125
1126 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1127 {
1128 struct r600_context *rctx = (struct r600_context *)ctx;
1129 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1130
1131 if (rctx->tes_shader == sel) {
1132 rctx->tes_shader = NULL;
1133 }
1134
1135 r600_delete_shader_selector(ctx, sel);
1136 }
1137
1138 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1139 {
1140 if (state->dirty_mask) {
1141 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1142 : util_bitcount(state->dirty_mask)*19;
1143 r600_mark_atom_dirty(rctx, &state->atom);
1144 }
1145 }
1146
1147 static void r600_set_constant_buffer(struct pipe_context *ctx,
1148 enum pipe_shader_type shader, uint index,
1149 const struct pipe_constant_buffer *input)
1150 {
1151 struct r600_context *rctx = (struct r600_context *)ctx;
1152 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1153 struct pipe_constant_buffer *cb;
1154 const uint8_t *ptr;
1155
1156 /* Note that the state tracker can unbind constant buffers by
1157 * passing NULL here.
1158 */
1159 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1160 state->enabled_mask &= ~(1 << index);
1161 state->dirty_mask &= ~(1 << index);
1162 pipe_resource_reference(&state->cb[index].buffer, NULL);
1163 return;
1164 }
1165
1166 cb = &state->cb[index];
1167 cb->buffer_size = input->buffer_size;
1168
1169 ptr = input->user_buffer;
1170
1171 if (ptr) {
1172 /* Upload the user buffer. */
1173 if (R600_BIG_ENDIAN) {
1174 uint32_t *tmpPtr;
1175 unsigned i, size = input->buffer_size;
1176
1177 if (!(tmpPtr = malloc(size))) {
1178 R600_ERR("Failed to allocate BE swap buffer.\n");
1179 return;
1180 }
1181
1182 for (i = 0; i < size / 4; ++i) {
1183 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1184 }
1185
1186 u_upload_data(ctx->stream_uploader, 0, size, 256,
1187 tmpPtr, &cb->buffer_offset, &cb->buffer);
1188 free(tmpPtr);
1189 } else {
1190 u_upload_data(ctx->stream_uploader, 0,
1191 input->buffer_size, 256, ptr,
1192 &cb->buffer_offset, &cb->buffer);
1193 }
1194 /* account it in gtt */
1195 rctx->b.gtt += input->buffer_size;
1196 } else {
1197 /* Setup the hw buffer. */
1198 cb->buffer_offset = input->buffer_offset;
1199 pipe_resource_reference(&cb->buffer, input->buffer);
1200 r600_context_add_resource_size(ctx, input->buffer);
1201 }
1202
1203 state->enabled_mask |= 1 << index;
1204 state->dirty_mask |= 1 << index;
1205 r600_constant_buffers_dirty(rctx, state);
1206 }
1207
1208 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1209 {
1210 struct r600_context *rctx = (struct r600_context*)pipe;
1211
1212 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1213 return;
1214
1215 rctx->sample_mask.sample_mask = sample_mask;
1216 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1217 }
1218
1219 static void r600_update_driver_const_buffers(struct r600_context *rctx)
1220 {
1221 int sh, size;
1222 void *ptr;
1223 struct pipe_constant_buffer cb;
1224 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
1225 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1226 if (!info->vs_ucp_dirty &&
1227 !info->texture_const_dirty &&
1228 !info->ps_sample_pos_dirty)
1229 continue;
1230
1231 ptr = info->constants;
1232 size = info->alloc_size;
1233 if (info->vs_ucp_dirty) {
1234 assert(sh == PIPE_SHADER_VERTEX);
1235 if (!size) {
1236 ptr = rctx->clip_state.state.ucp;
1237 size = R600_UCP_SIZE;
1238 } else {
1239 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1240 }
1241 info->vs_ucp_dirty = false;
1242 }
1243
1244 if (info->ps_sample_pos_dirty) {
1245 assert(sh == PIPE_SHADER_FRAGMENT);
1246 if (!size) {
1247 ptr = rctx->sample_positions;
1248 size = R600_UCP_SIZE;
1249 } else {
1250 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1251 }
1252 info->ps_sample_pos_dirty = false;
1253 }
1254
1255 if (info->texture_const_dirty) {
1256 assert (ptr);
1257 assert (size);
1258 if (sh == PIPE_SHADER_VERTEX)
1259 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1260 if (sh == PIPE_SHADER_FRAGMENT)
1261 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1262 }
1263 info->texture_const_dirty = false;
1264
1265 cb.buffer = NULL;
1266 cb.user_buffer = ptr;
1267 cb.buffer_offset = 0;
1268 cb.buffer_size = size;
1269 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1270 pipe_resource_reference(&cb.buffer, NULL);
1271 }
1272 }
1273
1274 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1275 int array_size, uint32_t *base_offset)
1276 {
1277 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1278 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1279 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1280 info->alloc_size = array_size + R600_UCP_SIZE;
1281 }
1282 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1283 info->texture_const_dirty = true;
1284 *base_offset = R600_UCP_SIZE;
1285 return info->constants;
1286 }
1287 /*
1288 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1289 * doesn't require full swizzles it does need masking and setting alpha
1290 * to one, so we setup a set of 5 constants with the masks + alpha value
1291 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1292 * then OR the alpha with the value given here.
1293 * We use a 6th constant to store the txq buffer size in
1294 * we use 7th slot for number of cube layers in a cube map array.
1295 */
1296 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1297 {
1298 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1299 int bits;
1300 uint32_t array_size;
1301 int i, j;
1302 uint32_t *constants;
1303 uint32_t base_offset;
1304 if (!samplers->views.dirty_buffer_constants)
1305 return;
1306
1307 samplers->views.dirty_buffer_constants = FALSE;
1308
1309 bits = util_last_bit(samplers->views.enabled_mask);
1310 array_size = bits * 8 * sizeof(uint32_t) * 4;
1311
1312 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1313
1314 for (i = 0; i < bits; i++) {
1315 if (samplers->views.enabled_mask & (1 << i)) {
1316 int offset = (base_offset / 4) + i * 8;
1317 const struct util_format_description *desc;
1318 desc = util_format_description(samplers->views.views[i]->base.format);
1319
1320 for (j = 0; j < 4; j++)
1321 if (j < desc->nr_channels)
1322 constants[offset+j] = 0xffffffff;
1323 else
1324 constants[offset+j] = 0x0;
1325 if (desc->nr_channels < 4) {
1326 if (desc->channel[0].pure_integer)
1327 constants[offset+4] = 1;
1328 else
1329 constants[offset+4] = fui(1.0);
1330 } else
1331 constants[offset + 4] = 0;
1332
1333 constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1334 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1335 }
1336 }
1337
1338 }
1339
1340 /* On evergreen we store two values
1341 * 1. buffer size for TXQ
1342 * 2. number of cube layers in a cube map array.
1343 */
1344 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1345 {
1346 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1347 struct r600_image_state *images = NULL;
1348 struct r600_image_state *buffers = NULL;
1349 int bits, sview_bits, img_bits;
1350 uint32_t array_size;
1351 int i;
1352 uint32_t *constants;
1353 uint32_t base_offset;
1354
1355 if (shader_type == PIPE_SHADER_FRAGMENT) {
1356 images = &rctx->fragment_images;
1357 buffers = &rctx->fragment_buffers;
1358 }
1359
1360 if (!samplers->views.dirty_buffer_constants &&
1361 (images && !images->dirty_buffer_constants) &&
1362 (buffers && !buffers->dirty_buffer_constants))
1363 return;
1364
1365 if (images)
1366 images->dirty_buffer_constants = FALSE;
1367 if (buffers)
1368 buffers->dirty_buffer_constants = FALSE;
1369 samplers->views.dirty_buffer_constants = FALSE;
1370
1371 bits = sview_bits = util_last_bit(samplers->views.enabled_mask);
1372 if (images)
1373 bits += util_last_bit(images->enabled_mask);
1374 img_bits = bits;
1375 if (buffers)
1376 bits += util_last_bit(buffers->enabled_mask);
1377 array_size = bits * 2 * sizeof(uint32_t) * 4;
1378
1379 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1380 &base_offset);
1381
1382 for (i = 0; i < sview_bits; i++) {
1383 if (samplers->views.enabled_mask & (1 << i)) {
1384 uint32_t offset = (base_offset / 4) + i * 2;
1385 constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1386 constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
1387 }
1388 }
1389 if (images) {
1390 for (i = sview_bits; i < img_bits; i++) {
1391 int idx = i - sview_bits;
1392 if (images->enabled_mask & (1 << idx)) {
1393 uint32_t offset = (base_offset / 4) + i * 2;
1394 constants[offset] = images->views[i].base.resource->width0 / util_format_get_blocksize(images->views[i].base.format);
1395 constants[offset + 1] = images->views[i].base.resource->array_size / 6;
1396 }
1397 }
1398 }
1399 if (buffers) {
1400 for (i = img_bits; i < bits; i++) {
1401 int idx = i - img_bits;
1402 if (buffers->enabled_mask & (1 << idx)) {
1403 uint32_t offset = (base_offset / 4) + i * 2;
1404 constants[offset] = buffers->views[i].base.resource->width0 / util_format_get_blocksize(buffers->views[i].base.format);
1405 constants[offset + 1] = 0;
1406 }
1407 }
1408 }
1409 }
1410
1411 /* set sample xy locations as array of fragment shader constants */
1412 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1413 {
1414 int i;
1415 struct pipe_context *ctx = &rctx->b.b;
1416
1417 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1418 assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4);
1419
1420 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1421 for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1422 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1423 /* Also fill in center-zeroed positions used for interpolateAtSample */
1424 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1425 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1426 }
1427
1428 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1429 }
1430
1431 static void update_shader_atom(struct pipe_context *ctx,
1432 struct r600_shader_state *state,
1433 struct r600_pipe_shader *shader)
1434 {
1435 struct r600_context *rctx = (struct r600_context *)ctx;
1436
1437 state->shader = shader;
1438 if (shader) {
1439 state->atom.num_dw = shader->command_buffer.num_dw;
1440 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1441 } else {
1442 state->atom.num_dw = 0;
1443 }
1444 r600_mark_atom_dirty(rctx, &state->atom);
1445 }
1446
1447 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1448 {
1449 if (rctx->shader_stages.geom_enable != enable) {
1450 rctx->shader_stages.geom_enable = enable;
1451 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1452 }
1453
1454 if (rctx->gs_rings.enable != enable) {
1455 rctx->gs_rings.enable = enable;
1456 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1457
1458 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1459 unsigned size = 0x1C000;
1460 rctx->gs_rings.esgs_ring.buffer =
1461 pipe_buffer_create(rctx->b.b.screen, 0,
1462 PIPE_USAGE_DEFAULT, size);
1463 rctx->gs_rings.esgs_ring.buffer_size = size;
1464
1465 size = 0x4000000;
1466
1467 rctx->gs_rings.gsvs_ring.buffer =
1468 pipe_buffer_create(rctx->b.b.screen, 0,
1469 PIPE_USAGE_DEFAULT, size);
1470 rctx->gs_rings.gsvs_ring.buffer_size = size;
1471 }
1472
1473 if (enable) {
1474 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1475 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1476 if (rctx->tes_shader) {
1477 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1478 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1479 } else {
1480 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1481 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1482 }
1483 } else {
1484 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1485 R600_GS_RING_CONST_BUFFER, NULL);
1486 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1487 R600_GS_RING_CONST_BUFFER, NULL);
1488 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1489 R600_GS_RING_CONST_BUFFER, NULL);
1490 }
1491 }
1492 }
1493
1494 static void r600_update_clip_state(struct r600_context *rctx,
1495 struct r600_pipe_shader *current)
1496 {
1497 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1498 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1499 current->shader.cull_dist_write != rctx->clip_misc_state.cull_dist_write ||
1500 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1501 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1502 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1503 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1504 rctx->clip_misc_state.cull_dist_write = current->shader.cull_dist_write;
1505 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1506 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1507 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1508 }
1509 }
1510
1511 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1512 {
1513 struct ureg_src const0, const1;
1514 struct ureg_dst tessouter, tessinner;
1515 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1516
1517 if (!ureg)
1518 return; /* if we get here, we're screwed */
1519
1520 assert(!rctx->fixed_func_tcs_shader);
1521
1522 ureg_DECL_constant2D(ureg, 0, 3, R600_LDS_INFO_CONST_BUFFER);
1523 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 2),
1524 R600_LDS_INFO_CONST_BUFFER);
1525 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 3),
1526 R600_LDS_INFO_CONST_BUFFER);
1527
1528 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1529 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1530
1531 ureg_MOV(ureg, tessouter, const0);
1532 ureg_MOV(ureg, tessinner, const1);
1533 ureg_END(ureg);
1534
1535 rctx->fixed_func_tcs_shader =
1536 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1537 }
1538
1539 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only)
1540 {
1541 unsigned i;
1542 unsigned counter;
1543
1544 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1545 if (counter != rctx->b.last_compressed_colortex_counter) {
1546 rctx->b.last_compressed_colortex_counter = counter;
1547
1548 if (compute_only) {
1549 r600_update_compressed_colortex_mask(&rctx->samplers[PIPE_SHADER_COMPUTE].views);
1550 } else {
1551 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1552 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1553 }
1554 }
1555 if (!compute_only)
1556 r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
1557 r600_update_compressed_colortex_mask_images(&rctx->compute_images);
1558 }
1559
1560 /* Decompress textures if needed. */
1561 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1562 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1563
1564 if (compute_only)
1565 if (i != PIPE_SHADER_COMPUTE)
1566 continue;
1567 if (views->compressed_depthtex_mask) {
1568 r600_decompress_depth_textures(rctx, views);
1569 }
1570 if (views->compressed_colortex_mask) {
1571 r600_decompress_color_textures(rctx, views);
1572 }
1573 }
1574
1575 {
1576 struct r600_image_state *istate;
1577
1578 if (!compute_only) {
1579 istate = &rctx->fragment_images;
1580 if (istate->compressed_depthtex_mask)
1581 r600_decompress_depth_images(rctx, istate);
1582 if (istate->compressed_colortex_mask)
1583 r600_decompress_color_images(rctx, istate);
1584 }
1585
1586 istate = &rctx->compute_images;
1587 if (istate->compressed_depthtex_mask)
1588 r600_decompress_depth_images(rctx, istate);
1589 if (istate->compressed_colortex_mask)
1590 r600_decompress_color_images(rctx, istate);
1591 }
1592 }
1593
1594 #define SELECT_SHADER_OR_FAIL(x) do { \
1595 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1596 if (unlikely(!rctx->x##_shader->current)) \
1597 return false; \
1598 } while(0)
1599
1600 #define UPDATE_SHADER(hw, sw) do { \
1601 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1602 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1603 } while(0)
1604
1605 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1606 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1607 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1608 clip_so_current = rctx->sw##_shader->current; \
1609 } \
1610 } while(0)
1611
1612 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1613 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1614 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1615 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1616 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1617 } \
1618 } while(0)
1619
1620 #define SET_NULL_SHADER(hw) do { \
1621 if (rctx->hw_shader_stages[(hw)].shader) \
1622 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1623 } while (0)
1624
1625 static bool r600_update_derived_state(struct r600_context *rctx)
1626 {
1627 struct pipe_context * ctx = (struct pipe_context*)rctx;
1628 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1629 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1630 bool blend_disable;
1631 bool need_buf_const;
1632 struct r600_pipe_shader *clip_so_current = NULL;
1633
1634 if (!rctx->blitter->running)
1635 r600_update_compressed_resource_state(rctx, false);
1636
1637 SELECT_SHADER_OR_FAIL(ps);
1638
1639 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1640
1641 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1642
1643 if (rctx->gs_shader)
1644 SELECT_SHADER_OR_FAIL(gs);
1645
1646 /* Hull Shader */
1647 if (rctx->tcs_shader) {
1648 SELECT_SHADER_OR_FAIL(tcs);
1649
1650 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1651 } else if (rctx->tes_shader) {
1652 if (!rctx->fixed_func_tcs_shader) {
1653 r600_generate_fixed_func_tcs(rctx);
1654 if (!rctx->fixed_func_tcs_shader)
1655 return false;
1656
1657 }
1658 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1659
1660 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1661 } else
1662 SET_NULL_SHADER(EG_HW_STAGE_HS);
1663
1664 if (rctx->tes_shader) {
1665 SELECT_SHADER_OR_FAIL(tes);
1666 }
1667
1668 SELECT_SHADER_OR_FAIL(vs);
1669
1670 if (rctx->gs_shader) {
1671 if (!rctx->shader_stages.geom_enable) {
1672 rctx->shader_stages.geom_enable = true;
1673 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1674 }
1675
1676 /* gs_shader provides GS and VS (copy shader) */
1677 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1678
1679 /* vs_shader is used as ES */
1680
1681 if (rctx->tes_shader) {
1682 /* VS goes to LS, TES goes to ES */
1683 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1684 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1685 } else {
1686 /* vs_shader is used as ES */
1687 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1688 SET_NULL_SHADER(EG_HW_STAGE_LS);
1689 }
1690 } else {
1691 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1692 SET_NULL_SHADER(R600_HW_STAGE_GS);
1693 SET_NULL_SHADER(R600_HW_STAGE_ES);
1694 rctx->shader_stages.geom_enable = false;
1695 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1696 }
1697
1698 if (rctx->tes_shader) {
1699 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1700 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1701 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1702 } else {
1703 SET_NULL_SHADER(EG_HW_STAGE_LS);
1704 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1705 }
1706 }
1707
1708 /* Update clip misc state. */
1709 if (clip_so_current) {
1710 r600_update_clip_state(rctx, clip_so_current);
1711 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1712 }
1713
1714 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1715 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1716 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1717
1718 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1719 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1720 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1721 }
1722
1723 if (rctx->b.chip_class <= R700) {
1724 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1725
1726 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1727 rctx->cb_misc_state.multiwrite = multiwrite;
1728 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1729 }
1730 }
1731
1732 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1733 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1734 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1735
1736 if (rctx->b.chip_class >= EVERGREEN)
1737 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1738 else
1739 r600_update_ps_state(ctx, rctx->ps_shader->current);
1740 }
1741
1742 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1743 }
1744 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
1745
1746 if (rctx->b.chip_class >= EVERGREEN) {
1747 evergreen_update_db_shader_control(rctx);
1748 } else {
1749 r600_update_db_shader_control(rctx);
1750 }
1751
1752 /* on R600 we stuff masks + txq info into one constant buffer */
1753 /* on evergreen we only need a txq info one */
1754 if (rctx->ps_shader) {
1755 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1756 if (need_buf_const) {
1757 if (rctx->b.chip_class < EVERGREEN)
1758 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1759 else
1760 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1761 }
1762 }
1763
1764 if (rctx->vs_shader) {
1765 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1766 if (need_buf_const) {
1767 if (rctx->b.chip_class < EVERGREEN)
1768 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1769 else
1770 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1771 }
1772 }
1773
1774 if (rctx->gs_shader) {
1775 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1776 if (need_buf_const) {
1777 if (rctx->b.chip_class < EVERGREEN)
1778 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1779 else
1780 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1781 }
1782 }
1783
1784 r600_update_driver_const_buffers(rctx);
1785
1786 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1787 if (!r600_adjust_gprs(rctx)) {
1788 /* discard rendering */
1789 return false;
1790 }
1791 }
1792
1793 if (rctx->b.chip_class == EVERGREEN) {
1794 if (!evergreen_adjust_gprs(rctx)) {
1795 /* discard rendering */
1796 return false;
1797 }
1798 }
1799
1800 blend_disable = (rctx->dual_src_blend &&
1801 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1802
1803 if (blend_disable != rctx->force_blend_disable) {
1804 rctx->force_blend_disable = blend_disable;
1805 r600_bind_blend_state_internal(rctx,
1806 rctx->blend_state.cso,
1807 blend_disable);
1808 }
1809
1810 return true;
1811 }
1812
1813 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1814 {
1815 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1816 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1817
1818 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1819 state->pa_cl_clip_cntl |
1820 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1821 S_028810_CLIP_DISABLE(state->clip_disable));
1822 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1823 state->pa_cl_vs_out_cntl |
1824 (state->clip_plane_enable & state->clip_dist_write) |
1825 (state->cull_dist_write << 8));
1826 /* reuse needs to be set off if we write oViewport */
1827 if (rctx->b.chip_class >= EVERGREEN)
1828 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
1829 S_028AB4_REUSE_OFF(state->vs_out_viewport));
1830 }
1831
1832 /* rast_prim is the primitive type after GS. */
1833 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
1834 {
1835 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1836 enum pipe_prim_type rast_prim = rctx->current_rast_prim;
1837
1838 /* Skip this if not rendering lines. */
1839 if (rast_prim != PIPE_PRIM_LINES &&
1840 rast_prim != PIPE_PRIM_LINE_LOOP &&
1841 rast_prim != PIPE_PRIM_LINE_STRIP &&
1842 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
1843 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
1844 return;
1845
1846 if (rast_prim == rctx->last_rast_prim)
1847 return;
1848
1849 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1850 * reset the stipple pattern at each packet (line strips, line loops).
1851 */
1852 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1853 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2) |
1854 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1855 rctx->last_rast_prim = rast_prim;
1856 }
1857
1858 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1859 {
1860 struct r600_context *rctx = (struct r600_context *)ctx;
1861 struct pipe_resource *indexbuf = info->has_user_indices ? NULL : info->index.resource;
1862 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1863 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
1864 bool has_user_indices = info->has_user_indices;
1865 uint64_t mask;
1866 unsigned num_patches, dirty_tex_counter, index_offset = 0;
1867 unsigned index_size = info->index_size;
1868 int index_bias;
1869 struct r600_shader_atomic combined_atomics[8];
1870 uint8_t atomic_used_mask;
1871
1872 if (!info->indirect && !info->count && (index_size || !info->count_from_stream_output)) {
1873 return;
1874 }
1875
1876 if (unlikely(!rctx->vs_shader)) {
1877 assert(0);
1878 return;
1879 }
1880 if (unlikely(!rctx->ps_shader &&
1881 (!rctx->rasterizer || !rctx->rasterizer->rasterizer_discard))) {
1882 assert(0);
1883 return;
1884 }
1885
1886 /* make sure that the gfx ring is only one active */
1887 if (radeon_emitted(rctx->b.dma.cs, 0)) {
1888 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1889 }
1890
1891 /* Re-emit the framebuffer state if needed. */
1892 dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
1893 if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) {
1894 rctx->b.last_dirty_tex_counter = dirty_tex_counter;
1895 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1896 rctx->framebuffer.do_update_surf_dirtiness = true;
1897 }
1898
1899 if (rctx->gs_shader) {
1900 /* Determine whether the GS triangle strip adjacency fix should
1901 * be applied. Rotate every other triangle if
1902 * - triangle strips with adjacency are fed to the GS and
1903 * - primitive restart is disabled (the rotation doesn't help
1904 * when the restart occurs after an odd number of triangles).
1905 */
1906 bool gs_tri_strip_adj_fix =
1907 !rctx->tes_shader &&
1908 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1909 !info->primitive_restart;
1910 if (gs_tri_strip_adj_fix != rctx->gs_tri_strip_adj_fix)
1911 rctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1912 }
1913 if (!r600_update_derived_state(rctx)) {
1914 /* useless to render because current rendering command
1915 * can't be achieved
1916 */
1917 return;
1918 }
1919
1920 rctx->current_rast_prim = (rctx->gs_shader)? rctx->gs_shader->gs_output_prim
1921 : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
1922 : info->mode;
1923
1924 if (rctx->b.chip_class >= EVERGREEN)
1925 evergreen_emit_atomic_buffer_setup(rctx, NULL, combined_atomics, &atomic_used_mask);
1926
1927 if (index_size) {
1928 index_offset += info->start * index_size;
1929
1930 /* Translate 8-bit indices to 16-bit. */
1931 if (unlikely(index_size == 1)) {
1932 struct pipe_resource *out_buffer = NULL;
1933 unsigned out_offset;
1934 void *ptr;
1935 unsigned start, count;
1936
1937 if (likely(!info->indirect)) {
1938 start = 0;
1939 count = info->count;
1940 }
1941 else {
1942 /* Have to get start/count from indirect buffer, slow path ahead... */
1943 struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect->buffer;
1944 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
1945 PIPE_TRANSFER_READ);
1946 if (data) {
1947 data += info->indirect->offset / sizeof(unsigned);
1948 start = data[2] * index_size;
1949 count = data[0];
1950 }
1951 else {
1952 start = 0;
1953 count = 0;
1954 }
1955 }
1956
1957 u_upload_alloc(ctx->stream_uploader, start, count * 2,
1958 256, &out_offset, &out_buffer, &ptr);
1959 if (unlikely(!ptr))
1960 return;
1961
1962 util_shorten_ubyte_elts_to_userptr(
1963 &rctx->b.b, info, 0, 0, index_offset, count, ptr);
1964
1965 indexbuf = out_buffer;
1966 index_offset = out_offset;
1967 index_size = 2;
1968 has_user_indices = false;
1969 }
1970
1971 /* Upload the index buffer.
1972 * The upload is skipped for small index counts on little-endian machines
1973 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1974 * Indirect draws never use immediate indices.
1975 * Note: Instanced rendering in combination with immediate indices hangs. */
1976 if (has_user_indices && (R600_BIG_ENDIAN || info->indirect ||
1977 info->instance_count > 1 ||
1978 info->count*index_size > 20)) {
1979 indexbuf = NULL;
1980 u_upload_data(ctx->stream_uploader, 0,
1981 info->count * index_size, 256,
1982 info->index.user, &index_offset, &indexbuf);
1983 has_user_indices = false;
1984 }
1985 index_bias = info->index_bias;
1986 } else {
1987 index_bias = info->start;
1988 }
1989
1990 /* Set the index offset and primitive restart. */
1991 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info->primitive_restart ||
1992 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info->restart_index ||
1993 rctx->vgt_state.vgt_indx_offset != index_bias ||
1994 (rctx->vgt_state.last_draw_was_indirect && !info->indirect)) {
1995 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info->primitive_restart;
1996 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info->restart_index;
1997 rctx->vgt_state.vgt_indx_offset = index_bias;
1998 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
1999 }
2000
2001 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2002 if (rctx->b.chip_class == R600) {
2003 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
2004 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2005 }
2006
2007 if (rctx->b.chip_class >= EVERGREEN)
2008 evergreen_setup_tess_constants(rctx, info, &num_patches);
2009
2010 /* Emit states. */
2011 r600_need_cs_space(rctx, has_user_indices ? 5 : 0, TRUE);
2012 r600_flush_emit(rctx);
2013
2014 mask = rctx->dirty_atoms;
2015 while (mask != 0) {
2016 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
2017 }
2018
2019 if (rctx->b.chip_class == CAYMAN) {
2020 /* Copied from radeonsi. */
2021 unsigned primgroup_size = 128; /* recommended without a GS */
2022 bool ia_switch_on_eop = false;
2023 bool partial_vs_wave = false;
2024
2025 if (rctx->gs_shader)
2026 primgroup_size = 64; /* recommended with a GS */
2027
2028 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
2029 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
2030 ia_switch_on_eop = true;
2031 }
2032
2033 if (r600_get_strmout_en(&rctx->b))
2034 partial_vs_wave = true;
2035
2036 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
2037 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
2038 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
2039 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
2040 }
2041
2042 if (rctx->b.chip_class >= EVERGREEN) {
2043 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info,
2044 num_patches);
2045
2046 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
2047 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
2048 }
2049
2050 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2051 * even though it should have no effect on those. */
2052 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
2053 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
2054 unsigned prim = info->mode;
2055
2056 if (rctx->gs_shader) {
2057 prim = rctx->gs_shader->gs_output_prim;
2058 }
2059 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
2060
2061 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
2062 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
2063 info->mode == R600_PRIM_RECTANGLE_LIST) {
2064 su_sc_mode_cntl &= C_028814_CULL_FRONT;
2065 }
2066 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
2067 }
2068
2069 /* Update start instance. */
2070 if (!info->indirect && rctx->last_start_instance != info->start_instance) {
2071 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
2072 rctx->last_start_instance = info->start_instance;
2073 }
2074
2075 /* Update the primitive type. */
2076 if (rctx->last_primitive_type != info->mode) {
2077 r600_emit_rasterizer_prim_state(rctx);
2078 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2079 r600_conv_pipe_prim(info->mode));
2080
2081 rctx->last_primitive_type = info->mode;
2082 }
2083
2084 /* Draw packets. */
2085 if (likely(!info->indirect)) {
2086 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2087 radeon_emit(cs, info->instance_count);
2088 } else {
2089 uint64_t va = r600_resource(info->indirect->buffer)->gpu_address;
2090 assert(rctx->b.chip_class >= EVERGREEN);
2091
2092 // Invalidate so non-indirect draw calls reset this state
2093 rctx->vgt_state.last_draw_was_indirect = true;
2094 rctx->last_start_instance = -1;
2095
2096 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0));
2097 radeon_emit(cs, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE);
2098 radeon_emit(cs, va);
2099 radeon_emit(cs, (va >> 32UL) & 0xFF);
2100
2101 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2102 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2103 (struct r600_resource*)info->indirect->buffer,
2104 RADEON_USAGE_READ,
2105 RADEON_PRIO_DRAW_INDIRECT));
2106 }
2107
2108 if (index_size) {
2109 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2110 radeon_emit(cs, index_size == 4 ?
2111 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
2112 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)));
2113
2114 if (has_user_indices) {
2115 unsigned size_bytes = info->count*index_size;
2116 unsigned size_dw = align(size_bytes, 4) / 4;
2117 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
2118 radeon_emit(cs, info->count);
2119 radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
2120 radeon_emit_array(cs, info->index.user, size_dw);
2121 } else {
2122 uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
2123
2124 if (likely(!info->indirect)) {
2125 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit));
2126 radeon_emit(cs, va);
2127 radeon_emit(cs, (va >> 32UL) & 0xFF);
2128 radeon_emit(cs, info->count);
2129 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2130 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2131 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2132 (struct r600_resource*)indexbuf,
2133 RADEON_USAGE_READ,
2134 RADEON_PRIO_INDEX_BUFFER));
2135 }
2136 else {
2137 uint32_t max_size = (indexbuf->width0 - index_offset) / index_size;
2138
2139 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0));
2140 radeon_emit(cs, va);
2141 radeon_emit(cs, (va >> 32UL) & 0xFF);
2142
2143 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2144 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2145 (struct r600_resource*)indexbuf,
2146 RADEON_USAGE_READ,
2147 RADEON_PRIO_INDEX_BUFFER));
2148
2149 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
2150 radeon_emit(cs, max_size);
2151
2152 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
2153 radeon_emit(cs, info->indirect->offset);
2154 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2155 }
2156 }
2157 } else {
2158 if (unlikely(info->count_from_stream_output)) {
2159 struct r600_so_target *t = (struct r600_so_target*)info->count_from_stream_output;
2160 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
2161
2162 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
2163
2164 radeon_emit(cs, PKT3(PKT3_COPY_DW, 4, 0));
2165 radeon_emit(cs, COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG);
2166 radeon_emit(cs, va & 0xFFFFFFFFUL); /* src address lo */
2167 radeon_emit(cs, (va >> 32UL) & 0xFFUL); /* src address hi */
2168 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); /* dst register */
2169 radeon_emit(cs, 0); /* unused */
2170
2171 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2172 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2173 t->buf_filled_size, RADEON_USAGE_READ,
2174 RADEON_PRIO_SO_FILLED_SIZE));
2175 }
2176
2177 if (likely(!info->indirect)) {
2178 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
2179 radeon_emit(cs, info->count);
2180 }
2181 else {
2182 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
2183 radeon_emit(cs, info->indirect->offset);
2184 }
2185 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2186 (info->count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0));
2187 }
2188
2189 /* SMX returns CONTEXT_DONE too early workaround */
2190 if (rctx->b.family == CHIP_R600 ||
2191 rctx->b.family == CHIP_RV610 ||
2192 rctx->b.family == CHIP_RV630 ||
2193 rctx->b.family == CHIP_RV635) {
2194 /* if we have gs shader or streamout
2195 we need to do a wait idle after every draw */
2196 if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
2197 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2198 }
2199 }
2200
2201 /* ES ring rolling over at EOP - workaround */
2202 if (rctx->b.chip_class == R600) {
2203 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2204 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT));
2205 }
2206
2207
2208 if (rctx->b.chip_class >= EVERGREEN)
2209 evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, &atomic_used_mask);
2210
2211 if (rctx->trace_buf)
2212 eg_trace_emit(rctx);
2213
2214 if (rctx->framebuffer.do_update_surf_dirtiness) {
2215 /* Set the depth buffer as dirty. */
2216 if (rctx->framebuffer.state.zsbuf) {
2217 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2218 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2219
2220 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2221
2222 if (rtex->surface.has_stencil)
2223 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2224 }
2225 if (rctx->framebuffer.compressed_cb_mask) {
2226 struct pipe_surface *surf;
2227 struct r600_texture *rtex;
2228 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2229
2230 do {
2231 unsigned i = u_bit_scan(&mask);
2232 surf = rctx->framebuffer.state.cbufs[i];
2233 rtex = (struct r600_texture*)surf->texture;
2234
2235 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2236
2237 } while (mask);
2238 }
2239 rctx->framebuffer.do_update_surf_dirtiness = false;
2240 }
2241
2242 if (index_size && indexbuf != info->index.resource)
2243 pipe_resource_reference(&indexbuf, NULL);
2244 rctx->b.num_draw_calls++;
2245 }
2246
2247 uint32_t r600_translate_stencil_op(int s_op)
2248 {
2249 switch (s_op) {
2250 case PIPE_STENCIL_OP_KEEP:
2251 return V_028800_STENCIL_KEEP;
2252 case PIPE_STENCIL_OP_ZERO:
2253 return V_028800_STENCIL_ZERO;
2254 case PIPE_STENCIL_OP_REPLACE:
2255 return V_028800_STENCIL_REPLACE;
2256 case PIPE_STENCIL_OP_INCR:
2257 return V_028800_STENCIL_INCR;
2258 case PIPE_STENCIL_OP_DECR:
2259 return V_028800_STENCIL_DECR;
2260 case PIPE_STENCIL_OP_INCR_WRAP:
2261 return V_028800_STENCIL_INCR_WRAP;
2262 case PIPE_STENCIL_OP_DECR_WRAP:
2263 return V_028800_STENCIL_DECR_WRAP;
2264 case PIPE_STENCIL_OP_INVERT:
2265 return V_028800_STENCIL_INVERT;
2266 default:
2267 R600_ERR("Unknown stencil op %d", s_op);
2268 assert(0);
2269 break;
2270 }
2271 return 0;
2272 }
2273
2274 uint32_t r600_translate_fill(uint32_t func)
2275 {
2276 switch(func) {
2277 case PIPE_POLYGON_MODE_FILL:
2278 return 2;
2279 case PIPE_POLYGON_MODE_LINE:
2280 return 1;
2281 case PIPE_POLYGON_MODE_POINT:
2282 return 0;
2283 default:
2284 assert(0);
2285 return 0;
2286 }
2287 }
2288
2289 unsigned r600_tex_wrap(unsigned wrap)
2290 {
2291 switch (wrap) {
2292 default:
2293 case PIPE_TEX_WRAP_REPEAT:
2294 return V_03C000_SQ_TEX_WRAP;
2295 case PIPE_TEX_WRAP_CLAMP:
2296 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2297 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2298 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2299 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2300 return V_03C000_SQ_TEX_CLAMP_BORDER;
2301 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2302 return V_03C000_SQ_TEX_MIRROR;
2303 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2304 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2305 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2306 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2307 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2308 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2309 }
2310 }
2311
2312 unsigned r600_tex_mipfilter(unsigned filter)
2313 {
2314 switch (filter) {
2315 case PIPE_TEX_MIPFILTER_NEAREST:
2316 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2317 case PIPE_TEX_MIPFILTER_LINEAR:
2318 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2319 default:
2320 case PIPE_TEX_MIPFILTER_NONE:
2321 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2322 }
2323 }
2324
2325 unsigned r600_tex_compare(unsigned compare)
2326 {
2327 switch (compare) {
2328 default:
2329 case PIPE_FUNC_NEVER:
2330 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2331 case PIPE_FUNC_LESS:
2332 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2333 case PIPE_FUNC_EQUAL:
2334 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2335 case PIPE_FUNC_LEQUAL:
2336 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2337 case PIPE_FUNC_GREATER:
2338 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2339 case PIPE_FUNC_NOTEQUAL:
2340 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2341 case PIPE_FUNC_GEQUAL:
2342 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2343 case PIPE_FUNC_ALWAYS:
2344 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2345 }
2346 }
2347
2348 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2349 {
2350 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2351 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2352 (linear_filter &&
2353 (wrap == PIPE_TEX_WRAP_CLAMP ||
2354 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2355 }
2356
2357 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2358 {
2359 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2360 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2361
2362 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2363 state->border_color.ui[2] || state->border_color.ui[3]) &&
2364 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2365 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2366 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2367 }
2368
2369 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2370 {
2371
2372 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2373 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2374
2375 if (!shader)
2376 return;
2377
2378 r600_emit_command_buffer(cs, &shader->command_buffer);
2379 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2380 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2381 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY));
2382 }
2383
2384 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2385 const unsigned char *swizzle_view,
2386 boolean vtx)
2387 {
2388 unsigned i;
2389 unsigned char swizzle[4];
2390 unsigned result = 0;
2391 const uint32_t tex_swizzle_shift[4] = {
2392 16, 19, 22, 25,
2393 };
2394 const uint32_t vtx_swizzle_shift[4] = {
2395 3, 6, 9, 12,
2396 };
2397 const uint32_t swizzle_bit[4] = {
2398 0, 1, 2, 3,
2399 };
2400 const uint32_t *swizzle_shift = tex_swizzle_shift;
2401
2402 if (vtx)
2403 swizzle_shift = vtx_swizzle_shift;
2404
2405 if (swizzle_view) {
2406 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2407 } else {
2408 memcpy(swizzle, swizzle_format, 4);
2409 }
2410
2411 /* Get swizzle. */
2412 for (i = 0; i < 4; i++) {
2413 switch (swizzle[i]) {
2414 case PIPE_SWIZZLE_Y:
2415 result |= swizzle_bit[1] << swizzle_shift[i];
2416 break;
2417 case PIPE_SWIZZLE_Z:
2418 result |= swizzle_bit[2] << swizzle_shift[i];
2419 break;
2420 case PIPE_SWIZZLE_W:
2421 result |= swizzle_bit[3] << swizzle_shift[i];
2422 break;
2423 case PIPE_SWIZZLE_0:
2424 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2425 break;
2426 case PIPE_SWIZZLE_1:
2427 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2428 break;
2429 default: /* PIPE_SWIZZLE_X */
2430 result |= swizzle_bit[0] << swizzle_shift[i];
2431 }
2432 }
2433 return result;
2434 }
2435
2436 /* texture format translate */
2437 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2438 enum pipe_format format,
2439 const unsigned char *swizzle_view,
2440 uint32_t *word4_p, uint32_t *yuv_format_p,
2441 bool do_endian_swap)
2442 {
2443 struct r600_screen *rscreen = (struct r600_screen *)screen;
2444 uint32_t result = 0, word4 = 0, yuv_format = 0;
2445 const struct util_format_description *desc;
2446 boolean uniform = TRUE;
2447 bool is_srgb_valid = FALSE;
2448 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2449 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2450 const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
2451 const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
2452 const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
2453
2454 int i;
2455 const uint32_t sign_bit[4] = {
2456 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2457 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2458 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2459 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2460 };
2461
2462 /* Need to replace the specified texture formats in case of big-endian.
2463 * These formats are formats that have channels with number of bits
2464 * not divisible by 8.
2465 * Mesa conversion functions don't swap bits for those formats, and because
2466 * we transmit this over a serial bus to the GPU (PCIe), the
2467 * bit-endianess is important!!!
2468 * In case we have an "opposite" format, just use that for the swizzling
2469 * information. If we don't have such an "opposite" format, we need
2470 * to use a fixed swizzle info instead (see below)
2471 */
2472 if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
2473 format = PIPE_FORMAT_A4R4_UNORM;
2474
2475 desc = util_format_description(format);
2476 if (!desc)
2477 goto out_unknown;
2478
2479 /* Depth and stencil swizzling is handled separately. */
2480 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2481 /* Need to check for specific texture formats that don't have
2482 * an "opposite" format we can use. For those formats, we directly
2483 * specify the swizzling, which is the LE swizzling as defined in
2484 * u_format.csv
2485 */
2486 if (do_endian_swap) {
2487 if (format == PIPE_FORMAT_L4A4_UNORM)
2488 word4 |= r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, FALSE);
2489 else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
2490 word4 |= r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, FALSE);
2491 else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || format == PIPE_FORMAT_B5G6R5_UNORM)
2492 word4 |= r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, FALSE);
2493 else
2494 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2495 } else {
2496 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2497 }
2498 }
2499
2500 /* Colorspace (return non-RGB formats directly). */
2501 switch (desc->colorspace) {
2502 /* Depth stencil formats */
2503 case UTIL_FORMAT_COLORSPACE_ZS:
2504 switch (format) {
2505 /* Depth sampler formats. */
2506 case PIPE_FORMAT_Z16_UNORM:
2507 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2508 result = FMT_16;
2509 goto out_word4;
2510 case PIPE_FORMAT_Z24X8_UNORM:
2511 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2512 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2513 result = FMT_8_24;
2514 goto out_word4;
2515 case PIPE_FORMAT_X8Z24_UNORM:
2516 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2517 if (rscreen->b.chip_class < EVERGREEN)
2518 goto out_unknown;
2519 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2520 result = FMT_24_8;
2521 goto out_word4;
2522 case PIPE_FORMAT_Z32_FLOAT:
2523 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2524 result = FMT_32_FLOAT;
2525 goto out_word4;
2526 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2527 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2528 result = FMT_X24_8_32_FLOAT;
2529 goto out_word4;
2530 /* Stencil sampler formats. */
2531 case PIPE_FORMAT_S8_UINT:
2532 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2533 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2534 result = FMT_8;
2535 goto out_word4;
2536 case PIPE_FORMAT_X24S8_UINT:
2537 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2538 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2539 result = FMT_8_24;
2540 goto out_word4;
2541 case PIPE_FORMAT_S8X24_UINT:
2542 if (rscreen->b.chip_class < EVERGREEN)
2543 goto out_unknown;
2544 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2545 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2546 result = FMT_24_8;
2547 goto out_word4;
2548 case PIPE_FORMAT_X32_S8X24_UINT:
2549 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2550 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2551 result = FMT_X24_8_32_FLOAT;
2552 goto out_word4;
2553 default:
2554 goto out_unknown;
2555 }
2556
2557 case UTIL_FORMAT_COLORSPACE_YUV:
2558 yuv_format |= (1 << 30);
2559 switch (format) {
2560 case PIPE_FORMAT_UYVY:
2561 case PIPE_FORMAT_YUYV:
2562 default:
2563 break;
2564 }
2565 goto out_unknown; /* XXX */
2566
2567 case UTIL_FORMAT_COLORSPACE_SRGB:
2568 word4 |= S_038010_FORCE_DEGAMMA(1);
2569 break;
2570
2571 default:
2572 break;
2573 }
2574
2575 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2576 switch (format) {
2577 case PIPE_FORMAT_RGTC1_SNORM:
2578 case PIPE_FORMAT_LATC1_SNORM:
2579 word4 |= sign_bit[0];
2580 case PIPE_FORMAT_RGTC1_UNORM:
2581 case PIPE_FORMAT_LATC1_UNORM:
2582 result = FMT_BC4;
2583 goto out_word4;
2584 case PIPE_FORMAT_RGTC2_SNORM:
2585 case PIPE_FORMAT_LATC2_SNORM:
2586 word4 |= sign_bit[0] | sign_bit[1];
2587 case PIPE_FORMAT_RGTC2_UNORM:
2588 case PIPE_FORMAT_LATC2_UNORM:
2589 result = FMT_BC5;
2590 goto out_word4;
2591 default:
2592 goto out_unknown;
2593 }
2594 }
2595
2596 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2597 switch (format) {
2598 case PIPE_FORMAT_DXT1_RGB:
2599 case PIPE_FORMAT_DXT1_RGBA:
2600 case PIPE_FORMAT_DXT1_SRGB:
2601 case PIPE_FORMAT_DXT1_SRGBA:
2602 result = FMT_BC1;
2603 is_srgb_valid = TRUE;
2604 goto out_word4;
2605 case PIPE_FORMAT_DXT3_RGBA:
2606 case PIPE_FORMAT_DXT3_SRGBA:
2607 result = FMT_BC2;
2608 is_srgb_valid = TRUE;
2609 goto out_word4;
2610 case PIPE_FORMAT_DXT5_RGBA:
2611 case PIPE_FORMAT_DXT5_SRGBA:
2612 result = FMT_BC3;
2613 is_srgb_valid = TRUE;
2614 goto out_word4;
2615 default:
2616 goto out_unknown;
2617 }
2618 }
2619
2620 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2621 if (rscreen->b.chip_class < EVERGREEN)
2622 goto out_unknown;
2623
2624 switch (format) {
2625 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2626 case PIPE_FORMAT_BPTC_SRGBA:
2627 result = FMT_BC7;
2628 is_srgb_valid = TRUE;
2629 goto out_word4;
2630 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2631 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2632 /* fall through */
2633 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2634 result = FMT_BC6;
2635 goto out_word4;
2636 default:
2637 goto out_unknown;
2638 }
2639 }
2640
2641 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2642 switch (format) {
2643 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2644 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2645 result = FMT_GB_GR;
2646 goto out_word4;
2647 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2648 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2649 result = FMT_BG_RG;
2650 goto out_word4;
2651 default:
2652 goto out_unknown;
2653 }
2654 }
2655
2656 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2657 result = FMT_5_9_9_9_SHAREDEXP;
2658 goto out_word4;
2659 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2660 result = FMT_10_11_11_FLOAT;
2661 goto out_word4;
2662 }
2663
2664
2665 for (i = 0; i < desc->nr_channels; i++) {
2666 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2667 word4 |= sign_bit[i];
2668 }
2669 }
2670
2671 /* R8G8Bx_SNORM - XXX CxV8U8 */
2672
2673 /* See whether the components are of the same size. */
2674 for (i = 1; i < desc->nr_channels; i++) {
2675 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2676 }
2677
2678 /* Non-uniform formats. */
2679 if (!uniform) {
2680 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2681 desc->channel[0].pure_integer)
2682 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2683 switch(desc->nr_channels) {
2684 case 3:
2685 if (desc->channel[0].size == 5 &&
2686 desc->channel[1].size == 6 &&
2687 desc->channel[2].size == 5) {
2688 result = FMT_5_6_5;
2689 goto out_word4;
2690 }
2691 goto out_unknown;
2692 case 4:
2693 if (desc->channel[0].size == 5 &&
2694 desc->channel[1].size == 5 &&
2695 desc->channel[2].size == 5 &&
2696 desc->channel[3].size == 1) {
2697 result = FMT_1_5_5_5;
2698 goto out_word4;
2699 }
2700 if (desc->channel[0].size == 10 &&
2701 desc->channel[1].size == 10 &&
2702 desc->channel[2].size == 10 &&
2703 desc->channel[3].size == 2) {
2704 result = FMT_2_10_10_10;
2705 goto out_word4;
2706 }
2707 goto out_unknown;
2708 }
2709 goto out_unknown;
2710 }
2711
2712 /* Find the first non-VOID channel. */
2713 for (i = 0; i < 4; i++) {
2714 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2715 break;
2716 }
2717 }
2718
2719 if (i == 4)
2720 goto out_unknown;
2721
2722 /* uniform formats */
2723 switch (desc->channel[i].type) {
2724 case UTIL_FORMAT_TYPE_UNSIGNED:
2725 case UTIL_FORMAT_TYPE_SIGNED:
2726 #if 0
2727 if (!desc->channel[i].normalized &&
2728 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2729 goto out_unknown;
2730 }
2731 #endif
2732 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2733 desc->channel[i].pure_integer)
2734 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2735
2736 switch (desc->channel[i].size) {
2737 case 4:
2738 switch (desc->nr_channels) {
2739 case 2:
2740 result = FMT_4_4;
2741 goto out_word4;
2742 case 4:
2743 result = FMT_4_4_4_4;
2744 goto out_word4;
2745 }
2746 goto out_unknown;
2747 case 8:
2748 switch (desc->nr_channels) {
2749 case 1:
2750 result = FMT_8;
2751 goto out_word4;
2752 case 2:
2753 result = FMT_8_8;
2754 goto out_word4;
2755 case 4:
2756 result = FMT_8_8_8_8;
2757 is_srgb_valid = TRUE;
2758 goto out_word4;
2759 }
2760 goto out_unknown;
2761 case 16:
2762 switch (desc->nr_channels) {
2763 case 1:
2764 result = FMT_16;
2765 goto out_word4;
2766 case 2:
2767 result = FMT_16_16;
2768 goto out_word4;
2769 case 4:
2770 result = FMT_16_16_16_16;
2771 goto out_word4;
2772 }
2773 goto out_unknown;
2774 case 32:
2775 switch (desc->nr_channels) {
2776 case 1:
2777 result = FMT_32;
2778 goto out_word4;
2779 case 2:
2780 result = FMT_32_32;
2781 goto out_word4;
2782 case 4:
2783 result = FMT_32_32_32_32;
2784 goto out_word4;
2785 }
2786 }
2787 goto out_unknown;
2788
2789 case UTIL_FORMAT_TYPE_FLOAT:
2790 switch (desc->channel[i].size) {
2791 case 16:
2792 switch (desc->nr_channels) {
2793 case 1:
2794 result = FMT_16_FLOAT;
2795 goto out_word4;
2796 case 2:
2797 result = FMT_16_16_FLOAT;
2798 goto out_word4;
2799 case 4:
2800 result = FMT_16_16_16_16_FLOAT;
2801 goto out_word4;
2802 }
2803 goto out_unknown;
2804 case 32:
2805 switch (desc->nr_channels) {
2806 case 1:
2807 result = FMT_32_FLOAT;
2808 goto out_word4;
2809 case 2:
2810 result = FMT_32_32_FLOAT;
2811 goto out_word4;
2812 case 4:
2813 result = FMT_32_32_32_32_FLOAT;
2814 goto out_word4;
2815 }
2816 }
2817 goto out_unknown;
2818 }
2819
2820 out_word4:
2821
2822 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2823 return ~0;
2824 if (word4_p)
2825 *word4_p = word4;
2826 if (yuv_format_p)
2827 *yuv_format_p = yuv_format;
2828 return result;
2829 out_unknown:
2830 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2831 return ~0;
2832 }
2833
2834 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
2835 bool do_endian_swap)
2836 {
2837 const struct util_format_description *desc = util_format_description(format);
2838 int channel = util_format_get_first_non_void_channel(format);
2839 bool is_float;
2840 if (!desc)
2841 return ~0U;
2842
2843 #define HAS_SIZE(x,y,z,w) \
2844 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2845 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2846
2847 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2848 return V_0280A0_COLOR_10_11_11_FLOAT;
2849
2850 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2851 channel == -1)
2852 return ~0U;
2853
2854 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2855
2856 switch (desc->nr_channels) {
2857 case 1:
2858 switch (desc->channel[0].size) {
2859 case 8:
2860 return V_0280A0_COLOR_8;
2861 case 16:
2862 if (is_float)
2863 return V_0280A0_COLOR_16_FLOAT;
2864 else
2865 return V_0280A0_COLOR_16;
2866 case 32:
2867 if (is_float)
2868 return V_0280A0_COLOR_32_FLOAT;
2869 else
2870 return V_0280A0_COLOR_32;
2871 }
2872 break;
2873 case 2:
2874 if (desc->channel[0].size == desc->channel[1].size) {
2875 switch (desc->channel[0].size) {
2876 case 4:
2877 if (chip <= R700)
2878 return V_0280A0_COLOR_4_4;
2879 else
2880 return ~0U; /* removed on Evergreen */
2881 case 8:
2882 return V_0280A0_COLOR_8_8;
2883 case 16:
2884 if (is_float)
2885 return V_0280A0_COLOR_16_16_FLOAT;
2886 else
2887 return V_0280A0_COLOR_16_16;
2888 case 32:
2889 if (is_float)
2890 return V_0280A0_COLOR_32_32_FLOAT;
2891 else
2892 return V_0280A0_COLOR_32_32;
2893 }
2894 } else if (HAS_SIZE(8,24,0,0)) {
2895 return (do_endian_swap ? V_0280A0_COLOR_8_24 : V_0280A0_COLOR_24_8);
2896 } else if (HAS_SIZE(24,8,0,0)) {
2897 return V_0280A0_COLOR_8_24;
2898 }
2899 break;
2900 case 3:
2901 if (HAS_SIZE(5,6,5,0)) {
2902 return V_0280A0_COLOR_5_6_5;
2903 } else if (HAS_SIZE(32,8,24,0)) {
2904 return V_0280A0_COLOR_X24_8_32_FLOAT;
2905 }
2906 break;
2907 case 4:
2908 if (desc->channel[0].size == desc->channel[1].size &&
2909 desc->channel[0].size == desc->channel[2].size &&
2910 desc->channel[0].size == desc->channel[3].size) {
2911 switch (desc->channel[0].size) {
2912 case 4:
2913 return V_0280A0_COLOR_4_4_4_4;
2914 case 8:
2915 return V_0280A0_COLOR_8_8_8_8;
2916 case 16:
2917 if (is_float)
2918 return V_0280A0_COLOR_16_16_16_16_FLOAT;
2919 else
2920 return V_0280A0_COLOR_16_16_16_16;
2921 case 32:
2922 if (is_float)
2923 return V_0280A0_COLOR_32_32_32_32_FLOAT;
2924 else
2925 return V_0280A0_COLOR_32_32_32_32;
2926 }
2927 } else if (HAS_SIZE(5,5,5,1)) {
2928 return V_0280A0_COLOR_1_5_5_5;
2929 } else if (HAS_SIZE(10,10,10,2)) {
2930 return V_0280A0_COLOR_2_10_10_10;
2931 }
2932 break;
2933 }
2934 return ~0U;
2935 }
2936
2937 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
2938 {
2939 if (R600_BIG_ENDIAN) {
2940 switch(colorformat) {
2941 /* 8-bit buffers. */
2942 case V_0280A0_COLOR_4_4:
2943 case V_0280A0_COLOR_8:
2944 return ENDIAN_NONE;
2945
2946 /* 16-bit buffers. */
2947 case V_0280A0_COLOR_8_8:
2948 /*
2949 * No need to do endian swaps on array formats,
2950 * as mesa<-->pipe formats conversion take into account
2951 * the endianess
2952 */
2953 return ENDIAN_NONE;
2954
2955 case V_0280A0_COLOR_5_6_5:
2956 case V_0280A0_COLOR_1_5_5_5:
2957 case V_0280A0_COLOR_4_4_4_4:
2958 case V_0280A0_COLOR_16:
2959 return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
2960
2961 /* 32-bit buffers. */
2962 case V_0280A0_COLOR_8_8_8_8:
2963 /*
2964 * No need to do endian swaps on array formats,
2965 * as mesa<-->pipe formats conversion take into account
2966 * the endianess
2967 */
2968 return ENDIAN_NONE;
2969
2970 case V_0280A0_COLOR_2_10_10_10:
2971 case V_0280A0_COLOR_8_24:
2972 case V_0280A0_COLOR_24_8:
2973 case V_0280A0_COLOR_32_FLOAT:
2974 return (do_endian_swap ? ENDIAN_8IN32 : ENDIAN_NONE);
2975
2976 case V_0280A0_COLOR_16_16_FLOAT:
2977 case V_0280A0_COLOR_16_16:
2978 return ENDIAN_8IN16;
2979
2980 /* 64-bit buffers. */
2981 case V_0280A0_COLOR_16_16_16_16:
2982 case V_0280A0_COLOR_16_16_16_16_FLOAT:
2983 return ENDIAN_8IN16;
2984
2985 case V_0280A0_COLOR_32_32_FLOAT:
2986 case V_0280A0_COLOR_32_32:
2987 case V_0280A0_COLOR_X24_8_32_FLOAT:
2988 return ENDIAN_8IN32;
2989
2990 /* 128-bit buffers. */
2991 case V_0280A0_COLOR_32_32_32_32_FLOAT:
2992 case V_0280A0_COLOR_32_32_32_32:
2993 return ENDIAN_8IN32;
2994 default:
2995 return ENDIAN_NONE; /* Unsupported. */
2996 }
2997 } else {
2998 return ENDIAN_NONE;
2999 }
3000 }
3001
3002 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
3003 {
3004 struct r600_context *rctx = (struct r600_context*)ctx;
3005 struct r600_resource *rbuffer = r600_resource(buf);
3006 unsigned i, shader, mask;
3007 struct r600_pipe_sampler_view *view;
3008
3009 /* Reallocate the buffer in the same pipe_resource. */
3010 r600_alloc_resource(&rctx->screen->b, rbuffer);
3011
3012 /* We changed the buffer, now we need to bind it where the old one was bound. */
3013 /* Vertex buffers. */
3014 mask = rctx->vertex_buffer_state.enabled_mask;
3015 while (mask) {
3016 i = u_bit_scan(&mask);
3017 if (rctx->vertex_buffer_state.vb[i].buffer.resource == &rbuffer->b.b) {
3018 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
3019 r600_vertex_buffers_dirty(rctx);
3020 }
3021 }
3022 /* Streamout buffers. */
3023 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
3024 if (rctx->b.streamout.targets[i] &&
3025 rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
3026 if (rctx->b.streamout.begin_emitted) {
3027 r600_emit_streamout_end(&rctx->b);
3028 }
3029 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
3030 r600_streamout_buffers_dirty(&rctx->b);
3031 }
3032 }
3033
3034 /* Constant buffers. */
3035 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3036 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
3037 bool found = false;
3038 uint32_t mask = state->enabled_mask;
3039
3040 while (mask) {
3041 unsigned i = u_bit_scan(&mask);
3042 if (state->cb[i].buffer == &rbuffer->b.b) {
3043 found = true;
3044 state->dirty_mask |= 1 << i;
3045 }
3046 }
3047 if (found) {
3048 r600_constant_buffers_dirty(rctx, state);
3049 }
3050 }
3051
3052 /* Texture buffer objects - update the virtual addresses in descriptors. */
3053 LIST_FOR_EACH_ENTRY(view, &rctx->texture_buffers, list) {
3054 if (view->base.texture == &rbuffer->b.b) {
3055 uint64_t offset = view->base.u.buf.offset;
3056 uint64_t va = rbuffer->gpu_address + offset;
3057
3058 view->tex_resource_words[0] = va;
3059 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
3060 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
3061 }
3062 }
3063 /* Texture buffer objects - make bindings dirty if needed. */
3064 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3065 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
3066 bool found = false;
3067 uint32_t mask = state->enabled_mask;
3068
3069 while (mask) {
3070 unsigned i = u_bit_scan(&mask);
3071 if (state->views[i]->base.texture == &rbuffer->b.b) {
3072 found = true;
3073 state->dirty_mask |= 1 << i;
3074 }
3075 }
3076 if (found) {
3077 r600_sampler_views_dirty(rctx, state);
3078 }
3079 }
3080
3081 /* SSBOs */
3082 struct r600_image_state *istate = &rctx->fragment_buffers;
3083 {
3084 uint32_t mask = istate->enabled_mask;
3085 bool found = false;
3086 while (mask) {
3087 unsigned i = u_bit_scan(&mask);
3088 if (istate->views[i].base.resource == &rbuffer->b.b) {
3089 found = true;
3090 istate->dirty_mask |= 1 << i;
3091 }
3092 }
3093 if (found) {
3094 r600_mark_atom_dirty(rctx, &istate->atom);
3095 }
3096 }
3097
3098 }
3099
3100 static void r600_set_active_query_state(struct pipe_context *ctx, boolean enable)
3101 {
3102 struct r600_context *rctx = (struct r600_context*)ctx;
3103
3104 /* Pipeline stat & streamout queries. */
3105 if (enable) {
3106 rctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
3107 rctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
3108 } else {
3109 rctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
3110 rctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
3111 }
3112
3113 /* Occlusion queries. */
3114 if (rctx->db_misc_state.occlusion_queries_disabled != !enable) {
3115 rctx->db_misc_state.occlusion_queries_disabled = !enable;
3116 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3117 }
3118 }
3119
3120 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3121 bool include_draw_vbo)
3122 {
3123 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
3124 }
3125
3126 /* keep this at the end of this file, please */
3127 void r600_init_common_state_functions(struct r600_context *rctx)
3128 {
3129 rctx->b.b.create_fs_state = r600_create_ps_state;
3130 rctx->b.b.create_vs_state = r600_create_vs_state;
3131 rctx->b.b.create_gs_state = r600_create_gs_state;
3132 rctx->b.b.create_tcs_state = r600_create_tcs_state;
3133 rctx->b.b.create_tes_state = r600_create_tes_state;
3134 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
3135 rctx->b.b.bind_blend_state = r600_bind_blend_state;
3136 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
3137 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
3138 rctx->b.b.bind_fs_state = r600_bind_ps_state;
3139 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
3140 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
3141 rctx->b.b.bind_vs_state = r600_bind_vs_state;
3142 rctx->b.b.bind_gs_state = r600_bind_gs_state;
3143 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
3144 rctx->b.b.bind_tes_state = r600_bind_tes_state;
3145 rctx->b.b.delete_blend_state = r600_delete_blend_state;
3146 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
3147 rctx->b.b.delete_fs_state = r600_delete_ps_state;
3148 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
3149 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
3150 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
3151 rctx->b.b.delete_vs_state = r600_delete_vs_state;
3152 rctx->b.b.delete_gs_state = r600_delete_gs_state;
3153 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
3154 rctx->b.b.delete_tes_state = r600_delete_tes_state;
3155 rctx->b.b.set_blend_color = r600_set_blend_color;
3156 rctx->b.b.set_clip_state = r600_set_clip_state;
3157 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
3158 rctx->b.b.set_sample_mask = r600_set_sample_mask;
3159 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
3160 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
3161 rctx->b.b.set_sampler_views = r600_set_sampler_views;
3162 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
3163 rctx->b.b.memory_barrier = r600_memory_barrier;
3164 rctx->b.b.texture_barrier = r600_texture_barrier;
3165 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
3166 rctx->b.b.set_active_query_state = r600_set_active_query_state;
3167 rctx->b.b.draw_vbo = r600_draw_vbo;
3168 rctx->b.invalidate_buffer = r600_invalidate_buffer;
3169 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
3170 }