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[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 assert(!cb->buf);
43 cb->buf = CALLOC(1, 4 * num_dw);
44 cb->max_num_dw = num_dw;
45 }
46
47 void r600_release_command_buffer(struct r600_command_buffer *cb)
48 {
49 FREE(cb->buf);
50 }
51
52 void r600_add_atom(struct r600_context *rctx,
53 struct r600_atom *atom,
54 unsigned id)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->id = id;
60 }
61
62 void r600_init_atom(struct r600_context *rctx,
63 struct r600_atom *atom,
64 unsigned id,
65 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
66 unsigned num_dw)
67 {
68 atom->emit = (void*)emit;
69 atom->num_dw = num_dw;
70 r600_add_atom(rctx, atom, id);
71 }
72
73 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 r600_emit_command_buffer(rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
76 }
77
78 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
79 {
80 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
81 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
82 unsigned alpha_ref = a->sx_alpha_ref;
83
84 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
85 alpha_ref &= ~0x1FFF;
86 }
87
88 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
89 a->sx_alpha_test_control |
90 S_028410_ALPHA_TEST_BYPASS(a->bypass));
91 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
92 }
93
94 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
95 {
96 struct r600_context *rctx = (struct r600_context *)ctx;
97 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
98 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
99
100 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
101 PIPE_BARRIER_SHADER_BUFFER |
102 PIPE_BARRIER_TEXTURE |
103 PIPE_BARRIER_IMAGE |
104 PIPE_BARRIER_STREAMOUT_BUFFER |
105 PIPE_BARRIER_GLOBAL_BUFFER)) {
106 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
107 R600_CONTEXT_INV_TEX_CACHE;
108 }
109
110 if (flags & (PIPE_BARRIER_FRAMEBUFFER|
111 PIPE_BARRIER_IMAGE))
112 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
113
114 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
115 }
116
117 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 struct r600_context *rctx = (struct r600_context *)ctx;
120
121 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
122 R600_CONTEXT_FLUSH_AND_INV_CB |
123 R600_CONTEXT_FLUSH_AND_INV |
124 R600_CONTEXT_WAIT_3D_IDLE;
125 rctx->framebuffer.do_update_surf_dirtiness = true;
126 }
127
128 static unsigned r600_conv_pipe_prim(unsigned prim)
129 {
130 static const unsigned prim_conv[] = {
131 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
132 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
133 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
134 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
135 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
136 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
137 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
138 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
139 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
140 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
141 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
145 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
146 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
147 };
148 assert(prim < ARRAY_SIZE(prim_conv));
149 return prim_conv[prim];
150 }
151
152 unsigned r600_conv_prim_to_gs_out(unsigned mode)
153 {
154 static const int prim_conv[] = {
155 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
156 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
157 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
158 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
159 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
160 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
161 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
162 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
163 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
164 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
165 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
166 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
167 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
168 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
169 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
170 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
171 };
172 assert(mode < ARRAY_SIZE(prim_conv));
173
174 return prim_conv[mode];
175 }
176
177 /* common state between evergreen and r600 */
178
179 static void r600_bind_blend_state_internal(struct r600_context *rctx,
180 struct r600_blend_state *blend, bool blend_disable)
181 {
182 unsigned color_control;
183 bool update_cb = false;
184
185 rctx->alpha_to_one = blend->alpha_to_one;
186 rctx->dual_src_blend = blend->dual_src_blend;
187
188 if (!blend_disable) {
189 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
190 color_control = blend->cb_color_control;
191 } else {
192 /* Blending is disabled. */
193 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
194 color_control = blend->cb_color_control_no_blend;
195 }
196
197 /* Update derived states. */
198 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
199 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
200 update_cb = true;
201 }
202 if (rctx->b.chip_class <= R700 &&
203 rctx->cb_misc_state.cb_color_control != color_control) {
204 rctx->cb_misc_state.cb_color_control = color_control;
205 update_cb = true;
206 }
207 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
208 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
209 update_cb = true;
210 }
211 if (update_cb) {
212 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
213 }
214 if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) {
215 rctx->framebuffer.dual_src_blend = blend->dual_src_blend;
216 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
217 }
218 }
219
220 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
221 {
222 struct r600_context *rctx = (struct r600_context *)ctx;
223 struct r600_blend_state *blend = (struct r600_blend_state *)state;
224
225 if (!blend) {
226 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
227 return;
228 }
229
230 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
231 }
232
233 static void r600_set_blend_color(struct pipe_context *ctx,
234 const struct pipe_blend_color *state)
235 {
236 struct r600_context *rctx = (struct r600_context *)ctx;
237
238 rctx->blend_color.state = *state;
239 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
240 }
241
242 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
243 {
244 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
245 struct pipe_blend_color *state = &rctx->blend_color.state;
246
247 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
248 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
249 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
250 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
251 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
252 }
253
254 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
255 {
256 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
257 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
258
259 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
260 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
261 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
262 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
263 if (a->last_draw_was_indirect) {
264 a->last_draw_was_indirect = false;
265 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
266 }
267 }
268
269 static void r600_set_clip_state(struct pipe_context *ctx,
270 const struct pipe_clip_state *state)
271 {
272 struct r600_context *rctx = (struct r600_context *)ctx;
273
274 rctx->clip_state.state = *state;
275 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
276 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
277 }
278
279 static void r600_set_stencil_ref(struct pipe_context *ctx,
280 const struct r600_stencil_ref *state)
281 {
282 struct r600_context *rctx = (struct r600_context *)ctx;
283
284 rctx->stencil_ref.state = *state;
285 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
286 }
287
288 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
289 {
290 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
291 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
292
293 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
294 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
295 S_028430_STENCILREF(a->state.ref_value[0]) |
296 S_028430_STENCILMASK(a->state.valuemask[0]) |
297 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
298 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
299 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
300 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
301 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
302 }
303
304 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
305 const struct pipe_stencil_ref *state)
306 {
307 struct r600_context *rctx = (struct r600_context *)ctx;
308 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
309 struct r600_stencil_ref ref;
310
311 rctx->stencil_ref.pipe_state = *state;
312
313 if (!dsa)
314 return;
315
316 ref.ref_value[0] = state->ref_value[0];
317 ref.ref_value[1] = state->ref_value[1];
318 ref.valuemask[0] = dsa->valuemask[0];
319 ref.valuemask[1] = dsa->valuemask[1];
320 ref.writemask[0] = dsa->writemask[0];
321 ref.writemask[1] = dsa->writemask[1];
322
323 r600_set_stencil_ref(ctx, &ref);
324 }
325
326 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
327 {
328 struct r600_context *rctx = (struct r600_context *)ctx;
329 struct r600_dsa_state *dsa = state;
330 struct r600_stencil_ref ref;
331
332 if (!state) {
333 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
334 return;
335 }
336
337 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
338
339 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
340 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
341 ref.valuemask[0] = dsa->valuemask[0];
342 ref.valuemask[1] = dsa->valuemask[1];
343 ref.writemask[0] = dsa->writemask[0];
344 ref.writemask[1] = dsa->writemask[1];
345 if (rctx->zwritemask != dsa->zwritemask) {
346 rctx->zwritemask = dsa->zwritemask;
347 if (rctx->b.chip_class >= EVERGREEN) {
348 /* work around some issue when not writing to zbuffer
349 * we are having lockup on evergreen so do not enable
350 * hyperz when not writing zbuffer
351 */
352 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
353 }
354 }
355
356 r600_set_stencil_ref(ctx, &ref);
357
358 /* Update alphatest state. */
359 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
360 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
361 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
362 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
363 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
364 }
365 }
366
367 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
368 {
369 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
370 struct r600_context *rctx = (struct r600_context *)ctx;
371
372 if (!state)
373 return;
374
375 rctx->rasterizer = rs;
376
377 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
378
379 if (rs->offset_enable &&
380 (rs->offset_units != rctx->poly_offset_state.offset_units ||
381 rs->offset_scale != rctx->poly_offset_state.offset_scale ||
382 rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
383 rctx->poly_offset_state.offset_units = rs->offset_units;
384 rctx->poly_offset_state.offset_scale = rs->offset_scale;
385 rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
386 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
387 }
388
389 /* Update clip_misc_state. */
390 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
391 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
392 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
393 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
394 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
395 }
396
397 r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
398
399 /* Re-emit PA_SC_LINE_STIPPLE. */
400 rctx->last_primitive_type = -1;
401 }
402
403 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
404 {
405 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
406
407 r600_release_command_buffer(&rs->buffer);
408 FREE(rs);
409 }
410
411 static void r600_sampler_view_destroy(struct pipe_context *ctx,
412 struct pipe_sampler_view *state)
413 {
414 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
415
416 if (view->tex_resource->gpu_address &&
417 view->tex_resource->b.b.target == PIPE_BUFFER)
418 LIST_DELINIT(&view->list);
419
420 pipe_resource_reference(&state->texture, NULL);
421 FREE(view);
422 }
423
424 void r600_sampler_states_dirty(struct r600_context *rctx,
425 struct r600_sampler_states *state)
426 {
427 if (state->dirty_mask) {
428 if (state->dirty_mask & state->has_bordercolor_mask) {
429 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
430 }
431 state->atom.num_dw =
432 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
433 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
434 r600_mark_atom_dirty(rctx, &state->atom);
435 }
436 }
437
438 static void r600_bind_sampler_states(struct pipe_context *pipe,
439 enum pipe_shader_type shader,
440 unsigned start,
441 unsigned count, void **states)
442 {
443 struct r600_context *rctx = (struct r600_context *)pipe;
444 struct r600_textures_info *dst = &rctx->samplers[shader];
445 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
446 int seamless_cube_map = -1;
447 unsigned i;
448 /* This sets 1-bit for states with index >= count. */
449 uint32_t disable_mask = ~((1ull << count) - 1);
450 /* These are the new states set by this function. */
451 uint32_t new_mask = 0;
452
453 assert(start == 0); /* XXX fix below */
454
455 if (!states) {
456 disable_mask = ~0u;
457 count = 0;
458 }
459
460 for (i = 0; i < count; i++) {
461 struct r600_pipe_sampler_state *rstate = rstates[i];
462
463 if (rstate == dst->states.states[i]) {
464 continue;
465 }
466
467 if (rstate) {
468 if (rstate->border_color_use) {
469 dst->states.has_bordercolor_mask |= 1 << i;
470 } else {
471 dst->states.has_bordercolor_mask &= ~(1 << i);
472 }
473 seamless_cube_map = rstate->seamless_cube_map;
474
475 new_mask |= 1 << i;
476 } else {
477 disable_mask |= 1 << i;
478 }
479 }
480
481 memcpy(dst->states.states, rstates, sizeof(void*) * count);
482 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
483
484 dst->states.enabled_mask &= ~disable_mask;
485 dst->states.dirty_mask &= dst->states.enabled_mask;
486 dst->states.enabled_mask |= new_mask;
487 dst->states.dirty_mask |= new_mask;
488 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
489
490 r600_sampler_states_dirty(rctx, &dst->states);
491
492 /* Seamless cubemap state. */
493 if (rctx->b.chip_class <= R700 &&
494 seamless_cube_map != -1 &&
495 seamless_cube_map != rctx->seamless_cube_map.enabled) {
496 /* change in TA_CNTL_AUX need a pipeline flush */
497 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
498 rctx->seamless_cube_map.enabled = seamless_cube_map;
499 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
500 }
501 }
502
503 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
504 {
505 free(state);
506 }
507
508 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
509 {
510 struct r600_context *rctx = (struct r600_context *)ctx;
511 struct r600_blend_state *blend = (struct r600_blend_state*)state;
512
513 if (rctx->blend_state.cso == state) {
514 ctx->bind_blend_state(ctx, NULL);
515 }
516
517 r600_release_command_buffer(&blend->buffer);
518 r600_release_command_buffer(&blend->buffer_no_blend);
519 FREE(blend);
520 }
521
522 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
523 {
524 struct r600_context *rctx = (struct r600_context *)ctx;
525 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
526
527 if (rctx->dsa_state.cso == state) {
528 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
529 }
530
531 r600_release_command_buffer(&dsa->buffer);
532 free(dsa);
533 }
534
535 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
536 {
537 struct r600_context *rctx = (struct r600_context *)ctx;
538
539 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
540 }
541
542 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
543 {
544 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
545 r600_resource_reference(&shader->buffer, NULL);
546 FREE(shader);
547 }
548
549 void r600_vertex_buffers_dirty(struct r600_context *rctx)
550 {
551 if (rctx->vertex_buffer_state.dirty_mask) {
552 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
553 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
554 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
555 }
556 }
557
558 static void r600_set_vertex_buffers(struct pipe_context *ctx,
559 unsigned start_slot, unsigned count,
560 const struct pipe_vertex_buffer *input)
561 {
562 struct r600_context *rctx = (struct r600_context *)ctx;
563 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
564 struct pipe_vertex_buffer *vb = state->vb + start_slot;
565 unsigned i;
566 uint32_t disable_mask = 0;
567 /* These are the new buffers set by this function. */
568 uint32_t new_buffer_mask = 0;
569
570 /* Set vertex buffers. */
571 if (input) {
572 for (i = 0; i < count; i++) {
573 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
574 if (input[i].buffer.resource) {
575 vb[i].stride = input[i].stride;
576 vb[i].buffer_offset = input[i].buffer_offset;
577 pipe_resource_reference(&vb[i].buffer.resource, input[i].buffer.resource);
578 new_buffer_mask |= 1 << i;
579 r600_context_add_resource_size(ctx, input[i].buffer.resource);
580 } else {
581 pipe_resource_reference(&vb[i].buffer.resource, NULL);
582 disable_mask |= 1 << i;
583 }
584 }
585 }
586 } else {
587 for (i = 0; i < count; i++) {
588 pipe_resource_reference(&vb[i].buffer.resource, NULL);
589 }
590 disable_mask = ((1ull << count) - 1);
591 }
592
593 disable_mask <<= start_slot;
594 new_buffer_mask <<= start_slot;
595
596 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
597 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
598 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
599 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
600
601 r600_vertex_buffers_dirty(rctx);
602 }
603
604 void r600_sampler_views_dirty(struct r600_context *rctx,
605 struct r600_samplerview_state *state)
606 {
607 if (state->dirty_mask) {
608 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
609 util_bitcount(state->dirty_mask);
610 r600_mark_atom_dirty(rctx, &state->atom);
611 }
612 }
613
614 static void r600_set_sampler_views(struct pipe_context *pipe,
615 enum pipe_shader_type shader,
616 unsigned start, unsigned count,
617 struct pipe_sampler_view **views)
618 {
619 struct r600_context *rctx = (struct r600_context *) pipe;
620 struct r600_textures_info *dst = &rctx->samplers[shader];
621 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
622 uint32_t dirty_sampler_states_mask = 0;
623 unsigned i;
624 /* This sets 1-bit for textures with index >= count. */
625 uint32_t disable_mask = ~((1ull << count) - 1);
626 /* These are the new textures set by this function. */
627 uint32_t new_mask = 0;
628
629 /* Set textures with index >= count to NULL. */
630 uint32_t remaining_mask;
631
632 assert(start == 0); /* XXX fix below */
633
634 if (!views) {
635 disable_mask = ~0u;
636 count = 0;
637 }
638
639 remaining_mask = dst->views.enabled_mask & disable_mask;
640
641 while (remaining_mask) {
642 i = u_bit_scan(&remaining_mask);
643 assert(dst->views.views[i]);
644
645 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
646 }
647
648 for (i = 0; i < count; i++) {
649 if (rviews[i] == dst->views.views[i]) {
650 continue;
651 }
652
653 if (rviews[i]) {
654 struct r600_texture *rtex =
655 (struct r600_texture*)rviews[i]->base.texture;
656 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
657
658 if (!is_buffer && rtex->db_compatible) {
659 dst->views.compressed_depthtex_mask |= 1 << i;
660 } else {
661 dst->views.compressed_depthtex_mask &= ~(1 << i);
662 }
663
664 /* Track compressed colorbuffers. */
665 if (!is_buffer && rtex->cmask.size) {
666 dst->views.compressed_colortex_mask |= 1 << i;
667 } else {
668 dst->views.compressed_colortex_mask &= ~(1 << i);
669 }
670
671 /* Changing from array to non-arrays textures and vice versa requires
672 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
673 if (rctx->b.chip_class <= R700 &&
674 (dst->states.enabled_mask & (1 << i)) &&
675 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
676 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
677 dirty_sampler_states_mask |= 1 << i;
678 }
679
680 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
681 new_mask |= 1 << i;
682 r600_context_add_resource_size(pipe, views[i]->texture);
683 } else {
684 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
685 disable_mask |= 1 << i;
686 }
687 }
688
689 dst->views.enabled_mask &= ~disable_mask;
690 dst->views.dirty_mask &= dst->views.enabled_mask;
691 dst->views.enabled_mask |= new_mask;
692 dst->views.dirty_mask |= new_mask;
693 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
694 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
695 dst->views.dirty_buffer_constants = TRUE;
696 r600_sampler_views_dirty(rctx, &dst->views);
697
698 if (dirty_sampler_states_mask) {
699 dst->states.dirty_mask |= dirty_sampler_states_mask;
700 r600_sampler_states_dirty(rctx, &dst->states);
701 }
702 }
703
704 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
705 {
706 uint32_t mask = views->enabled_mask;
707
708 while (mask) {
709 unsigned i = u_bit_scan(&mask);
710 struct pipe_resource *res = views->views[i]->base.texture;
711
712 if (res && res->target != PIPE_BUFFER) {
713 struct r600_texture *rtex = (struct r600_texture *)res;
714
715 if (rtex->cmask.size) {
716 views->compressed_colortex_mask |= 1 << i;
717 } else {
718 views->compressed_colortex_mask &= ~(1 << i);
719 }
720 }
721 }
722 }
723
724 static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
725 enum pipe_shader_type shader)
726 {
727 const struct r600_context *rctx = (struct r600_context *)ctx;
728 int value = 0;
729 switch (shader) {
730 case PIPE_SHADER_FRAGMENT:
731 case PIPE_SHADER_COMPUTE:
732 default:
733 break;
734 case PIPE_SHADER_VERTEX:
735 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
736 break;
737 case PIPE_SHADER_GEOMETRY:
738 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
739 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
740 break;
741 case PIPE_SHADER_TESS_EVAL:
742 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
743 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
744 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0);
745 break;
746 case PIPE_SHADER_TESS_CTRL:
747 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
748 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
749 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0) +
750 rctx->tes_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
751 break;
752 }
753 return value;
754 }
755
756 static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
757 {
758 uint32_t mask = images->enabled_mask;
759
760 while (mask) {
761 unsigned i = u_bit_scan(&mask);
762 struct pipe_resource *res = images->views[i].base.resource;
763
764 if (res && res->target != PIPE_BUFFER) {
765 struct r600_texture *rtex = (struct r600_texture *)res;
766
767 if (rtex->cmask.size) {
768 images->compressed_colortex_mask |= 1 << i;
769 } else {
770 images->compressed_colortex_mask &= ~(1 << i);
771 }
772 }
773 }
774 }
775
776 /* Compute the key for the hw shader variant */
777 static inline void r600_shader_selector_key(const struct pipe_context *ctx,
778 const struct r600_pipe_shader_selector *sel,
779 union r600_shader_key *key)
780 {
781 const struct r600_context *rctx = (struct r600_context *)ctx;
782 memset(key, 0, sizeof(*key));
783
784 switch (sel->type) {
785 case PIPE_SHADER_VERTEX: {
786 key->vs.as_ls = (rctx->tes_shader != NULL);
787 if (!key->vs.as_ls)
788 key->vs.as_es = (rctx->gs_shader != NULL);
789
790 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
791 key->vs.as_gs_a = true;
792 key->vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
793 }
794 key->vs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_VERTEX);
795 break;
796 }
797 case PIPE_SHADER_GEOMETRY:
798 key->gs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_GEOMETRY);
799 key->gs.tri_strip_adj_fix = rctx->gs_tri_strip_adj_fix;
800 break;
801 case PIPE_SHADER_FRAGMENT: {
802 if (rctx->ps_shader->info.images_declared)
803 key->ps.image_size_const_offset = util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask);
804 key->ps.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_FRAGMENT);
805 key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
806 key->ps.alpha_to_one = rctx->alpha_to_one &&
807 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
808 !rctx->framebuffer.cb0_is_integer;
809 key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
810 /* Dual-source blending only makes sense with nr_cbufs == 1. */
811 if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend)
812 key->ps.nr_cbufs = 2;
813 break;
814 }
815 case PIPE_SHADER_TESS_EVAL:
816 key->tes.as_es = (rctx->gs_shader != NULL);
817 key->tes.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_EVAL);
818 break;
819 case PIPE_SHADER_TESS_CTRL:
820 key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
821 key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_CTRL);
822 break;
823 case PIPE_SHADER_COMPUTE:
824 break;
825 default:
826 assert(0);
827 }
828 }
829
830 /* Select the hw shader variant depending on the current state.
831 * (*dirty) is set to 1 if current variant was changed */
832 int r600_shader_select(struct pipe_context *ctx,
833 struct r600_pipe_shader_selector* sel,
834 bool *dirty)
835 {
836 union r600_shader_key key;
837 struct r600_pipe_shader * shader = NULL;
838 int r;
839
840 r600_shader_selector_key(ctx, sel, &key);
841
842 /* Check if we don't need to change anything.
843 * This path is also used for most shaders that don't need multiple
844 * variants, it will cost just a computation of the key and this
845 * test. */
846 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
847 return 0;
848 }
849
850 /* lookup if we have other variants in the list */
851 if (sel->num_shaders > 1) {
852 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
853
854 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
855 p = c;
856 c = c->next_variant;
857 }
858
859 if (c) {
860 p->next_variant = c->next_variant;
861 shader = c;
862 }
863 }
864
865 if (unlikely(!shader)) {
866 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
867 shader->selector = sel;
868
869 r = r600_pipe_shader_create(ctx, shader, key);
870 if (unlikely(r)) {
871 R600_ERR("Failed to build shader variant (type=%u) %d\n",
872 sel->type, r);
873 sel->current = NULL;
874 FREE(shader);
875 return r;
876 }
877
878 /* We don't know the value of nr_ps_max_color_exports until we built
879 * at least one variant, so we may need to recompute the key after
880 * building first variant. */
881 if (sel->type == PIPE_SHADER_FRAGMENT &&
882 sel->num_shaders == 0) {
883 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
884 r600_shader_selector_key(ctx, sel, &key);
885 }
886
887 memcpy(&shader->key, &key, sizeof(key));
888 sel->num_shaders++;
889 }
890
891 if (dirty)
892 *dirty = true;
893
894 shader->next_variant = sel->current;
895 sel->current = shader;
896
897 return 0;
898 }
899
900 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
901 const struct tgsi_token *tokens,
902 unsigned pipe_shader_type)
903 {
904 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
905
906 sel->type = pipe_shader_type;
907 sel->tokens = tgsi_dup_tokens(tokens);
908 tgsi_scan_shader(tokens, &sel->info);
909 return sel;
910 }
911
912 static void *r600_create_shader_state(struct pipe_context *ctx,
913 const struct pipe_shader_state *state,
914 unsigned pipe_shader_type)
915 {
916 int i;
917 struct r600_pipe_shader_selector *sel = r600_create_shader_state_tokens(ctx, state->tokens, pipe_shader_type);
918
919 sel->so = state->stream_output;
920
921 switch (pipe_shader_type) {
922 case PIPE_SHADER_GEOMETRY:
923 sel->gs_output_prim =
924 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
925 sel->gs_max_out_vertices =
926 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
927 sel->gs_num_invocations =
928 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
929 break;
930 case PIPE_SHADER_VERTEX:
931 case PIPE_SHADER_TESS_CTRL:
932 sel->lds_patch_outputs_written_mask = 0;
933 sel->lds_outputs_written_mask = 0;
934
935 for (i = 0; i < sel->info.num_outputs; i++) {
936 unsigned name = sel->info.output_semantic_name[i];
937 unsigned index = sel->info.output_semantic_index[i];
938
939 switch (name) {
940 case TGSI_SEMANTIC_TESSINNER:
941 case TGSI_SEMANTIC_TESSOUTER:
942 case TGSI_SEMANTIC_PATCH:
943 sel->lds_patch_outputs_written_mask |=
944 1ull << r600_get_lds_unique_index(name, index);
945 break;
946 default:
947 sel->lds_outputs_written_mask |=
948 1ull << r600_get_lds_unique_index(name, index);
949 }
950 }
951 break;
952 default:
953 break;
954 }
955
956 return sel;
957 }
958
959 static void *r600_create_ps_state(struct pipe_context *ctx,
960 const struct pipe_shader_state *state)
961 {
962 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
963 }
964
965 static void *r600_create_vs_state(struct pipe_context *ctx,
966 const struct pipe_shader_state *state)
967 {
968 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
969 }
970
971 static void *r600_create_gs_state(struct pipe_context *ctx,
972 const struct pipe_shader_state *state)
973 {
974 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
975 }
976
977 static void *r600_create_tcs_state(struct pipe_context *ctx,
978 const struct pipe_shader_state *state)
979 {
980 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
981 }
982
983 static void *r600_create_tes_state(struct pipe_context *ctx,
984 const struct pipe_shader_state *state)
985 {
986 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
987 }
988
989 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
990 {
991 struct r600_context *rctx = (struct r600_context *)ctx;
992
993 if (!state)
994 state = rctx->dummy_pixel_shader;
995
996 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
997 }
998
999 static struct tgsi_shader_info *r600_get_vs_info(struct r600_context *rctx)
1000 {
1001 if (rctx->gs_shader)
1002 return &rctx->gs_shader->info;
1003 else if (rctx->tes_shader)
1004 return &rctx->tes_shader->info;
1005 else if (rctx->vs_shader)
1006 return &rctx->vs_shader->info;
1007 else
1008 return NULL;
1009 }
1010
1011 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
1012 {
1013 struct r600_context *rctx = (struct r600_context *)ctx;
1014
1015 if (!state || rctx->vs_shader == state)
1016 return;
1017
1018 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
1019 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1020 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
1021 }
1022
1023 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
1024 {
1025 struct r600_context *rctx = (struct r600_context *)ctx;
1026
1027 if (state == rctx->gs_shader)
1028 return;
1029
1030 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
1031 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1032
1033 if (!state)
1034 return;
1035 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
1036 }
1037
1038 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
1039 {
1040 struct r600_context *rctx = (struct r600_context *)ctx;
1041
1042 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
1043 }
1044
1045 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
1046 {
1047 struct r600_context *rctx = (struct r600_context *)ctx;
1048
1049 if (state == rctx->tes_shader)
1050 return;
1051
1052 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
1053 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1054
1055 if (!state)
1056 return;
1057 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1058 }
1059
1060 void r600_delete_shader_selector(struct pipe_context *ctx,
1061 struct r600_pipe_shader_selector *sel)
1062 {
1063 struct r600_pipe_shader *p = sel->current, *c;
1064 while (p) {
1065 c = p->next_variant;
1066 r600_pipe_shader_destroy(ctx, p);
1067 free(p);
1068 p = c;
1069 }
1070
1071 free(sel->tokens);
1072 free(sel);
1073 }
1074
1075
1076 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1077 {
1078 struct r600_context *rctx = (struct r600_context *)ctx;
1079 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1080
1081 if (rctx->ps_shader == sel) {
1082 rctx->ps_shader = NULL;
1083 }
1084
1085 r600_delete_shader_selector(ctx, sel);
1086 }
1087
1088 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1089 {
1090 struct r600_context *rctx = (struct r600_context *)ctx;
1091 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1092
1093 if (rctx->vs_shader == sel) {
1094 rctx->vs_shader = NULL;
1095 }
1096
1097 r600_delete_shader_selector(ctx, sel);
1098 }
1099
1100
1101 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1102 {
1103 struct r600_context *rctx = (struct r600_context *)ctx;
1104 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1105
1106 if (rctx->gs_shader == sel) {
1107 rctx->gs_shader = NULL;
1108 }
1109
1110 r600_delete_shader_selector(ctx, sel);
1111 }
1112
1113 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1114 {
1115 struct r600_context *rctx = (struct r600_context *)ctx;
1116 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1117
1118 if (rctx->tcs_shader == sel) {
1119 rctx->tcs_shader = NULL;
1120 }
1121
1122 r600_delete_shader_selector(ctx, sel);
1123 }
1124
1125 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1126 {
1127 struct r600_context *rctx = (struct r600_context *)ctx;
1128 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1129
1130 if (rctx->tes_shader == sel) {
1131 rctx->tes_shader = NULL;
1132 }
1133
1134 r600_delete_shader_selector(ctx, sel);
1135 }
1136
1137 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1138 {
1139 if (state->dirty_mask) {
1140 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1141 : util_bitcount(state->dirty_mask)*19;
1142 r600_mark_atom_dirty(rctx, &state->atom);
1143 }
1144 }
1145
1146 static void r600_set_constant_buffer(struct pipe_context *ctx,
1147 enum pipe_shader_type shader, uint index,
1148 const struct pipe_constant_buffer *input)
1149 {
1150 struct r600_context *rctx = (struct r600_context *)ctx;
1151 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1152 struct pipe_constant_buffer *cb;
1153 const uint8_t *ptr;
1154
1155 /* Note that the state tracker can unbind constant buffers by
1156 * passing NULL here.
1157 */
1158 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1159 state->enabled_mask &= ~(1 << index);
1160 state->dirty_mask &= ~(1 << index);
1161 pipe_resource_reference(&state->cb[index].buffer, NULL);
1162 return;
1163 }
1164
1165 cb = &state->cb[index];
1166 cb->buffer_size = input->buffer_size;
1167
1168 ptr = input->user_buffer;
1169
1170 if (ptr) {
1171 /* Upload the user buffer. */
1172 if (R600_BIG_ENDIAN) {
1173 uint32_t *tmpPtr;
1174 unsigned i, size = input->buffer_size;
1175
1176 if (!(tmpPtr = malloc(size))) {
1177 R600_ERR("Failed to allocate BE swap buffer.\n");
1178 return;
1179 }
1180
1181 for (i = 0; i < size / 4; ++i) {
1182 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1183 }
1184
1185 u_upload_data(ctx->stream_uploader, 0, size, 256,
1186 tmpPtr, &cb->buffer_offset, &cb->buffer);
1187 free(tmpPtr);
1188 } else {
1189 u_upload_data(ctx->stream_uploader, 0,
1190 input->buffer_size, 256, ptr,
1191 &cb->buffer_offset, &cb->buffer);
1192 }
1193 /* account it in gtt */
1194 rctx->b.gtt += input->buffer_size;
1195 } else {
1196 /* Setup the hw buffer. */
1197 cb->buffer_offset = input->buffer_offset;
1198 pipe_resource_reference(&cb->buffer, input->buffer);
1199 r600_context_add_resource_size(ctx, input->buffer);
1200 }
1201
1202 state->enabled_mask |= 1 << index;
1203 state->dirty_mask |= 1 << index;
1204 r600_constant_buffers_dirty(rctx, state);
1205 }
1206
1207 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1208 {
1209 struct r600_context *rctx = (struct r600_context*)pipe;
1210
1211 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1212 return;
1213
1214 rctx->sample_mask.sample_mask = sample_mask;
1215 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1216 }
1217
1218 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only)
1219 {
1220 int sh, size;
1221 void *ptr;
1222 struct pipe_constant_buffer cb;
1223 int start, end;
1224
1225 start = compute_only ? PIPE_SHADER_COMPUTE : 0;
1226 end = compute_only ? PIPE_SHADER_TYPES : PIPE_SHADER_COMPUTE;
1227
1228 for (sh = start; sh < end; sh++) {
1229 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1230 if (!info->vs_ucp_dirty &&
1231 !info->texture_const_dirty &&
1232 !info->ps_sample_pos_dirty &&
1233 !info->tcs_default_levels_dirty &&
1234 !info->cs_block_grid_size_dirty)
1235 continue;
1236
1237 ptr = info->constants;
1238 size = info->alloc_size;
1239 if (info->vs_ucp_dirty) {
1240 assert(sh == PIPE_SHADER_VERTEX);
1241 if (!size) {
1242 ptr = rctx->clip_state.state.ucp;
1243 size = R600_UCP_SIZE;
1244 } else {
1245 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1246 }
1247 info->vs_ucp_dirty = false;
1248 }
1249
1250 else if (info->ps_sample_pos_dirty) {
1251 assert(sh == PIPE_SHADER_FRAGMENT);
1252 if (!size) {
1253 ptr = rctx->sample_positions;
1254 size = R600_UCP_SIZE;
1255 } else {
1256 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1257 }
1258 info->ps_sample_pos_dirty = false;
1259 }
1260
1261 else if (info->cs_block_grid_size_dirty) {
1262 assert(sh == PIPE_SHADER_COMPUTE);
1263 if (!size) {
1264 ptr = rctx->cs_block_grid_sizes;
1265 size = R600_CS_BLOCK_GRID_SIZE;
1266 } else {
1267 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1268 }
1269 info->cs_block_grid_size_dirty = false;
1270 }
1271
1272 else if (info->tcs_default_levels_dirty) {
1273 /*
1274 * We'd only really need this for default tcs shader.
1275 */
1276 assert(sh == PIPE_SHADER_TESS_CTRL);
1277 if (!size) {
1278 ptr = rctx->tess_state;
1279 size = R600_TCS_DEFAULT_LEVELS_SIZE;
1280 } else {
1281 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1282 }
1283 info->tcs_default_levels_dirty = false;
1284 }
1285
1286 if (info->texture_const_dirty) {
1287 assert (ptr);
1288 assert (size);
1289 if (sh == PIPE_SHADER_VERTEX)
1290 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1291 if (sh == PIPE_SHADER_FRAGMENT)
1292 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1293 if (sh == PIPE_SHADER_COMPUTE)
1294 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1295 if (sh == PIPE_SHADER_TESS_CTRL)
1296 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1297 }
1298 info->texture_const_dirty = false;
1299
1300 cb.buffer = NULL;
1301 cb.user_buffer = ptr;
1302 cb.buffer_offset = 0;
1303 cb.buffer_size = size;
1304 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1305 pipe_resource_reference(&cb.buffer, NULL);
1306 }
1307 }
1308
1309 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1310 int array_size, uint32_t *base_offset)
1311 {
1312 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1313 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1314 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1315 info->alloc_size = array_size + R600_UCP_SIZE;
1316 }
1317 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1318 info->texture_const_dirty = true;
1319 *base_offset = R600_UCP_SIZE;
1320 return info->constants;
1321 }
1322 /*
1323 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1324 * doesn't require full swizzles it does need masking and setting alpha
1325 * to one, so we setup a set of 5 constants with the masks + alpha value
1326 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1327 * then OR the alpha with the value given here.
1328 * We use a 6th constant to store the txq buffer size in
1329 * we use 7th slot for number of cube layers in a cube map array.
1330 */
1331 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1332 {
1333 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1334 int bits;
1335 uint32_t array_size;
1336 int i, j;
1337 uint32_t *constants;
1338 uint32_t base_offset;
1339 if (!samplers->views.dirty_buffer_constants)
1340 return;
1341
1342 samplers->views.dirty_buffer_constants = FALSE;
1343
1344 bits = util_last_bit(samplers->views.enabled_mask);
1345 array_size = bits * 8 * sizeof(uint32_t);
1346
1347 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1348
1349 for (i = 0; i < bits; i++) {
1350 if (samplers->views.enabled_mask & (1 << i)) {
1351 int offset = (base_offset / 4) + i * 8;
1352 const struct util_format_description *desc;
1353 desc = util_format_description(samplers->views.views[i]->base.format);
1354
1355 for (j = 0; j < 4; j++)
1356 if (j < desc->nr_channels)
1357 constants[offset+j] = 0xffffffff;
1358 else
1359 constants[offset+j] = 0x0;
1360 if (desc->nr_channels < 4) {
1361 if (desc->channel[0].pure_integer)
1362 constants[offset+4] = 1;
1363 else
1364 constants[offset+4] = fui(1.0);
1365 } else
1366 constants[offset + 4] = 0;
1367
1368 constants[offset + 5] = samplers->views.views[i]->base.u.buf.size /
1369 util_format_get_blocksize(samplers->views.views[i]->base.format);
1370 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1371 }
1372 }
1373
1374 }
1375
1376 /* On evergreen we store one value
1377 * 1. number of cube layers in a cube map array.
1378 */
1379 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1380 {
1381 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1382 struct r600_image_state *images = NULL;
1383 int bits, sview_bits, img_bits;
1384 uint32_t array_size;
1385 int i;
1386 uint32_t *constants;
1387 uint32_t base_offset;
1388
1389 if (shader_type == PIPE_SHADER_FRAGMENT) {
1390 images = &rctx->fragment_images;
1391 } else if (shader_type == PIPE_SHADER_COMPUTE) {
1392 images = &rctx->compute_images;
1393 }
1394
1395 if (!samplers->views.dirty_buffer_constants &&
1396 !(images && images->dirty_buffer_constants))
1397 return;
1398
1399 if (images)
1400 images->dirty_buffer_constants = FALSE;
1401 samplers->views.dirty_buffer_constants = FALSE;
1402
1403 bits = sview_bits = util_last_bit(samplers->views.enabled_mask);
1404 if (images)
1405 bits += util_last_bit(images->enabled_mask);
1406 img_bits = bits;
1407
1408 array_size = bits * sizeof(uint32_t);
1409
1410 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1411 &base_offset);
1412
1413 for (i = 0; i < sview_bits; i++) {
1414 if (samplers->views.enabled_mask & (1 << i)) {
1415 uint32_t offset = (base_offset / 4) + i;
1416 constants[offset] = samplers->views.views[i]->base.texture->array_size / 6;
1417 }
1418 }
1419 if (images) {
1420 for (i = sview_bits; i < img_bits; i++) {
1421 int idx = i - sview_bits;
1422 if (images->enabled_mask & (1 << idx)) {
1423 uint32_t offset = (base_offset / 4) + i;
1424 constants[offset] = images->views[idx].base.resource->array_size / 6;
1425 }
1426 }
1427 }
1428 }
1429
1430 /* set sample xy locations as array of fragment shader constants */
1431 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1432 {
1433 int i;
1434 struct pipe_context *ctx = &rctx->b.b;
1435
1436 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1437 assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4);
1438
1439 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1440 for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1441 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1442 /* Also fill in center-zeroed positions used for interpolateAtSample */
1443 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1444 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1445 }
1446
1447 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1448 }
1449
1450 static void update_shader_atom(struct pipe_context *ctx,
1451 struct r600_shader_state *state,
1452 struct r600_pipe_shader *shader)
1453 {
1454 struct r600_context *rctx = (struct r600_context *)ctx;
1455
1456 state->shader = shader;
1457 if (shader) {
1458 state->atom.num_dw = shader->command_buffer.num_dw;
1459 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1460 } else {
1461 state->atom.num_dw = 0;
1462 }
1463 r600_mark_atom_dirty(rctx, &state->atom);
1464 }
1465
1466 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1467 {
1468 if (rctx->shader_stages.geom_enable != enable) {
1469 rctx->shader_stages.geom_enable = enable;
1470 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1471 }
1472
1473 if (rctx->gs_rings.enable != enable) {
1474 rctx->gs_rings.enable = enable;
1475 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1476
1477 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1478 unsigned size = 0x1C000;
1479 rctx->gs_rings.esgs_ring.buffer =
1480 pipe_buffer_create(rctx->b.b.screen, 0,
1481 PIPE_USAGE_DEFAULT, size);
1482 rctx->gs_rings.esgs_ring.buffer_size = size;
1483
1484 size = 0x4000000;
1485
1486 rctx->gs_rings.gsvs_ring.buffer =
1487 pipe_buffer_create(rctx->b.b.screen, 0,
1488 PIPE_USAGE_DEFAULT, size);
1489 rctx->gs_rings.gsvs_ring.buffer_size = size;
1490 }
1491
1492 if (enable) {
1493 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1494 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1495 if (rctx->tes_shader) {
1496 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1497 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1498 } else {
1499 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1500 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1501 }
1502 } else {
1503 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1504 R600_GS_RING_CONST_BUFFER, NULL);
1505 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1506 R600_GS_RING_CONST_BUFFER, NULL);
1507 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1508 R600_GS_RING_CONST_BUFFER, NULL);
1509 }
1510 }
1511 }
1512
1513 static void r600_update_clip_state(struct r600_context *rctx,
1514 struct r600_pipe_shader *current)
1515 {
1516 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1517 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1518 current->shader.cull_dist_write != rctx->clip_misc_state.cull_dist_write ||
1519 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1520 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1521 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1522 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1523 rctx->clip_misc_state.cull_dist_write = current->shader.cull_dist_write;
1524 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1525 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1526 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1527 }
1528 }
1529
1530 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1531 {
1532 struct ureg_src const0, const1;
1533 struct ureg_dst tessouter, tessinner;
1534 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1535
1536 if (!ureg)
1537 return; /* if we get here, we're screwed */
1538
1539 assert(!rctx->fixed_func_tcs_shader);
1540
1541 ureg_DECL_constant2D(ureg, 0, 1, R600_BUFFER_INFO_CONST_BUFFER);
1542 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1543 R600_BUFFER_INFO_CONST_BUFFER);
1544 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1545 R600_BUFFER_INFO_CONST_BUFFER);
1546
1547 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1548 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1549
1550 ureg_MOV(ureg, tessouter, const0);
1551 ureg_MOV(ureg, tessinner, const1);
1552 ureg_END(ureg);
1553
1554 rctx->fixed_func_tcs_shader =
1555 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1556 }
1557
1558 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only)
1559 {
1560 unsigned i;
1561 unsigned counter;
1562
1563 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1564 if (counter != rctx->b.last_compressed_colortex_counter) {
1565 rctx->b.last_compressed_colortex_counter = counter;
1566
1567 if (compute_only) {
1568 r600_update_compressed_colortex_mask(&rctx->samplers[PIPE_SHADER_COMPUTE].views);
1569 } else {
1570 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1571 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1572 }
1573 }
1574 if (!compute_only)
1575 r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
1576 r600_update_compressed_colortex_mask_images(&rctx->compute_images);
1577 }
1578
1579 /* Decompress textures if needed. */
1580 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1581 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1582
1583 if (compute_only)
1584 if (i != PIPE_SHADER_COMPUTE)
1585 continue;
1586 if (views->compressed_depthtex_mask) {
1587 r600_decompress_depth_textures(rctx, views);
1588 }
1589 if (views->compressed_colortex_mask) {
1590 r600_decompress_color_textures(rctx, views);
1591 }
1592 }
1593
1594 {
1595 struct r600_image_state *istate;
1596
1597 if (!compute_only) {
1598 istate = &rctx->fragment_images;
1599 if (istate->compressed_depthtex_mask)
1600 r600_decompress_depth_images(rctx, istate);
1601 if (istate->compressed_colortex_mask)
1602 r600_decompress_color_images(rctx, istate);
1603 }
1604
1605 istate = &rctx->compute_images;
1606 if (istate->compressed_depthtex_mask)
1607 r600_decompress_depth_images(rctx, istate);
1608 if (istate->compressed_colortex_mask)
1609 r600_decompress_color_images(rctx, istate);
1610 }
1611 }
1612
1613 /* update MEM_SCRATCH buffers if needed */
1614 void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
1615 struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
1616 unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg)
1617 {
1618 unsigned num_ses = rctx->screen->b.info.max_se;
1619 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
1620 unsigned nthreads = 128;
1621
1622 unsigned itemsize = shader->scratch_space_needed * 4;
1623 unsigned size = align(itemsize * nthreads * num_pipes * num_ses * 4, 256);
1624
1625 if (scratch->dirty ||
1626 unlikely(shader->scratch_space_needed != scratch->item_size ||
1627 size > scratch->size)) {
1628 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1629
1630 scratch->dirty = false;
1631
1632 if (size > scratch->size) {
1633 // Release prior one if any
1634 if (scratch->buffer) {
1635 pipe_resource_reference((struct pipe_resource**)&scratch->buffer, NULL);
1636 }
1637
1638 scratch->buffer = (struct r600_resource *)pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1639 PIPE_USAGE_DEFAULT, size);
1640 if (scratch->buffer) {
1641 scratch->size = size;
1642 }
1643 }
1644
1645 scratch->item_size = shader->scratch_space_needed;
1646
1647 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1648 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1649 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1650
1651 // multi-SE chips need programming per SE
1652 for (unsigned se = 0; se < num_ses; se++) {
1653 struct r600_resource *rbuffer = scratch->buffer;
1654 unsigned size_per_se = size / num_ses;
1655
1656 // Direct to particular SE
1657 if (num_ses > 1) {
1658 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1659 S_0802C_INSTANCE_INDEX(0) |
1660 S_0802C_SE_INDEX(se) |
1661 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1662 S_0802C_SE_BROADCAST_WRITES(0));
1663 }
1664
1665 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8);
1666 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1667 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1668 RADEON_USAGE_READWRITE,
1669 RADEON_PRIO_SCRATCH_BUFFER));
1670 radeon_set_context_reg(cs, item_size_reg, itemsize);
1671 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8);
1672 }
1673
1674 // Restore broadcast mode
1675 if (num_ses > 1) {
1676 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1677 S_0802C_INSTANCE_INDEX(0) |
1678 S_0802C_SE_INDEX(0) |
1679 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1680 S_0802C_SE_BROADCAST_WRITES(1));
1681 }
1682
1683 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1684 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1685 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1686 }
1687 }
1688
1689 void r600_setup_scratch_buffers(struct r600_context *rctx) {
1690 static const struct {
1691 unsigned ring_base;
1692 unsigned item_size;
1693 unsigned ring_size;
1694 } regs[R600_NUM_HW_STAGES] = {
1695 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE },
1696 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE },
1697 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE },
1698 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE }
1699 };
1700
1701 for (unsigned i = 0; i < R600_NUM_HW_STAGES; i++) {
1702 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
1703
1704 if (stage && unlikely(stage->scratch_space_needed)) {
1705 r600_setup_scratch_area_for_shader(rctx, stage,
1706 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
1707 }
1708 }
1709 }
1710
1711 #define SELECT_SHADER_OR_FAIL(x) do { \
1712 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1713 if (unlikely(!rctx->x##_shader->current)) \
1714 return false; \
1715 } while(0)
1716
1717 #define UPDATE_SHADER(hw, sw) do { \
1718 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1719 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1720 } while(0)
1721
1722 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1723 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1724 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1725 clip_so_current = rctx->sw##_shader->current; \
1726 } \
1727 } while(0)
1728
1729 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1730 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1731 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1732 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1733 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1734 } \
1735 } while(0)
1736
1737 #define SET_NULL_SHADER(hw) do { \
1738 if (rctx->hw_shader_stages[(hw)].shader) \
1739 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1740 } while (0)
1741
1742 static bool r600_update_derived_state(struct r600_context *rctx)
1743 {
1744 struct pipe_context * ctx = (struct pipe_context*)rctx;
1745 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1746 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1747 bool blend_disable;
1748 bool need_buf_const;
1749 struct r600_pipe_shader *clip_so_current = NULL;
1750
1751 if (!rctx->blitter->running)
1752 r600_update_compressed_resource_state(rctx, false);
1753
1754 SELECT_SHADER_OR_FAIL(ps);
1755
1756 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1757
1758 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1759
1760 if (rctx->gs_shader)
1761 SELECT_SHADER_OR_FAIL(gs);
1762
1763 /* Hull Shader */
1764 if (rctx->tcs_shader) {
1765 SELECT_SHADER_OR_FAIL(tcs);
1766
1767 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1768 } else if (rctx->tes_shader) {
1769 if (!rctx->fixed_func_tcs_shader) {
1770 r600_generate_fixed_func_tcs(rctx);
1771 if (!rctx->fixed_func_tcs_shader)
1772 return false;
1773
1774 }
1775 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1776
1777 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1778 } else
1779 SET_NULL_SHADER(EG_HW_STAGE_HS);
1780
1781 if (rctx->tes_shader) {
1782 SELECT_SHADER_OR_FAIL(tes);
1783 }
1784
1785 SELECT_SHADER_OR_FAIL(vs);
1786
1787 if (rctx->gs_shader) {
1788 if (!rctx->shader_stages.geom_enable) {
1789 rctx->shader_stages.geom_enable = true;
1790 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1791 }
1792
1793 /* gs_shader provides GS and VS (copy shader) */
1794 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1795
1796 /* vs_shader is used as ES */
1797
1798 if (rctx->tes_shader) {
1799 /* VS goes to LS, TES goes to ES */
1800 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1801 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1802 } else {
1803 /* vs_shader is used as ES */
1804 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1805 SET_NULL_SHADER(EG_HW_STAGE_LS);
1806 }
1807 } else {
1808 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1809 SET_NULL_SHADER(R600_HW_STAGE_GS);
1810 SET_NULL_SHADER(R600_HW_STAGE_ES);
1811 rctx->shader_stages.geom_enable = false;
1812 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1813 }
1814
1815 if (rctx->tes_shader) {
1816 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1817 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1818 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1819 } else {
1820 SET_NULL_SHADER(EG_HW_STAGE_LS);
1821 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1822 }
1823 }
1824
1825 /*
1826 * XXX: I believe there's some fatal flaw in the dirty state logic when
1827 * enabling/disabling tes.
1828 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1829 * it will therefore overwrite the VS slots. If it now gets disabled,
1830 * the VS needs to rebind all buffer/resource/sampler slots - not only
1831 * has TES overwritten the corresponding slots, but when the VS was
1832 * operating as LS the things with correpsonding dirty bits got bound
1833 * to LS slots and won't reflect what is dirty as VS stage even if the
1834 * TES didn't overwrite it. The story for re-enabled TES is similar.
1835 * In any case, we're not allowed to submit any TES state when
1836 * TES is disabled (the state tracker may not do this but this looks
1837 * like an optimization to me, not something which can be relied on).
1838 */
1839
1840 /* Update clip misc state. */
1841 if (clip_so_current) {
1842 r600_update_clip_state(rctx, clip_so_current);
1843 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1844 }
1845
1846 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1847 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1848 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1849
1850 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs ||
1851 rctx->cb_misc_state.ps_color_export_mask != rctx->ps_shader->current->ps_color_export_mask) {
1852 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1853 rctx->cb_misc_state.ps_color_export_mask = rctx->ps_shader->current->ps_color_export_mask;
1854 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1855 }
1856
1857 if (rctx->b.chip_class <= R700) {
1858 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1859
1860 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1861 rctx->cb_misc_state.multiwrite = multiwrite;
1862 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1863 }
1864 }
1865
1866 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1867 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1868 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1869
1870 if (rctx->b.chip_class >= EVERGREEN)
1871 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1872 else
1873 r600_update_ps_state(ctx, rctx->ps_shader->current);
1874 }
1875
1876 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1877 }
1878 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
1879
1880 if (rctx->b.chip_class >= EVERGREEN) {
1881 evergreen_update_db_shader_control(rctx);
1882 } else {
1883 r600_update_db_shader_control(rctx);
1884 }
1885
1886 /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */
1887 if (rctx->b.chip_class >= EVERGREEN) {
1888 evergreen_setup_scratch_buffers(rctx);
1889 } else {
1890 r600_setup_scratch_buffers(rctx);
1891 }
1892
1893 /* on R600 we stuff masks + txq info into one constant buffer */
1894 /* on evergreen we only need a txq info one */
1895 if (rctx->ps_shader) {
1896 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1897 if (need_buf_const) {
1898 if (rctx->b.chip_class < EVERGREEN)
1899 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1900 else
1901 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1902 }
1903 }
1904
1905 if (rctx->vs_shader) {
1906 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1907 if (need_buf_const) {
1908 if (rctx->b.chip_class < EVERGREEN)
1909 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1910 else
1911 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1912 }
1913 }
1914
1915 if (rctx->gs_shader) {
1916 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1917 if (need_buf_const) {
1918 if (rctx->b.chip_class < EVERGREEN)
1919 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1920 else
1921 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1922 }
1923 }
1924
1925 if (rctx->tes_shader) {
1926 assert(rctx->b.chip_class >= EVERGREEN);
1927 need_buf_const = rctx->tes_shader->current->shader.uses_tex_buffers ||
1928 rctx->tes_shader->current->shader.has_txq_cube_array_z_comp;
1929 if (need_buf_const) {
1930 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_EVAL);
1931 }
1932 if (rctx->tcs_shader) {
1933 need_buf_const = rctx->tcs_shader->current->shader.uses_tex_buffers ||
1934 rctx->tcs_shader->current->shader.has_txq_cube_array_z_comp;
1935 if (need_buf_const) {
1936 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_CTRL);
1937 }
1938 }
1939 }
1940
1941 r600_update_driver_const_buffers(rctx, false);
1942
1943 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1944 if (!r600_adjust_gprs(rctx)) {
1945 /* discard rendering */
1946 return false;
1947 }
1948 }
1949
1950 if (rctx->b.chip_class == EVERGREEN) {
1951 if (!evergreen_adjust_gprs(rctx)) {
1952 /* discard rendering */
1953 return false;
1954 }
1955 }
1956
1957 blend_disable = (rctx->dual_src_blend &&
1958 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1959
1960 if (blend_disable != rctx->force_blend_disable) {
1961 rctx->force_blend_disable = blend_disable;
1962 r600_bind_blend_state_internal(rctx,
1963 rctx->blend_state.cso,
1964 blend_disable);
1965 }
1966
1967 return true;
1968 }
1969
1970 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1971 {
1972 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1973 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1974
1975 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1976 state->pa_cl_clip_cntl |
1977 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1978 S_028810_CLIP_DISABLE(state->clip_disable));
1979 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1980 state->pa_cl_vs_out_cntl |
1981 (state->clip_plane_enable & state->clip_dist_write) |
1982 (state->cull_dist_write << 8));
1983 /* reuse needs to be set off if we write oViewport */
1984 if (rctx->b.chip_class >= EVERGREEN)
1985 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
1986 S_028AB4_REUSE_OFF(state->vs_out_viewport));
1987 }
1988
1989 /* rast_prim is the primitive type after GS. */
1990 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
1991 {
1992 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1993 enum pipe_prim_type rast_prim = rctx->current_rast_prim;
1994
1995 /* Skip this if not rendering lines. */
1996 if (rast_prim != PIPE_PRIM_LINES &&
1997 rast_prim != PIPE_PRIM_LINE_LOOP &&
1998 rast_prim != PIPE_PRIM_LINE_STRIP &&
1999 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
2000 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
2001 return;
2002
2003 if (rast_prim == rctx->last_rast_prim)
2004 return;
2005
2006 /* For lines, reset the stipple pattern at each primitive. Otherwise,
2007 * reset the stipple pattern at each packet (line strips, line loops).
2008 */
2009 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
2010 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2) |
2011 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
2012 rctx->last_rast_prim = rast_prim;
2013 }
2014
2015 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
2016 {
2017 struct r600_context *rctx = (struct r600_context *)ctx;
2018 struct pipe_resource *indexbuf = info->has_user_indices ? NULL : info->index.resource;
2019 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2020 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
2021 bool has_user_indices = info->has_user_indices;
2022 uint64_t mask;
2023 unsigned num_patches, dirty_tex_counter, index_offset = 0;
2024 unsigned index_size = info->index_size;
2025 int index_bias;
2026 struct r600_shader_atomic combined_atomics[8];
2027 uint8_t atomic_used_mask;
2028
2029 if (!info->indirect && !info->count && (index_size || !info->count_from_stream_output)) {
2030 return;
2031 }
2032
2033 if (unlikely(!rctx->vs_shader)) {
2034 assert(0);
2035 return;
2036 }
2037 if (unlikely(!rctx->ps_shader &&
2038 (!rctx->rasterizer || !rctx->rasterizer->rasterizer_discard))) {
2039 assert(0);
2040 return;
2041 }
2042
2043 /* make sure that the gfx ring is only one active */
2044 if (radeon_emitted(rctx->b.dma.cs, 0)) {
2045 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2046 }
2047
2048 if (rctx->cmd_buf_is_compute) {
2049 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2050 rctx->cmd_buf_is_compute = false;
2051 }
2052
2053 /* Re-emit the framebuffer state if needed. */
2054 dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
2055 if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) {
2056 rctx->b.last_dirty_tex_counter = dirty_tex_counter;
2057 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
2058 rctx->framebuffer.do_update_surf_dirtiness = true;
2059 }
2060
2061 if (rctx->gs_shader) {
2062 /* Determine whether the GS triangle strip adjacency fix should
2063 * be applied. Rotate every other triangle if
2064 * - triangle strips with adjacency are fed to the GS and
2065 * - primitive restart is disabled (the rotation doesn't help
2066 * when the restart occurs after an odd number of triangles).
2067 */
2068 bool gs_tri_strip_adj_fix =
2069 !rctx->tes_shader &&
2070 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
2071 !info->primitive_restart;
2072 if (gs_tri_strip_adj_fix != rctx->gs_tri_strip_adj_fix)
2073 rctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
2074 }
2075 if (!r600_update_derived_state(rctx)) {
2076 /* useless to render because current rendering command
2077 * can't be achieved
2078 */
2079 return;
2080 }
2081
2082 rctx->current_rast_prim = (rctx->gs_shader)? rctx->gs_shader->gs_output_prim
2083 : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
2084 : info->mode;
2085
2086 if (rctx->b.chip_class >= EVERGREEN)
2087 evergreen_emit_atomic_buffer_setup(rctx, NULL, combined_atomics, &atomic_used_mask);
2088
2089 if (index_size) {
2090 index_offset += info->start * index_size;
2091
2092 /* Translate 8-bit indices to 16-bit. */
2093 if (unlikely(index_size == 1)) {
2094 struct pipe_resource *out_buffer = NULL;
2095 unsigned out_offset;
2096 void *ptr;
2097 unsigned start, count;
2098
2099 if (likely(!info->indirect)) {
2100 start = 0;
2101 count = info->count;
2102 }
2103 else {
2104 /* Have to get start/count from indirect buffer, slow path ahead... */
2105 struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect->buffer;
2106 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
2107 PIPE_TRANSFER_READ);
2108 if (data) {
2109 data += info->indirect->offset / sizeof(unsigned);
2110 start = data[2] * index_size;
2111 count = data[0];
2112 }
2113 else {
2114 start = 0;
2115 count = 0;
2116 }
2117 }
2118
2119 u_upload_alloc(ctx->stream_uploader, start, count * 2,
2120 256, &out_offset, &out_buffer, &ptr);
2121 if (unlikely(!ptr))
2122 return;
2123
2124 util_shorten_ubyte_elts_to_userptr(
2125 &rctx->b.b, info, 0, 0, index_offset, count, ptr);
2126
2127 indexbuf = out_buffer;
2128 index_offset = out_offset;
2129 index_size = 2;
2130 has_user_indices = false;
2131 }
2132
2133 /* Upload the index buffer.
2134 * The upload is skipped for small index counts on little-endian machines
2135 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2136 * Indirect draws never use immediate indices.
2137 * Note: Instanced rendering in combination with immediate indices hangs. */
2138 if (has_user_indices && (R600_BIG_ENDIAN || info->indirect ||
2139 info->instance_count > 1 ||
2140 info->count*index_size > 20)) {
2141 indexbuf = NULL;
2142 u_upload_data(ctx->stream_uploader, 0,
2143 info->count * index_size, 256,
2144 info->index.user, &index_offset, &indexbuf);
2145 has_user_indices = false;
2146 }
2147 index_bias = info->index_bias;
2148 } else {
2149 index_bias = info->start;
2150 }
2151
2152 /* Set the index offset and primitive restart. */
2153 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info->primitive_restart ||
2154 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info->restart_index ||
2155 rctx->vgt_state.vgt_indx_offset != index_bias ||
2156 (rctx->vgt_state.last_draw_was_indirect && !info->indirect)) {
2157 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info->primitive_restart;
2158 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info->restart_index;
2159 rctx->vgt_state.vgt_indx_offset = index_bias;
2160 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
2161 }
2162
2163 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2164 if (rctx->b.chip_class == R600) {
2165 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
2166 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2167 }
2168
2169 if (rctx->b.chip_class >= EVERGREEN)
2170 evergreen_setup_tess_constants(rctx, info, &num_patches);
2171
2172 /* Emit states. */
2173 r600_need_cs_space(rctx, has_user_indices ? 5 : 0, TRUE);
2174 r600_flush_emit(rctx);
2175
2176 mask = rctx->dirty_atoms;
2177 while (mask != 0) {
2178 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
2179 }
2180
2181 if (rctx->b.chip_class == CAYMAN) {
2182 /* Copied from radeonsi. */
2183 unsigned primgroup_size = 128; /* recommended without a GS */
2184 bool ia_switch_on_eop = false;
2185 bool partial_vs_wave = false;
2186
2187 if (rctx->gs_shader)
2188 primgroup_size = 64; /* recommended with a GS */
2189
2190 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
2191 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
2192 ia_switch_on_eop = true;
2193 }
2194
2195 if (r600_get_strmout_en(&rctx->b))
2196 partial_vs_wave = true;
2197
2198 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
2199 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
2200 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
2201 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
2202 }
2203
2204 if (rctx->b.chip_class >= EVERGREEN) {
2205 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info,
2206 num_patches);
2207
2208 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
2209 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
2210 }
2211
2212 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2213 * even though it should have no effect on those. */
2214 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
2215 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
2216 unsigned prim = info->mode;
2217
2218 if (rctx->gs_shader) {
2219 prim = rctx->gs_shader->gs_output_prim;
2220 }
2221 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
2222
2223 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
2224 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
2225 info->mode == R600_PRIM_RECTANGLE_LIST) {
2226 su_sc_mode_cntl &= C_028814_CULL_FRONT;
2227 }
2228 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
2229 }
2230
2231 /* Update start instance. */
2232 if (!info->indirect && rctx->last_start_instance != info->start_instance) {
2233 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
2234 rctx->last_start_instance = info->start_instance;
2235 }
2236
2237 /* Update the primitive type. */
2238 if (rctx->last_primitive_type != info->mode) {
2239 r600_emit_rasterizer_prim_state(rctx);
2240 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2241 r600_conv_pipe_prim(info->mode));
2242
2243 rctx->last_primitive_type = info->mode;
2244 }
2245
2246 /* Draw packets. */
2247 if (likely(!info->indirect)) {
2248 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2249 radeon_emit(cs, info->instance_count);
2250 } else {
2251 uint64_t va = r600_resource(info->indirect->buffer)->gpu_address;
2252 assert(rctx->b.chip_class >= EVERGREEN);
2253
2254 // Invalidate so non-indirect draw calls reset this state
2255 rctx->vgt_state.last_draw_was_indirect = true;
2256 rctx->last_start_instance = -1;
2257
2258 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0));
2259 radeon_emit(cs, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE);
2260 radeon_emit(cs, va);
2261 radeon_emit(cs, (va >> 32UL) & 0xFF);
2262
2263 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2264 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2265 (struct r600_resource*)info->indirect->buffer,
2266 RADEON_USAGE_READ,
2267 RADEON_PRIO_DRAW_INDIRECT));
2268 }
2269
2270 if (index_size) {
2271 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2272 radeon_emit(cs, index_size == 4 ?
2273 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
2274 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)));
2275
2276 if (has_user_indices) {
2277 unsigned size_bytes = info->count*index_size;
2278 unsigned size_dw = align(size_bytes, 4) / 4;
2279 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
2280 radeon_emit(cs, info->count);
2281 radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
2282 radeon_emit_array(cs, info->index.user, size_dw);
2283 } else {
2284 uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
2285
2286 if (likely(!info->indirect)) {
2287 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit));
2288 radeon_emit(cs, va);
2289 radeon_emit(cs, (va >> 32UL) & 0xFF);
2290 radeon_emit(cs, info->count);
2291 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2292 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2293 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2294 (struct r600_resource*)indexbuf,
2295 RADEON_USAGE_READ,
2296 RADEON_PRIO_INDEX_BUFFER));
2297 }
2298 else {
2299 uint32_t max_size = (indexbuf->width0 - index_offset) / index_size;
2300
2301 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0));
2302 radeon_emit(cs, va);
2303 radeon_emit(cs, (va >> 32UL) & 0xFF);
2304
2305 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2306 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2307 (struct r600_resource*)indexbuf,
2308 RADEON_USAGE_READ,
2309 RADEON_PRIO_INDEX_BUFFER));
2310
2311 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
2312 radeon_emit(cs, max_size);
2313
2314 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
2315 radeon_emit(cs, info->indirect->offset);
2316 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2317 }
2318 }
2319 } else {
2320 if (unlikely(info->count_from_stream_output)) {
2321 struct r600_so_target *t = (struct r600_so_target*)info->count_from_stream_output;
2322 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
2323
2324 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
2325
2326 radeon_emit(cs, PKT3(PKT3_COPY_DW, 4, 0));
2327 radeon_emit(cs, COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG);
2328 radeon_emit(cs, va & 0xFFFFFFFFUL); /* src address lo */
2329 radeon_emit(cs, (va >> 32UL) & 0xFFUL); /* src address hi */
2330 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); /* dst register */
2331 radeon_emit(cs, 0); /* unused */
2332
2333 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2334 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2335 t->buf_filled_size, RADEON_USAGE_READ,
2336 RADEON_PRIO_SO_FILLED_SIZE));
2337 }
2338
2339 if (likely(!info->indirect)) {
2340 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
2341 radeon_emit(cs, info->count);
2342 }
2343 else {
2344 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
2345 radeon_emit(cs, info->indirect->offset);
2346 }
2347 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2348 (info->count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0));
2349 }
2350
2351 /* SMX returns CONTEXT_DONE too early workaround */
2352 if (rctx->b.family == CHIP_R600 ||
2353 rctx->b.family == CHIP_RV610 ||
2354 rctx->b.family == CHIP_RV630 ||
2355 rctx->b.family == CHIP_RV635) {
2356 /* if we have gs shader or streamout
2357 we need to do a wait idle after every draw */
2358 if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
2359 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2360 }
2361 }
2362
2363 /* ES ring rolling over at EOP - workaround */
2364 if (rctx->b.chip_class == R600) {
2365 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2366 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT));
2367 }
2368
2369
2370 if (rctx->b.chip_class >= EVERGREEN)
2371 evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, &atomic_used_mask);
2372
2373 if (rctx->trace_buf)
2374 eg_trace_emit(rctx);
2375
2376 if (rctx->framebuffer.do_update_surf_dirtiness) {
2377 /* Set the depth buffer as dirty. */
2378 if (rctx->framebuffer.state.zsbuf) {
2379 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2380 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2381
2382 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2383
2384 if (rtex->surface.has_stencil)
2385 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2386 }
2387 if (rctx->framebuffer.compressed_cb_mask) {
2388 struct pipe_surface *surf;
2389 struct r600_texture *rtex;
2390 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2391
2392 do {
2393 unsigned i = u_bit_scan(&mask);
2394 surf = rctx->framebuffer.state.cbufs[i];
2395 rtex = (struct r600_texture*)surf->texture;
2396
2397 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2398
2399 } while (mask);
2400 }
2401 rctx->framebuffer.do_update_surf_dirtiness = false;
2402 }
2403
2404 if (index_size && indexbuf != info->index.resource)
2405 pipe_resource_reference(&indexbuf, NULL);
2406 rctx->b.num_draw_calls++;
2407 }
2408
2409 uint32_t r600_translate_stencil_op(int s_op)
2410 {
2411 switch (s_op) {
2412 case PIPE_STENCIL_OP_KEEP:
2413 return V_028800_STENCIL_KEEP;
2414 case PIPE_STENCIL_OP_ZERO:
2415 return V_028800_STENCIL_ZERO;
2416 case PIPE_STENCIL_OP_REPLACE:
2417 return V_028800_STENCIL_REPLACE;
2418 case PIPE_STENCIL_OP_INCR:
2419 return V_028800_STENCIL_INCR;
2420 case PIPE_STENCIL_OP_DECR:
2421 return V_028800_STENCIL_DECR;
2422 case PIPE_STENCIL_OP_INCR_WRAP:
2423 return V_028800_STENCIL_INCR_WRAP;
2424 case PIPE_STENCIL_OP_DECR_WRAP:
2425 return V_028800_STENCIL_DECR_WRAP;
2426 case PIPE_STENCIL_OP_INVERT:
2427 return V_028800_STENCIL_INVERT;
2428 default:
2429 R600_ERR("Unknown stencil op %d", s_op);
2430 assert(0);
2431 break;
2432 }
2433 return 0;
2434 }
2435
2436 uint32_t r600_translate_fill(uint32_t func)
2437 {
2438 switch(func) {
2439 case PIPE_POLYGON_MODE_FILL:
2440 return 2;
2441 case PIPE_POLYGON_MODE_LINE:
2442 return 1;
2443 case PIPE_POLYGON_MODE_POINT:
2444 return 0;
2445 default:
2446 assert(0);
2447 return 0;
2448 }
2449 }
2450
2451 unsigned r600_tex_wrap(unsigned wrap)
2452 {
2453 switch (wrap) {
2454 default:
2455 case PIPE_TEX_WRAP_REPEAT:
2456 return V_03C000_SQ_TEX_WRAP;
2457 case PIPE_TEX_WRAP_CLAMP:
2458 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2459 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2460 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2461 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2462 return V_03C000_SQ_TEX_CLAMP_BORDER;
2463 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2464 return V_03C000_SQ_TEX_MIRROR;
2465 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2466 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2467 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2468 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2469 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2470 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2471 }
2472 }
2473
2474 unsigned r600_tex_mipfilter(unsigned filter)
2475 {
2476 switch (filter) {
2477 case PIPE_TEX_MIPFILTER_NEAREST:
2478 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2479 case PIPE_TEX_MIPFILTER_LINEAR:
2480 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2481 default:
2482 case PIPE_TEX_MIPFILTER_NONE:
2483 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2484 }
2485 }
2486
2487 unsigned r600_tex_compare(unsigned compare)
2488 {
2489 switch (compare) {
2490 default:
2491 case PIPE_FUNC_NEVER:
2492 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2493 case PIPE_FUNC_LESS:
2494 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2495 case PIPE_FUNC_EQUAL:
2496 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2497 case PIPE_FUNC_LEQUAL:
2498 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2499 case PIPE_FUNC_GREATER:
2500 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2501 case PIPE_FUNC_NOTEQUAL:
2502 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2503 case PIPE_FUNC_GEQUAL:
2504 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2505 case PIPE_FUNC_ALWAYS:
2506 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2507 }
2508 }
2509
2510 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2511 {
2512 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2513 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2514 (linear_filter &&
2515 (wrap == PIPE_TEX_WRAP_CLAMP ||
2516 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2517 }
2518
2519 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2520 {
2521 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2522 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2523
2524 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2525 state->border_color.ui[2] || state->border_color.ui[3]) &&
2526 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2527 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2528 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2529 }
2530
2531 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2532 {
2533
2534 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2535 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2536
2537 if (!shader)
2538 return;
2539
2540 r600_emit_command_buffer(cs, &shader->command_buffer);
2541 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2542 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2543 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY));
2544 }
2545
2546 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2547 const unsigned char *swizzle_view,
2548 boolean vtx)
2549 {
2550 unsigned i;
2551 unsigned char swizzle[4];
2552 unsigned result = 0;
2553 const uint32_t tex_swizzle_shift[4] = {
2554 16, 19, 22, 25,
2555 };
2556 const uint32_t vtx_swizzle_shift[4] = {
2557 3, 6, 9, 12,
2558 };
2559 const uint32_t swizzle_bit[4] = {
2560 0, 1, 2, 3,
2561 };
2562 const uint32_t *swizzle_shift = tex_swizzle_shift;
2563
2564 if (vtx)
2565 swizzle_shift = vtx_swizzle_shift;
2566
2567 if (swizzle_view) {
2568 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2569 } else {
2570 memcpy(swizzle, swizzle_format, 4);
2571 }
2572
2573 /* Get swizzle. */
2574 for (i = 0; i < 4; i++) {
2575 switch (swizzle[i]) {
2576 case PIPE_SWIZZLE_Y:
2577 result |= swizzle_bit[1] << swizzle_shift[i];
2578 break;
2579 case PIPE_SWIZZLE_Z:
2580 result |= swizzle_bit[2] << swizzle_shift[i];
2581 break;
2582 case PIPE_SWIZZLE_W:
2583 result |= swizzle_bit[3] << swizzle_shift[i];
2584 break;
2585 case PIPE_SWIZZLE_0:
2586 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2587 break;
2588 case PIPE_SWIZZLE_1:
2589 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2590 break;
2591 default: /* PIPE_SWIZZLE_X */
2592 result |= swizzle_bit[0] << swizzle_shift[i];
2593 }
2594 }
2595 return result;
2596 }
2597
2598 /* texture format translate */
2599 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2600 enum pipe_format format,
2601 const unsigned char *swizzle_view,
2602 uint32_t *word4_p, uint32_t *yuv_format_p,
2603 bool do_endian_swap)
2604 {
2605 struct r600_screen *rscreen = (struct r600_screen *)screen;
2606 uint32_t result = 0, word4 = 0, yuv_format = 0;
2607 const struct util_format_description *desc;
2608 boolean uniform = TRUE;
2609 bool is_srgb_valid = FALSE;
2610 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2611 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2612 const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
2613 const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
2614 const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
2615
2616 int i;
2617 const uint32_t sign_bit[4] = {
2618 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2619 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2620 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2621 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2622 };
2623
2624 /* Need to replace the specified texture formats in case of big-endian.
2625 * These formats are formats that have channels with number of bits
2626 * not divisible by 8.
2627 * Mesa conversion functions don't swap bits for those formats, and because
2628 * we transmit this over a serial bus to the GPU (PCIe), the
2629 * bit-endianess is important!!!
2630 * In case we have an "opposite" format, just use that for the swizzling
2631 * information. If we don't have such an "opposite" format, we need
2632 * to use a fixed swizzle info instead (see below)
2633 */
2634 if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
2635 format = PIPE_FORMAT_A4R4_UNORM;
2636
2637 desc = util_format_description(format);
2638 if (!desc)
2639 goto out_unknown;
2640
2641 /* Depth and stencil swizzling is handled separately. */
2642 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2643 /* Need to check for specific texture formats that don't have
2644 * an "opposite" format we can use. For those formats, we directly
2645 * specify the swizzling, which is the LE swizzling as defined in
2646 * u_format.csv
2647 */
2648 if (do_endian_swap) {
2649 if (format == PIPE_FORMAT_L4A4_UNORM)
2650 word4 |= r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, FALSE);
2651 else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
2652 word4 |= r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, FALSE);
2653 else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || format == PIPE_FORMAT_B5G6R5_UNORM)
2654 word4 |= r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, FALSE);
2655 else
2656 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2657 } else {
2658 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2659 }
2660 }
2661
2662 /* Colorspace (return non-RGB formats directly). */
2663 switch (desc->colorspace) {
2664 /* Depth stencil formats */
2665 case UTIL_FORMAT_COLORSPACE_ZS:
2666 switch (format) {
2667 /* Depth sampler formats. */
2668 case PIPE_FORMAT_Z16_UNORM:
2669 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2670 result = FMT_16;
2671 goto out_word4;
2672 case PIPE_FORMAT_Z24X8_UNORM:
2673 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2674 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2675 result = FMT_8_24;
2676 goto out_word4;
2677 case PIPE_FORMAT_X8Z24_UNORM:
2678 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2679 if (rscreen->b.chip_class < EVERGREEN)
2680 goto out_unknown;
2681 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2682 result = FMT_24_8;
2683 goto out_word4;
2684 case PIPE_FORMAT_Z32_FLOAT:
2685 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2686 result = FMT_32_FLOAT;
2687 goto out_word4;
2688 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2689 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2690 result = FMT_X24_8_32_FLOAT;
2691 goto out_word4;
2692 /* Stencil sampler formats. */
2693 case PIPE_FORMAT_S8_UINT:
2694 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2695 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2696 result = FMT_8;
2697 goto out_word4;
2698 case PIPE_FORMAT_X24S8_UINT:
2699 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2700 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2701 result = FMT_8_24;
2702 goto out_word4;
2703 case PIPE_FORMAT_S8X24_UINT:
2704 if (rscreen->b.chip_class < EVERGREEN)
2705 goto out_unknown;
2706 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2707 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2708 result = FMT_24_8;
2709 goto out_word4;
2710 case PIPE_FORMAT_X32_S8X24_UINT:
2711 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2712 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2713 result = FMT_X24_8_32_FLOAT;
2714 goto out_word4;
2715 default:
2716 goto out_unknown;
2717 }
2718
2719 case UTIL_FORMAT_COLORSPACE_YUV:
2720 yuv_format |= (1 << 30);
2721 switch (format) {
2722 case PIPE_FORMAT_UYVY:
2723 case PIPE_FORMAT_YUYV:
2724 default:
2725 break;
2726 }
2727 goto out_unknown; /* XXX */
2728
2729 case UTIL_FORMAT_COLORSPACE_SRGB:
2730 word4 |= S_038010_FORCE_DEGAMMA(1);
2731 break;
2732
2733 default:
2734 break;
2735 }
2736
2737 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2738 switch (format) {
2739 case PIPE_FORMAT_RGTC1_SNORM:
2740 case PIPE_FORMAT_LATC1_SNORM:
2741 word4 |= sign_bit[0];
2742 case PIPE_FORMAT_RGTC1_UNORM:
2743 case PIPE_FORMAT_LATC1_UNORM:
2744 result = FMT_BC4;
2745 goto out_word4;
2746 case PIPE_FORMAT_RGTC2_SNORM:
2747 case PIPE_FORMAT_LATC2_SNORM:
2748 word4 |= sign_bit[0] | sign_bit[1];
2749 case PIPE_FORMAT_RGTC2_UNORM:
2750 case PIPE_FORMAT_LATC2_UNORM:
2751 result = FMT_BC5;
2752 goto out_word4;
2753 default:
2754 goto out_unknown;
2755 }
2756 }
2757
2758 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2759 switch (format) {
2760 case PIPE_FORMAT_DXT1_RGB:
2761 case PIPE_FORMAT_DXT1_RGBA:
2762 case PIPE_FORMAT_DXT1_SRGB:
2763 case PIPE_FORMAT_DXT1_SRGBA:
2764 result = FMT_BC1;
2765 is_srgb_valid = TRUE;
2766 goto out_word4;
2767 case PIPE_FORMAT_DXT3_RGBA:
2768 case PIPE_FORMAT_DXT3_SRGBA:
2769 result = FMT_BC2;
2770 is_srgb_valid = TRUE;
2771 goto out_word4;
2772 case PIPE_FORMAT_DXT5_RGBA:
2773 case PIPE_FORMAT_DXT5_SRGBA:
2774 result = FMT_BC3;
2775 is_srgb_valid = TRUE;
2776 goto out_word4;
2777 default:
2778 goto out_unknown;
2779 }
2780 }
2781
2782 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2783 if (rscreen->b.chip_class < EVERGREEN)
2784 goto out_unknown;
2785
2786 switch (format) {
2787 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2788 case PIPE_FORMAT_BPTC_SRGBA:
2789 result = FMT_BC7;
2790 is_srgb_valid = TRUE;
2791 goto out_word4;
2792 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2793 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2794 /* fall through */
2795 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2796 result = FMT_BC6;
2797 goto out_word4;
2798 default:
2799 goto out_unknown;
2800 }
2801 }
2802
2803 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2804 switch (format) {
2805 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2806 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2807 result = FMT_GB_GR;
2808 goto out_word4;
2809 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2810 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2811 result = FMT_BG_RG;
2812 goto out_word4;
2813 default:
2814 goto out_unknown;
2815 }
2816 }
2817
2818 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2819 result = FMT_5_9_9_9_SHAREDEXP;
2820 goto out_word4;
2821 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2822 result = FMT_10_11_11_FLOAT;
2823 goto out_word4;
2824 }
2825
2826
2827 for (i = 0; i < desc->nr_channels; i++) {
2828 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2829 word4 |= sign_bit[i];
2830 }
2831 }
2832
2833 /* R8G8Bx_SNORM - XXX CxV8U8 */
2834
2835 /* See whether the components are of the same size. */
2836 for (i = 1; i < desc->nr_channels; i++) {
2837 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2838 }
2839
2840 /* Non-uniform formats. */
2841 if (!uniform) {
2842 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2843 desc->channel[0].pure_integer)
2844 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2845 switch(desc->nr_channels) {
2846 case 3:
2847 if (desc->channel[0].size == 5 &&
2848 desc->channel[1].size == 6 &&
2849 desc->channel[2].size == 5) {
2850 result = FMT_5_6_5;
2851 goto out_word4;
2852 }
2853 goto out_unknown;
2854 case 4:
2855 if (desc->channel[0].size == 5 &&
2856 desc->channel[1].size == 5 &&
2857 desc->channel[2].size == 5 &&
2858 desc->channel[3].size == 1) {
2859 result = FMT_1_5_5_5;
2860 goto out_word4;
2861 }
2862 if (desc->channel[0].size == 10 &&
2863 desc->channel[1].size == 10 &&
2864 desc->channel[2].size == 10 &&
2865 desc->channel[3].size == 2) {
2866 result = FMT_2_10_10_10;
2867 goto out_word4;
2868 }
2869 goto out_unknown;
2870 }
2871 goto out_unknown;
2872 }
2873
2874 /* Find the first non-VOID channel. */
2875 for (i = 0; i < 4; i++) {
2876 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2877 break;
2878 }
2879 }
2880
2881 if (i == 4)
2882 goto out_unknown;
2883
2884 /* uniform formats */
2885 switch (desc->channel[i].type) {
2886 case UTIL_FORMAT_TYPE_UNSIGNED:
2887 case UTIL_FORMAT_TYPE_SIGNED:
2888 #if 0
2889 if (!desc->channel[i].normalized &&
2890 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2891 goto out_unknown;
2892 }
2893 #endif
2894 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2895 desc->channel[i].pure_integer)
2896 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2897
2898 switch (desc->channel[i].size) {
2899 case 4:
2900 switch (desc->nr_channels) {
2901 case 2:
2902 result = FMT_4_4;
2903 goto out_word4;
2904 case 4:
2905 result = FMT_4_4_4_4;
2906 goto out_word4;
2907 }
2908 goto out_unknown;
2909 case 8:
2910 switch (desc->nr_channels) {
2911 case 1:
2912 result = FMT_8;
2913 goto out_word4;
2914 case 2:
2915 result = FMT_8_8;
2916 goto out_word4;
2917 case 4:
2918 result = FMT_8_8_8_8;
2919 is_srgb_valid = TRUE;
2920 goto out_word4;
2921 }
2922 goto out_unknown;
2923 case 16:
2924 switch (desc->nr_channels) {
2925 case 1:
2926 result = FMT_16;
2927 goto out_word4;
2928 case 2:
2929 result = FMT_16_16;
2930 goto out_word4;
2931 case 4:
2932 result = FMT_16_16_16_16;
2933 goto out_word4;
2934 }
2935 goto out_unknown;
2936 case 32:
2937 switch (desc->nr_channels) {
2938 case 1:
2939 result = FMT_32;
2940 goto out_word4;
2941 case 2:
2942 result = FMT_32_32;
2943 goto out_word4;
2944 case 4:
2945 result = FMT_32_32_32_32;
2946 goto out_word4;
2947 }
2948 }
2949 goto out_unknown;
2950
2951 case UTIL_FORMAT_TYPE_FLOAT:
2952 switch (desc->channel[i].size) {
2953 case 16:
2954 switch (desc->nr_channels) {
2955 case 1:
2956 result = FMT_16_FLOAT;
2957 goto out_word4;
2958 case 2:
2959 result = FMT_16_16_FLOAT;
2960 goto out_word4;
2961 case 4:
2962 result = FMT_16_16_16_16_FLOAT;
2963 goto out_word4;
2964 }
2965 goto out_unknown;
2966 case 32:
2967 switch (desc->nr_channels) {
2968 case 1:
2969 result = FMT_32_FLOAT;
2970 goto out_word4;
2971 case 2:
2972 result = FMT_32_32_FLOAT;
2973 goto out_word4;
2974 case 4:
2975 result = FMT_32_32_32_32_FLOAT;
2976 goto out_word4;
2977 }
2978 }
2979 goto out_unknown;
2980 }
2981
2982 out_word4:
2983
2984 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2985 return ~0;
2986 if (word4_p)
2987 *word4_p = word4;
2988 if (yuv_format_p)
2989 *yuv_format_p = yuv_format;
2990 return result;
2991 out_unknown:
2992 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2993 return ~0;
2994 }
2995
2996 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
2997 bool do_endian_swap)
2998 {
2999 const struct util_format_description *desc = util_format_description(format);
3000 int channel = util_format_get_first_non_void_channel(format);
3001 bool is_float;
3002 if (!desc)
3003 return ~0U;
3004
3005 #define HAS_SIZE(x,y,z,w) \
3006 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
3007 desc->channel[2].size == (z) && desc->channel[3].size == (w))
3008
3009 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
3010 return V_0280A0_COLOR_10_11_11_FLOAT;
3011
3012 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
3013 channel == -1)
3014 return ~0U;
3015
3016 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
3017
3018 switch (desc->nr_channels) {
3019 case 1:
3020 switch (desc->channel[0].size) {
3021 case 8:
3022 return V_0280A0_COLOR_8;
3023 case 16:
3024 if (is_float)
3025 return V_0280A0_COLOR_16_FLOAT;
3026 else
3027 return V_0280A0_COLOR_16;
3028 case 32:
3029 if (is_float)
3030 return V_0280A0_COLOR_32_FLOAT;
3031 else
3032 return V_0280A0_COLOR_32;
3033 }
3034 break;
3035 case 2:
3036 if (desc->channel[0].size == desc->channel[1].size) {
3037 switch (desc->channel[0].size) {
3038 case 4:
3039 if (chip <= R700)
3040 return V_0280A0_COLOR_4_4;
3041 else
3042 return ~0U; /* removed on Evergreen */
3043 case 8:
3044 return V_0280A0_COLOR_8_8;
3045 case 16:
3046 if (is_float)
3047 return V_0280A0_COLOR_16_16_FLOAT;
3048 else
3049 return V_0280A0_COLOR_16_16;
3050 case 32:
3051 if (is_float)
3052 return V_0280A0_COLOR_32_32_FLOAT;
3053 else
3054 return V_0280A0_COLOR_32_32;
3055 }
3056 } else if (HAS_SIZE(8,24,0,0)) {
3057 return (do_endian_swap ? V_0280A0_COLOR_8_24 : V_0280A0_COLOR_24_8);
3058 } else if (HAS_SIZE(24,8,0,0)) {
3059 return V_0280A0_COLOR_8_24;
3060 }
3061 break;
3062 case 3:
3063 if (HAS_SIZE(5,6,5,0)) {
3064 return V_0280A0_COLOR_5_6_5;
3065 } else if (HAS_SIZE(32,8,24,0)) {
3066 return V_0280A0_COLOR_X24_8_32_FLOAT;
3067 }
3068 break;
3069 case 4:
3070 if (desc->channel[0].size == desc->channel[1].size &&
3071 desc->channel[0].size == desc->channel[2].size &&
3072 desc->channel[0].size == desc->channel[3].size) {
3073 switch (desc->channel[0].size) {
3074 case 4:
3075 return V_0280A0_COLOR_4_4_4_4;
3076 case 8:
3077 return V_0280A0_COLOR_8_8_8_8;
3078 case 16:
3079 if (is_float)
3080 return V_0280A0_COLOR_16_16_16_16_FLOAT;
3081 else
3082 return V_0280A0_COLOR_16_16_16_16;
3083 case 32:
3084 if (is_float)
3085 return V_0280A0_COLOR_32_32_32_32_FLOAT;
3086 else
3087 return V_0280A0_COLOR_32_32_32_32;
3088 }
3089 } else if (HAS_SIZE(5,5,5,1)) {
3090 return V_0280A0_COLOR_1_5_5_5;
3091 } else if (HAS_SIZE(10,10,10,2)) {
3092 return V_0280A0_COLOR_2_10_10_10;
3093 }
3094 break;
3095 }
3096 return ~0U;
3097 }
3098
3099 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
3100 {
3101 if (R600_BIG_ENDIAN) {
3102 switch(colorformat) {
3103 /* 8-bit buffers. */
3104 case V_0280A0_COLOR_4_4:
3105 case V_0280A0_COLOR_8:
3106 return ENDIAN_NONE;
3107
3108 /* 16-bit buffers. */
3109 case V_0280A0_COLOR_8_8:
3110 /*
3111 * No need to do endian swaps on array formats,
3112 * as mesa<-->pipe formats conversion take into account
3113 * the endianess
3114 */
3115 return ENDIAN_NONE;
3116
3117 case V_0280A0_COLOR_5_6_5:
3118 case V_0280A0_COLOR_1_5_5_5:
3119 case V_0280A0_COLOR_4_4_4_4:
3120 case V_0280A0_COLOR_16:
3121 return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
3122
3123 /* 32-bit buffers. */
3124 case V_0280A0_COLOR_8_8_8_8:
3125 /*
3126 * No need to do endian swaps on array formats,
3127 * as mesa<-->pipe formats conversion take into account
3128 * the endianess
3129 */
3130 return ENDIAN_NONE;
3131
3132 case V_0280A0_COLOR_2_10_10_10:
3133 case V_0280A0_COLOR_8_24:
3134 case V_0280A0_COLOR_24_8:
3135 case V_0280A0_COLOR_32_FLOAT:
3136 return (do_endian_swap ? ENDIAN_8IN32 : ENDIAN_NONE);
3137
3138 case V_0280A0_COLOR_16_16_FLOAT:
3139 case V_0280A0_COLOR_16_16:
3140 return ENDIAN_8IN16;
3141
3142 /* 64-bit buffers. */
3143 case V_0280A0_COLOR_16_16_16_16:
3144 case V_0280A0_COLOR_16_16_16_16_FLOAT:
3145 return ENDIAN_8IN16;
3146
3147 case V_0280A0_COLOR_32_32_FLOAT:
3148 case V_0280A0_COLOR_32_32:
3149 case V_0280A0_COLOR_X24_8_32_FLOAT:
3150 return ENDIAN_8IN32;
3151
3152 /* 128-bit buffers. */
3153 case V_0280A0_COLOR_32_32_32_32_FLOAT:
3154 case V_0280A0_COLOR_32_32_32_32:
3155 return ENDIAN_8IN32;
3156 default:
3157 return ENDIAN_NONE; /* Unsupported. */
3158 }
3159 } else {
3160 return ENDIAN_NONE;
3161 }
3162 }
3163
3164 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
3165 {
3166 struct r600_context *rctx = (struct r600_context*)ctx;
3167 struct r600_resource *rbuffer = r600_resource(buf);
3168 unsigned i, shader, mask;
3169 struct r600_pipe_sampler_view *view;
3170
3171 /* Reallocate the buffer in the same pipe_resource. */
3172 r600_alloc_resource(&rctx->screen->b, rbuffer);
3173
3174 /* We changed the buffer, now we need to bind it where the old one was bound. */
3175 /* Vertex buffers. */
3176 mask = rctx->vertex_buffer_state.enabled_mask;
3177 while (mask) {
3178 i = u_bit_scan(&mask);
3179 if (rctx->vertex_buffer_state.vb[i].buffer.resource == &rbuffer->b.b) {
3180 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
3181 r600_vertex_buffers_dirty(rctx);
3182 }
3183 }
3184 /* Streamout buffers. */
3185 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
3186 if (rctx->b.streamout.targets[i] &&
3187 rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
3188 if (rctx->b.streamout.begin_emitted) {
3189 r600_emit_streamout_end(&rctx->b);
3190 }
3191 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
3192 r600_streamout_buffers_dirty(&rctx->b);
3193 }
3194 }
3195
3196 /* Constant buffers. */
3197 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3198 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
3199 bool found = false;
3200 uint32_t mask = state->enabled_mask;
3201
3202 while (mask) {
3203 unsigned i = u_bit_scan(&mask);
3204 if (state->cb[i].buffer == &rbuffer->b.b) {
3205 found = true;
3206 state->dirty_mask |= 1 << i;
3207 }
3208 }
3209 if (found) {
3210 r600_constant_buffers_dirty(rctx, state);
3211 }
3212 }
3213
3214 /* Texture buffer objects - update the virtual addresses in descriptors. */
3215 LIST_FOR_EACH_ENTRY(view, &rctx->texture_buffers, list) {
3216 if (view->base.texture == &rbuffer->b.b) {
3217 uint64_t offset = view->base.u.buf.offset;
3218 uint64_t va = rbuffer->gpu_address + offset;
3219
3220 view->tex_resource_words[0] = va;
3221 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
3222 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
3223 }
3224 }
3225 /* Texture buffer objects - make bindings dirty if needed. */
3226 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3227 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
3228 bool found = false;
3229 uint32_t mask = state->enabled_mask;
3230
3231 while (mask) {
3232 unsigned i = u_bit_scan(&mask);
3233 if (state->views[i]->base.texture == &rbuffer->b.b) {
3234 found = true;
3235 state->dirty_mask |= 1 << i;
3236 }
3237 }
3238 if (found) {
3239 r600_sampler_views_dirty(rctx, state);
3240 }
3241 }
3242
3243 /* SSBOs */
3244 struct r600_image_state *istate = &rctx->fragment_buffers;
3245 {
3246 uint32_t mask = istate->enabled_mask;
3247 bool found = false;
3248 while (mask) {
3249 unsigned i = u_bit_scan(&mask);
3250 if (istate->views[i].base.resource == &rbuffer->b.b) {
3251 found = true;
3252 istate->dirty_mask |= 1 << i;
3253 }
3254 }
3255 if (found) {
3256 r600_mark_atom_dirty(rctx, &istate->atom);
3257 }
3258 }
3259
3260 }
3261
3262 static void r600_set_active_query_state(struct pipe_context *ctx, boolean enable)
3263 {
3264 struct r600_context *rctx = (struct r600_context*)ctx;
3265
3266 /* Pipeline stat & streamout queries. */
3267 if (enable) {
3268 rctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
3269 rctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
3270 } else {
3271 rctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
3272 rctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
3273 }
3274
3275 /* Occlusion queries. */
3276 if (rctx->db_misc_state.occlusion_queries_disabled != !enable) {
3277 rctx->db_misc_state.occlusion_queries_disabled = !enable;
3278 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3279 }
3280 }
3281
3282 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3283 bool include_draw_vbo)
3284 {
3285 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
3286 }
3287
3288 /* keep this at the end of this file, please */
3289 void r600_init_common_state_functions(struct r600_context *rctx)
3290 {
3291 rctx->b.b.create_fs_state = r600_create_ps_state;
3292 rctx->b.b.create_vs_state = r600_create_vs_state;
3293 rctx->b.b.create_gs_state = r600_create_gs_state;
3294 rctx->b.b.create_tcs_state = r600_create_tcs_state;
3295 rctx->b.b.create_tes_state = r600_create_tes_state;
3296 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
3297 rctx->b.b.bind_blend_state = r600_bind_blend_state;
3298 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
3299 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
3300 rctx->b.b.bind_fs_state = r600_bind_ps_state;
3301 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
3302 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
3303 rctx->b.b.bind_vs_state = r600_bind_vs_state;
3304 rctx->b.b.bind_gs_state = r600_bind_gs_state;
3305 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
3306 rctx->b.b.bind_tes_state = r600_bind_tes_state;
3307 rctx->b.b.delete_blend_state = r600_delete_blend_state;
3308 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
3309 rctx->b.b.delete_fs_state = r600_delete_ps_state;
3310 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
3311 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
3312 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
3313 rctx->b.b.delete_vs_state = r600_delete_vs_state;
3314 rctx->b.b.delete_gs_state = r600_delete_gs_state;
3315 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
3316 rctx->b.b.delete_tes_state = r600_delete_tes_state;
3317 rctx->b.b.set_blend_color = r600_set_blend_color;
3318 rctx->b.b.set_clip_state = r600_set_clip_state;
3319 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
3320 rctx->b.b.set_sample_mask = r600_set_sample_mask;
3321 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
3322 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
3323 rctx->b.b.set_sampler_views = r600_set_sampler_views;
3324 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
3325 rctx->b.b.memory_barrier = r600_memory_barrier;
3326 rctx->b.b.texture_barrier = r600_texture_barrier;
3327 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
3328 rctx->b.b.set_active_query_state = r600_set_active_query_state;
3329
3330 rctx->b.b.draw_vbo = r600_draw_vbo;
3331 rctx->b.invalidate_buffer = r600_invalidate_buffer;
3332 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
3333 }