src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  38 {
  39         static const int prim_conv[] = {
  40                 V_008958_DI_PT_POINTLIST,
  41                 V_008958_DI_PT_LINELIST,
  42                 V_008958_DI_PT_LINELOOP,
  43                 V_008958_DI_PT_LINESTRIP,
  44                 V_008958_DI_PT_TRILIST,
  45                 V_008958_DI_PT_TRISTRIP,
  46                 V_008958_DI_PT_TRIFAN,
  47                 V_008958_DI_PT_QUADLIST,
  48                 V_008958_DI_PT_QUADSTRIP,
  49                 V_008958_DI_PT_POLYGON,
  50                 -1,
  51                 -1,
  52                 -1,
  53                 -1
  54         };
  55
  56         *prim = prim_conv[pprim];
  57         if (*prim == -1) {
  58                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
  59                 return false;
  60         }
  61         return true;
  62 }
  63
  64 /* common state between evergreen and r600 */
  65 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
  66 {
  67         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  68         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
  69         struct r600_pipe_state *rstate;
  70
  71         if (state == NULL)
  72                 return;
  73         rstate = &blend->rstate;
  74         rctx->states[rstate->id] = rstate;
  75         rctx->cb_target_mask = blend->cb_target_mask;
  76         r600_context_pipe_state_set(&rctx->ctx, rstate);
  77 }
  78
  79 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
  80 {
  81         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  82         struct r600_pipe_dsa *dsa = state;
  83         struct r600_pipe_state *rstate;
  84
  85         if (state == NULL)
  86                 return;
  87         rstate = &dsa->rstate;
  88         rctx->states[rstate->id] = rstate;
  89         rctx->alpha_ref = dsa->alpha_ref;
  90         rctx->alpha_ref_dirty = true;
  91         r600_context_pipe_state_set(&rctx->ctx, rstate);
  92 }
  93
  94 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
  95 {
  96         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
  97         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
  98
  99         if (state == NULL)
 100                 return;
 101
 102         rctx->clamp_vertex_color = rs->clamp_vertex_color;
 103         rctx->clamp_fragment_color = rs->clamp_fragment_color;
 104
 105         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 106
 107         rctx->rasterizer = rs;
 108
 109         rctx->states[rs->rstate.id] = &rs->rstate;
 110         r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 111
 112         if (rctx->chip_class >= EVERGREEN) {
 113                 evergreen_polygon_offset_update(rctx);
 114         } else {
 115                 r600_polygon_offset_update(rctx);
 116         }
 117 }
 118
 119 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 120 {
 121         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 122         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 123
 124         if (rctx->rasterizer == rs) {
 125                 rctx->rasterizer = NULL;
 126         }
 127         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 128                 rctx->states[rs->rstate.id] = NULL;
 129         }
 130         free(rs);
 131 }
 132
 133 void r600_sampler_view_destroy(struct pipe_context *ctx,
 134                                struct pipe_sampler_view *state)
 135 {
 136         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 137
 138         pipe_resource_reference(&state->texture, NULL);
 139         FREE(resource);
 140 }
 141
 142 void r600_delete_state(struct pipe_context *ctx, void *state)
 143 {
 144         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 145         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 146
 147         if (rctx->states[rstate->id] == rstate) {
 148                 rctx->states[rstate->id] = NULL;
 149         }
 150         for (int i = 0; i < rstate->nregs; i++) {
 151                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 152         }
 153         free(rstate);
 154 }
 155
 156 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 157 {
 158         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 159         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 160
 161         rctx->vertex_elements = v;
 162         if (v) {
 163                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 164                                                 v->vmgr_elements);
 165
 166                 rctx->states[v->rstate.id] = &v->rstate;
 167                 r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
 168         }
 169 }
 170
 171 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 172 {
 173         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 174         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 175
 176         if (rctx->states[v->rstate.id] == &v->rstate) {
 177                 rctx->states[v->rstate.id] = NULL;
 178         }
 179         if (rctx->vertex_elements == state)
 180                 rctx->vertex_elements = NULL;
 181
 182         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 183         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 184         FREE(state);
 185 }
 186
 187
 188 void r600_set_index_buffer(struct pipe_context *ctx,
 189                            const struct pipe_index_buffer *ib)
 190 {
 191         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 192
 193         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 194 }
 195
 196 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 197                              const struct pipe_vertex_buffer *buffers)
 198 {
 199         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 200         int i;
 201
 202         /* Zero states. */
 203         for (i = 0; i < count; i++) {
 204                 if (!buffers[i].buffer) {
 205                         if (rctx->chip_class >= EVERGREEN) {
 206                                 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 207                         } else {
 208                                 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 209                         }
 210                 }
 211         }
 212         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 213                 if (rctx->chip_class >= EVERGREEN) {
 214                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 215                 } else {
 216                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 217                 }
 218         }
 219
 220         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 221 }
 222
 223 void *r600_create_vertex_elements(struct pipe_context *ctx,
 224                                   unsigned count,
 225                                   const struct pipe_vertex_element *elements)
 226 {
 227         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 228         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 229
 230         assert(count < 32);
 231         if (!v)
 232                 return NULL;
 233
 234         v->count = count;
 235         v->vmgr_elements =
 236                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 237                                                   elements, v->elements);
 238
 239         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 240                 FREE(v);
 241                 return NULL;
 242         }
 243
 244         return v;
 245 }
 246
 247 void *r600_create_shader_state(struct pipe_context *ctx,
 248                                const struct pipe_shader_state *state)
 249 {
 250         struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
 251         int r;
 252
 253         shader->tokens = tgsi_dup_tokens(state->tokens);
 254
 255         r =  r600_pipe_shader_create(ctx, shader);
 256         if (r) {
 257                 return NULL;
 258         }
 259         return shader;
 260 }
 261
 262 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 263 {
 264         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 265
 266         /* TODO delete old shader */
 267         rctx->ps_shader = (struct r600_pipe_shader *)state;
 268         if (state) {
 269                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 270         }
 271         if (rctx->ps_shader && rctx->vs_shader) {
 272                 r600_adjust_gprs(rctx);
 273         }
 274 }
 275
 276 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 277 {
 278         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 279
 280         /* TODO delete old shader */
 281         rctx->vs_shader = (struct r600_pipe_shader *)state;
 282         if (state) {
 283                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
 284         }
 285         if (rctx->ps_shader && rctx->vs_shader) {
 286                 r600_adjust_gprs(rctx);
 287         }
 288 }
 289
 290 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 291 {
 292         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 293         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 294
 295         if (rctx->ps_shader == shader) {
 296                 rctx->ps_shader = NULL;
 297         }
 298
 299         free(shader->tokens);
 300         r600_pipe_shader_destroy(ctx, shader);
 301         free(shader);
 302 }
 303
 304 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 305 {
 306         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 307         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 308
 309         if (rctx->vs_shader == shader) {
 310                 rctx->vs_shader = NULL;
 311         }
 312
 313         free(shader->tokens);
 314         r600_pipe_shader_destroy(ctx, shader);
 315         free(shader);
 316 }
 317
 318 static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
 319 {
 320         unsigned alpha_ref;
 321         struct r600_pipe_state rstate;
 322
 323         alpha_ref = rctx->alpha_ref;
 324         rstate.nregs = 0;
 325         if (rctx->export_16bpc)
 326                 alpha_ref &= ~0x1FFF;
 327         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0);
 328
 329         r600_context_pipe_state_set(&rctx->ctx, &rstate);
 330         rctx->alpha_ref_dirty = false;
 331 }
 332
 333 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 334                               struct pipe_resource *buffer)
 335 {
 336         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 337         struct r600_resource *rbuffer = r600_resource(buffer);
 338         struct r600_pipe_resource_state *rstate;
 339         uint32_t offset;
 340
 341         /* Note that the state tracker can unbind constant buffers by
 342          * passing NULL here.
 343          */
 344         if (buffer == NULL) {
 345                 return;
 346         }
 347
 348         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 349
 350         switch (shader) {
 351         case PIPE_SHADER_VERTEX:
 352                 rctx->vs_const_buffer.nregs = 0;
 353                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 354                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
 355                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 356                                         0xFFFFFFFF, NULL, 0);
 357                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 358                                         R_028980_ALU_CONST_CACHE_VS_0,
 359                                         offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 360                 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
 361
 362                 rstate = &rctx->vs_const_buffer_resource[index];
 363                 if (!rstate->id) {
 364                         if (rctx->chip_class >= EVERGREEN) {
 365                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 366                         } else {
 367                                 r600_pipe_init_buffer_resource(rctx, rstate);
 368                         }
 369                 }
 370
 371                 if (rctx->chip_class >= EVERGREEN) {
 372                         evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 373                         evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 374                 } else {
 375                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 376                         r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 377                 }
 378                 break;
 379         case PIPE_SHADER_FRAGMENT:
 380                 rctx->ps_const_buffer.nregs = 0;
 381                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 382                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 383                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 384                                         0xFFFFFFFF, NULL, 0);
 385                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 386                                         R_028940_ALU_CONST_CACHE_PS_0,
 387                                         offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
 388                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
 389
 390                 rstate = &rctx->ps_const_buffer_resource[index];
 391                 if (!rstate->id) {
 392                         if (rctx->chip_class >= EVERGREEN) {
 393                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 394                         } else {
 395                                 r600_pipe_init_buffer_resource(rctx, rstate);
 396                         }
 397                 }
 398                 if (rctx->chip_class >= EVERGREEN) {
 399                         evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 400                         evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 401                 } else {
 402                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 403                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 404                 }
 405                 break;
 406         default:
 407                 R600_ERR("unsupported %d\n", shader);
 408                 return;
 409         }
 410
 411         if (buffer != &rbuffer->b.b.b)
 412                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 413 }
 414
 415 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 416 {
 417         struct r600_pipe_resource_state *rstate;
 418         struct r600_resource *rbuffer;
 419         struct pipe_vertex_buffer *vertex_buffer;
 420         unsigned i, count, offset;
 421
 422         if (rctx->vertex_elements->vbuffer_need_offset) {
 423                 /* one resource per vertex elements */
 424                 count = rctx->vertex_elements->count;
 425         } else {
 426                 /* bind vertex buffer once */
 427                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 428         }
 429
 430         for (i = 0 ; i < count; i++) {
 431                 rstate = &rctx->fs_resource[i];
 432
 433                 if (rctx->vertex_elements->vbuffer_need_offset) {
 434                         /* one resource per vertex elements */
 435                         unsigned vbuffer_index;
 436                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 437                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 438                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 439                         offset = rctx->vertex_elements->vbuffer_offset[i];
 440                 } else {
 441                         /* bind vertex buffer once */
 442                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 443                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 444                         offset = 0;
 445                 }
 446                 if (vertex_buffer == NULL || rbuffer == NULL)
 447                         continue;
 448                 offset += vertex_buffer->buffer_offset;
 449
 450                 if (!rstate->id) {
 451                         if (rctx->chip_class >= EVERGREEN) {
 452                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 453                         } else {
 454                                 r600_pipe_init_buffer_resource(rctx, rstate);
 455                         }
 456                 }
 457
 458                 if (rctx->chip_class >= EVERGREEN) {
 459                         evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 460                         evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 461                 } else {
 462                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 463                         r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 464                 }
 465         }
 466 }
 467
 468 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 469 {
 470         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 471         int r;
 472
 473         r600_pipe_shader_destroy(ctx, shader);
 474         r = r600_pipe_shader_create(ctx, shader);
 475         if (r) {
 476                 return r;
 477         }
 478         r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
 479
 480         return 0;
 481 }
 482
 483 static void r600_update_derived_state(struct r600_pipe_context *rctx)
 484 {
 485         struct pipe_context * ctx = (struct pipe_context*)rctx;
 486
 487         if (!rctx->blitter->running) {
 488                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 489                         r600_flush_depth_textures(rctx);
 490         }
 491
 492         if (rctx->chip_class < EVERGREEN) {
 493                 r600_update_sampler_states(rctx);
 494         }
 495
 496         if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color) {
 497                 r600_shader_rebuild(&rctx->context, rctx->vs_shader);
 498         }
 499
 500         if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
 501             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 502              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 503                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 504         }
 505
 506         if (rctx->alpha_ref_dirty) {
 507                 r600_update_alpha_ref(rctx);
 508         }
 509
 510         if (rctx->ps_shader && rctx->sprite_coord_enable &&
 511                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) {
 512
 513                 if (rctx->chip_class >= EVERGREEN)
 514                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 515                 else
 516                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 517
 518                 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
 519         }
 520
 521 }
 522
 523 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 524 {
 525         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 526         struct pipe_draw_info info = *dinfo;
 527         struct r600_draw rdraw = {};
 528         struct pipe_index_buffer ib = {};
 529         unsigned prim, mask, ls_mask = 0;
 530
 531         if (!info.count ||
 532             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 533             !r600_conv_pipe_prim(info.mode, &prim)) {
 534                 return;
 535         }
 536
 537         r600_update_derived_state(rctx);
 538
 539         u_vbuf_draw_begin(rctx->vbuf_mgr, dinfo);
 540         r600_vertex_buffer_update(rctx);
 541
 542         rdraw.vgt_num_indices = info.count;
 543         rdraw.vgt_num_instances = info.instance_count;
 544
 545         if (info.indexed) {
 546                 /* Initialize the index buffer struct. */
 547                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 548                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 549                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 550
 551                 /* Translate or upload, if needed. */
 552                 r600_translate_index_buffer(rctx, &ib, info.count);
 553
 554                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 555                         r600_upload_index_buffer(rctx, &ib, info.count);
 556                 }
 557
 558                 /* Initialize the r600_draw struct with index buffer info. */
 559                 if (ib.index_size == 4) {
 560                         rdraw.vgt_index_type = VGT_INDEX_32 |
 561                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 562                 } else {
 563                         rdraw.vgt_index_type = VGT_INDEX_16 |
 564                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 565                 }
 566                 rdraw.indices = (struct r600_resource*)ib.buffer;
 567                 rdraw.indices_bo_offset = ib.offset;
 568                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 569         } else {
 570                 info.index_bias = info.start;
 571                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 572         }
 573
 574         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 575
 576         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 577                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 578                 rctx->vgt.nregs = 0;
 579                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0);
 580                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0);
 581                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, 0xFFFFFFFF, NULL, 0);
 582                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, 0xFFFFFFFF, NULL, 0);
 583                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, 0xFFFFFFFF, NULL, 0);
 584                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, 0xFFFFFFFF, NULL, 0);
 585                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0);
 586                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
 587                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0);
 588                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE,
 589                                         0,
 590                                         S_028A0C_AUTO_RESET_CNTL(3), NULL, 0);
 591                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
 592                                         0,
 593                                         S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
 594         }
 595
 596         rctx->vgt.nregs = 0;
 597         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 598         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 599         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 600         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 601         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 602         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 603         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 604         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 605         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 606
 607         if (prim == V_008958_DI_PT_LINELIST)
 608                 ls_mask = 1;
 609         else if (prim == V_008958_DI_PT_LINESTRIP)
 610                 ls_mask = 2;
 611         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask));
 612
 613         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 614                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));
 615         }
 616
 617         r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);
 618
 619         if (rctx->chip_class >= EVERGREEN) {
 620                 evergreen_context_draw(&rctx->ctx, &rdraw);
 621         } else {
 622                 r600_context_draw(&rctx->ctx, &rdraw);
 623         }
 624
 625         if (rctx->framebuffer.zsbuf)
 626         {
 627                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 628                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 629         }
 630
 631         pipe_resource_reference(&ib.buffer, NULL);
 632         u_vbuf_draw_end(rctx->vbuf_mgr);
 633 }
 634
 635 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 636                               struct r600_pipe_state *state,
 637                               u32 offset, u32 value, u32 mask,
 638                               u32 range_id, u32 block_id,
 639                               struct r600_resource *bo,
 640                               enum radeon_bo_usage usage)
 641 {
 642         struct r600_range *range;
 643         struct r600_block *block;
 644
 645         if (bo) assert(usage);
 646
 647         range = &ctx->range[range_id];
 648         block = range->blocks[block_id];
 649         state->regs[state->nregs].block = block;
 650         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 651
 652         state->regs[state->nregs].value = value;
 653         state->regs[state->nregs].mask = mask;
 654         state->regs[state->nregs].bo = bo;
 655         state->regs[state->nregs].bo_usage = usage;
 656
 657         state->nregs++;
 658         assert(state->nregs < R600_BLOCK_MAX_REG);
 659 }
 660
 661 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 662                                      u32 offset, u32 value, u32 mask,
 663                                      struct r600_resource *bo,
 664                                      enum radeon_bo_usage usage)
 665 {
 666         if (bo) assert(usage);
 667
 668         state->regs[state->nregs].id = offset;
 669         state->regs[state->nregs].block = NULL;
 670         state->regs[state->nregs].value = value;
 671         state->regs[state->nregs].mask = mask;
 672         state->regs[state->nregs].bo = bo;
 673         state->regs[state->nregs].bo_usage = usage;
 674
 675         state->nregs++;
 676         assert(state->nregs < R600_BLOCK_MAX_REG);
 677 }