projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600: add cull distance support
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
39
40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
41 {
42 assert(!cb->buf);
43 cb->buf = CALLOC(1, 4 * num_dw);
44 cb->max_num_dw = num_dw;
45 }
46
47 void r600_release_command_buffer(struct r600_command_buffer *cb)
48 {
49 FREE(cb->buf);
50 }
51
52 void r600_add_atom(struct r600_context *rctx,
53 struct r600_atom *atom,
54 unsigned id)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->id = id;
60 }
61
62 void r600_init_atom(struct r600_context *rctx,
63 struct r600_atom *atom,
64 unsigned id,
65 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
66 unsigned num_dw)
67 {
68 atom->emit = (void*)emit;
69 atom->num_dw = num_dw;
70 r600_add_atom(rctx, atom, id);
71 }
72
73 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 r600_emit_command_buffer(rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
76 }
77
78 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
79 {
80 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
81 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
82 unsigned alpha_ref = a->sx_alpha_ref;
83
84 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
85 alpha_ref &= ~0x1FFF;
86 }
87
88 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
89 a->sx_alpha_test_control |
90 S_028410_ALPHA_TEST_BYPASS(a->bypass));
91 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
92 }
93
94 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
95 {
96 struct r600_context *rctx = (struct r600_context *)ctx;
97 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
98 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
99
100 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
101 PIPE_BARRIER_SHADER_BUFFER |
102 PIPE_BARRIER_TEXTURE |
103 PIPE_BARRIER_IMAGE |
104 PIPE_BARRIER_STREAMOUT_BUFFER |
105 PIPE_BARRIER_GLOBAL_BUFFER)) {
106 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
107 R600_CONTEXT_INV_TEX_CACHE;
108 }
109
110 if (flags & (PIPE_BARRIER_FRAMEBUFFER|
111 PIPE_BARRIER_IMAGE))
112 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
113
114 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
115 }
116
117 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
118 {
119 struct r600_context *rctx = (struct r600_context *)ctx;
120
121 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
122 R600_CONTEXT_FLUSH_AND_INV_CB |
123 R600_CONTEXT_FLUSH_AND_INV |
124 R600_CONTEXT_WAIT_3D_IDLE;
125 rctx->framebuffer.do_update_surf_dirtiness = true;
126 }
127
128 static unsigned r600_conv_pipe_prim(unsigned prim)
129 {
130 static const unsigned prim_conv[] = {
131 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
132 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
133 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
134 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
135 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
136 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
137 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
138 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
139 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
140 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
141 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
145 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
146 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
147 };
148 assert(prim < ARRAY_SIZE(prim_conv));
149 return prim_conv[prim];
150 }
151
152 unsigned r600_conv_prim_to_gs_out(unsigned mode)
153 {
154 static const int prim_conv[] = {
155 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
156 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
157 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
158 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
159 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
160 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
161 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
162 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
163 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
164 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
165 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
166 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
167 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
168 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
169 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
170 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
171 };
172 assert(mode < ARRAY_SIZE(prim_conv));
173
174 return prim_conv[mode];
175 }
176
177 /* common state between evergreen and r600 */
178
179 static void r600_bind_blend_state_internal(struct r600_context *rctx,
180 struct r600_blend_state *blend, bool blend_disable)
181 {
182 unsigned color_control;
183 bool update_cb = false;
184
185 rctx->alpha_to_one = blend->alpha_to_one;
186 rctx->dual_src_blend = blend->dual_src_blend;
187
188 if (!blend_disable) {
189 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
190 color_control = blend->cb_color_control;
191 } else {
192 /* Blending is disabled. */
193 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
194 color_control = blend->cb_color_control_no_blend;
195 }
196
197 /* Update derived states. */
198 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
199 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
200 update_cb = true;
201 }
202 if (rctx->b.chip_class <= R700 &&
203 rctx->cb_misc_state.cb_color_control != color_control) {
204 rctx->cb_misc_state.cb_color_control = color_control;
205 update_cb = true;
206 }
207 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
208 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
209 update_cb = true;
210 }
211 if (update_cb) {
212 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
213 }
214 if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) {
215 rctx->framebuffer.dual_src_blend = blend->dual_src_blend;
216 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
217 }
218 }
219
220 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
221 {
222 struct r600_context *rctx = (struct r600_context *)ctx;
223 struct r600_blend_state *blend = (struct r600_blend_state *)state;
224
225 if (!blend) {
226 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
227 return;
228 }
229
230 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
231 }
232
233 static void r600_set_blend_color(struct pipe_context *ctx,
234 const struct pipe_blend_color *state)
235 {
236 struct r600_context *rctx = (struct r600_context *)ctx;
237
238 rctx->blend_color.state = *state;
239 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
240 }
241
242 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
243 {
244 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
245 struct pipe_blend_color *state = &rctx->blend_color.state;
246
247 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
248 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
249 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
250 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
251 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
252 }
253
254 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
255 {
256 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
257 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
258
259 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
260 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
261 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
262 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
263 if (a->last_draw_was_indirect) {
264 a->last_draw_was_indirect = false;
265 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
266 }
267 }
268
269 static void r600_set_clip_state(struct pipe_context *ctx,
270 const struct pipe_clip_state *state)
271 {
272 struct r600_context *rctx = (struct r600_context *)ctx;
273
274 rctx->clip_state.state = *state;
275 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
276 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
277 }
278
279 static void r600_set_stencil_ref(struct pipe_context *ctx,
280 const struct r600_stencil_ref *state)
281 {
282 struct r600_context *rctx = (struct r600_context *)ctx;
283
284 rctx->stencil_ref.state = *state;
285 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
286 }
287
288 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
289 {
290 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
291 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
292
293 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
294 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
295 S_028430_STENCILREF(a->state.ref_value[0]) |
296 S_028430_STENCILMASK(a->state.valuemask[0]) |
297 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
298 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
299 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
300 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
301 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
302 }
303
304 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
305 const struct pipe_stencil_ref *state)
306 {
307 struct r600_context *rctx = (struct r600_context *)ctx;
308 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
309 struct r600_stencil_ref ref;
310
311 rctx->stencil_ref.pipe_state = *state;
312
313 if (!dsa)
314 return;
315
316 ref.ref_value[0] = state->ref_value[0];
317 ref.ref_value[1] = state->ref_value[1];
318 ref.valuemask[0] = dsa->valuemask[0];
319 ref.valuemask[1] = dsa->valuemask[1];
320 ref.writemask[0] = dsa->writemask[0];
321 ref.writemask[1] = dsa->writemask[1];
322
323 r600_set_stencil_ref(ctx, &ref);
324 }
325
326 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
327 {
328 struct r600_context *rctx = (struct r600_context *)ctx;
329 struct r600_dsa_state *dsa = state;
330 struct r600_stencil_ref ref;
331
332 if (!state) {
333 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
334 return;
335 }
336
337 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
338
339 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
340 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
341 ref.valuemask[0] = dsa->valuemask[0];
342 ref.valuemask[1] = dsa->valuemask[1];
343 ref.writemask[0] = dsa->writemask[0];
344 ref.writemask[1] = dsa->writemask[1];
345 if (rctx->zwritemask != dsa->zwritemask) {
346 rctx->zwritemask = dsa->zwritemask;
347 if (rctx->b.chip_class >= EVERGREEN) {
348 /* work around some issue when not writing to zbuffer
349 * we are having lockup on evergreen so do not enable
350 * hyperz when not writing zbuffer
351 */
352 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
353 }
354 }
355
356 r600_set_stencil_ref(ctx, &ref);
357
358 /* Update alphatest state. */
359 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
360 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
361 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
362 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
363 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
364 }
365 }
366
367 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
368 {
369 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
370 struct r600_context *rctx = (struct r600_context *)ctx;
371
372 if (!state)
373 return;
374
375 rctx->rasterizer = rs;
376
377 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
378
379 if (rs->offset_enable &&
380 (rs->offset_units != rctx->poly_offset_state.offset_units ||
381 rs->offset_scale != rctx->poly_offset_state.offset_scale ||
382 rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
383 rctx->poly_offset_state.offset_units = rs->offset_units;
384 rctx->poly_offset_state.offset_scale = rs->offset_scale;
385 rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
386 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
387 }
388
389 /* Update clip_misc_state. */
390 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
391 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
392 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
393 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
394 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
395 }
396
397 r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
398
399 /* Re-emit PA_SC_LINE_STIPPLE. */
400 rctx->last_primitive_type = -1;
401 }
402
403 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
404 {
405 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
406
407 r600_release_command_buffer(&rs->buffer);
408 FREE(rs);
409 }
410
411 static void r600_sampler_view_destroy(struct pipe_context *ctx,
412 struct pipe_sampler_view *state)
413 {
414 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
415
416 if (view->tex_resource->gpu_address &&
417 view->tex_resource->b.b.target == PIPE_BUFFER)
418 LIST_DELINIT(&view->list);
419
420 pipe_resource_reference(&state->texture, NULL);
421 FREE(view);
422 }
423
424 void r600_sampler_states_dirty(struct r600_context *rctx,
425 struct r600_sampler_states *state)
426 {
427 if (state->dirty_mask) {
428 if (state->dirty_mask & state->has_bordercolor_mask) {
429 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
430 }
431 state->atom.num_dw =
432 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
433 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
434 r600_mark_atom_dirty(rctx, &state->atom);
435 }
436 }
437
438 static void r600_bind_sampler_states(struct pipe_context *pipe,
439 enum pipe_shader_type shader,
440 unsigned start,
441 unsigned count, void **states)
442 {
443 struct r600_context *rctx = (struct r600_context *)pipe;
444 struct r600_textures_info *dst = &rctx->samplers[shader];
445 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
446 int seamless_cube_map = -1;
447 unsigned i;
448 /* This sets 1-bit for states with index >= count. */
449 uint32_t disable_mask = ~((1ull << count) - 1);
450 /* These are the new states set by this function. */
451 uint32_t new_mask = 0;
452
453 assert(start == 0); /* XXX fix below */
454
455 if (!states) {
456 disable_mask = ~0u;
457 count = 0;
458 }
459
460 for (i = 0; i < count; i++) {
461 struct r600_pipe_sampler_state *rstate = rstates[i];
462
463 if (rstate == dst->states.states[i]) {
464 continue;
465 }
466
467 if (rstate) {
468 if (rstate->border_color_use) {
469 dst->states.has_bordercolor_mask |= 1 << i;
470 } else {
471 dst->states.has_bordercolor_mask &= ~(1 << i);
472 }
473 seamless_cube_map = rstate->seamless_cube_map;
474
475 new_mask |= 1 << i;
476 } else {
477 disable_mask |= 1 << i;
478 }
479 }
480
481 memcpy(dst->states.states, rstates, sizeof(void*) * count);
482 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
483
484 dst->states.enabled_mask &= ~disable_mask;
485 dst->states.dirty_mask &= dst->states.enabled_mask;
486 dst->states.enabled_mask |= new_mask;
487 dst->states.dirty_mask |= new_mask;
488 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
489
490 r600_sampler_states_dirty(rctx, &dst->states);
491
492 /* Seamless cubemap state. */
493 if (rctx->b.chip_class <= R700 &&
494 seamless_cube_map != -1 &&
495 seamless_cube_map != rctx->seamless_cube_map.enabled) {
496 /* change in TA_CNTL_AUX need a pipeline flush */
497 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
498 rctx->seamless_cube_map.enabled = seamless_cube_map;
499 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
500 }
501 }
502
503 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
504 {
505 free(state);
506 }
507
508 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
509 {
510 struct r600_context *rctx = (struct r600_context *)ctx;
511 struct r600_blend_state *blend = (struct r600_blend_state*)state;
512
513 if (rctx->blend_state.cso == state) {
514 ctx->bind_blend_state(ctx, NULL);
515 }
516
517 r600_release_command_buffer(&blend->buffer);
518 r600_release_command_buffer(&blend->buffer_no_blend);
519 FREE(blend);
520 }
521
522 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
523 {
524 struct r600_context *rctx = (struct r600_context *)ctx;
525 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
526
527 if (rctx->dsa_state.cso == state) {
528 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
529 }
530
531 r600_release_command_buffer(&dsa->buffer);
532 free(dsa);
533 }
534
535 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
536 {
537 struct r600_context *rctx = (struct r600_context *)ctx;
538
539 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
540 }
541
542 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
543 {
544 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
545 r600_resource_reference(&shader->buffer, NULL);
546 FREE(shader);
547 }
548
549 void r600_vertex_buffers_dirty(struct r600_context *rctx)
550 {
551 if (rctx->vertex_buffer_state.dirty_mask) {
552 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
553 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
554 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
555 }
556 }
557
558 static void r600_set_vertex_buffers(struct pipe_context *ctx,
559 unsigned start_slot, unsigned count,
560 const struct pipe_vertex_buffer *input)
561 {
562 struct r600_context *rctx = (struct r600_context *)ctx;
563 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
564 struct pipe_vertex_buffer *vb = state->vb + start_slot;
565 unsigned i;
566 uint32_t disable_mask = 0;
567 /* These are the new buffers set by this function. */
568 uint32_t new_buffer_mask = 0;
569
570 /* Set vertex buffers. */
571 if (input) {
572 for (i = 0; i < count; i++) {
573 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
574 if (input[i].buffer.resource) {
575 vb[i].stride = input[i].stride;
576 vb[i].buffer_offset = input[i].buffer_offset;
577 pipe_resource_reference(&vb[i].buffer.resource, input[i].buffer.resource);
578 new_buffer_mask |= 1 << i;
579 r600_context_add_resource_size(ctx, input[i].buffer.resource);
580 } else {
581 pipe_resource_reference(&vb[i].buffer.resource, NULL);
582 disable_mask |= 1 << i;
583 }
584 }
585 }
586 } else {
587 for (i = 0; i < count; i++) {
588 pipe_resource_reference(&vb[i].buffer.resource, NULL);
589 }
590 disable_mask = ((1ull << count) - 1);
591 }
592
593 disable_mask <<= start_slot;
594 new_buffer_mask <<= start_slot;
595
596 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
597 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
598 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
599 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
600
601 r600_vertex_buffers_dirty(rctx);
602 }
603
604 void r600_sampler_views_dirty(struct r600_context *rctx,
605 struct r600_samplerview_state *state)
606 {
607 if (state->dirty_mask) {
608 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
609 util_bitcount(state->dirty_mask);
610 r600_mark_atom_dirty(rctx, &state->atom);
611 }
612 }
613
614 static void r600_set_sampler_views(struct pipe_context *pipe,
615 enum pipe_shader_type shader,
616 unsigned start, unsigned count,
617 struct pipe_sampler_view **views)
618 {
619 struct r600_context *rctx = (struct r600_context *) pipe;
620 struct r600_textures_info *dst = &rctx->samplers[shader];
621 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
622 uint32_t dirty_sampler_states_mask = 0;
623 unsigned i;
624 /* This sets 1-bit for textures with index >= count. */
625 uint32_t disable_mask = ~((1ull << count) - 1);
626 /* These are the new textures set by this function. */
627 uint32_t new_mask = 0;
628
629 /* Set textures with index >= count to NULL. */
630 uint32_t remaining_mask;
631
632 assert(start == 0); /* XXX fix below */
633
634 if (!views) {
635 disable_mask = ~0u;
636 count = 0;
637 }
638
639 remaining_mask = dst->views.enabled_mask & disable_mask;
640
641 while (remaining_mask) {
642 i = u_bit_scan(&remaining_mask);
643 assert(dst->views.views[i]);
644
645 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
646 }
647
648 for (i = 0; i < count; i++) {
649 if (rviews[i] == dst->views.views[i]) {
650 continue;
651 }
652
653 if (rviews[i]) {
654 struct r600_texture *rtex =
655 (struct r600_texture*)rviews[i]->base.texture;
656 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
657
658 if (!is_buffer && rtex->db_compatible) {
659 dst->views.compressed_depthtex_mask |= 1 << i;
660 } else {
661 dst->views.compressed_depthtex_mask &= ~(1 << i);
662 }
663
664 /* Track compressed colorbuffers. */
665 if (!is_buffer && rtex->cmask.size) {
666 dst->views.compressed_colortex_mask |= 1 << i;
667 } else {
668 dst->views.compressed_colortex_mask &= ~(1 << i);
669 }
670
671 /* Changing from array to non-arrays textures and vice versa requires
672 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
673 if (rctx->b.chip_class <= R700 &&
674 (dst->states.enabled_mask & (1 << i)) &&
675 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
676 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
677 dirty_sampler_states_mask |= 1 << i;
678 }
679
680 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
681 new_mask |= 1 << i;
682 r600_context_add_resource_size(pipe, views[i]->texture);
683 } else {
684 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
685 disable_mask |= 1 << i;
686 }
687 }
688
689 dst->views.enabled_mask &= ~disable_mask;
690 dst->views.dirty_mask &= dst->views.enabled_mask;
691 dst->views.enabled_mask |= new_mask;
692 dst->views.dirty_mask |= new_mask;
693 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
694 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
695 dst->views.dirty_buffer_constants = TRUE;
696 r600_sampler_views_dirty(rctx, &dst->views);
697
698 if (dirty_sampler_states_mask) {
699 dst->states.dirty_mask |= dirty_sampler_states_mask;
700 r600_sampler_states_dirty(rctx, &dst->states);
701 }
702 }
703
704 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
705 {
706 uint32_t mask = views->enabled_mask;
707
708 while (mask) {
709 unsigned i = u_bit_scan(&mask);
710 struct pipe_resource *res = views->views[i]->base.texture;
711
712 if (res && res->target != PIPE_BUFFER) {
713 struct r600_texture *rtex = (struct r600_texture *)res;
714
715 if (rtex->cmask.size) {
716 views->compressed_colortex_mask |= 1 << i;
717 } else {
718 views->compressed_colortex_mask &= ~(1 << i);
719 }
720 }
721 }
722 }
723
724 static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
725 enum pipe_shader_type shader)
726 {
727 const struct r600_context *rctx = (struct r600_context *)ctx;
728 int value = 0;
729 switch (shader) {
730 case PIPE_SHADER_FRAGMENT:
731 case PIPE_SHADER_COMPUTE:
732 default:
733 break;
734 case PIPE_SHADER_VERTEX:
735 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
736 break;
737 case PIPE_SHADER_GEOMETRY:
738 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
739 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
740 break;
741 case PIPE_SHADER_TESS_EVAL:
742 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
743 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
744 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0);
745 break;
746 case PIPE_SHADER_TESS_CTRL:
747 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
748 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
749 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0) +
750 rctx->tes_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
751 break;
752 }
753 return value;
754 }
755
756 static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
757 {
758 uint32_t mask = images->enabled_mask;
759
760 while (mask) {
761 unsigned i = u_bit_scan(&mask);
762 struct pipe_resource *res = images->views[i].base.resource;
763
764 if (res && res->target != PIPE_BUFFER) {
765 struct r600_texture *rtex = (struct r600_texture *)res;
766
767 if (rtex->cmask.size) {
768 images->compressed_colortex_mask |= 1 << i;
769 } else {
770 images->compressed_colortex_mask &= ~(1 << i);
771 }
772 }
773 }
774 }
775
776 /* Compute the key for the hw shader variant */
777 static inline void r600_shader_selector_key(const struct pipe_context *ctx,
778 const struct r600_pipe_shader_selector *sel,
779 union r600_shader_key *key)
780 {
781 const struct r600_context *rctx = (struct r600_context *)ctx;
782 memset(key, 0, sizeof(*key));
783
784 switch (sel->type) {
785 case PIPE_SHADER_VERTEX: {
786 key->vs.as_ls = (rctx->tes_shader != NULL);
787 if (!key->vs.as_ls)
788 key->vs.as_es = (rctx->gs_shader != NULL);
789
790 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
791 key->vs.as_gs_a = true;
792 key->vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
793 }
794 key->vs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_VERTEX);
795 break;
796 }
797 case PIPE_SHADER_GEOMETRY:
798 key->gs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_GEOMETRY);
799 key->gs.tri_strip_adj_fix = rctx->gs_tri_strip_adj_fix;
800 break;
801 case PIPE_SHADER_FRAGMENT: {
802 if (rctx->ps_shader->info.images_declared)
803 key->ps.image_size_const_offset = util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask);
804 key->ps.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_FRAGMENT);
805 key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
806 key->ps.alpha_to_one = rctx->alpha_to_one &&
807 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
808 !rctx->framebuffer.cb0_is_integer;
809 key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
810 /* Dual-source blending only makes sense with nr_cbufs == 1. */
811 if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend)
812 key->ps.nr_cbufs = 2;
813 break;
814 }
815 case PIPE_SHADER_TESS_EVAL:
816 key->tes.as_es = (rctx->gs_shader != NULL);
817 key->tes.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_EVAL);
818 break;
819 case PIPE_SHADER_TESS_CTRL:
820 key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
821 key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_CTRL);
822 break;
823 default:
824 assert(0);
825 }
826 }
827
828 /* Select the hw shader variant depending on the current state.
829 * (*dirty) is set to 1 if current variant was changed */
830 static int r600_shader_select(struct pipe_context *ctx,
831 struct r600_pipe_shader_selector* sel,
832 bool *dirty)
833 {
834 union r600_shader_key key;
835 struct r600_pipe_shader * shader = NULL;
836 int r;
837
838 r600_shader_selector_key(ctx, sel, &key);
839
840 /* Check if we don't need to change anything.
841 * This path is also used for most shaders that don't need multiple
842 * variants, it will cost just a computation of the key and this
843 * test. */
844 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
845 return 0;
846 }
847
848 /* lookup if we have other variants in the list */
849 if (sel->num_shaders > 1) {
850 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
851
852 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
853 p = c;
854 c = c->next_variant;
855 }
856
857 if (c) {
858 p->next_variant = c->next_variant;
859 shader = c;
860 }
861 }
862
863 if (unlikely(!shader)) {
864 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
865 shader->selector = sel;
866
867 r = r600_pipe_shader_create(ctx, shader, key);
868 if (unlikely(r)) {
869 R600_ERR("Failed to build shader variant (type=%u) %d\n",
870 sel->type, r);
871 sel->current = NULL;
872 FREE(shader);
873 return r;
874 }
875
876 /* We don't know the value of nr_ps_max_color_exports until we built
877 * at least one variant, so we may need to recompute the key after
878 * building first variant. */
879 if (sel->type == PIPE_SHADER_FRAGMENT &&
880 sel->num_shaders == 0) {
881 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
882 r600_shader_selector_key(ctx, sel, &key);
883 }
884
885 memcpy(&shader->key, &key, sizeof(key));
886 sel->num_shaders++;
887 }
888
889 if (dirty)
890 *dirty = true;
891
892 shader->next_variant = sel->current;
893 sel->current = shader;
894
895 return 0;
896 }
897
898 static void *r600_create_shader_state(struct pipe_context *ctx,
899 const struct pipe_shader_state *state,
900 unsigned pipe_shader_type)
901 {
902 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
903 int i;
904
905 sel->type = pipe_shader_type;
906 sel->tokens = tgsi_dup_tokens(state->tokens);
907 sel->so = state->stream_output;
908 tgsi_scan_shader(state->tokens, &sel->info);
909
910 switch (pipe_shader_type) {
911 case PIPE_SHADER_GEOMETRY:
912 sel->gs_output_prim =
913 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
914 sel->gs_max_out_vertices =
915 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
916 sel->gs_num_invocations =
917 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
918 break;
919 case PIPE_SHADER_VERTEX:
920 case PIPE_SHADER_TESS_CTRL:
921 sel->lds_patch_outputs_written_mask = 0;
922 sel->lds_outputs_written_mask = 0;
923
924 for (i = 0; i < sel->info.num_outputs; i++) {
925 unsigned name = sel->info.output_semantic_name[i];
926 unsigned index = sel->info.output_semantic_index[i];
927
928 switch (name) {
929 case TGSI_SEMANTIC_TESSINNER:
930 case TGSI_SEMANTIC_TESSOUTER:
931 case TGSI_SEMANTIC_PATCH:
932 sel->lds_patch_outputs_written_mask |=
933 1ull << r600_get_lds_unique_index(name, index);
934 break;
935 default:
936 sel->lds_outputs_written_mask |=
937 1ull << r600_get_lds_unique_index(name, index);
938 }
939 }
940 break;
941 default:
942 break;
943 }
944
945 return sel;
946 }
947
948 static void *r600_create_ps_state(struct pipe_context *ctx,
949 const struct pipe_shader_state *state)
950 {
951 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
952 }
953
954 static void *r600_create_vs_state(struct pipe_context *ctx,
955 const struct pipe_shader_state *state)
956 {
957 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
958 }
959
960 static void *r600_create_gs_state(struct pipe_context *ctx,
961 const struct pipe_shader_state *state)
962 {
963 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
964 }
965
966 static void *r600_create_tcs_state(struct pipe_context *ctx,
967 const struct pipe_shader_state *state)
968 {
969 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
970 }
971
972 static void *r600_create_tes_state(struct pipe_context *ctx,
973 const struct pipe_shader_state *state)
974 {
975 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
976 }
977
978 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
979 {
980 struct r600_context *rctx = (struct r600_context *)ctx;
981
982 if (!state)
983 state = rctx->dummy_pixel_shader;
984
985 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
986 }
987
988 static struct tgsi_shader_info *r600_get_vs_info(struct r600_context *rctx)
989 {
990 if (rctx->gs_shader)
991 return &rctx->gs_shader->info;
992 else if (rctx->tes_shader)
993 return &rctx->tes_shader->info;
994 else if (rctx->vs_shader)
995 return &rctx->vs_shader->info;
996 else
997 return NULL;
998 }
999
1000 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
1001 {
1002 struct r600_context *rctx = (struct r600_context *)ctx;
1003
1004 if (!state || rctx->vs_shader == state)
1005 return;
1006
1007 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
1008 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1009 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
1010 }
1011
1012 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
1013 {
1014 struct r600_context *rctx = (struct r600_context *)ctx;
1015
1016 if (state == rctx->gs_shader)
1017 return;
1018
1019 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
1020 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1021
1022 if (!state)
1023 return;
1024 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
1025 }
1026
1027 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
1028 {
1029 struct r600_context *rctx = (struct r600_context *)ctx;
1030
1031 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
1032 }
1033
1034 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
1035 {
1036 struct r600_context *rctx = (struct r600_context *)ctx;
1037
1038 if (state == rctx->tes_shader)
1039 return;
1040
1041 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
1042 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1043
1044 if (!state)
1045 return;
1046 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1047 }
1048
1049 static void r600_delete_shader_selector(struct pipe_context *ctx,
1050 struct r600_pipe_shader_selector *sel)
1051 {
1052 struct r600_pipe_shader *p = sel->current, *c;
1053 while (p) {
1054 c = p->next_variant;
1055 r600_pipe_shader_destroy(ctx, p);
1056 free(p);
1057 p = c;
1058 }
1059
1060 free(sel->tokens);
1061 free(sel);
1062 }
1063
1064
1065 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1066 {
1067 struct r600_context *rctx = (struct r600_context *)ctx;
1068 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1069
1070 if (rctx->ps_shader == sel) {
1071 rctx->ps_shader = NULL;
1072 }
1073
1074 r600_delete_shader_selector(ctx, sel);
1075 }
1076
1077 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1078 {
1079 struct r600_context *rctx = (struct r600_context *)ctx;
1080 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1081
1082 if (rctx->vs_shader == sel) {
1083 rctx->vs_shader = NULL;
1084 }
1085
1086 r600_delete_shader_selector(ctx, sel);
1087 }
1088
1089
1090 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1091 {
1092 struct r600_context *rctx = (struct r600_context *)ctx;
1093 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1094
1095 if (rctx->gs_shader == sel) {
1096 rctx->gs_shader = NULL;
1097 }
1098
1099 r600_delete_shader_selector(ctx, sel);
1100 }
1101
1102 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1103 {
1104 struct r600_context *rctx = (struct r600_context *)ctx;
1105 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1106
1107 if (rctx->tcs_shader == sel) {
1108 rctx->tcs_shader = NULL;
1109 }
1110
1111 r600_delete_shader_selector(ctx, sel);
1112 }
1113
1114 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1115 {
1116 struct r600_context *rctx = (struct r600_context *)ctx;
1117 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1118
1119 if (rctx->tes_shader == sel) {
1120 rctx->tes_shader = NULL;
1121 }
1122
1123 r600_delete_shader_selector(ctx, sel);
1124 }
1125
1126 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1127 {
1128 if (state->dirty_mask) {
1129 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1130 : util_bitcount(state->dirty_mask)*19;
1131 r600_mark_atom_dirty(rctx, &state->atom);
1132 }
1133 }
1134
1135 static void r600_set_constant_buffer(struct pipe_context *ctx,
1136 enum pipe_shader_type shader, uint index,
1137 const struct pipe_constant_buffer *input)
1138 {
1139 struct r600_context *rctx = (struct r600_context *)ctx;
1140 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1141 struct pipe_constant_buffer *cb;
1142 const uint8_t *ptr;
1143
1144 /* Note that the state tracker can unbind constant buffers by
1145 * passing NULL here.
1146 */
1147 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1148 state->enabled_mask &= ~(1 << index);
1149 state->dirty_mask &= ~(1 << index);
1150 pipe_resource_reference(&state->cb[index].buffer, NULL);
1151 return;
1152 }
1153
1154 cb = &state->cb[index];
1155 cb->buffer_size = input->buffer_size;
1156
1157 ptr = input->user_buffer;
1158
1159 if (ptr) {
1160 /* Upload the user buffer. */
1161 if (R600_BIG_ENDIAN) {
1162 uint32_t *tmpPtr;
1163 unsigned i, size = input->buffer_size;
1164
1165 if (!(tmpPtr = malloc(size))) {
1166 R600_ERR("Failed to allocate BE swap buffer.\n");
1167 return;
1168 }
1169
1170 for (i = 0; i < size / 4; ++i) {
1171 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1172 }
1173
1174 u_upload_data(ctx->stream_uploader, 0, size, 256,
1175 tmpPtr, &cb->buffer_offset, &cb->buffer);
1176 free(tmpPtr);
1177 } else {
1178 u_upload_data(ctx->stream_uploader, 0,
1179 input->buffer_size, 256, ptr,
1180 &cb->buffer_offset, &cb->buffer);
1181 }
1182 /* account it in gtt */
1183 rctx->b.gtt += input->buffer_size;
1184 } else {
1185 /* Setup the hw buffer. */
1186 cb->buffer_offset = input->buffer_offset;
1187 pipe_resource_reference(&cb->buffer, input->buffer);
1188 r600_context_add_resource_size(ctx, input->buffer);
1189 }
1190
1191 state->enabled_mask |= 1 << index;
1192 state->dirty_mask |= 1 << index;
1193 r600_constant_buffers_dirty(rctx, state);
1194 }
1195
1196 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1197 {
1198 struct r600_context *rctx = (struct r600_context*)pipe;
1199
1200 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1201 return;
1202
1203 rctx->sample_mask.sample_mask = sample_mask;
1204 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1205 }
1206
1207 static void r600_update_driver_const_buffers(struct r600_context *rctx)
1208 {
1209 int sh, size;
1210 void *ptr;
1211 struct pipe_constant_buffer cb;
1212 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
1213 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1214 if (!info->vs_ucp_dirty &&
1215 !info->texture_const_dirty &&
1216 !info->ps_sample_pos_dirty)
1217 continue;
1218
1219 ptr = info->constants;
1220 size = info->alloc_size;
1221 if (info->vs_ucp_dirty) {
1222 assert(sh == PIPE_SHADER_VERTEX);
1223 if (!size) {
1224 ptr = rctx->clip_state.state.ucp;
1225 size = R600_UCP_SIZE;
1226 } else {
1227 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1228 }
1229 info->vs_ucp_dirty = false;
1230 }
1231
1232 if (info->ps_sample_pos_dirty) {
1233 assert(sh == PIPE_SHADER_FRAGMENT);
1234 if (!size) {
1235 ptr = rctx->sample_positions;
1236 size = R600_UCP_SIZE;
1237 } else {
1238 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1239 }
1240 info->ps_sample_pos_dirty = false;
1241 }
1242
1243 if (info->texture_const_dirty) {
1244 assert (ptr);
1245 assert (size);
1246 if (sh == PIPE_SHADER_VERTEX)
1247 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1248 if (sh == PIPE_SHADER_FRAGMENT)
1249 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1250 }
1251 info->texture_const_dirty = false;
1252
1253 cb.buffer = NULL;
1254 cb.user_buffer = ptr;
1255 cb.buffer_offset = 0;
1256 cb.buffer_size = size;
1257 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1258 pipe_resource_reference(&cb.buffer, NULL);
1259 }
1260 }
1261
1262 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1263 int array_size, uint32_t *base_offset)
1264 {
1265 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1266 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1267 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1268 info->alloc_size = array_size + R600_UCP_SIZE;
1269 }
1270 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1271 info->texture_const_dirty = true;
1272 *base_offset = R600_UCP_SIZE;
1273 return info->constants;
1274 }
1275 /*
1276 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1277 * doesn't require full swizzles it does need masking and setting alpha
1278 * to one, so we setup a set of 5 constants with the masks + alpha value
1279 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1280 * then OR the alpha with the value given here.
1281 * We use a 6th constant to store the txq buffer size in
1282 * we use 7th slot for number of cube layers in a cube map array.
1283 */
1284 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1285 {
1286 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1287 int bits;
1288 uint32_t array_size;
1289 int i, j;
1290 uint32_t *constants;
1291 uint32_t base_offset;
1292 if (!samplers->views.dirty_buffer_constants)
1293 return;
1294
1295 samplers->views.dirty_buffer_constants = FALSE;
1296
1297 bits = util_last_bit(samplers->views.enabled_mask);
1298 array_size = bits * 8 * sizeof(uint32_t) * 4;
1299
1300 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1301
1302 for (i = 0; i < bits; i++) {
1303 if (samplers->views.enabled_mask & (1 << i)) {
1304 int offset = (base_offset / 4) + i * 8;
1305 const struct util_format_description *desc;
1306 desc = util_format_description(samplers->views.views[i]->base.format);
1307
1308 for (j = 0; j < 4; j++)
1309 if (j < desc->nr_channels)
1310 constants[offset+j] = 0xffffffff;
1311 else
1312 constants[offset+j] = 0x0;
1313 if (desc->nr_channels < 4) {
1314 if (desc->channel[0].pure_integer)
1315 constants[offset+4] = 1;
1316 else
1317 constants[offset+4] = fui(1.0);
1318 } else
1319 constants[offset + 4] = 0;
1320
1321 constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1322 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1323 }
1324 }
1325
1326 }
1327
1328 /* On evergreen we store two values
1329 * 1. buffer size for TXQ
1330 * 2. number of cube layers in a cube map array.
1331 */
1332 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1333 {
1334 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1335 struct r600_image_state *images = NULL;
1336 int bits, sview_bits;
1337 uint32_t array_size;
1338 int i;
1339 uint32_t *constants;
1340 uint32_t base_offset;
1341
1342 if (shader_type == PIPE_SHADER_FRAGMENT)
1343 images = &rctx->fragment_images;
1344
1345 if (!samplers->views.dirty_buffer_constants &&
1346 (images && !images->dirty_buffer_constants))
1347 return;
1348
1349 if (images)
1350 images->dirty_buffer_constants = FALSE;
1351 samplers->views.dirty_buffer_constants = FALSE;
1352
1353 bits = sview_bits = util_last_bit(samplers->views.enabled_mask);
1354 if (images)
1355 bits += util_last_bit(images->enabled_mask);
1356 array_size = bits * 2 * sizeof(uint32_t) * 4;
1357
1358 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1359 &base_offset);
1360
1361 for (i = 0; i < sview_bits; i++) {
1362 if (samplers->views.enabled_mask & (1 << i)) {
1363 uint32_t offset = (base_offset / 4) + i * 2;
1364 constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1365 constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
1366 }
1367 }
1368 if (images) {
1369 for (i = sview_bits; i < bits; i++) {
1370 int idx = i - sview_bits;
1371 if (images->enabled_mask & (1 << idx)) {
1372 uint32_t offset = (base_offset / 4) + i * 2;
1373 constants[offset] = images->views[i].base.resource->width0 / util_format_get_blocksize(images->views[i].base.format);
1374 constants[offset + 1] = images->views[i].base.resource->array_size / 6;
1375 }
1376 }
1377 }
1378 }
1379
1380 /* set sample xy locations as array of fragment shader constants */
1381 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1382 {
1383 int i;
1384 struct pipe_context *ctx = &rctx->b.b;
1385
1386 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1387 assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4);
1388
1389 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1390 for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1391 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1392 /* Also fill in center-zeroed positions used for interpolateAtSample */
1393 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1394 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1395 }
1396
1397 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1398 }
1399
1400 static void update_shader_atom(struct pipe_context *ctx,
1401 struct r600_shader_state *state,
1402 struct r600_pipe_shader *shader)
1403 {
1404 struct r600_context *rctx = (struct r600_context *)ctx;
1405
1406 state->shader = shader;
1407 if (shader) {
1408 state->atom.num_dw = shader->command_buffer.num_dw;
1409 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1410 } else {
1411 state->atom.num_dw = 0;
1412 }
1413 r600_mark_atom_dirty(rctx, &state->atom);
1414 }
1415
1416 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1417 {
1418 if (rctx->shader_stages.geom_enable != enable) {
1419 rctx->shader_stages.geom_enable = enable;
1420 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1421 }
1422
1423 if (rctx->gs_rings.enable != enable) {
1424 rctx->gs_rings.enable = enable;
1425 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1426
1427 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1428 unsigned size = 0x1C000;
1429 rctx->gs_rings.esgs_ring.buffer =
1430 pipe_buffer_create(rctx->b.b.screen, 0,
1431 PIPE_USAGE_DEFAULT, size);
1432 rctx->gs_rings.esgs_ring.buffer_size = size;
1433
1434 size = 0x4000000;
1435
1436 rctx->gs_rings.gsvs_ring.buffer =
1437 pipe_buffer_create(rctx->b.b.screen, 0,
1438 PIPE_USAGE_DEFAULT, size);
1439 rctx->gs_rings.gsvs_ring.buffer_size = size;
1440 }
1441
1442 if (enable) {
1443 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1444 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1445 if (rctx->tes_shader) {
1446 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1447 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1448 } else {
1449 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1450 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1451 }
1452 } else {
1453 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1454 R600_GS_RING_CONST_BUFFER, NULL);
1455 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1456 R600_GS_RING_CONST_BUFFER, NULL);
1457 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1458 R600_GS_RING_CONST_BUFFER, NULL);
1459 }
1460 }
1461 }
1462
1463 static void r600_update_clip_state(struct r600_context *rctx,
1464 struct r600_pipe_shader *current)
1465 {
1466 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1467 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1468 current->shader.cull_dist_write != rctx->clip_misc_state.cull_dist_write ||
1469 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1470 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1471 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1472 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1473 rctx->clip_misc_state.cull_dist_write = current->shader.cull_dist_write;
1474 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1475 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1476 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1477 }
1478 }
1479
1480 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1481 {
1482 struct ureg_src const0, const1;
1483 struct ureg_dst tessouter, tessinner;
1484 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1485
1486 if (!ureg)
1487 return; /* if we get here, we're screwed */
1488
1489 assert(!rctx->fixed_func_tcs_shader);
1490
1491 ureg_DECL_constant2D(ureg, 0, 3, R600_LDS_INFO_CONST_BUFFER);
1492 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 2),
1493 R600_LDS_INFO_CONST_BUFFER);
1494 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 3),
1495 R600_LDS_INFO_CONST_BUFFER);
1496
1497 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1498 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1499
1500 ureg_MOV(ureg, tessouter, const0);
1501 ureg_MOV(ureg, tessinner, const1);
1502 ureg_END(ureg);
1503
1504 rctx->fixed_func_tcs_shader =
1505 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1506 }
1507
1508 static void r600_update_compressed_resource_state(struct r600_context *rctx)
1509 {
1510 unsigned i;
1511 unsigned counter;
1512
1513 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1514 if (counter != rctx->b.last_compressed_colortex_counter) {
1515 rctx->b.last_compressed_colortex_counter = counter;
1516
1517 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1518 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1519 }
1520 r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
1521 }
1522
1523 /* Decompress textures if needed. */
1524 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1525 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1526 if (views->compressed_depthtex_mask) {
1527 r600_decompress_depth_textures(rctx, views);
1528 }
1529 if (views->compressed_colortex_mask) {
1530 r600_decompress_color_textures(rctx, views);
1531 }
1532 }
1533
1534 {
1535 struct r600_image_state *istate;
1536 istate = &rctx->fragment_images;
1537 if (istate->compressed_depthtex_mask)
1538 r600_decompress_depth_images(rctx, istate);
1539 if (istate->compressed_colortex_mask)
1540 r600_decompress_color_images(rctx, istate);
1541 }
1542 }
1543
1544 #define SELECT_SHADER_OR_FAIL(x) do { \
1545 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1546 if (unlikely(!rctx->x##_shader->current)) \
1547 return false; \
1548 } while(0)
1549
1550 #define UPDATE_SHADER(hw, sw) do { \
1551 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1552 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1553 } while(0)
1554
1555 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1556 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1557 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1558 clip_so_current = rctx->sw##_shader->current; \
1559 } \
1560 } while(0)
1561
1562 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1563 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1564 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1565 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1566 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1567 } \
1568 } while(0)
1569
1570 #define SET_NULL_SHADER(hw) do { \
1571 if (rctx->hw_shader_stages[(hw)].shader) \
1572 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1573 } while (0)
1574
1575 static bool r600_update_derived_state(struct r600_context *rctx)
1576 {
1577 struct pipe_context * ctx = (struct pipe_context*)rctx;
1578 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1579 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1580 bool blend_disable;
1581 bool need_buf_const;
1582 struct r600_pipe_shader *clip_so_current = NULL;
1583
1584 if (!rctx->blitter->running)
1585 r600_update_compressed_resource_state(rctx);
1586
1587 SELECT_SHADER_OR_FAIL(ps);
1588
1589 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1590
1591 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1592
1593 if (rctx->gs_shader)
1594 SELECT_SHADER_OR_FAIL(gs);
1595
1596 /* Hull Shader */
1597 if (rctx->tcs_shader) {
1598 SELECT_SHADER_OR_FAIL(tcs);
1599
1600 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1601 } else if (rctx->tes_shader) {
1602 if (!rctx->fixed_func_tcs_shader) {
1603 r600_generate_fixed_func_tcs(rctx);
1604 if (!rctx->fixed_func_tcs_shader)
1605 return false;
1606
1607 }
1608 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1609
1610 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1611 } else
1612 SET_NULL_SHADER(EG_HW_STAGE_HS);
1613
1614 if (rctx->tes_shader) {
1615 SELECT_SHADER_OR_FAIL(tes);
1616 }
1617
1618 SELECT_SHADER_OR_FAIL(vs);
1619
1620 if (rctx->gs_shader) {
1621 if (!rctx->shader_stages.geom_enable) {
1622 rctx->shader_stages.geom_enable = true;
1623 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1624 }
1625
1626 /* gs_shader provides GS and VS (copy shader) */
1627 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1628
1629 /* vs_shader is used as ES */
1630
1631 if (rctx->tes_shader) {
1632 /* VS goes to LS, TES goes to ES */
1633 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1634 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1635 } else {
1636 /* vs_shader is used as ES */
1637 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1638 SET_NULL_SHADER(EG_HW_STAGE_LS);
1639 }
1640 } else {
1641 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1642 SET_NULL_SHADER(R600_HW_STAGE_GS);
1643 SET_NULL_SHADER(R600_HW_STAGE_ES);
1644 rctx->shader_stages.geom_enable = false;
1645 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1646 }
1647
1648 if (rctx->tes_shader) {
1649 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1650 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1651 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1652 } else {
1653 SET_NULL_SHADER(EG_HW_STAGE_LS);
1654 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1655 }
1656 }
1657
1658 /* Update clip misc state. */
1659 if (clip_so_current) {
1660 r600_update_clip_state(rctx, clip_so_current);
1661 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1662 }
1663
1664 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1665 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1666 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1667
1668 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1669 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1670 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1671 }
1672
1673 if (rctx->b.chip_class <= R700) {
1674 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1675
1676 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1677 rctx->cb_misc_state.multiwrite = multiwrite;
1678 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1679 }
1680 }
1681
1682 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1683 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1684 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1685
1686 if (rctx->b.chip_class >= EVERGREEN)
1687 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1688 else
1689 r600_update_ps_state(ctx, rctx->ps_shader->current);
1690 }
1691
1692 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1693 }
1694 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
1695
1696 if (rctx->b.chip_class >= EVERGREEN) {
1697 evergreen_update_db_shader_control(rctx);
1698 } else {
1699 r600_update_db_shader_control(rctx);
1700 }
1701
1702 /* on R600 we stuff masks + txq info into one constant buffer */
1703 /* on evergreen we only need a txq info one */
1704 if (rctx->ps_shader) {
1705 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1706 if (need_buf_const) {
1707 if (rctx->b.chip_class < EVERGREEN)
1708 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1709 else
1710 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1711 }
1712 }
1713
1714 if (rctx->vs_shader) {
1715 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1716 if (need_buf_const) {
1717 if (rctx->b.chip_class < EVERGREEN)
1718 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1719 else
1720 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1721 }
1722 }
1723
1724 if (rctx->gs_shader) {
1725 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1726 if (need_buf_const) {
1727 if (rctx->b.chip_class < EVERGREEN)
1728 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1729 else
1730 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1731 }
1732 }
1733
1734 r600_update_driver_const_buffers(rctx);
1735
1736 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1737 if (!r600_adjust_gprs(rctx)) {
1738 /* discard rendering */
1739 return false;
1740 }
1741 }
1742
1743 if (rctx->b.chip_class == EVERGREEN) {
1744 if (!evergreen_adjust_gprs(rctx)) {
1745 /* discard rendering */
1746 return false;
1747 }
1748 }
1749
1750 blend_disable = (rctx->dual_src_blend &&
1751 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1752
1753 if (blend_disable != rctx->force_blend_disable) {
1754 rctx->force_blend_disable = blend_disable;
1755 r600_bind_blend_state_internal(rctx,
1756 rctx->blend_state.cso,
1757 blend_disable);
1758 }
1759
1760 return true;
1761 }
1762
1763 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1764 {
1765 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1766 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1767
1768 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1769 state->pa_cl_clip_cntl |
1770 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1771 S_028810_CLIP_DISABLE(state->clip_disable));
1772 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1773 state->pa_cl_vs_out_cntl |
1774 (state->clip_plane_enable & state->clip_dist_write) |
1775 (state->cull_dist_write << 8));
1776 /* reuse needs to be set off if we write oViewport */
1777 if (rctx->b.chip_class >= EVERGREEN)
1778 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
1779 S_028AB4_REUSE_OFF(state->vs_out_viewport));
1780 }
1781
1782 /* rast_prim is the primitive type after GS. */
1783 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
1784 {
1785 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1786 enum pipe_prim_type rast_prim = rctx->current_rast_prim;
1787
1788 /* Skip this if not rendering lines. */
1789 if (rast_prim != PIPE_PRIM_LINES &&
1790 rast_prim != PIPE_PRIM_LINE_LOOP &&
1791 rast_prim != PIPE_PRIM_LINE_STRIP &&
1792 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
1793 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
1794 return;
1795
1796 if (rast_prim == rctx->last_rast_prim)
1797 return;
1798
1799 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1800 * reset the stipple pattern at each packet (line strips, line loops).
1801 */
1802 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1803 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2) |
1804 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1805 rctx->last_rast_prim = rast_prim;
1806 }
1807
1808 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1809 {
1810 struct r600_context *rctx = (struct r600_context *)ctx;
1811 struct pipe_resource *indexbuf = info->has_user_indices ? NULL : info->index.resource;
1812 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1813 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
1814 bool has_user_indices = info->has_user_indices;
1815 uint64_t mask;
1816 unsigned num_patches, dirty_tex_counter, index_offset = 0;
1817 unsigned index_size = info->index_size;
1818 int index_bias;
1819 struct r600_shader_atomic combined_atomics[8];
1820 uint8_t atomic_used_mask;
1821
1822 if (!info->indirect && !info->count && (index_size || !info->count_from_stream_output)) {
1823 return;
1824 }
1825
1826 if (unlikely(!rctx->vs_shader)) {
1827 assert(0);
1828 return;
1829 }
1830 if (unlikely(!rctx->ps_shader &&
1831 (!rctx->rasterizer || !rctx->rasterizer->rasterizer_discard))) {
1832 assert(0);
1833 return;
1834 }
1835
1836 /* make sure that the gfx ring is only one active */
1837 if (radeon_emitted(rctx->b.dma.cs, 0)) {
1838 rctx->b.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1839 }
1840
1841 /* Re-emit the framebuffer state if needed. */
1842 dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
1843 if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) {
1844 rctx->b.last_dirty_tex_counter = dirty_tex_counter;
1845 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1846 rctx->framebuffer.do_update_surf_dirtiness = true;
1847 }
1848
1849 if (rctx->gs_shader) {
1850 /* Determine whether the GS triangle strip adjacency fix should
1851 * be applied. Rotate every other triangle if
1852 * - triangle strips with adjacency are fed to the GS and
1853 * - primitive restart is disabled (the rotation doesn't help
1854 * when the restart occurs after an odd number of triangles).
1855 */
1856 bool gs_tri_strip_adj_fix =
1857 !rctx->tes_shader &&
1858 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1859 !info->primitive_restart;
1860 if (gs_tri_strip_adj_fix != rctx->gs_tri_strip_adj_fix)
1861 rctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1862 }
1863 if (!r600_update_derived_state(rctx)) {
1864 /* useless to render because current rendering command
1865 * can't be achieved
1866 */
1867 return;
1868 }
1869
1870 rctx->current_rast_prim = (rctx->gs_shader)? rctx->gs_shader->gs_output_prim
1871 : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
1872 : info->mode;
1873
1874 if (rctx->b.chip_class >= EVERGREEN)
1875 evergreen_emit_atomic_buffer_setup(rctx, combined_atomics, &atomic_used_mask);
1876
1877 if (index_size) {
1878 index_offset += info->start * index_size;
1879
1880 /* Translate 8-bit indices to 16-bit. */
1881 if (unlikely(index_size == 1)) {
1882 struct pipe_resource *out_buffer = NULL;
1883 unsigned out_offset;
1884 void *ptr;
1885 unsigned start, count;
1886
1887 if (likely(!info->indirect)) {
1888 start = 0;
1889 count = info->count;
1890 }
1891 else {
1892 /* Have to get start/count from indirect buffer, slow path ahead... */
1893 struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect->buffer;
1894 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
1895 PIPE_TRANSFER_READ);
1896 if (data) {
1897 data += info->indirect->offset / sizeof(unsigned);
1898 start = data[2] * index_size;
1899 count = data[0];
1900 }
1901 else {
1902 start = 0;
1903 count = 0;
1904 }
1905 }
1906
1907 u_upload_alloc(ctx->stream_uploader, start, count * 2,
1908 256, &out_offset, &out_buffer, &ptr);
1909 if (unlikely(!ptr))
1910 return;
1911
1912 util_shorten_ubyte_elts_to_userptr(
1913 &rctx->b.b, info, 0, 0, index_offset, count, ptr);
1914
1915 indexbuf = out_buffer;
1916 index_offset = out_offset;
1917 index_size = 2;
1918 has_user_indices = false;
1919 }
1920
1921 /* Upload the index buffer.
1922 * The upload is skipped for small index counts on little-endian machines
1923 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1924 * Indirect draws never use immediate indices.
1925 * Note: Instanced rendering in combination with immediate indices hangs. */
1926 if (has_user_indices && (R600_BIG_ENDIAN || info->indirect ||
1927 info->instance_count > 1 ||
1928 info->count*index_size > 20)) {
1929 indexbuf = NULL;
1930 u_upload_data(ctx->stream_uploader, 0,
1931 info->count * index_size, 256,
1932 info->index.user, &index_offset, &indexbuf);
1933 has_user_indices = false;
1934 }
1935 index_bias = info->index_bias;
1936 } else {
1937 index_bias = info->start;
1938 }
1939
1940 /* Set the index offset and primitive restart. */
1941 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info->primitive_restart ||
1942 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info->restart_index ||
1943 rctx->vgt_state.vgt_indx_offset != index_bias ||
1944 (rctx->vgt_state.last_draw_was_indirect && !info->indirect)) {
1945 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info->primitive_restart;
1946 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info->restart_index;
1947 rctx->vgt_state.vgt_indx_offset = index_bias;
1948 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
1949 }
1950
1951 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1952 if (rctx->b.chip_class == R600) {
1953 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1954 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1955 }
1956
1957 if (rctx->b.chip_class >= EVERGREEN)
1958 evergreen_setup_tess_constants(rctx, info, &num_patches);
1959
1960 /* Emit states. */
1961 r600_need_cs_space(rctx, has_user_indices ? 5 : 0, TRUE);
1962 r600_flush_emit(rctx);
1963
1964 mask = rctx->dirty_atoms;
1965 while (mask != 0) {
1966 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
1967 }
1968
1969 if (rctx->b.chip_class == CAYMAN) {
1970 /* Copied from radeonsi. */
1971 unsigned primgroup_size = 128; /* recommended without a GS */
1972 bool ia_switch_on_eop = false;
1973 bool partial_vs_wave = false;
1974
1975 if (rctx->gs_shader)
1976 primgroup_size = 64; /* recommended with a GS */
1977
1978 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
1979 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
1980 ia_switch_on_eop = true;
1981 }
1982
1983 if (r600_get_strmout_en(&rctx->b))
1984 partial_vs_wave = true;
1985
1986 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
1987 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
1988 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
1989 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
1990 }
1991
1992 if (rctx->b.chip_class >= EVERGREEN) {
1993 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info,
1994 num_patches);
1995
1996 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
1997 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
1998 }
1999
2000 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2001 * even though it should have no effect on those. */
2002 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
2003 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
2004 unsigned prim = info->mode;
2005
2006 if (rctx->gs_shader) {
2007 prim = rctx->gs_shader->gs_output_prim;
2008 }
2009 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
2010
2011 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
2012 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
2013 info->mode == R600_PRIM_RECTANGLE_LIST) {
2014 su_sc_mode_cntl &= C_028814_CULL_FRONT;
2015 }
2016 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
2017 }
2018
2019 /* Update start instance. */
2020 if (!info->indirect && rctx->last_start_instance != info->start_instance) {
2021 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
2022 rctx->last_start_instance = info->start_instance;
2023 }
2024
2025 /* Update the primitive type. */
2026 if (rctx->last_primitive_type != info->mode) {
2027 r600_emit_rasterizer_prim_state(rctx);
2028 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2029 r600_conv_pipe_prim(info->mode));
2030
2031 rctx->last_primitive_type = info->mode;
2032 }
2033
2034 /* Draw packets. */
2035 if (likely(!info->indirect)) {
2036 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2037 radeon_emit(cs, info->instance_count);
2038 } else {
2039 uint64_t va = r600_resource(info->indirect->buffer)->gpu_address;
2040 assert(rctx->b.chip_class >= EVERGREEN);
2041
2042 // Invalidate so non-indirect draw calls reset this state
2043 rctx->vgt_state.last_draw_was_indirect = true;
2044 rctx->last_start_instance = -1;
2045
2046 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0));
2047 radeon_emit(cs, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE);
2048 radeon_emit(cs, va);
2049 radeon_emit(cs, (va >> 32UL) & 0xFF);
2050
2051 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2052 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2053 (struct r600_resource*)info->indirect->buffer,
2054 RADEON_USAGE_READ,
2055 RADEON_PRIO_DRAW_INDIRECT));
2056 }
2057
2058 if (index_size) {
2059 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2060 radeon_emit(cs, index_size == 4 ?
2061 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
2062 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)));
2063
2064 if (has_user_indices) {
2065 unsigned size_bytes = info->count*index_size;
2066 unsigned size_dw = align(size_bytes, 4) / 4;
2067 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
2068 radeon_emit(cs, info->count);
2069 radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
2070 radeon_emit_array(cs, info->index.user, size_dw);
2071 } else {
2072 uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
2073
2074 if (likely(!info->indirect)) {
2075 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit));
2076 radeon_emit(cs, va);
2077 radeon_emit(cs, (va >> 32UL) & 0xFF);
2078 radeon_emit(cs, info->count);
2079 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2080 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2081 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2082 (struct r600_resource*)indexbuf,
2083 RADEON_USAGE_READ,
2084 RADEON_PRIO_INDEX_BUFFER));
2085 }
2086 else {
2087 uint32_t max_size = (indexbuf->width0 - index_offset) / index_size;
2088
2089 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0));
2090 radeon_emit(cs, va);
2091 radeon_emit(cs, (va >> 32UL) & 0xFF);
2092
2093 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2094 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2095 (struct r600_resource*)indexbuf,
2096 RADEON_USAGE_READ,
2097 RADEON_PRIO_INDEX_BUFFER));
2098
2099 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
2100 radeon_emit(cs, max_size);
2101
2102 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
2103 radeon_emit(cs, info->indirect->offset);
2104 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2105 }
2106 }
2107 } else {
2108 if (unlikely(info->count_from_stream_output)) {
2109 struct r600_so_target *t = (struct r600_so_target*)info->count_from_stream_output;
2110 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
2111
2112 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
2113
2114 radeon_emit(cs, PKT3(PKT3_COPY_DW, 4, 0));
2115 radeon_emit(cs, COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG);
2116 radeon_emit(cs, va & 0xFFFFFFFFUL); /* src address lo */
2117 radeon_emit(cs, (va >> 32UL) & 0xFFUL); /* src address hi */
2118 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); /* dst register */
2119 radeon_emit(cs, 0); /* unused */
2120
2121 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2122 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2123 t->buf_filled_size, RADEON_USAGE_READ,
2124 RADEON_PRIO_SO_FILLED_SIZE));
2125 }
2126
2127 if (likely(!info->indirect)) {
2128 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
2129 radeon_emit(cs, info->count);
2130 }
2131 else {
2132 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
2133 radeon_emit(cs, info->indirect->offset);
2134 }
2135 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2136 (info->count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0));
2137 }
2138
2139 /* SMX returns CONTEXT_DONE too early workaround */
2140 if (rctx->b.family == CHIP_R600 ||
2141 rctx->b.family == CHIP_RV610 ||
2142 rctx->b.family == CHIP_RV630 ||
2143 rctx->b.family == CHIP_RV635) {
2144 /* if we have gs shader or streamout
2145 we need to do a wait idle after every draw */
2146 if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
2147 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2148 }
2149 }
2150
2151 /* ES ring rolling over at EOP - workaround */
2152 if (rctx->b.chip_class == R600) {
2153 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2154 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT));
2155 }
2156
2157
2158 if (rctx->b.chip_class >= EVERGREEN)
2159 evergreen_emit_atomic_buffer_save(rctx, combined_atomics, &atomic_used_mask);
2160
2161 if (rctx->trace_buf)
2162 eg_trace_emit(rctx);
2163
2164 if (rctx->framebuffer.do_update_surf_dirtiness) {
2165 /* Set the depth buffer as dirty. */
2166 if (rctx->framebuffer.state.zsbuf) {
2167 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2168 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2169
2170 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2171
2172 if (rtex->surface.has_stencil)
2173 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2174 }
2175 if (rctx->framebuffer.compressed_cb_mask) {
2176 struct pipe_surface *surf;
2177 struct r600_texture *rtex;
2178 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2179
2180 do {
2181 unsigned i = u_bit_scan(&mask);
2182 surf = rctx->framebuffer.state.cbufs[i];
2183 rtex = (struct r600_texture*)surf->texture;
2184
2185 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2186
2187 } while (mask);
2188 }
2189 rctx->framebuffer.do_update_surf_dirtiness = false;
2190 }
2191
2192 if (index_size && indexbuf != info->index.resource)
2193 pipe_resource_reference(&indexbuf, NULL);
2194 rctx->b.num_draw_calls++;
2195 }
2196
2197 uint32_t r600_translate_stencil_op(int s_op)
2198 {
2199 switch (s_op) {
2200 case PIPE_STENCIL_OP_KEEP:
2201 return V_028800_STENCIL_KEEP;
2202 case PIPE_STENCIL_OP_ZERO:
2203 return V_028800_STENCIL_ZERO;
2204 case PIPE_STENCIL_OP_REPLACE:
2205 return V_028800_STENCIL_REPLACE;
2206 case PIPE_STENCIL_OP_INCR:
2207 return V_028800_STENCIL_INCR;
2208 case PIPE_STENCIL_OP_DECR:
2209 return V_028800_STENCIL_DECR;
2210 case PIPE_STENCIL_OP_INCR_WRAP:
2211 return V_028800_STENCIL_INCR_WRAP;
2212 case PIPE_STENCIL_OP_DECR_WRAP:
2213 return V_028800_STENCIL_DECR_WRAP;
2214 case PIPE_STENCIL_OP_INVERT:
2215 return V_028800_STENCIL_INVERT;
2216 default:
2217 R600_ERR("Unknown stencil op %d", s_op);
2218 assert(0);
2219 break;
2220 }
2221 return 0;
2222 }
2223
2224 uint32_t r600_translate_fill(uint32_t func)
2225 {
2226 switch(func) {
2227 case PIPE_POLYGON_MODE_FILL:
2228 return 2;
2229 case PIPE_POLYGON_MODE_LINE:
2230 return 1;
2231 case PIPE_POLYGON_MODE_POINT:
2232 return 0;
2233 default:
2234 assert(0);
2235 return 0;
2236 }
2237 }
2238
2239 unsigned r600_tex_wrap(unsigned wrap)
2240 {
2241 switch (wrap) {
2242 default:
2243 case PIPE_TEX_WRAP_REPEAT:
2244 return V_03C000_SQ_TEX_WRAP;
2245 case PIPE_TEX_WRAP_CLAMP:
2246 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2247 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2248 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2249 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2250 return V_03C000_SQ_TEX_CLAMP_BORDER;
2251 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2252 return V_03C000_SQ_TEX_MIRROR;
2253 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2254 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2255 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2256 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2257 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2258 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2259 }
2260 }
2261
2262 unsigned r600_tex_mipfilter(unsigned filter)
2263 {
2264 switch (filter) {
2265 case PIPE_TEX_MIPFILTER_NEAREST:
2266 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2267 case PIPE_TEX_MIPFILTER_LINEAR:
2268 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2269 default:
2270 case PIPE_TEX_MIPFILTER_NONE:
2271 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2272 }
2273 }
2274
2275 unsigned r600_tex_compare(unsigned compare)
2276 {
2277 switch (compare) {
2278 default:
2279 case PIPE_FUNC_NEVER:
2280 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2281 case PIPE_FUNC_LESS:
2282 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2283 case PIPE_FUNC_EQUAL:
2284 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2285 case PIPE_FUNC_LEQUAL:
2286 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2287 case PIPE_FUNC_GREATER:
2288 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2289 case PIPE_FUNC_NOTEQUAL:
2290 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2291 case PIPE_FUNC_GEQUAL:
2292 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2293 case PIPE_FUNC_ALWAYS:
2294 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2295 }
2296 }
2297
2298 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2299 {
2300 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2301 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2302 (linear_filter &&
2303 (wrap == PIPE_TEX_WRAP_CLAMP ||
2304 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2305 }
2306
2307 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2308 {
2309 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2310 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2311
2312 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2313 state->border_color.ui[2] || state->border_color.ui[3]) &&
2314 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2315 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2316 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2317 }
2318
2319 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2320 {
2321
2322 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2323 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2324
2325 if (!shader)
2326 return;
2327
2328 r600_emit_command_buffer(cs, &shader->command_buffer);
2329 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2330 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2331 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY));
2332 }
2333
2334 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2335 const unsigned char *swizzle_view,
2336 boolean vtx)
2337 {
2338 unsigned i;
2339 unsigned char swizzle[4];
2340 unsigned result = 0;
2341 const uint32_t tex_swizzle_shift[4] = {
2342 16, 19, 22, 25,
2343 };
2344 const uint32_t vtx_swizzle_shift[4] = {
2345 3, 6, 9, 12,
2346 };
2347 const uint32_t swizzle_bit[4] = {
2348 0, 1, 2, 3,
2349 };
2350 const uint32_t *swizzle_shift = tex_swizzle_shift;
2351
2352 if (vtx)
2353 swizzle_shift = vtx_swizzle_shift;
2354
2355 if (swizzle_view) {
2356 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2357 } else {
2358 memcpy(swizzle, swizzle_format, 4);
2359 }
2360
2361 /* Get swizzle. */
2362 for (i = 0; i < 4; i++) {
2363 switch (swizzle[i]) {
2364 case PIPE_SWIZZLE_Y:
2365 result |= swizzle_bit[1] << swizzle_shift[i];
2366 break;
2367 case PIPE_SWIZZLE_Z:
2368 result |= swizzle_bit[2] << swizzle_shift[i];
2369 break;
2370 case PIPE_SWIZZLE_W:
2371 result |= swizzle_bit[3] << swizzle_shift[i];
2372 break;
2373 case PIPE_SWIZZLE_0:
2374 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2375 break;
2376 case PIPE_SWIZZLE_1:
2377 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2378 break;
2379 default: /* PIPE_SWIZZLE_X */
2380 result |= swizzle_bit[0] << swizzle_shift[i];
2381 }
2382 }
2383 return result;
2384 }
2385
2386 /* texture format translate */
2387 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2388 enum pipe_format format,
2389 const unsigned char *swizzle_view,
2390 uint32_t *word4_p, uint32_t *yuv_format_p,
2391 bool do_endian_swap)
2392 {
2393 struct r600_screen *rscreen = (struct r600_screen *)screen;
2394 uint32_t result = 0, word4 = 0, yuv_format = 0;
2395 const struct util_format_description *desc;
2396 boolean uniform = TRUE;
2397 bool is_srgb_valid = FALSE;
2398 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2399 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2400 const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
2401 const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
2402 const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
2403
2404 int i;
2405 const uint32_t sign_bit[4] = {
2406 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2407 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2408 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2409 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2410 };
2411
2412 /* Need to replace the specified texture formats in case of big-endian.
2413 * These formats are formats that have channels with number of bits
2414 * not divisible by 8.
2415 * Mesa conversion functions don't swap bits for those formats, and because
2416 * we transmit this over a serial bus to the GPU (PCIe), the
2417 * bit-endianess is important!!!
2418 * In case we have an "opposite" format, just use that for the swizzling
2419 * information. If we don't have such an "opposite" format, we need
2420 * to use a fixed swizzle info instead (see below)
2421 */
2422 if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
2423 format = PIPE_FORMAT_A4R4_UNORM;
2424
2425 desc = util_format_description(format);
2426 if (!desc)
2427 goto out_unknown;
2428
2429 /* Depth and stencil swizzling is handled separately. */
2430 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2431 /* Need to check for specific texture formats that don't have
2432 * an "opposite" format we can use. For those formats, we directly
2433 * specify the swizzling, which is the LE swizzling as defined in
2434 * u_format.csv
2435 */
2436 if (do_endian_swap) {
2437 if (format == PIPE_FORMAT_L4A4_UNORM)
2438 word4 |= r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, FALSE);
2439 else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
2440 word4 |= r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, FALSE);
2441 else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || format == PIPE_FORMAT_B5G6R5_UNORM)
2442 word4 |= r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, FALSE);
2443 else
2444 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2445 } else {
2446 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
2447 }
2448 }
2449
2450 /* Colorspace (return non-RGB formats directly). */
2451 switch (desc->colorspace) {
2452 /* Depth stencil formats */
2453 case UTIL_FORMAT_COLORSPACE_ZS:
2454 switch (format) {
2455 /* Depth sampler formats. */
2456 case PIPE_FORMAT_Z16_UNORM:
2457 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2458 result = FMT_16;
2459 goto out_word4;
2460 case PIPE_FORMAT_Z24X8_UNORM:
2461 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2462 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2463 result = FMT_8_24;
2464 goto out_word4;
2465 case PIPE_FORMAT_X8Z24_UNORM:
2466 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2467 if (rscreen->b.chip_class < EVERGREEN)
2468 goto out_unknown;
2469 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2470 result = FMT_24_8;
2471 goto out_word4;
2472 case PIPE_FORMAT_Z32_FLOAT:
2473 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2474 result = FMT_32_FLOAT;
2475 goto out_word4;
2476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2477 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2478 result = FMT_X24_8_32_FLOAT;
2479 goto out_word4;
2480 /* Stencil sampler formats. */
2481 case PIPE_FORMAT_S8_UINT:
2482 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2483 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2484 result = FMT_8;
2485 goto out_word4;
2486 case PIPE_FORMAT_X24S8_UINT:
2487 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2488 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2489 result = FMT_8_24;
2490 goto out_word4;
2491 case PIPE_FORMAT_S8X24_UINT:
2492 if (rscreen->b.chip_class < EVERGREEN)
2493 goto out_unknown;
2494 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2495 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
2496 result = FMT_24_8;
2497 goto out_word4;
2498 case PIPE_FORMAT_X32_S8X24_UINT:
2499 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2500 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
2501 result = FMT_X24_8_32_FLOAT;
2502 goto out_word4;
2503 default:
2504 goto out_unknown;
2505 }
2506
2507 case UTIL_FORMAT_COLORSPACE_YUV:
2508 yuv_format |= (1 << 30);
2509 switch (format) {
2510 case PIPE_FORMAT_UYVY:
2511 case PIPE_FORMAT_YUYV:
2512 default:
2513 break;
2514 }
2515 goto out_unknown; /* XXX */
2516
2517 case UTIL_FORMAT_COLORSPACE_SRGB:
2518 word4 |= S_038010_FORCE_DEGAMMA(1);
2519 break;
2520
2521 default:
2522 break;
2523 }
2524
2525 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2526 switch (format) {
2527 case PIPE_FORMAT_RGTC1_SNORM:
2528 case PIPE_FORMAT_LATC1_SNORM:
2529 word4 |= sign_bit[0];
2530 case PIPE_FORMAT_RGTC1_UNORM:
2531 case PIPE_FORMAT_LATC1_UNORM:
2532 result = FMT_BC4;
2533 goto out_word4;
2534 case PIPE_FORMAT_RGTC2_SNORM:
2535 case PIPE_FORMAT_LATC2_SNORM:
2536 word4 |= sign_bit[0] | sign_bit[1];
2537 case PIPE_FORMAT_RGTC2_UNORM:
2538 case PIPE_FORMAT_LATC2_UNORM:
2539 result = FMT_BC5;
2540 goto out_word4;
2541 default:
2542 goto out_unknown;
2543 }
2544 }
2545
2546 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2547 switch (format) {
2548 case PIPE_FORMAT_DXT1_RGB:
2549 case PIPE_FORMAT_DXT1_RGBA:
2550 case PIPE_FORMAT_DXT1_SRGB:
2551 case PIPE_FORMAT_DXT1_SRGBA:
2552 result = FMT_BC1;
2553 is_srgb_valid = TRUE;
2554 goto out_word4;
2555 case PIPE_FORMAT_DXT3_RGBA:
2556 case PIPE_FORMAT_DXT3_SRGBA:
2557 result = FMT_BC2;
2558 is_srgb_valid = TRUE;
2559 goto out_word4;
2560 case PIPE_FORMAT_DXT5_RGBA:
2561 case PIPE_FORMAT_DXT5_SRGBA:
2562 result = FMT_BC3;
2563 is_srgb_valid = TRUE;
2564 goto out_word4;
2565 default:
2566 goto out_unknown;
2567 }
2568 }
2569
2570 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2571 if (rscreen->b.chip_class < EVERGREEN)
2572 goto out_unknown;
2573
2574 switch (format) {
2575 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2576 case PIPE_FORMAT_BPTC_SRGBA:
2577 result = FMT_BC7;
2578 is_srgb_valid = TRUE;
2579 goto out_word4;
2580 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2581 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2582 /* fall through */
2583 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2584 result = FMT_BC6;
2585 goto out_word4;
2586 default:
2587 goto out_unknown;
2588 }
2589 }
2590
2591 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2592 switch (format) {
2593 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2594 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2595 result = FMT_GB_GR;
2596 goto out_word4;
2597 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2598 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2599 result = FMT_BG_RG;
2600 goto out_word4;
2601 default:
2602 goto out_unknown;
2603 }
2604 }
2605
2606 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2607 result = FMT_5_9_9_9_SHAREDEXP;
2608 goto out_word4;
2609 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2610 result = FMT_10_11_11_FLOAT;
2611 goto out_word4;
2612 }
2613
2614
2615 for (i = 0; i < desc->nr_channels; i++) {
2616 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2617 word4 |= sign_bit[i];
2618 }
2619 }
2620
2621 /* R8G8Bx_SNORM - XXX CxV8U8 */
2622
2623 /* See whether the components are of the same size. */
2624 for (i = 1; i < desc->nr_channels; i++) {
2625 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2626 }
2627
2628 /* Non-uniform formats. */
2629 if (!uniform) {
2630 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2631 desc->channel[0].pure_integer)
2632 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2633 switch(desc->nr_channels) {
2634 case 3:
2635 if (desc->channel[0].size == 5 &&
2636 desc->channel[1].size == 6 &&
2637 desc->channel[2].size == 5) {
2638 result = FMT_5_6_5;
2639 goto out_word4;
2640 }
2641 goto out_unknown;
2642 case 4:
2643 if (desc->channel[0].size == 5 &&
2644 desc->channel[1].size == 5 &&
2645 desc->channel[2].size == 5 &&
2646 desc->channel[3].size == 1) {
2647 result = FMT_1_5_5_5;
2648 goto out_word4;
2649 }
2650 if (desc->channel[0].size == 10 &&
2651 desc->channel[1].size == 10 &&
2652 desc->channel[2].size == 10 &&
2653 desc->channel[3].size == 2) {
2654 result = FMT_2_10_10_10;
2655 goto out_word4;
2656 }
2657 goto out_unknown;
2658 }
2659 goto out_unknown;
2660 }
2661
2662 /* Find the first non-VOID channel. */
2663 for (i = 0; i < 4; i++) {
2664 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2665 break;
2666 }
2667 }
2668
2669 if (i == 4)
2670 goto out_unknown;
2671
2672 /* uniform formats */
2673 switch (desc->channel[i].type) {
2674 case UTIL_FORMAT_TYPE_UNSIGNED:
2675 case UTIL_FORMAT_TYPE_SIGNED:
2676 #if 0
2677 if (!desc->channel[i].normalized &&
2678 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2679 goto out_unknown;
2680 }
2681 #endif
2682 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2683 desc->channel[i].pure_integer)
2684 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2685
2686 switch (desc->channel[i].size) {
2687 case 4:
2688 switch (desc->nr_channels) {
2689 case 2:
2690 result = FMT_4_4;
2691 goto out_word4;
2692 case 4:
2693 result = FMT_4_4_4_4;
2694 goto out_word4;
2695 }
2696 goto out_unknown;
2697 case 8:
2698 switch (desc->nr_channels) {
2699 case 1:
2700 result = FMT_8;
2701 goto out_word4;
2702 case 2:
2703 result = FMT_8_8;
2704 goto out_word4;
2705 case 4:
2706 result = FMT_8_8_8_8;
2707 is_srgb_valid = TRUE;
2708 goto out_word4;
2709 }
2710 goto out_unknown;
2711 case 16:
2712 switch (desc->nr_channels) {
2713 case 1:
2714 result = FMT_16;
2715 goto out_word4;
2716 case 2:
2717 result = FMT_16_16;
2718 goto out_word4;
2719 case 4:
2720 result = FMT_16_16_16_16;
2721 goto out_word4;
2722 }
2723 goto out_unknown;
2724 case 32:
2725 switch (desc->nr_channels) {
2726 case 1:
2727 result = FMT_32;
2728 goto out_word4;
2729 case 2:
2730 result = FMT_32_32;
2731 goto out_word4;
2732 case 4:
2733 result = FMT_32_32_32_32;
2734 goto out_word4;
2735 }
2736 }
2737 goto out_unknown;
2738
2739 case UTIL_FORMAT_TYPE_FLOAT:
2740 switch (desc->channel[i].size) {
2741 case 16:
2742 switch (desc->nr_channels) {
2743 case 1:
2744 result = FMT_16_FLOAT;
2745 goto out_word4;
2746 case 2:
2747 result = FMT_16_16_FLOAT;
2748 goto out_word4;
2749 case 4:
2750 result = FMT_16_16_16_16_FLOAT;
2751 goto out_word4;
2752 }
2753 goto out_unknown;
2754 case 32:
2755 switch (desc->nr_channels) {
2756 case 1:
2757 result = FMT_32_FLOAT;
2758 goto out_word4;
2759 case 2:
2760 result = FMT_32_32_FLOAT;
2761 goto out_word4;
2762 case 4:
2763 result = FMT_32_32_32_32_FLOAT;
2764 goto out_word4;
2765 }
2766 }
2767 goto out_unknown;
2768 }
2769
2770 out_word4:
2771
2772 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2773 return ~0;
2774 if (word4_p)
2775 *word4_p = word4;
2776 if (yuv_format_p)
2777 *yuv_format_p = yuv_format;
2778 return result;
2779 out_unknown:
2780 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2781 return ~0;
2782 }
2783
2784 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
2785 bool do_endian_swap)
2786 {
2787 const struct util_format_description *desc = util_format_description(format);
2788 int channel = util_format_get_first_non_void_channel(format);
2789 bool is_float;
2790 if (!desc)
2791 return ~0U;
2792
2793 #define HAS_SIZE(x,y,z,w) \
2794 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2795 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2796
2797 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2798 return V_0280A0_COLOR_10_11_11_FLOAT;
2799
2800 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2801 channel == -1)
2802 return ~0U;
2803
2804 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2805
2806 switch (desc->nr_channels) {
2807 case 1:
2808 switch (desc->channel[0].size) {
2809 case 8:
2810 return V_0280A0_COLOR_8;
2811 case 16:
2812 if (is_float)
2813 return V_0280A0_COLOR_16_FLOAT;
2814 else
2815 return V_0280A0_COLOR_16;
2816 case 32:
2817 if (is_float)
2818 return V_0280A0_COLOR_32_FLOAT;
2819 else
2820 return V_0280A0_COLOR_32;
2821 }
2822 break;
2823 case 2:
2824 if (desc->channel[0].size == desc->channel[1].size) {
2825 switch (desc->channel[0].size) {
2826 case 4:
2827 if (chip <= R700)
2828 return V_0280A0_COLOR_4_4;
2829 else
2830 return ~0U; /* removed on Evergreen */
2831 case 8:
2832 return V_0280A0_COLOR_8_8;
2833 case 16:
2834 if (is_float)
2835 return V_0280A0_COLOR_16_16_FLOAT;
2836 else
2837 return V_0280A0_COLOR_16_16;
2838 case 32:
2839 if (is_float)
2840 return V_0280A0_COLOR_32_32_FLOAT;
2841 else
2842 return V_0280A0_COLOR_32_32;
2843 }
2844 } else if (HAS_SIZE(8,24,0,0)) {
2845 return (do_endian_swap ? V_0280A0_COLOR_8_24 : V_0280A0_COLOR_24_8);
2846 } else if (HAS_SIZE(24,8,0,0)) {
2847 return V_0280A0_COLOR_8_24;
2848 }
2849 break;
2850 case 3:
2851 if (HAS_SIZE(5,6,5,0)) {
2852 return V_0280A0_COLOR_5_6_5;
2853 } else if (HAS_SIZE(32,8,24,0)) {
2854 return V_0280A0_COLOR_X24_8_32_FLOAT;
2855 }
2856 break;
2857 case 4:
2858 if (desc->channel[0].size == desc->channel[1].size &&
2859 desc->channel[0].size == desc->channel[2].size &&
2860 desc->channel[0].size == desc->channel[3].size) {
2861 switch (desc->channel[0].size) {
2862 case 4:
2863 return V_0280A0_COLOR_4_4_4_4;
2864 case 8:
2865 return V_0280A0_COLOR_8_8_8_8;
2866 case 16:
2867 if (is_float)
2868 return V_0280A0_COLOR_16_16_16_16_FLOAT;
2869 else
2870 return V_0280A0_COLOR_16_16_16_16;
2871 case 32:
2872 if (is_float)
2873 return V_0280A0_COLOR_32_32_32_32_FLOAT;
2874 else
2875 return V_0280A0_COLOR_32_32_32_32;
2876 }
2877 } else if (HAS_SIZE(5,5,5,1)) {
2878 return V_0280A0_COLOR_1_5_5_5;
2879 } else if (HAS_SIZE(10,10,10,2)) {
2880 return V_0280A0_COLOR_2_10_10_10;
2881 }
2882 break;
2883 }
2884 return ~0U;
2885 }
2886
2887 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
2888 {
2889 if (R600_BIG_ENDIAN) {
2890 switch(colorformat) {
2891 /* 8-bit buffers. */
2892 case V_0280A0_COLOR_4_4:
2893 case V_0280A0_COLOR_8:
2894 return ENDIAN_NONE;
2895
2896 /* 16-bit buffers. */
2897 case V_0280A0_COLOR_8_8:
2898 /*
2899 * No need to do endian swaps on array formats,
2900 * as mesa<-->pipe formats conversion take into account
2901 * the endianess
2902 */
2903 return ENDIAN_NONE;
2904
2905 case V_0280A0_COLOR_5_6_5:
2906 case V_0280A0_COLOR_1_5_5_5:
2907 case V_0280A0_COLOR_4_4_4_4:
2908 case V_0280A0_COLOR_16:
2909 return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
2910
2911 /* 32-bit buffers. */
2912 case V_0280A0_COLOR_8_8_8_8:
2913 /*
2914 * No need to do endian swaps on array formats,
2915 * as mesa<-->pipe formats conversion take into account
2916 * the endianess
2917 */
2918 return ENDIAN_NONE;
2919
2920 case V_0280A0_COLOR_2_10_10_10:
2921 case V_0280A0_COLOR_8_24:
2922 case V_0280A0_COLOR_24_8:
2923 case V_0280A0_COLOR_32_FLOAT:
2924 return (do_endian_swap ? ENDIAN_8IN32 : ENDIAN_NONE);
2925
2926 case V_0280A0_COLOR_16_16_FLOAT:
2927 case V_0280A0_COLOR_16_16:
2928 return ENDIAN_8IN16;
2929
2930 /* 64-bit buffers. */
2931 case V_0280A0_COLOR_16_16_16_16:
2932 case V_0280A0_COLOR_16_16_16_16_FLOAT:
2933 return ENDIAN_8IN16;
2934
2935 case V_0280A0_COLOR_32_32_FLOAT:
2936 case V_0280A0_COLOR_32_32:
2937 case V_0280A0_COLOR_X24_8_32_FLOAT:
2938 return ENDIAN_8IN32;
2939
2940 /* 128-bit buffers. */
2941 case V_0280A0_COLOR_32_32_32_32_FLOAT:
2942 case V_0280A0_COLOR_32_32_32_32:
2943 return ENDIAN_8IN32;
2944 default:
2945 return ENDIAN_NONE; /* Unsupported. */
2946 }
2947 } else {
2948 return ENDIAN_NONE;
2949 }
2950 }
2951
2952 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2953 {
2954 struct r600_context *rctx = (struct r600_context*)ctx;
2955 struct r600_resource *rbuffer = r600_resource(buf);
2956 unsigned i, shader, mask;
2957 struct r600_pipe_sampler_view *view;
2958
2959 /* Reallocate the buffer in the same pipe_resource. */
2960 r600_alloc_resource(&rctx->screen->b, rbuffer);
2961
2962 /* We changed the buffer, now we need to bind it where the old one was bound. */
2963 /* Vertex buffers. */
2964 mask = rctx->vertex_buffer_state.enabled_mask;
2965 while (mask) {
2966 i = u_bit_scan(&mask);
2967 if (rctx->vertex_buffer_state.vb[i].buffer.resource == &rbuffer->b.b) {
2968 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2969 r600_vertex_buffers_dirty(rctx);
2970 }
2971 }
2972 /* Streamout buffers. */
2973 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2974 if (rctx->b.streamout.targets[i] &&
2975 rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2976 if (rctx->b.streamout.begin_emitted) {
2977 r600_emit_streamout_end(&rctx->b);
2978 }
2979 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2980 r600_streamout_buffers_dirty(&rctx->b);
2981 }
2982 }
2983
2984 /* Constant buffers. */
2985 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2986 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2987 bool found = false;
2988 uint32_t mask = state->enabled_mask;
2989
2990 while (mask) {
2991 unsigned i = u_bit_scan(&mask);
2992 if (state->cb[i].buffer == &rbuffer->b.b) {
2993 found = true;
2994 state->dirty_mask |= 1 << i;
2995 }
2996 }
2997 if (found) {
2998 r600_constant_buffers_dirty(rctx, state);
2999 }
3000 }
3001
3002 /* Texture buffer objects - update the virtual addresses in descriptors. */
3003 LIST_FOR_EACH_ENTRY(view, &rctx->texture_buffers, list) {
3004 if (view->base.texture == &rbuffer->b.b) {
3005 uint64_t offset = view->base.u.buf.offset;
3006 uint64_t va = rbuffer->gpu_address + offset;
3007
3008 view->tex_resource_words[0] = va;
3009 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
3010 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
3011 }
3012 }
3013 /* Texture buffer objects - make bindings dirty if needed. */
3014 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3015 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
3016 bool found = false;
3017 uint32_t mask = state->enabled_mask;
3018
3019 while (mask) {
3020 unsigned i = u_bit_scan(&mask);
3021 if (state->views[i]->base.texture == &rbuffer->b.b) {
3022 found = true;
3023 state->dirty_mask |= 1 << i;
3024 }
3025 }
3026 if (found) {
3027 r600_sampler_views_dirty(rctx, state);
3028 }
3029 }
3030 }
3031
3032 static void r600_set_active_query_state(struct pipe_context *ctx, boolean enable)
3033 {
3034 struct r600_context *rctx = (struct r600_context*)ctx;
3035
3036 /* Pipeline stat & streamout queries. */
3037 if (enable) {
3038 rctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
3039 rctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
3040 } else {
3041 rctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
3042 rctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
3043 }
3044
3045 /* Occlusion queries. */
3046 if (rctx->db_misc_state.occlusion_queries_disabled != !enable) {
3047 rctx->db_misc_state.occlusion_queries_disabled = !enable;
3048 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3049 }
3050 }
3051
3052 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3053 bool include_draw_vbo)
3054 {
3055 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
3056 }
3057
3058 /* keep this at the end of this file, please */
3059 void r600_init_common_state_functions(struct r600_context *rctx)
3060 {
3061 rctx->b.b.create_fs_state = r600_create_ps_state;
3062 rctx->b.b.create_vs_state = r600_create_vs_state;
3063 rctx->b.b.create_gs_state = r600_create_gs_state;
3064 rctx->b.b.create_tcs_state = r600_create_tcs_state;
3065 rctx->b.b.create_tes_state = r600_create_tes_state;
3066 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
3067 rctx->b.b.bind_blend_state = r600_bind_blend_state;
3068 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
3069 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
3070 rctx->b.b.bind_fs_state = r600_bind_ps_state;
3071 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
3072 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
3073 rctx->b.b.bind_vs_state = r600_bind_vs_state;
3074 rctx->b.b.bind_gs_state = r600_bind_gs_state;
3075 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
3076 rctx->b.b.bind_tes_state = r600_bind_tes_state;
3077 rctx->b.b.delete_blend_state = r600_delete_blend_state;
3078 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
3079 rctx->b.b.delete_fs_state = r600_delete_ps_state;
3080 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
3081 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
3082 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
3083 rctx->b.b.delete_vs_state = r600_delete_vs_state;
3084 rctx->b.b.delete_gs_state = r600_delete_gs_state;
3085 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
3086 rctx->b.b.delete_tes_state = r600_delete_tes_state;
3087 rctx->b.b.set_blend_color = r600_set_blend_color;
3088 rctx->b.b.set_clip_state = r600_set_clip_state;
3089 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
3090 rctx->b.b.set_sample_mask = r600_set_sample_mask;
3091 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
3092 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
3093 rctx->b.b.set_sampler_views = r600_set_sampler_views;
3094 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
3095 rctx->b.b.memory_barrier = r600_memory_barrier;
3096 rctx->b.b.texture_barrier = r600_texture_barrier;
3097 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
3098 rctx->b.b.set_active_query_state = r600_set_active_query_state;
3099 rctx->b.b.draw_vbo = r600_draw_vbo;
3100 rctx->b.invalidate_buffer = r600_invalidate_buffer;
3101 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
3102 }