2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
38 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
41 cb
->buf
= CALLOC(1, 4 * num_dw
);
42 cb
->max_num_dw
= num_dw
;
45 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
50 void r600_add_atom(struct r600_context
*rctx
,
51 struct r600_atom
*atom
,
54 assert(id
< R600_NUM_ATOMS
);
55 assert(rctx
->atoms
[id
] == NULL
);
56 rctx
->atoms
[id
] = atom
;
61 void r600_init_atom(struct r600_context
*rctx
,
62 struct r600_atom
*atom
,
64 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
67 atom
->emit
= (void*)emit
;
68 atom
->num_dw
= num_dw
;
69 r600_add_atom(rctx
, atom
, id
);
72 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
74 r600_emit_command_buffer(rctx
->b
.rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
77 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
79 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
80 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
81 unsigned alpha_ref
= a
->sx_alpha_ref
;
83 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
87 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
88 a
->sx_alpha_test_control
|
89 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
90 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
93 static void r600_texture_barrier(struct pipe_context
*ctx
)
95 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
97 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
98 R600_CONTEXT_FLUSH_AND_INV_CB
|
99 R600_CONTEXT_FLUSH_AND_INV
|
100 R600_CONTEXT_WAIT_3D_IDLE
;
103 static unsigned r600_conv_pipe_prim(unsigned prim
)
105 static const unsigned prim_conv
[] = {
106 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
107 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
108 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
109 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
110 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
111 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
112 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
113 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
114 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
115 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
116 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
117 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
118 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
119 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
120 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
122 assert(prim
< Elements(prim_conv
));
123 return prim_conv
[prim
];
126 /* common state between evergreen and r600 */
128 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
129 struct r600_blend_state
*blend
, bool blend_disable
)
131 unsigned color_control
;
132 bool update_cb
= false;
134 rctx
->alpha_to_one
= blend
->alpha_to_one
;
135 rctx
->dual_src_blend
= blend
->dual_src_blend
;
137 if (!blend_disable
) {
138 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
139 color_control
= blend
->cb_color_control
;
141 /* Blending is disabled. */
142 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
143 color_control
= blend
->cb_color_control_no_blend
;
146 /* Update derived states. */
147 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
148 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
151 if (rctx
->b
.chip_class
<= R700
&&
152 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
153 rctx
->cb_misc_state
.cb_color_control
= color_control
;
156 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
157 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
161 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
165 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
167 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
168 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
171 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
175 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
178 static void r600_set_blend_color(struct pipe_context
*ctx
,
179 const struct pipe_blend_color
*state
)
181 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
183 rctx
->blend_color
.state
= *state
;
184 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
187 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
189 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
190 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
192 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
193 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
194 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
195 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
196 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
199 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
201 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
202 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
204 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
205 r600_write_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
206 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
207 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
208 if (a
->last_draw_was_indirect
) {
209 a
->last_draw_was_indirect
= false;
210 r600_write_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
214 static void r600_set_clip_state(struct pipe_context
*ctx
,
215 const struct pipe_clip_state
*state
)
217 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
218 struct pipe_constant_buffer cb
;
220 rctx
->clip_state
.state
= *state
;
221 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
224 cb
.user_buffer
= state
->ucp
;
225 cb
.buffer_offset
= 0;
226 cb
.buffer_size
= 4*4*8;
227 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
228 pipe_resource_reference(&cb
.buffer
, NULL
);
231 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
232 const struct r600_stencil_ref
*state
)
234 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
236 rctx
->stencil_ref
.state
= *state
;
237 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
240 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
242 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
243 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
245 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
246 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
247 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
248 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
249 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
250 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
251 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
252 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
253 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
256 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
257 const struct pipe_stencil_ref
*state
)
259 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
260 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
261 struct r600_stencil_ref ref
;
263 rctx
->stencil_ref
.pipe_state
= *state
;
268 ref
.ref_value
[0] = state
->ref_value
[0];
269 ref
.ref_value
[1] = state
->ref_value
[1];
270 ref
.valuemask
[0] = dsa
->valuemask
[0];
271 ref
.valuemask
[1] = dsa
->valuemask
[1];
272 ref
.writemask
[0] = dsa
->writemask
[0];
273 ref
.writemask
[1] = dsa
->writemask
[1];
275 r600_set_stencil_ref(ctx
, &ref
);
278 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
280 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
281 struct r600_dsa_state
*dsa
= state
;
282 struct r600_stencil_ref ref
;
285 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
289 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
291 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
292 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
293 ref
.valuemask
[0] = dsa
->valuemask
[0];
294 ref
.valuemask
[1] = dsa
->valuemask
[1];
295 ref
.writemask
[0] = dsa
->writemask
[0];
296 ref
.writemask
[1] = dsa
->writemask
[1];
297 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
298 rctx
->zwritemask
= dsa
->zwritemask
;
299 if (rctx
->b
.chip_class
>= EVERGREEN
) {
300 /* work around some issue when not writing to zbuffer
301 * we are having lockup on evergreen so do not enable
302 * hyperz when not writing zbuffer
304 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
308 r600_set_stencil_ref(ctx
, &ref
);
310 /* Update alphatest state. */
311 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
312 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
313 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
314 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
315 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
319 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
321 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
322 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
327 rctx
->rasterizer
= rs
;
329 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
331 if (rs
->offset_enable
&&
332 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
333 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
334 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
335 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
336 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
339 /* Update clip_misc_state. */
340 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
341 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
342 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
343 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
344 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
347 /* Workaround for a missing scissor enable on r600. */
348 if (rctx
->b
.chip_class
== R600
&&
349 rs
->scissor_enable
!= rctx
->scissor
[0].enable
) {
350 rctx
->scissor
[0].enable
= rs
->scissor_enable
;
351 r600_mark_atom_dirty(rctx
, &rctx
->scissor
[0].atom
);
354 /* Re-emit PA_SC_LINE_STIPPLE. */
355 rctx
->last_primitive_type
= -1;
358 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
360 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
362 r600_release_command_buffer(&rs
->buffer
);
366 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
367 struct pipe_sampler_view
*state
)
369 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
371 if (view
->tex_resource
->gpu_address
&&
372 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
373 LIST_DELINIT(&view
->list
);
375 pipe_resource_reference(&state
->texture
, NULL
);
379 void r600_sampler_states_dirty(struct r600_context
*rctx
,
380 struct r600_sampler_states
*state
)
382 if (state
->dirty_mask
) {
383 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
384 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
387 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
388 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
389 r600_mark_atom_dirty(rctx
, &state
->atom
);
393 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
396 unsigned count
, void **states
)
398 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
399 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
400 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
401 int seamless_cube_map
= -1;
403 /* This sets 1-bit for states with index >= count. */
404 uint32_t disable_mask
= ~((1ull << count
) - 1);
405 /* These are the new states set by this function. */
406 uint32_t new_mask
= 0;
408 assert(start
== 0); /* XXX fix below */
415 for (i
= 0; i
< count
; i
++) {
416 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
418 if (rstate
== dst
->states
.states
[i
]) {
423 if (rstate
->border_color_use
) {
424 dst
->states
.has_bordercolor_mask
|= 1 << i
;
426 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
428 seamless_cube_map
= rstate
->seamless_cube_map
;
432 disable_mask
|= 1 << i
;
436 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
437 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
439 dst
->states
.enabled_mask
&= ~disable_mask
;
440 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
441 dst
->states
.enabled_mask
|= new_mask
;
442 dst
->states
.dirty_mask
|= new_mask
;
443 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
445 r600_sampler_states_dirty(rctx
, &dst
->states
);
447 /* Seamless cubemap state. */
448 if (rctx
->b
.chip_class
<= R700
&&
449 seamless_cube_map
!= -1 &&
450 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
451 /* change in TA_CNTL_AUX need a pipeline flush */
452 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
453 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
454 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
458 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
463 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
465 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
466 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
468 if (rctx
->blend_state
.cso
== state
) {
469 ctx
->bind_blend_state(ctx
, NULL
);
472 r600_release_command_buffer(&blend
->buffer
);
473 r600_release_command_buffer(&blend
->buffer_no_blend
);
477 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
479 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
480 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
482 if (rctx
->dsa_state
.cso
== state
) {
483 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
486 r600_release_command_buffer(&dsa
->buffer
);
490 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
492 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
494 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
497 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
499 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
500 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
504 static void r600_set_index_buffer(struct pipe_context
*ctx
,
505 const struct pipe_index_buffer
*ib
)
507 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
510 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
511 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
512 r600_context_add_resource_size(ctx
, ib
->buffer
);
514 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
518 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
520 if (rctx
->vertex_buffer_state
.dirty_mask
) {
521 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
;
522 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
523 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
524 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
528 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
529 unsigned start_slot
, unsigned count
,
530 const struct pipe_vertex_buffer
*input
)
532 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
533 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
534 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
536 uint32_t disable_mask
= 0;
537 /* These are the new buffers set by this function. */
538 uint32_t new_buffer_mask
= 0;
540 /* Set vertex buffers. */
542 for (i
= 0; i
< count
; i
++) {
543 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
544 if (input
[i
].buffer
) {
545 vb
[i
].stride
= input
[i
].stride
;
546 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
547 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
548 new_buffer_mask
|= 1 << i
;
549 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
551 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
552 disable_mask
|= 1 << i
;
557 for (i
= 0; i
< count
; i
++) {
558 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
560 disable_mask
= ((1ull << count
) - 1);
563 disable_mask
<<= start_slot
;
564 new_buffer_mask
<<= start_slot
;
566 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
567 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
568 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
569 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
571 r600_vertex_buffers_dirty(rctx
);
574 void r600_sampler_views_dirty(struct r600_context
*rctx
,
575 struct r600_samplerview_state
*state
)
577 if (state
->dirty_mask
) {
578 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
579 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
580 util_bitcount(state
->dirty_mask
);
581 r600_mark_atom_dirty(rctx
, &state
->atom
);
585 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
586 unsigned start
, unsigned count
,
587 struct pipe_sampler_view
**views
)
589 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
590 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
591 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
592 uint32_t dirty_sampler_states_mask
= 0;
594 /* This sets 1-bit for textures with index >= count. */
595 uint32_t disable_mask
= ~((1ull << count
) - 1);
596 /* These are the new textures set by this function. */
597 uint32_t new_mask
= 0;
599 /* Set textures with index >= count to NULL. */
600 uint32_t remaining_mask
;
602 assert(start
== 0); /* XXX fix below */
609 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
611 while (remaining_mask
) {
612 i
= u_bit_scan(&remaining_mask
);
613 assert(dst
->views
.views
[i
]);
615 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
618 for (i
= 0; i
< count
; i
++) {
619 if (rviews
[i
] == dst
->views
.views
[i
]) {
624 struct r600_texture
*rtex
=
625 (struct r600_texture
*)rviews
[i
]->base
.texture
;
627 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
628 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
629 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
631 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
634 /* Track compressed colorbuffers. */
635 if (rtex
->cmask
.size
) {
636 dst
->views
.compressed_colortex_mask
|= 1 << i
;
638 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
641 /* Changing from array to non-arrays textures and vice versa requires
642 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
643 if (rctx
->b
.chip_class
<= R700
&&
644 (dst
->states
.enabled_mask
& (1 << i
)) &&
645 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
646 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
647 dirty_sampler_states_mask
|= 1 << i
;
650 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
652 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
654 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
655 disable_mask
|= 1 << i
;
659 dst
->views
.enabled_mask
&= ~disable_mask
;
660 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
661 dst
->views
.enabled_mask
|= new_mask
;
662 dst
->views
.dirty_mask
|= new_mask
;
663 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
664 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
665 dst
->views
.dirty_buffer_constants
= TRUE
;
666 r600_sampler_views_dirty(rctx
, &dst
->views
);
668 if (dirty_sampler_states_mask
) {
669 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
670 r600_sampler_states_dirty(rctx
, &dst
->states
);
674 static void r600_set_viewport_states(struct pipe_context
*ctx
,
676 unsigned num_viewports
,
677 const struct pipe_viewport_state
*state
)
679 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
682 for (i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
683 rctx
->viewport
[i
].state
= state
[i
- start_slot
];
684 r600_mark_atom_dirty(rctx
, &rctx
->viewport
[i
].atom
);
688 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
690 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
691 struct r600_viewport_state
*rstate
= (struct r600_viewport_state
*)atom
;
692 struct pipe_viewport_state
*state
= &rstate
->state
;
693 int offset
= rstate
->idx
* 6 * 4;
695 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
+ offset
, 6);
696 radeon_emit(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
697 radeon_emit(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
698 radeon_emit(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
699 radeon_emit(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
700 radeon_emit(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
701 radeon_emit(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
704 /* Compute the key for the hw shader variant */
705 static inline struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
706 struct r600_pipe_shader_selector
* sel
)
708 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
709 struct r600_shader_key key
;
710 memset(&key
, 0, sizeof(key
));
712 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
713 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
714 key
.alpha_to_one
= rctx
->alpha_to_one
&&
715 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
716 !rctx
->framebuffer
.cb0_is_integer
;
717 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
718 /* Dual-source blending only makes sense with nr_cbufs == 1. */
719 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
721 } else if (sel
->type
== PIPE_SHADER_VERTEX
) {
722 key
.vs_as_es
= (rctx
->gs_shader
!= NULL
);
723 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
724 key
.vs_as_gs_a
= true;
725 key
.vs_prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
731 /* Select the hw shader variant depending on the current state.
732 * (*dirty) is set to 1 if current variant was changed */
733 static int r600_shader_select(struct pipe_context
*ctx
,
734 struct r600_pipe_shader_selector
* sel
,
737 struct r600_shader_key key
;
738 struct r600_pipe_shader
* shader
= NULL
;
741 memset(&key
, 0, sizeof(key
));
742 key
= r600_shader_selector_key(ctx
, sel
);
744 /* Check if we don't need to change anything.
745 * This path is also used for most shaders that don't need multiple
746 * variants, it will cost just a computation of the key and this
748 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
752 /* lookup if we have other variants in the list */
753 if (sel
->num_shaders
> 1) {
754 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
756 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
762 p
->next_variant
= c
->next_variant
;
767 if (unlikely(!shader
)) {
768 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
769 shader
->selector
= sel
;
771 r
= r600_pipe_shader_create(ctx
, shader
, key
);
773 R600_ERR("Failed to build shader variant (type=%u) %d\n",
780 /* We don't know the value of nr_ps_max_color_exports until we built
781 * at least one variant, so we may need to recompute the key after
782 * building first variant. */
783 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
784 sel
->num_shaders
== 0) {
785 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
786 key
= r600_shader_selector_key(ctx
, sel
);
789 memcpy(&shader
->key
, &key
, sizeof(key
));
796 shader
->next_variant
= sel
->current
;
797 sel
->current
= shader
;
802 static void *r600_create_shader_state(struct pipe_context
*ctx
,
803 const struct pipe_shader_state
*state
,
804 unsigned pipe_shader_type
)
806 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
808 sel
->type
= pipe_shader_type
;
809 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
810 sel
->so
= state
->stream_output
;
814 static void *r600_create_ps_state(struct pipe_context
*ctx
,
815 const struct pipe_shader_state
*state
)
817 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
820 static void *r600_create_vs_state(struct pipe_context
*ctx
,
821 const struct pipe_shader_state
*state
)
823 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
826 static void *r600_create_gs_state(struct pipe_context
*ctx
,
827 const struct pipe_shader_state
*state
)
829 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
832 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
834 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
837 state
= rctx
->dummy_pixel_shader
;
839 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
842 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
844 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
849 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
850 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
853 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
855 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
857 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
861 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
864 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
865 struct r600_pipe_shader_selector
*sel
)
867 struct r600_pipe_shader
*p
= sel
->current
, *c
;
870 r600_pipe_shader_destroy(ctx
, p
);
880 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
882 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
883 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
885 if (rctx
->ps_shader
== sel
) {
886 rctx
->ps_shader
= NULL
;
889 r600_delete_shader_selector(ctx
, sel
);
892 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
894 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
895 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
897 if (rctx
->vs_shader
== sel
) {
898 rctx
->vs_shader
= NULL
;
901 r600_delete_shader_selector(ctx
, sel
);
905 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
907 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
908 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
910 if (rctx
->gs_shader
== sel
) {
911 rctx
->gs_shader
= NULL
;
914 r600_delete_shader_selector(ctx
, sel
);
918 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
920 if (state
->dirty_mask
) {
921 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
922 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
923 : util_bitcount(state
->dirty_mask
)*19;
924 r600_mark_atom_dirty(rctx
, &state
->atom
);
928 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
929 struct pipe_constant_buffer
*input
)
931 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
932 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
933 struct pipe_constant_buffer
*cb
;
936 /* Note that the state tracker can unbind constant buffers by
939 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
940 state
->enabled_mask
&= ~(1 << index
);
941 state
->dirty_mask
&= ~(1 << index
);
942 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
946 cb
= &state
->cb
[index
];
947 cb
->buffer_size
= input
->buffer_size
;
949 ptr
= input
->user_buffer
;
952 /* Upload the user buffer. */
953 if (R600_BIG_ENDIAN
) {
955 unsigned i
, size
= input
->buffer_size
;
957 if (!(tmpPtr
= malloc(size
))) {
958 R600_ERR("Failed to allocate BE swap buffer.\n");
962 for (i
= 0; i
< size
/ 4; ++i
) {
963 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
966 u_upload_data(rctx
->b
.uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
969 u_upload_data(rctx
->b
.uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
971 /* account it in gtt */
972 rctx
->b
.gtt
+= input
->buffer_size
;
974 /* Setup the hw buffer. */
975 cb
->buffer_offset
= input
->buffer_offset
;
976 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
977 r600_context_add_resource_size(ctx
, input
->buffer
);
980 state
->enabled_mask
|= 1 << index
;
981 state
->dirty_mask
|= 1 << index
;
982 r600_constant_buffers_dirty(rctx
, state
);
985 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
987 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
989 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
992 rctx
->sample_mask
.sample_mask
= sample_mask
;
993 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
997 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
998 * doesn't require full swizzles it does need masking and setting alpha
999 * to one, so we setup a set of 5 constants with the masks + alpha value
1000 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1001 * then OR the alpha with the value given here.
1002 * We use a 6th constant to store the txq buffer size in
1003 * we use 7th slot for number of cube layers in a cube map array.
1005 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1007 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1009 uint32_t array_size
;
1010 struct pipe_constant_buffer cb
;
1013 if (!samplers
->views
.dirty_buffer_constants
)
1016 samplers
->views
.dirty_buffer_constants
= FALSE
;
1018 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1019 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1020 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1021 memset(samplers
->buffer_constants
, 0, array_size
);
1022 for (i
= 0; i
< bits
; i
++) {
1023 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1025 const struct util_format_description
*desc
;
1026 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1028 for (j
= 0; j
< 4; j
++)
1029 if (j
< desc
->nr_channels
)
1030 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1032 samplers
->buffer_constants
[offset
+j
] = 0x0;
1033 if (desc
->nr_channels
< 4) {
1034 if (desc
->channel
[0].pure_integer
)
1035 samplers
->buffer_constants
[offset
+4] = 1;
1037 samplers
->buffer_constants
[offset
+4] = fui(1.0);
1039 samplers
->buffer_constants
[offset
+ 4] = 0;
1041 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1042 samplers
->buffer_constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1047 cb
.user_buffer
= samplers
->buffer_constants
;
1048 cb
.buffer_offset
= 0;
1049 cb
.buffer_size
= array_size
;
1050 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1051 pipe_resource_reference(&cb
.buffer
, NULL
);
1054 /* On evergreen we store two values
1055 * 1. buffer size for TXQ
1056 * 2. number of cube layers in a cube map array.
1058 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1060 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1062 uint32_t array_size
;
1063 struct pipe_constant_buffer cb
;
1066 if (!samplers
->views
.dirty_buffer_constants
)
1069 samplers
->views
.dirty_buffer_constants
= FALSE
;
1071 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1072 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1073 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1074 memset(samplers
->buffer_constants
, 0, array_size
);
1075 for (i
= 0; i
< bits
; i
++) {
1076 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1077 uint32_t offset
= i
* 2;
1078 samplers
->buffer_constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1079 samplers
->buffer_constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1084 cb
.user_buffer
= samplers
->buffer_constants
;
1085 cb
.buffer_offset
= 0;
1086 cb
.buffer_size
= array_size
;
1087 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1088 pipe_resource_reference(&cb
.buffer
, NULL
);
1091 /* set sample xy locations as array of fragment shader constants */
1092 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1094 struct pipe_constant_buffer constbuf
= {0};
1095 float values
[4*16] = {0.0f
};
1097 struct pipe_context
*ctx
= &rctx
->b
.b
;
1099 assert(rctx
->framebuffer
.nr_samples
<= Elements(values
)/4);
1100 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1101 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &values
[4*i
]);
1102 /* Also fill in center-zeroed positions used for interpolateAtSample */
1103 values
[4*i
+ 2] = values
[4*i
+ 0] - 0.5f
;
1104 values
[4*i
+ 3] = values
[4*i
+ 1] - 0.5f
;
1107 constbuf
.user_buffer
= values
;
1108 constbuf
.buffer_size
= rctx
->framebuffer
.nr_samples
* 4 * 4;
1109 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_FRAGMENT
,
1110 R600_SAMPLE_POSITIONS_CONST_BUFFER
, &constbuf
);
1111 pipe_resource_reference(&constbuf
.buffer
, NULL
);
1114 static void update_shader_atom(struct pipe_context
*ctx
,
1115 struct r600_shader_state
*state
,
1116 struct r600_pipe_shader
*shader
)
1118 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1120 state
->shader
= shader
;
1122 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1123 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1125 state
->atom
.num_dw
= 0;
1127 r600_mark_atom_dirty(rctx
, &state
->atom
);
1130 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1132 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1133 rctx
->shader_stages
.geom_enable
= enable
;
1134 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1137 if (rctx
->gs_rings
.enable
!= enable
) {
1138 rctx
->gs_rings
.enable
= enable
;
1139 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1141 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1142 unsigned size
= 0x1C000;
1143 rctx
->gs_rings
.esgs_ring
.buffer
=
1144 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1145 PIPE_USAGE_DEFAULT
, size
);
1146 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1150 rctx
->gs_rings
.gsvs_ring
.buffer
=
1151 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1152 PIPE_USAGE_DEFAULT
, size
);
1153 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1157 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1158 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1159 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1160 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1162 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1163 R600_GS_RING_CONST_BUFFER
, NULL
);
1164 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1165 R600_GS_RING_CONST_BUFFER
, NULL
);
1170 static bool r600_update_derived_state(struct r600_context
*rctx
)
1172 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1173 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1175 bool need_buf_const
;
1176 if (!rctx
->blitter
->running
) {
1179 /* Decompress textures if needed. */
1180 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1181 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1182 if (views
->compressed_depthtex_mask
) {
1183 r600_decompress_depth_textures(rctx
, views
);
1185 if (views
->compressed_colortex_mask
) {
1186 r600_decompress_color_textures(rctx
, views
);
1191 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1192 if (unlikely(!rctx
->ps_shader
->current
))
1195 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1197 if (rctx
->gs_shader
) {
1198 r600_shader_select(ctx
, rctx
->gs_shader
, &gs_dirty
);
1199 if (unlikely(!rctx
->gs_shader
->current
))
1202 if (!rctx
->shader_stages
.geom_enable
) {
1203 rctx
->shader_stages
.geom_enable
= true;
1204 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1207 /* gs_shader provides GS and VS (copy shader) */
1208 if (unlikely(rctx
->geometry_shader
.shader
!= rctx
->gs_shader
->current
)) {
1209 update_shader_atom(ctx
, &rctx
->geometry_shader
, rctx
->gs_shader
->current
);
1210 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->gs_shader
->current
->gs_copy_shader
);
1211 /* Update clip misc state. */
1212 if (rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1213 rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1214 rctx
->clip_misc_state
.clip_disable
!= rctx
->gs_shader
->current
->shader
.vs_position_window_space
) {
1215 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
;
1216 rctx
->clip_misc_state
.clip_dist_write
= rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
;
1217 rctx
->clip_misc_state
.clip_disable
= rctx
->gs_shader
->current
->shader
.vs_position_window_space
;
1218 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1220 rctx
->b
.streamout
.enabled_stream_buffers_mask
= rctx
->gs_shader
->current
->gs_copy_shader
->enabled_stream_buffers_mask
;
1223 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1224 if (unlikely(!rctx
->vs_shader
->current
))
1227 /* vs_shader is used as ES */
1228 if (unlikely(vs_dirty
|| rctx
->export_shader
.shader
!= rctx
->vs_shader
->current
)) {
1229 update_shader_atom(ctx
, &rctx
->export_shader
, rctx
->vs_shader
->current
);
1232 if (unlikely(rctx
->geometry_shader
.shader
)) {
1233 update_shader_atom(ctx
, &rctx
->geometry_shader
, NULL
);
1234 update_shader_atom(ctx
, &rctx
->export_shader
, NULL
);
1235 rctx
->shader_stages
.geom_enable
= false;
1236 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1239 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1240 if (unlikely(!rctx
->vs_shader
->current
))
1243 if (unlikely(vs_dirty
|| rctx
->vertex_shader
.shader
!= rctx
->vs_shader
->current
)) {
1244 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->vs_shader
->current
);
1246 /* Update clip misc state. */
1247 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1248 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1249 rctx
->clip_misc_state
.clip_disable
!= rctx
->vs_shader
->current
->shader
.vs_position_window_space
) {
1250 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
1251 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
1252 rctx
->clip_misc_state
.clip_disable
= rctx
->vs_shader
->current
->shader
.vs_position_window_space
;
1253 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1255 rctx
->b
.streamout
.enabled_stream_buffers_mask
= rctx
->vs_shader
->current
->enabled_stream_buffers_mask
;
1260 if (unlikely(ps_dirty
|| rctx
->pixel_shader
.shader
!= rctx
->ps_shader
->current
||
1261 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1262 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1264 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1265 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1266 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1269 if (rctx
->b
.chip_class
<= R700
) {
1270 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1272 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1273 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1274 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1278 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1279 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1280 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1282 if (rctx
->b
.chip_class
>= EVERGREEN
)
1283 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1285 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1288 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1289 update_shader_atom(ctx
, &rctx
->pixel_shader
, rctx
->ps_shader
->current
);
1292 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1293 evergreen_update_db_shader_control(rctx
);
1295 r600_update_db_shader_control(rctx
);
1298 /* on R600 we stuff masks + txq info into one constant buffer */
1299 /* on evergreen we only need a txq info one */
1300 if (rctx
->ps_shader
) {
1301 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1302 if (need_buf_const
) {
1303 if (rctx
->b
.chip_class
< EVERGREEN
)
1304 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1306 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1310 if (rctx
->vs_shader
) {
1311 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1312 if (need_buf_const
) {
1313 if (rctx
->b
.chip_class
< EVERGREEN
)
1314 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1316 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1320 if (rctx
->gs_shader
) {
1321 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1322 if (need_buf_const
) {
1323 if (rctx
->b
.chip_class
< EVERGREEN
)
1324 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1326 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1330 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1331 if (!r600_adjust_gprs(rctx
)) {
1332 /* discard rendering */
1337 blend_disable
= (rctx
->dual_src_blend
&&
1338 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1340 if (blend_disable
!= rctx
->force_blend_disable
) {
1341 rctx
->force_blend_disable
= blend_disable
;
1342 r600_bind_blend_state_internal(rctx
,
1343 rctx
->blend_state
.cso
,
1350 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1352 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1353 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1355 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1356 state
->pa_cl_clip_cntl
|
1357 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1358 S_028810_CLIP_DISABLE(state
->clip_disable
));
1359 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1360 state
->pa_cl_vs_out_cntl
|
1361 (state
->clip_plane_enable
& state
->clip_dist_write
));
1364 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1366 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1367 struct pipe_draw_info info
= *dinfo
;
1368 struct pipe_index_buffer ib
= {};
1370 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1372 if (!info
.indirect
&& !info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1376 if (!rctx
->vs_shader
|| !rctx
->ps_shader
) {
1381 /* make sure that the gfx ring is only one active */
1382 if (rctx
->b
.rings
.dma
.cs
&& rctx
->b
.rings
.dma
.cs
->cdw
) {
1383 rctx
->b
.rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1386 if (!r600_update_derived_state(rctx
)) {
1387 /* useless to render because current rendering command
1394 /* Initialize the index buffer struct. */
1395 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1396 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1397 ib
.index_size
= rctx
->index_buffer
.index_size
;
1398 ib
.offset
= rctx
->index_buffer
.offset
;
1399 if (!info
.indirect
) {
1400 ib
.offset
+= info
.start
* ib
.index_size
;
1403 /* Translate 8-bit indices to 16-bit. */
1404 if (unlikely(ib
.index_size
== 1)) {
1405 struct pipe_resource
*out_buffer
= NULL
;
1406 unsigned out_offset
;
1408 unsigned start
, count
;
1410 if (likely(!info
.indirect
)) {
1415 /* Have to get start/count from indirect buffer, slow path ahead... */
1416 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
.indirect
;
1417 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1418 PIPE_TRANSFER_READ
);
1420 data
+= info
.indirect_offset
/ sizeof(unsigned);
1421 start
= data
[2] * ib
.index_size
;
1430 u_upload_alloc(rctx
->b
.uploader
, start
, count
* 2,
1431 &out_offset
, &out_buffer
, &ptr
);
1433 util_shorten_ubyte_elts_to_userptr(
1434 &rctx
->b
.b
, &ib
, 0, ib
.offset
+ start
, count
, ptr
);
1436 pipe_resource_reference(&ib
.buffer
, NULL
);
1437 ib
.user_buffer
= NULL
;
1438 ib
.buffer
= out_buffer
;
1439 ib
.offset
= out_offset
;
1443 /* Upload the index buffer.
1444 * The upload is skipped for small index counts on little-endian machines
1445 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1446 * Indirect draws never use immediate indices.
1447 * Note: Instanced rendering in combination with immediate indices hangs. */
1448 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.indirect
||
1449 info
.instance_count
> 1 ||
1450 info
.count
*ib
.index_size
> 20)) {
1451 u_upload_data(rctx
->b
.uploader
, 0, info
.count
* ib
.index_size
,
1452 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1453 ib
.user_buffer
= NULL
;
1456 info
.index_bias
= info
.start
;
1459 /* Set the index offset and primitive restart. */
1460 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1461 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1462 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
||
1463 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
.indirect
)) {
1464 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1465 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1466 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1467 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1470 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1471 if (rctx
->b
.chip_class
== R600
) {
1472 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1473 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1477 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1478 r600_flush_emit(rctx
);
1480 i
= r600_next_dirty_atom(rctx
, 0);
1481 while (i
< R600_NUM_ATOMS
) {
1482 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1483 i
= r600_next_dirty_atom(rctx
, i
+ 1);
1486 if (rctx
->b
.chip_class
== CAYMAN
) {
1487 /* Copied from radeonsi. */
1488 unsigned primgroup_size
= 128; /* recommended without a GS */
1489 bool ia_switch_on_eop
= false;
1490 bool partial_vs_wave
= false;
1492 if (rctx
->gs_shader
)
1493 primgroup_size
= 64; /* recommended with a GS */
1495 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1496 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1497 ia_switch_on_eop
= true;
1500 if (rctx
->b
.streamout
.streamout_enabled
||
1501 rctx
->b
.streamout
.prims_gen_query_enabled
)
1502 partial_vs_wave
= true;
1504 r600_write_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1505 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1506 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1507 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1510 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1511 * even though it should have no effect on those. */
1512 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1513 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1514 unsigned prim
= info
.mode
;
1516 if (rctx
->gs_shader
) {
1517 prim
= rctx
->gs_shader
->current
->shader
.gs_output_prim
;
1519 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1521 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1522 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1523 info
.mode
== R600_PRIM_RECTANGLE_LIST
) {
1524 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1526 r600_write_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1529 /* Update start instance. */
1530 if (!info
.indirect
&& rctx
->last_start_instance
!= info
.start_instance
) {
1531 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1532 rctx
->last_start_instance
= info
.start_instance
;
1535 /* Update the primitive type. */
1536 if (rctx
->last_primitive_type
!= info
.mode
) {
1537 unsigned ls_mask
= 0;
1539 if (info
.mode
== PIPE_PRIM_LINES
)
1541 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1542 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1545 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1546 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1547 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1548 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1549 r600_conv_pipe_prim(info
.mode
));
1551 rctx
->last_primitive_type
= info
.mode
;
1555 if (!info
.indirect
) {
1556 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->b
.predicate_drawing
);
1557 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1560 if (unlikely(info
.indirect
)) {
1561 uint64_t va
= r600_resource(info
.indirect
)->gpu_address
;
1562 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1564 // Invalidate so non-indirect draw calls reset this state
1565 rctx
->vgt_state
.last_draw_was_indirect
= true;
1566 rctx
->last_start_instance
= -1;
1568 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_SET_BASE
, 2, rctx
->b
.predicate_drawing
);
1569 cs
->buf
[cs
->cdw
++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
;
1570 cs
->buf
[cs
->cdw
++] = va
;
1571 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1573 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1574 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1575 (struct r600_resource
*)info
.indirect
,
1576 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
1580 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->b
.predicate_drawing
);
1581 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1582 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1583 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1585 if (ib
.user_buffer
) {
1586 unsigned size_bytes
= info
.count
*ib
.index_size
;
1587 unsigned size_dw
= align(size_bytes
, 4) / 4;
1588 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->b
.predicate_drawing
);
1589 cs
->buf
[cs
->cdw
++] = info
.count
;
1590 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1591 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1594 uint64_t va
= r600_resource(ib
.buffer
)->gpu_address
+ ib
.offset
;
1596 if (likely(!info
.indirect
)) {
1597 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->b
.predicate_drawing
);
1598 cs
->buf
[cs
->cdw
++] = va
;
1599 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1600 cs
->buf
[cs
->cdw
++] = info
.count
;
1601 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1602 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1603 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1604 (struct r600_resource
*)ib
.buffer
,
1605 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
1608 uint32_t max_size
= (ib
.buffer
->width0
- ib
.offset
) / ib
.index_size
;
1610 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_INDEX_BASE
, 1, rctx
->b
.predicate_drawing
);
1611 cs
->buf
[cs
->cdw
++] = va
;
1612 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1614 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1615 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1616 (struct r600_resource
*)ib
.buffer
,
1617 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
1619 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, rctx
->b
.predicate_drawing
);
1620 cs
->buf
[cs
->cdw
++] = max_size
;
1622 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, rctx
->b
.predicate_drawing
);
1623 cs
->buf
[cs
->cdw
++] = info
.indirect_offset
;
1624 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1628 if (unlikely(info
.count_from_stream_output
)) {
1629 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1630 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1632 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1634 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1635 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1636 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1637 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1638 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1639 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1641 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1642 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1643 t
->buf_filled_size
, RADEON_USAGE_READ
,
1647 if (likely(!info
.indirect
)) {
1648 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->b
.predicate_drawing
);
1649 cs
->buf
[cs
->cdw
++] = info
.count
;
1652 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_DRAW_INDIRECT
, 1, rctx
->b
.predicate_drawing
);
1653 cs
->buf
[cs
->cdw
++] = info
.indirect_offset
;
1655 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1656 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1659 if (rctx
->screen
->b
.trace_bo
) {
1660 r600_trace_emit(rctx
);
1663 /* Set the depth buffer as dirty. */
1664 if (rctx
->framebuffer
.state
.zsbuf
) {
1665 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1666 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1668 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1670 if (rctx
->framebuffer
.compressed_cb_mask
) {
1671 struct pipe_surface
*surf
;
1672 struct r600_texture
*rtex
;
1673 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1676 unsigned i
= u_bit_scan(&mask
);
1677 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1678 rtex
= (struct r600_texture
*)surf
->texture
;
1680 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1685 pipe_resource_reference(&ib
.buffer
, NULL
);
1686 rctx
->b
.num_draw_calls
++;
1689 uint32_t r600_translate_stencil_op(int s_op
)
1692 case PIPE_STENCIL_OP_KEEP
:
1693 return V_028800_STENCIL_KEEP
;
1694 case PIPE_STENCIL_OP_ZERO
:
1695 return V_028800_STENCIL_ZERO
;
1696 case PIPE_STENCIL_OP_REPLACE
:
1697 return V_028800_STENCIL_REPLACE
;
1698 case PIPE_STENCIL_OP_INCR
:
1699 return V_028800_STENCIL_INCR
;
1700 case PIPE_STENCIL_OP_DECR
:
1701 return V_028800_STENCIL_DECR
;
1702 case PIPE_STENCIL_OP_INCR_WRAP
:
1703 return V_028800_STENCIL_INCR_WRAP
;
1704 case PIPE_STENCIL_OP_DECR_WRAP
:
1705 return V_028800_STENCIL_DECR_WRAP
;
1706 case PIPE_STENCIL_OP_INVERT
:
1707 return V_028800_STENCIL_INVERT
;
1709 R600_ERR("Unknown stencil op %d", s_op
);
1716 uint32_t r600_translate_fill(uint32_t func
)
1719 case PIPE_POLYGON_MODE_FILL
:
1721 case PIPE_POLYGON_MODE_LINE
:
1723 case PIPE_POLYGON_MODE_POINT
:
1731 unsigned r600_tex_wrap(unsigned wrap
)
1735 case PIPE_TEX_WRAP_REPEAT
:
1736 return V_03C000_SQ_TEX_WRAP
;
1737 case PIPE_TEX_WRAP_CLAMP
:
1738 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1739 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1740 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1741 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1742 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1743 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1744 return V_03C000_SQ_TEX_MIRROR
;
1745 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1746 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1747 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1748 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1749 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1750 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1754 unsigned r600_tex_filter(unsigned filter
)
1758 case PIPE_TEX_FILTER_NEAREST
:
1759 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1760 case PIPE_TEX_FILTER_LINEAR
:
1761 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1765 unsigned r600_tex_mipfilter(unsigned filter
)
1768 case PIPE_TEX_MIPFILTER_NEAREST
:
1769 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1770 case PIPE_TEX_MIPFILTER_LINEAR
:
1771 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1773 case PIPE_TEX_MIPFILTER_NONE
:
1774 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1778 unsigned r600_tex_compare(unsigned compare
)
1782 case PIPE_FUNC_NEVER
:
1783 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1784 case PIPE_FUNC_LESS
:
1785 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1786 case PIPE_FUNC_EQUAL
:
1787 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1788 case PIPE_FUNC_LEQUAL
:
1789 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1790 case PIPE_FUNC_GREATER
:
1791 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1792 case PIPE_FUNC_NOTEQUAL
:
1793 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1794 case PIPE_FUNC_GEQUAL
:
1795 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1796 case PIPE_FUNC_ALWAYS
:
1797 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1801 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1803 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1804 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1806 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1807 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1810 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1812 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1813 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1815 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1816 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1817 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1818 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1819 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1822 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1825 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1826 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
1831 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
1832 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1833 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->bo
,
1834 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
1837 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
1838 const unsigned char *swizzle_view
,
1842 unsigned char swizzle
[4];
1843 unsigned result
= 0;
1844 const uint32_t tex_swizzle_shift
[4] = {
1847 const uint32_t vtx_swizzle_shift
[4] = {
1850 const uint32_t swizzle_bit
[4] = {
1853 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
1856 swizzle_shift
= vtx_swizzle_shift
;
1859 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1861 memcpy(swizzle
, swizzle_format
, 4);
1865 for (i
= 0; i
< 4; i
++) {
1866 switch (swizzle
[i
]) {
1867 case UTIL_FORMAT_SWIZZLE_Y
:
1868 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1870 case UTIL_FORMAT_SWIZZLE_Z
:
1871 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1873 case UTIL_FORMAT_SWIZZLE_W
:
1874 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1876 case UTIL_FORMAT_SWIZZLE_0
:
1877 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1879 case UTIL_FORMAT_SWIZZLE_1
:
1880 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1882 default: /* UTIL_FORMAT_SWIZZLE_X */
1883 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1889 /* texture format translate */
1890 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1891 enum pipe_format format
,
1892 const unsigned char *swizzle_view
,
1893 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1895 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1896 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1897 const struct util_format_description
*desc
;
1898 boolean uniform
= TRUE
;
1899 bool enable_s3tc
= rscreen
->b
.info
.drm_minor
>= 9;
1900 bool is_srgb_valid
= FALSE
;
1901 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
1902 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
1905 const uint32_t sign_bit
[4] = {
1906 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1907 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1908 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1909 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1911 desc
= util_format_description(format
);
1913 /* Depth and stencil swizzling is handled separately. */
1914 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
1915 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
1918 /* Colorspace (return non-RGB formats directly). */
1919 switch (desc
->colorspace
) {
1920 /* Depth stencil formats */
1921 case UTIL_FORMAT_COLORSPACE_ZS
:
1923 /* Depth sampler formats. */
1924 case PIPE_FORMAT_Z16_UNORM
:
1925 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1928 case PIPE_FORMAT_Z24X8_UNORM
:
1929 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1930 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1933 case PIPE_FORMAT_X8Z24_UNORM
:
1934 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1935 if (rscreen
->b
.chip_class
< EVERGREEN
)
1937 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1940 case PIPE_FORMAT_Z32_FLOAT
:
1941 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1942 result
= FMT_32_FLOAT
;
1944 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1945 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1946 result
= FMT_X24_8_32_FLOAT
;
1948 /* Stencil sampler formats. */
1949 case PIPE_FORMAT_S8_UINT
:
1950 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1951 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1954 case PIPE_FORMAT_X24S8_UINT
:
1955 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1956 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1959 case PIPE_FORMAT_S8X24_UINT
:
1960 if (rscreen
->b
.chip_class
< EVERGREEN
)
1962 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1963 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1966 case PIPE_FORMAT_X32_S8X24_UINT
:
1967 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1968 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1969 result
= FMT_X24_8_32_FLOAT
;
1975 case UTIL_FORMAT_COLORSPACE_YUV
:
1976 yuv_format
|= (1 << 30);
1978 case PIPE_FORMAT_UYVY
:
1979 case PIPE_FORMAT_YUYV
:
1983 goto out_unknown
; /* XXX */
1985 case UTIL_FORMAT_COLORSPACE_SRGB
:
1986 word4
|= S_038010_FORCE_DEGAMMA(1);
1993 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1998 case PIPE_FORMAT_RGTC1_SNORM
:
1999 case PIPE_FORMAT_LATC1_SNORM
:
2000 word4
|= sign_bit
[0];
2001 case PIPE_FORMAT_RGTC1_UNORM
:
2002 case PIPE_FORMAT_LATC1_UNORM
:
2005 case PIPE_FORMAT_RGTC2_SNORM
:
2006 case PIPE_FORMAT_LATC2_SNORM
:
2007 word4
|= sign_bit
[0] | sign_bit
[1];
2008 case PIPE_FORMAT_RGTC2_UNORM
:
2009 case PIPE_FORMAT_LATC2_UNORM
:
2017 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2022 if (!util_format_s3tc_enabled
) {
2027 case PIPE_FORMAT_DXT1_RGB
:
2028 case PIPE_FORMAT_DXT1_RGBA
:
2029 case PIPE_FORMAT_DXT1_SRGB
:
2030 case PIPE_FORMAT_DXT1_SRGBA
:
2032 is_srgb_valid
= TRUE
;
2034 case PIPE_FORMAT_DXT3_RGBA
:
2035 case PIPE_FORMAT_DXT3_SRGBA
:
2037 is_srgb_valid
= TRUE
;
2039 case PIPE_FORMAT_DXT5_RGBA
:
2040 case PIPE_FORMAT_DXT5_SRGBA
:
2042 is_srgb_valid
= TRUE
;
2049 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2053 if (rscreen
->b
.chip_class
< EVERGREEN
)
2057 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2058 case PIPE_FORMAT_BPTC_SRGBA
:
2060 is_srgb_valid
= TRUE
;
2062 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2063 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2065 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2073 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2075 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2076 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2079 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2080 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2088 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2089 result
= FMT_5_9_9_9_SHAREDEXP
;
2091 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2092 result
= FMT_10_11_11_FLOAT
;
2097 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2098 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2099 word4
|= sign_bit
[i
];
2103 /* R8G8Bx_SNORM - XXX CxV8U8 */
2105 /* See whether the components are of the same size. */
2106 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2107 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2110 /* Non-uniform formats. */
2112 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2113 desc
->channel
[0].pure_integer
)
2114 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2115 switch(desc
->nr_channels
) {
2117 if (desc
->channel
[0].size
== 5 &&
2118 desc
->channel
[1].size
== 6 &&
2119 desc
->channel
[2].size
== 5) {
2125 if (desc
->channel
[0].size
== 5 &&
2126 desc
->channel
[1].size
== 5 &&
2127 desc
->channel
[2].size
== 5 &&
2128 desc
->channel
[3].size
== 1) {
2129 result
= FMT_1_5_5_5
;
2132 if (desc
->channel
[0].size
== 10 &&
2133 desc
->channel
[1].size
== 10 &&
2134 desc
->channel
[2].size
== 10 &&
2135 desc
->channel
[3].size
== 2) {
2136 result
= FMT_2_10_10_10
;
2144 /* Find the first non-VOID channel. */
2145 for (i
= 0; i
< 4; i
++) {
2146 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2154 /* uniform formats */
2155 switch (desc
->channel
[i
].type
) {
2156 case UTIL_FORMAT_TYPE_UNSIGNED
:
2157 case UTIL_FORMAT_TYPE_SIGNED
:
2159 if (!desc
->channel
[i
].normalized
&&
2160 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2164 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2165 desc
->channel
[i
].pure_integer
)
2166 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2168 switch (desc
->channel
[i
].size
) {
2170 switch (desc
->nr_channels
) {
2175 result
= FMT_4_4_4_4
;
2180 switch (desc
->nr_channels
) {
2188 result
= FMT_8_8_8_8
;
2189 is_srgb_valid
= TRUE
;
2194 switch (desc
->nr_channels
) {
2202 result
= FMT_16_16_16_16
;
2207 switch (desc
->nr_channels
) {
2215 result
= FMT_32_32_32_32
;
2221 case UTIL_FORMAT_TYPE_FLOAT
:
2222 switch (desc
->channel
[i
].size
) {
2224 switch (desc
->nr_channels
) {
2226 result
= FMT_16_FLOAT
;
2229 result
= FMT_16_16_FLOAT
;
2232 result
= FMT_16_16_16_16_FLOAT
;
2237 switch (desc
->nr_channels
) {
2239 result
= FMT_32_FLOAT
;
2242 result
= FMT_32_32_FLOAT
;
2245 result
= FMT_32_32_32_32_FLOAT
;
2254 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2259 *yuv_format_p
= yuv_format
;
2262 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2266 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
)
2268 const struct util_format_description
*desc
= util_format_description(format
);
2269 int channel
= util_format_get_first_non_void_channel(format
);
2272 #define HAS_SIZE(x,y,z,w) \
2273 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2274 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2276 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2277 return V_0280A0_COLOR_10_11_11_FLOAT
;
2279 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2283 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2285 switch (desc
->nr_channels
) {
2287 switch (desc
->channel
[0].size
) {
2289 return V_0280A0_COLOR_8
;
2292 return V_0280A0_COLOR_16_FLOAT
;
2294 return V_0280A0_COLOR_16
;
2297 return V_0280A0_COLOR_32_FLOAT
;
2299 return V_0280A0_COLOR_32
;
2303 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2304 switch (desc
->channel
[0].size
) {
2307 return V_0280A0_COLOR_4_4
;
2309 return ~0U; /* removed on Evergreen */
2311 return V_0280A0_COLOR_8_8
;
2314 return V_0280A0_COLOR_16_16_FLOAT
;
2316 return V_0280A0_COLOR_16_16
;
2319 return V_0280A0_COLOR_32_32_FLOAT
;
2321 return V_0280A0_COLOR_32_32
;
2323 } else if (HAS_SIZE(8,24,0,0)) {
2324 return V_0280A0_COLOR_24_8
;
2325 } else if (HAS_SIZE(24,8,0,0)) {
2326 return V_0280A0_COLOR_8_24
;
2330 if (HAS_SIZE(5,6,5,0)) {
2331 return V_0280A0_COLOR_5_6_5
;
2332 } else if (HAS_SIZE(32,8,24,0)) {
2333 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2337 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2338 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2339 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2340 switch (desc
->channel
[0].size
) {
2342 return V_0280A0_COLOR_4_4_4_4
;
2344 return V_0280A0_COLOR_8_8_8_8
;
2347 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2349 return V_0280A0_COLOR_16_16_16_16
;
2352 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2354 return V_0280A0_COLOR_32_32_32_32
;
2356 } else if (HAS_SIZE(5,5,5,1)) {
2357 return V_0280A0_COLOR_1_5_5_5
;
2358 } else if (HAS_SIZE(10,10,10,2)) {
2359 return V_0280A0_COLOR_2_10_10_10
;
2366 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
2368 if (R600_BIG_ENDIAN
) {
2369 switch(colorformat
) {
2370 /* 8-bit buffers. */
2371 case V_0280A0_COLOR_4_4
:
2372 case V_0280A0_COLOR_8
:
2375 /* 16-bit buffers. */
2376 case V_0280A0_COLOR_5_6_5
:
2377 case V_0280A0_COLOR_1_5_5_5
:
2378 case V_0280A0_COLOR_4_4_4_4
:
2379 case V_0280A0_COLOR_16
:
2380 case V_0280A0_COLOR_8_8
:
2381 return ENDIAN_8IN16
;
2383 /* 32-bit buffers. */
2384 case V_0280A0_COLOR_8_8_8_8
:
2385 case V_0280A0_COLOR_2_10_10_10
:
2386 case V_0280A0_COLOR_8_24
:
2387 case V_0280A0_COLOR_24_8
:
2388 case V_0280A0_COLOR_32_FLOAT
:
2389 case V_0280A0_COLOR_16_16_FLOAT
:
2390 case V_0280A0_COLOR_16_16
:
2391 return ENDIAN_8IN32
;
2393 /* 64-bit buffers. */
2394 case V_0280A0_COLOR_16_16_16_16
:
2395 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2396 return ENDIAN_8IN16
;
2398 case V_0280A0_COLOR_32_32_FLOAT
:
2399 case V_0280A0_COLOR_32_32
:
2400 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2401 return ENDIAN_8IN32
;
2403 /* 128-bit buffers. */
2404 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2405 case V_0280A0_COLOR_32_32_32_32
:
2406 return ENDIAN_8IN32
;
2408 return ENDIAN_NONE
; /* Unsupported. */
2415 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2417 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2418 struct r600_resource
*rbuffer
= r600_resource(buf
);
2419 unsigned i
, shader
, mask
, alignment
= rbuffer
->buf
->alignment
;
2420 struct r600_pipe_sampler_view
*view
;
2422 /* Reallocate the buffer in the same pipe_resource. */
2423 r600_init_resource(&rctx
->screen
->b
, rbuffer
, rbuffer
->b
.b
.width0
,
2426 /* We changed the buffer, now we need to bind it where the old one was bound. */
2427 /* Vertex buffers. */
2428 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2430 i
= u_bit_scan(&mask
);
2431 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2432 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2433 r600_vertex_buffers_dirty(rctx
);
2436 /* Streamout buffers. */
2437 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2438 if (rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2439 if (rctx
->b
.streamout
.begin_emitted
) {
2440 r600_emit_streamout_end(&rctx
->b
);
2442 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2443 r600_streamout_buffers_dirty(&rctx
->b
);
2447 /* Constant buffers. */
2448 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2449 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2451 uint32_t mask
= state
->enabled_mask
;
2454 unsigned i
= u_bit_scan(&mask
);
2455 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2457 state
->dirty_mask
|= 1 << i
;
2461 r600_constant_buffers_dirty(rctx
, state
);
2465 /* Texture buffer objects - update the virtual addresses in descriptors. */
2466 LIST_FOR_EACH_ENTRY(view
, &rctx
->b
.texture_buffers
, list
) {
2467 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2468 unsigned stride
= util_format_get_blocksize(view
->base
.format
);
2469 uint64_t offset
= (uint64_t)view
->base
.u
.buf
.first_element
* stride
;
2470 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2472 view
->tex_resource_words
[0] = va
;
2473 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2474 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2477 /* Texture buffer objects - make bindings dirty if needed. */
2478 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2479 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2481 uint32_t mask
= state
->enabled_mask
;
2484 unsigned i
= u_bit_scan(&mask
);
2485 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2487 state
->dirty_mask
|= 1 << i
;
2491 r600_sampler_views_dirty(rctx
, state
);
2496 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2498 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2500 if (rctx
->db_misc_state
.occlusion_query_enabled
!= enable
) {
2501 rctx
->db_misc_state
.occlusion_query_enabled
= enable
;
2502 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2506 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2507 bool include_draw_vbo
)
2509 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2512 /* keep this at the end of this file, please */
2513 void r600_init_common_state_functions(struct r600_context
*rctx
)
2515 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2516 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2517 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2518 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2519 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2520 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2521 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2522 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2523 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2524 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2525 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2526 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2527 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2528 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2529 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2530 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2531 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2532 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2533 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2534 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2535 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2536 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2537 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2538 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2539 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2540 rctx
->b
.b
.set_viewport_states
= r600_set_viewport_states
;
2541 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2542 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2543 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2544 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2545 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2546 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2547 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2548 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2549 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2550 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;
2553 void r600_trace_emit(struct r600_context
*rctx
)
2555 struct r600_screen
*rscreen
= rctx
->screen
;
2556 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2560 va
= rscreen
->b
.trace_bo
->gpu_address
;
2561 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rscreen
->b
.trace_bo
,
2562 RADEON_USAGE_READWRITE
, RADEON_PRIO_MIN
);
2563 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
2564 radeon_emit(cs
, va
& 0xFFFFFFFFUL
);
2565 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
);
2566 radeon_emit(cs
, cs
->cdw
);
2567 radeon_emit(cs
, rscreen
->b
.cs_count
);
2568 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2569 radeon_emit(cs
, reloc
);