projects / mesa.git / blob
? search:


b5241a72e7341c097a57443f733f3d76102198e2
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
36 {
37 struct radeon_winsys_cs *cs = rctx->cs;
38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
39
40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
42 cs->cdw += cb->atom.num_dw;
43 }
44
45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
46 {
47 cb->atom.emit = r600_emit_command_buffer;
48 cb->atom.num_dw = 0;
49 cb->atom.flags = flags;
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
60 {
61 struct radeon_winsys_cs *cs = rctx->cs;
62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
63
64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
69
70 a->flush_flags = 0;
71 }
72
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 struct radeon_winsys_cs *cs = rctx->cs;
76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
78 }
79
80 void r600_init_atom(struct r600_atom *atom,
81 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
82 unsigned num_dw, enum r600_atom_flags flags)
83 {
84 atom->emit = emit;
85 atom->num_dw = num_dw;
86 atom->flags = flags;
87 }
88
89 void r600_init_common_atoms(struct r600_context *rctx)
90 {
91 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
92 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
93 }
94
95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
96 {
97 unsigned flags = 0;
98
99 if (rctx->framebuffer.nr_cbufs) {
100 flags |= S_0085F0_CB_ACTION_ENA(1) |
101 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
102 }
103
104 /* Workaround for broken flushing on some R6xx chipsets. */
105 if (rctx->family == CHIP_RV670 ||
106 rctx->family == CHIP_RS780 ||
107 rctx->family == CHIP_RS880) {
108 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
109 S_0085F0_DEST_BASE_0_ENA(1);
110 }
111 return flags;
112 }
113
114 void r600_texture_barrier(struct pipe_context *ctx)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117
118 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
119 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
120 }
121
122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
123 {
124 static const int prim_conv[] = {
125 V_008958_DI_PT_POINTLIST,
126 V_008958_DI_PT_LINELIST,
127 V_008958_DI_PT_LINELOOP,
128 V_008958_DI_PT_LINESTRIP,
129 V_008958_DI_PT_TRILIST,
130 V_008958_DI_PT_TRISTRIP,
131 V_008958_DI_PT_TRIFAN,
132 V_008958_DI_PT_QUADLIST,
133 V_008958_DI_PT_QUADSTRIP,
134 V_008958_DI_PT_POLYGON,
135 -1,
136 -1,
137 -1,
138 -1
139 };
140
141 *prim = prim_conv[pprim];
142 if (*prim == -1) {
143 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
144 return false;
145 }
146 return true;
147 }
148
149 /* common state between evergreen and r600 */
150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
151 {
152 struct r600_context *rctx = (struct r600_context *)ctx;
153 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
154 struct r600_pipe_state *rstate;
155
156 if (state == NULL)
157 return;
158 rstate = &blend->rstate;
159 rctx->states[rstate->id] = rstate;
160 rctx->cb_target_mask = blend->cb_target_mask;
161 /* Replace every bit except MULTIWRITE_ENABLE. */
162 rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
163 rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
164 rctx->dual_src_blend = blend->dual_src_blend;
165 r600_context_pipe_state_set(rctx, rstate);
166 }
167
168 void r600_set_blend_color(struct pipe_context *ctx,
169 const struct pipe_blend_color *state)
170 {
171 struct r600_context *rctx = (struct r600_context *)ctx;
172 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
173
174 if (rstate == NULL)
175 return;
176
177 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
178 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
179 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
180 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
181 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
182
183 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
184 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
185 r600_context_pipe_state_set(rctx, rstate);
186 }
187
188 static void r600_set_stencil_ref(struct pipe_context *ctx,
189 const struct r600_stencil_ref *state)
190 {
191 struct r600_context *rctx = (struct r600_context *)ctx;
192 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
193
194 if (rstate == NULL)
195 return;
196
197 rstate->id = R600_PIPE_STATE_STENCIL_REF;
198 r600_pipe_state_add_reg(rstate,
199 R_028430_DB_STENCILREFMASK,
200 S_028430_STENCILREF(state->ref_value[0]) |
201 S_028430_STENCILMASK(state->valuemask[0]) |
202 S_028430_STENCILWRITEMASK(state->writemask[0]));
203 r600_pipe_state_add_reg(rstate,
204 R_028434_DB_STENCILREFMASK_BF,
205 S_028434_STENCILREF_BF(state->ref_value[1]) |
206 S_028434_STENCILMASK_BF(state->valuemask[1]) |
207 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
208
209 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
210 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
211 r600_context_pipe_state_set(rctx, rstate);
212 }
213
214 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
215 const struct pipe_stencil_ref *state)
216 {
217 struct r600_context *rctx = (struct r600_context *)ctx;
218 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
219 struct r600_stencil_ref ref;
220
221 rctx->stencil_ref = *state;
222
223 if (!dsa)
224 return;
225
226 ref.ref_value[0] = state->ref_value[0];
227 ref.ref_value[1] = state->ref_value[1];
228 ref.valuemask[0] = dsa->valuemask[0];
229 ref.valuemask[1] = dsa->valuemask[1];
230 ref.writemask[0] = dsa->writemask[0];
231 ref.writemask[1] = dsa->writemask[1];
232
233 r600_set_stencil_ref(ctx, &ref);
234 }
235
236 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
237 {
238 struct r600_context *rctx = (struct r600_context *)ctx;
239 struct r600_pipe_dsa *dsa = state;
240 struct r600_pipe_state *rstate;
241 struct r600_stencil_ref ref;
242
243 if (state == NULL)
244 return;
245 rstate = &dsa->rstate;
246 rctx->states[rstate->id] = rstate;
247 rctx->sx_alpha_test_control &= ~0xff;
248 rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
249 rctx->alpha_ref = dsa->alpha_ref;
250 rctx->alpha_ref_dirty = true;
251 r600_context_pipe_state_set(rctx, rstate);
252
253 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
254 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
255 ref.valuemask[0] = dsa->valuemask[0];
256 ref.valuemask[1] = dsa->valuemask[1];
257 ref.writemask[0] = dsa->writemask[0];
258 ref.writemask[1] = dsa->writemask[1];
259
260 r600_set_stencil_ref(ctx, &ref);
261
262 if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
263 rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
264 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
265 }
266 }
267
268 void r600_set_max_scissor(struct r600_context *rctx)
269 {
270 /* Set a scissor state such that it doesn't do anything. */
271 struct pipe_scissor_state scissor;
272 scissor.minx = 0;
273 scissor.miny = 0;
274 scissor.maxx = 8192;
275 scissor.maxy = 8192;
276
277 r600_set_scissor_state(rctx, &scissor);
278 }
279
280 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
281 {
282 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
283 struct r600_context *rctx = (struct r600_context *)ctx;
284
285 if (state == NULL)
286 return;
287
288 rctx->sprite_coord_enable = rs->sprite_coord_enable;
289 rctx->two_side = rs->two_side;
290 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
291 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
292
293 rctx->rasterizer = rs;
294
295 rctx->states[rs->rstate.id] = &rs->rstate;
296 r600_context_pipe_state_set(rctx, &rs->rstate);
297
298 if (rctx->chip_class >= EVERGREEN) {
299 evergreen_polygon_offset_update(rctx);
300 } else {
301 r600_polygon_offset_update(rctx);
302 }
303
304 /* Workaround for a missing scissor enable on r600. */
305 if (rctx->chip_class == R600) {
306 if (rs->scissor_enable != rctx->scissor_enable) {
307 rctx->scissor_enable = rs->scissor_enable;
308
309 if (rs->scissor_enable) {
310 r600_set_scissor_state(rctx, &rctx->scissor_state);
311 } else {
312 r600_set_max_scissor(rctx);
313 }
314 }
315 }
316 }
317
318 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
319 {
320 struct r600_context *rctx = (struct r600_context *)ctx;
321 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
322
323 if (rctx->rasterizer == rs) {
324 rctx->rasterizer = NULL;
325 }
326 if (rctx->states[rs->rstate.id] == &rs->rstate) {
327 rctx->states[rs->rstate.id] = NULL;
328 }
329 free(rs);
330 }
331
332 void r600_sampler_view_destroy(struct pipe_context *ctx,
333 struct pipe_sampler_view *state)
334 {
335 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
336
337 pipe_resource_reference(&state->texture, NULL);
338 FREE(resource);
339 }
340
341 void r600_delete_state(struct pipe_context *ctx, void *state)
342 {
343 struct r600_context *rctx = (struct r600_context *)ctx;
344 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
345
346 if (rctx->states[rstate->id] == rstate) {
347 rctx->states[rstate->id] = NULL;
348 }
349 for (int i = 0; i < rstate->nregs; i++) {
350 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
351 }
352 free(rstate);
353 }
354
355 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
356 {
357 struct r600_context *rctx = (struct r600_context *)ctx;
358 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
359
360 rctx->vertex_elements = v;
361 if (v) {
362 r600_inval_shader_cache(rctx);
363
364 rctx->states[v->rstate.id] = &v->rstate;
365 r600_context_pipe_state_set(rctx, &v->rstate);
366 }
367 }
368
369 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
370 {
371 struct r600_context *rctx = (struct r600_context *)ctx;
372 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
373
374 if (rctx->states[v->rstate.id] == &v->rstate) {
375 rctx->states[v->rstate.id] = NULL;
376 }
377 if (rctx->vertex_elements == state)
378 rctx->vertex_elements = NULL;
379
380 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
381 FREE(state);
382 }
383
384 void r600_set_index_buffer(struct pipe_context *ctx,
385 const struct pipe_index_buffer *ib)
386 {
387 struct r600_context *rctx = (struct r600_context *)ctx;
388
389 if (ib) {
390 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
391 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
392 } else {
393 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
394 }
395 }
396
397 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
398 const struct pipe_vertex_buffer *buffers)
399 {
400 struct r600_context *rctx = (struct r600_context *)ctx;
401
402 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
403
404 r600_inval_vertex_cache(rctx);
405 rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
406 rctx->nr_vertex_buffers;
407 r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
408 }
409
410 void *r600_create_vertex_elements(struct pipe_context *ctx,
411 unsigned count,
412 const struct pipe_vertex_element *elements)
413 {
414 struct r600_context *rctx = (struct r600_context *)ctx;
415 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
416
417 assert(count < 32);
418 if (!v)
419 return NULL;
420
421 v->count = count;
422 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
423
424 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
425 FREE(v);
426 return NULL;
427 }
428
429 return v;
430 }
431
432 /* Compute the key for the hw shader variant */
433 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
434 struct r600_pipe_shader_selector * sel)
435 {
436 struct r600_context *rctx = (struct r600_context *)ctx;
437 unsigned key;
438
439 if (sel->type == PIPE_SHADER_FRAGMENT) {
440 key = rctx->two_side |
441 MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 1;
442 } else
443 key = 0;
444
445 return key;
446 }
447
448 /* Select the hw shader variant depending on the current state.
449 * (*dirty) is set to 1 if current variant was changed */
450 static int r600_shader_select(struct pipe_context *ctx,
451 struct r600_pipe_shader_selector* sel,
452 unsigned *dirty)
453 {
454 unsigned key;
455 struct r600_context *rctx = (struct r600_context *)ctx;
456 struct r600_pipe_shader * shader = NULL;
457 int r;
458
459 key = r600_shader_selector_key(ctx, sel);
460
461 /* Check if we don't need to change anything.
462 * This path is also used for most shaders that don't need multiple
463 * variants, it will cost just a computation of the key and this
464 * test. */
465 if (likely(sel->current && sel->current->key == key)) {
466 return 0;
467 }
468
469 /* lookup if we have other variants in the list */
470 if (sel->num_shaders > 1) {
471 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
472
473 while (c && c->key != key) {
474 p = c;
475 c = c->next_variant;
476 }
477
478 if (c) {
479 p->next_variant = c->next_variant;
480 shader = c;
481 }
482 }
483
484 if (unlikely(!shader)) {
485 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
486 shader->selector = sel;
487
488 r = r600_pipe_shader_create(ctx, shader);
489 if (unlikely(r)) {
490 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
491 sel->type, key, r);
492 sel->current = NULL;
493 return r;
494 }
495
496 /* We don't know the value of nr_ps_max_color_exports until we built
497 * at least one variant, so we may need to recompute the key after
498 * building first variant. */
499 if (sel->type == PIPE_SHADER_FRAGMENT &&
500 sel->num_shaders == 0) {
501 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
502 key = r600_shader_selector_key(ctx, sel);
503 }
504
505 shader->key = key;
506 sel->num_shaders++;
507 }
508
509 if (dirty)
510 *dirty = 1;
511
512 shader->next_variant = sel->current;
513 sel->current = shader;
514
515 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
516 r600_adjust_gprs(rctx);
517 }
518
519 return 0;
520 }
521
522 static void *r600_create_shader_state(struct pipe_context *ctx,
523 const struct pipe_shader_state *state,
524 unsigned pipe_shader_type)
525 {
526 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
527 int r;
528
529 sel->type = pipe_shader_type;
530 sel->tokens = tgsi_dup_tokens(state->tokens);
531 sel->so = state->stream_output;
532
533 r = r600_shader_select(ctx, sel, NULL);
534 if (r)
535 return NULL;
536
537 return sel;
538 }
539
540 void *r600_create_shader_state_ps(struct pipe_context *ctx,
541 const struct pipe_shader_state *state)
542 {
543 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
544 }
545
546 void *r600_create_shader_state_vs(struct pipe_context *ctx,
547 const struct pipe_shader_state *state)
548 {
549 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
550 }
551
552 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
553 {
554 struct r600_context *rctx = (struct r600_context *)ctx;
555
556 if (!state)
557 state = rctx->dummy_pixel_shader;
558
559 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
560 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
561
562
563 if (rctx->chip_class < EVERGREEN && rctx->vs_shader) {
564 r600_adjust_gprs(rctx);
565 }
566 }
567
568 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
569 {
570 struct r600_context *rctx = (struct r600_context *)ctx;
571
572 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
573 if (state) {
574 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
575
576 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
577 r600_adjust_gprs(rctx);
578 }
579 }
580
581 static void r600_delete_shader_selector(struct pipe_context *ctx,
582 struct r600_pipe_shader_selector *sel)
583 {
584 struct r600_pipe_shader *p = sel->current, *c;
585 while (p) {
586 c = p->next_variant;
587 r600_pipe_shader_destroy(ctx, p);
588 free(p);
589 p = c;
590 }
591
592 free(sel->tokens);
593 free(sel);
594 }
595
596
597 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
598 {
599 struct r600_context *rctx = (struct r600_context *)ctx;
600 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
601
602 if (rctx->ps_shader == sel) {
603 rctx->ps_shader = NULL;
604 }
605
606 r600_delete_shader_selector(ctx, sel);
607 }
608
609 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
610 {
611 struct r600_context *rctx = (struct r600_context *)ctx;
612 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
613
614 if (rctx->vs_shader == sel) {
615 rctx->vs_shader = NULL;
616 }
617
618 r600_delete_shader_selector(ctx, sel);
619 }
620
621 static void r600_update_alpha_ref(struct r600_context *rctx)
622 {
623 unsigned alpha_ref;
624 struct r600_pipe_state rstate;
625
626 alpha_ref = rctx->alpha_ref;
627 rstate.nregs = 0;
628 if (rctx->export_16bpc && rctx->chip_class >= EVERGREEN) {
629 alpha_ref &= ~0x1FFF;
630 }
631 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
632
633 r600_context_pipe_state_set(rctx, &rstate);
634 rctx->alpha_ref_dirty = false;
635 }
636
637 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
638 {
639 r600_inval_shader_cache(rctx);
640 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
641 : util_bitcount(state->dirty_mask)*19;
642 r600_atom_dirty(rctx, &state->atom);
643 }
644
645 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
646 struct pipe_constant_buffer *input)
647 {
648 struct r600_context *rctx = (struct r600_context *)ctx;
649 struct r600_constbuf_state *state;
650 struct pipe_constant_buffer *cb;
651 const uint8_t *ptr;
652
653 switch (shader) {
654 case PIPE_SHADER_VERTEX:
655 state = &rctx->vs_constbuf_state;
656 break;
657 case PIPE_SHADER_FRAGMENT:
658 state = &rctx->ps_constbuf_state;
659 break;
660 default:
661 return;
662 }
663
664 /* Note that the state tracker can unbind constant buffers by
665 * passing NULL here.
666 */
667 if (unlikely(!input)) {
668 state->enabled_mask &= ~(1 << index);
669 state->dirty_mask &= ~(1 << index);
670 pipe_resource_reference(&state->cb[index].buffer, NULL);
671 return;
672 }
673
674 cb = &state->cb[index];
675 cb->buffer_size = input->buffer_size;
676
677 ptr = input->user_buffer;
678
679 if (ptr) {
680 /* Upload the user buffer. */
681 if (R600_BIG_ENDIAN) {
682 uint32_t *tmpPtr;
683 unsigned i, size = input->buffer_size;
684
685 if (!(tmpPtr = malloc(size))) {
686 R600_ERR("Failed to allocate BE swap buffer.\n");
687 return;
688 }
689
690 for (i = 0; i < size / 4; ++i) {
691 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
692 }
693
694 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
695 free(tmpPtr);
696 } else {
697 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
698 }
699 } else {
700 /* Setup the hw buffer. */
701 cb->buffer_offset = input->buffer_offset;
702 pipe_resource_reference(&cb->buffer, input->buffer);
703 }
704
705 state->enabled_mask |= 1 << index;
706 state->dirty_mask |= 1 << index;
707 r600_constant_buffers_dirty(rctx, state);
708 }
709
710 struct pipe_stream_output_target *
711 r600_create_so_target(struct pipe_context *ctx,
712 struct pipe_resource *buffer,
713 unsigned buffer_offset,
714 unsigned buffer_size)
715 {
716 struct r600_context *rctx = (struct r600_context *)ctx;
717 struct r600_so_target *t;
718 void *ptr;
719
720 t = CALLOC_STRUCT(r600_so_target);
721 if (!t) {
722 return NULL;
723 }
724
725 t->b.reference.count = 1;
726 t->b.context = ctx;
727 pipe_resource_reference(&t->b.buffer, buffer);
728 t->b.buffer_offset = buffer_offset;
729 t->b.buffer_size = buffer_size;
730
731 t->filled_size = (struct r600_resource*)
732 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
733 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
734 memset(ptr, 0, t->filled_size->buf->size);
735 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
736
737 return &t->b;
738 }
739
740 void r600_so_target_destroy(struct pipe_context *ctx,
741 struct pipe_stream_output_target *target)
742 {
743 struct r600_so_target *t = (struct r600_so_target*)target;
744 pipe_resource_reference(&t->b.buffer, NULL);
745 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
746 FREE(t);
747 }
748
749 void r600_set_so_targets(struct pipe_context *ctx,
750 unsigned num_targets,
751 struct pipe_stream_output_target **targets,
752 unsigned append_bitmask)
753 {
754 struct r600_context *rctx = (struct r600_context *)ctx;
755 unsigned i;
756
757 /* Stop streamout. */
758 if (rctx->num_so_targets && !rctx->streamout_start) {
759 r600_context_streamout_end(rctx);
760 }
761
762 /* Set the new targets. */
763 for (i = 0; i < num_targets; i++) {
764 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
765 }
766 for (; i < rctx->num_so_targets; i++) {
767 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
768 }
769
770 rctx->num_so_targets = num_targets;
771 rctx->streamout_start = num_targets != 0;
772 rctx->streamout_append_bitmask = append_bitmask;
773 }
774
775 static void r600_update_derived_state(struct r600_context *rctx)
776 {
777 struct pipe_context * ctx = (struct pipe_context*)rctx;
778 unsigned ps_dirty = 0;
779
780 if (!rctx->blitter->running) {
781 if (rctx->have_depth_fb || rctx->have_depth_texture)
782 r600_flush_depth_textures(rctx);
783 }
784
785 if (rctx->chip_class < EVERGREEN) {
786 r600_update_sampler_states(rctx);
787 }
788
789 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
790
791 if (rctx->alpha_ref_dirty) {
792 r600_update_alpha_ref(rctx);
793 }
794
795 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
796 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
797 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
798
799 if (rctx->chip_class >= EVERGREEN)
800 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
801 else
802 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
803
804 ps_dirty = 1;
805 }
806
807 if (ps_dirty)
808 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
809
810 if (rctx->chip_class >= EVERGREEN) {
811 evergreen_update_dual_export_state(rctx);
812 } else {
813 r600_update_dual_export_state(rctx);
814 }
815
816 if (rctx->dual_src_blend) {
817 rctx->cb_shader_mask = rctx->ps_shader->current->ps_cb_shader_mask | rctx->fb_cb_shader_mask;
818 } else {
819 rctx->cb_shader_mask = rctx->fb_cb_shader_mask;
820 }
821 }
822
823 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
824 {
825 static const int prim_conv[] = {
826 V_028A6C_OUTPRIM_TYPE_POINTLIST,
827 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
828 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
829 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
830 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
831 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
832 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
833 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
834 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
835 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
836 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
837 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
838 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
839 V_028A6C_OUTPRIM_TYPE_TRISTRIP
840 };
841 assert(mode < Elements(prim_conv));
842
843 return prim_conv[mode];
844 }
845
846 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
847 {
848 struct r600_context *rctx = (struct r600_context *)ctx;
849 struct pipe_draw_info info = *dinfo;
850 struct pipe_index_buffer ib = {};
851 unsigned prim, mask, ls_mask = 0;
852 struct r600_block *dirty_block = NULL, *next_block = NULL;
853 struct r600_atom *state = NULL, *next_state = NULL;
854 struct radeon_winsys_cs *cs = rctx->cs;
855 uint64_t va;
856 uint8_t *ptr;
857
858 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
859 !r600_conv_pipe_prim(info.mode, &prim)) {
860 assert(0);
861 return;
862 }
863
864 if (!rctx->vs_shader) {
865 assert(0);
866 return;
867 }
868
869 r600_update_derived_state(rctx);
870
871 if (info.indexed) {
872 /* Initialize the index buffer struct. */
873 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
874 ib.user_buffer = rctx->index_buffer.user_buffer;
875 ib.index_size = rctx->index_buffer.index_size;
876 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
877
878 /* Translate or upload, if needed. */
879 r600_translate_index_buffer(rctx, &ib, info.count);
880
881 ptr = (uint8_t*)ib.user_buffer;
882 if (!ib.buffer && ptr) {
883 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
884 ptr, &ib.offset, &ib.buffer);
885 }
886 } else {
887 info.index_bias = info.start;
888 if (info.count_from_stream_output) {
889 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
890 }
891 }
892
893 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
894
895 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
896 rctx->vgt.id = R600_PIPE_STATE_VGT;
897 rctx->vgt.nregs = 0;
898 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
899 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
900 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask);
901 r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0);
902 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
903 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
904 r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
905 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
906 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
907 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
908 if (rctx->chip_class <= R700) {
909 unsigned multi_write = !!rctx->ps_shader->current->shader.fs_write_all &&
910 (rctx->nr_cbufs > 1);
911 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
912 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(multi_write);
913 r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
914 }
915 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
916 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
917 }
918
919 rctx->vgt.nregs = 0;
920 r600_pipe_state_mod_reg(&rctx->vgt, prim);
921 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
922 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
923 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
924 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
925 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
926 r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
927 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
928 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
929
930 if (prim == V_008958_DI_PT_LINELIST)
931 ls_mask = 1;
932 else if (prim == V_008958_DI_PT_LINESTRIP)
933 ls_mask = 2;
934 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
935 if (rctx->chip_class <= R700) {
936 unsigned multi_write = !!rctx->ps_shader->current->shader.fs_write_all &&
937 (rctx->nr_cbufs > 1);
938 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
939 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(multi_write);
940 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
941 }
942 r600_pipe_state_mod_reg(&rctx->vgt,
943 rctx->vs_shader->current->pa_cl_vs_out_cntl |
944 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
945 r600_pipe_state_mod_reg(&rctx->vgt,
946 rctx->pa_cl_clip_cntl |
947 (rctx->vs_shader->current->shader.clip_dist_write ||
948 rctx->vs_shader->current->shader.vs_prohibit_ucps ?
949 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
950
951 r600_context_pipe_state_set(rctx, &rctx->vgt);
952
953 /* Emit states (the function expects that we emit at most 17 dwords here). */
954 r600_need_cs_space(rctx, 0, TRUE);
955
956 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
957 r600_emit_atom(rctx, state);
958 }
959 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
960 r600_context_block_emit_dirty(rctx, dirty_block);
961 }
962 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
963 r600_context_block_resource_emit_dirty(rctx, dirty_block);
964 }
965 rctx->pm4_dirty_cdwords = 0;
966
967 /* Enable stream out if needed. */
968 if (rctx->streamout_start) {
969 r600_context_streamout_begin(rctx);
970 rctx->streamout_start = FALSE;
971 }
972
973 /* draw packet */
974 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
975 cs->buf[cs->cdw++] = ib.index_size == 4 ?
976 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
977 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
978 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
979 cs->buf[cs->cdw++] = info.instance_count;
980 if (info.indexed) {
981 va = r600_resource_va(ctx->screen, ib.buffer);
982 va += ib.offset;
983 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
984 cs->buf[cs->cdw++] = va;
985 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
986 cs->buf[cs->cdw++] = info.count;
987 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
988 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
989 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
990 } else {
991 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
992 cs->buf[cs->cdw++] = info.count;
993 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
994 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
995 }
996
997 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
998
999 if (rctx->framebuffer.zsbuf)
1000 {
1001 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
1002 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
1003 }
1004
1005 pipe_resource_reference(&ib.buffer, NULL);
1006 }
1007
1008 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1009 struct r600_pipe_state *state,
1010 uint32_t offset, uint32_t value,
1011 uint32_t range_id, uint32_t block_id,
1012 struct r600_resource *bo,
1013 enum radeon_bo_usage usage)
1014
1015 {
1016 struct r600_range *range;
1017 struct r600_block *block;
1018
1019 if (bo) assert(usage);
1020
1021 range = &ctx->range[range_id];
1022 block = range->blocks[block_id];
1023 state->regs[state->nregs].block = block;
1024 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1025
1026 state->regs[state->nregs].value = value;
1027 state->regs[state->nregs].bo = bo;
1028 state->regs[state->nregs].bo_usage = usage;
1029
1030 state->nregs++;
1031 assert(state->nregs < R600_BLOCK_MAX_REG);
1032 }
1033
1034 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1035 struct r600_pipe_state *state,
1036 uint32_t offset, uint32_t value,
1037 uint32_t range_id, uint32_t block_id)
1038 {
1039 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1040 range_id, block_id, NULL, 0);
1041 }
1042
1043 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
1044 uint32_t offset, uint32_t value,
1045 struct r600_resource *bo,
1046 enum radeon_bo_usage usage)
1047 {
1048 if (bo) assert(usage);
1049
1050 state->regs[state->nregs].id = offset;
1051 state->regs[state->nregs].block = NULL;
1052 state->regs[state->nregs].value = value;
1053 state->regs[state->nregs].bo = bo;
1054 state->regs[state->nregs].bo_usage = usage;
1055
1056 state->nregs++;
1057 assert(state->nregs < R600_BLOCK_MAX_REG);
1058 }
1059
1060 uint32_t r600_translate_stencil_op(int s_op)
1061 {
1062 switch (s_op) {
1063 case PIPE_STENCIL_OP_KEEP:
1064 return V_028800_STENCIL_KEEP;
1065 case PIPE_STENCIL_OP_ZERO:
1066 return V_028800_STENCIL_ZERO;
1067 case PIPE_STENCIL_OP_REPLACE:
1068 return V_028800_STENCIL_REPLACE;
1069 case PIPE_STENCIL_OP_INCR:
1070 return V_028800_STENCIL_INCR;
1071 case PIPE_STENCIL_OP_DECR:
1072 return V_028800_STENCIL_DECR;
1073 case PIPE_STENCIL_OP_INCR_WRAP:
1074 return V_028800_STENCIL_INCR_WRAP;
1075 case PIPE_STENCIL_OP_DECR_WRAP:
1076 return V_028800_STENCIL_DECR_WRAP;
1077 case PIPE_STENCIL_OP_INVERT:
1078 return V_028800_STENCIL_INVERT;
1079 default:
1080 R600_ERR("Unknown stencil op %d", s_op);
1081 assert(0);
1082 break;
1083 }
1084 return 0;
1085 }
1086
1087 uint32_t r600_translate_fill(uint32_t func)
1088 {
1089 switch(func) {
1090 case PIPE_POLYGON_MODE_FILL:
1091 return 2;
1092 case PIPE_POLYGON_MODE_LINE:
1093 return 1;
1094 case PIPE_POLYGON_MODE_POINT:
1095 return 0;
1096 default:
1097 assert(0);
1098 return 0;
1099 }
1100 }
1101
1102 unsigned r600_tex_wrap(unsigned wrap)
1103 {
1104 switch (wrap) {
1105 default:
1106 case PIPE_TEX_WRAP_REPEAT:
1107 return V_03C000_SQ_TEX_WRAP;
1108 case PIPE_TEX_WRAP_CLAMP:
1109 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1110 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1111 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1112 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1113 return V_03C000_SQ_TEX_CLAMP_BORDER;
1114 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1115 return V_03C000_SQ_TEX_MIRROR;
1116 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1117 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1118 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1119 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1120 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1121 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1122 }
1123 }
1124
1125 unsigned r600_tex_filter(unsigned filter)
1126 {
1127 switch (filter) {
1128 default:
1129 case PIPE_TEX_FILTER_NEAREST:
1130 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1131 case PIPE_TEX_FILTER_LINEAR:
1132 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1133 }
1134 }
1135
1136 unsigned r600_tex_mipfilter(unsigned filter)
1137 {
1138 switch (filter) {
1139 case PIPE_TEX_MIPFILTER_NEAREST:
1140 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1141 case PIPE_TEX_MIPFILTER_LINEAR:
1142 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1143 default:
1144 case PIPE_TEX_MIPFILTER_NONE:
1145 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1146 }
1147 }
1148
1149 unsigned r600_tex_compare(unsigned compare)
1150 {
1151 switch (compare) {
1152 default:
1153 case PIPE_FUNC_NEVER:
1154 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1155 case PIPE_FUNC_LESS:
1156 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1157 case PIPE_FUNC_EQUAL:
1158 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1159 case PIPE_FUNC_LEQUAL:
1160 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1161 case PIPE_FUNC_GREATER:
1162 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1163 case PIPE_FUNC_NOTEQUAL:
1164 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1165 case PIPE_FUNC_GEQUAL:
1166 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1167 case PIPE_FUNC_ALWAYS:
1168 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1169 }
1170 }