2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "tgsi/tgsi_parse.h"
38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
42 cb
->buf
= CALLOC(1, 4 * num_dw
);
43 cb
->max_num_dw
= num_dw
;
46 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
51 void r600_init_atom(struct r600_context
*rctx
,
52 struct r600_atom
*atom
,
54 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
57 assert(id
< R600_NUM_ATOMS
);
58 assert(rctx
->atoms
[id
] == NULL
);
59 rctx
->atoms
[id
] = atom
;
62 atom
->num_dw
= num_dw
;
66 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
68 r600_emit_command_buffer(rctx
->rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
71 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
73 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
74 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
75 unsigned alpha_ref
= a
->sx_alpha_ref
;
77 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
81 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
82 a
->sx_alpha_test_control
|
83 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
84 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
87 static void r600_texture_barrier(struct pipe_context
*ctx
)
89 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
91 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
92 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
93 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
96 static unsigned r600_conv_pipe_prim(unsigned prim
)
98 static const unsigned prim_conv
[] = {
99 V_008958_DI_PT_POINTLIST
,
100 V_008958_DI_PT_LINELIST
,
101 V_008958_DI_PT_LINELOOP
,
102 V_008958_DI_PT_LINESTRIP
,
103 V_008958_DI_PT_TRILIST
,
104 V_008958_DI_PT_TRISTRIP
,
105 V_008958_DI_PT_TRIFAN
,
106 V_008958_DI_PT_QUADLIST
,
107 V_008958_DI_PT_QUADSTRIP
,
108 V_008958_DI_PT_POLYGON
,
109 V_008958_DI_PT_LINELIST_ADJ
,
110 V_008958_DI_PT_LINESTRIP_ADJ
,
111 V_008958_DI_PT_TRILIST_ADJ
,
112 V_008958_DI_PT_TRISTRIP_ADJ
,
113 V_008958_DI_PT_RECTLIST
115 return prim_conv
[prim
];
118 /* common state between evergreen and r600 */
120 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
121 struct r600_blend_state
*blend
, bool blend_disable
)
123 unsigned color_control
;
124 bool update_cb
= false;
126 rctx
->alpha_to_one
= blend
->alpha_to_one
;
127 rctx
->dual_src_blend
= blend
->dual_src_blend
;
129 if (!blend_disable
) {
130 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
131 color_control
= blend
->cb_color_control
;
133 /* Blending is disabled. */
134 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
135 color_control
= blend
->cb_color_control_no_blend
;
138 /* Update derived states. */
139 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
140 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
143 if (rctx
->chip_class
<= R700
&&
144 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
145 rctx
->cb_misc_state
.cb_color_control
= color_control
;
148 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
149 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
153 rctx
->cb_misc_state
.atom
.dirty
= true;
157 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
159 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
160 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
165 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
168 static void r600_set_blend_color(struct pipe_context
*ctx
,
169 const struct pipe_blend_color
*state
)
171 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
173 rctx
->blend_color
.state
= *state
;
174 rctx
->blend_color
.atom
.dirty
= true;
177 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
179 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
180 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
182 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
183 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
184 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
185 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
186 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
189 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
191 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
192 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
194 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
195 r600_write_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, a
->vgt_multi_prim_ib_reset_indx
);
198 void r600_emit_vgt2_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
200 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
201 struct r600_vgt2_state
*a
= (struct r600_vgt2_state
*)atom
;
203 r600_write_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, a
->vgt_indx_offset
);
206 static void r600_set_clip_state(struct pipe_context
*ctx
,
207 const struct pipe_clip_state
*state
)
209 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
210 struct pipe_constant_buffer cb
;
212 rctx
->clip_state
.state
= *state
;
213 rctx
->clip_state
.atom
.dirty
= true;
216 cb
.user_buffer
= state
->ucp
;
217 cb
.buffer_offset
= 0;
218 cb
.buffer_size
= 4*4*8;
219 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
220 pipe_resource_reference(&cb
.buffer
, NULL
);
223 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
224 const struct r600_stencil_ref
*state
)
226 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
228 rctx
->stencil_ref
.state
= *state
;
229 rctx
->stencil_ref
.atom
.dirty
= true;
232 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
234 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
235 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
237 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
238 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
239 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
240 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
241 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
242 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
243 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
244 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
245 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
248 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
249 const struct pipe_stencil_ref
*state
)
251 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
252 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
253 struct r600_stencil_ref ref
;
255 rctx
->stencil_ref
.pipe_state
= *state
;
260 ref
.ref_value
[0] = state
->ref_value
[0];
261 ref
.ref_value
[1] = state
->ref_value
[1];
262 ref
.valuemask
[0] = dsa
->valuemask
[0];
263 ref
.valuemask
[1] = dsa
->valuemask
[1];
264 ref
.writemask
[0] = dsa
->writemask
[0];
265 ref
.writemask
[1] = dsa
->writemask
[1];
267 r600_set_stencil_ref(ctx
, &ref
);
270 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
272 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
273 struct r600_dsa_state
*dsa
= state
;
274 struct r600_stencil_ref ref
;
279 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
281 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
282 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
283 ref
.valuemask
[0] = dsa
->valuemask
[0];
284 ref
.valuemask
[1] = dsa
->valuemask
[1];
285 ref
.writemask
[0] = dsa
->writemask
[0];
286 ref
.writemask
[1] = dsa
->writemask
[1];
288 r600_set_stencil_ref(ctx
, &ref
);
290 /* Update alphatest state. */
291 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
292 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
293 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
294 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
295 rctx
->alphatest_state
.atom
.dirty
= true;
299 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
301 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
302 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
307 rctx
->rasterizer
= rs
;
309 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
311 if (rs
->offset_enable
&&
312 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
313 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
314 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
315 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
316 rctx
->poly_offset_state
.atom
.dirty
= true;
319 /* Update clip_misc_state. */
320 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
321 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
322 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
323 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
324 rctx
->clip_misc_state
.atom
.dirty
= true;
327 /* Workaround for a missing scissor enable on r600. */
328 if (rctx
->chip_class
== R600
&&
329 rs
->scissor_enable
!= rctx
->scissor
.enable
) {
330 rctx
->scissor
.enable
= rs
->scissor_enable
;
331 rctx
->scissor
.atom
.dirty
= true;
334 /* Re-emit PA_SC_LINE_STIPPLE. */
335 rctx
->last_primitive_type
= -1;
338 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
340 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
342 r600_release_command_buffer(&rs
->buffer
);
346 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
347 struct pipe_sampler_view
*state
)
349 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
351 pipe_resource_reference(&state
->texture
, NULL
);
355 void r600_sampler_states_dirty(struct r600_context
*rctx
,
356 struct r600_sampler_states
*state
)
358 if (state
->dirty_mask
) {
359 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
360 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
363 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
364 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
365 state
->atom
.dirty
= true;
369 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
372 unsigned count
, void **states
)
374 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
375 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
376 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
377 int seamless_cube_map
= -1;
379 /* This sets 1-bit for states with index >= count. */
380 uint32_t disable_mask
= ~((1ull << count
) - 1);
381 /* These are the new states set by this function. */
382 uint32_t new_mask
= 0;
384 assert(start
== 0); /* XXX fix below */
386 for (i
= 0; i
< count
; i
++) {
387 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
389 if (rstate
== dst
->states
.states
[i
]) {
394 if (rstate
->border_color_use
) {
395 dst
->states
.has_bordercolor_mask
|= 1 << i
;
397 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
399 seamless_cube_map
= rstate
->seamless_cube_map
;
403 disable_mask
|= 1 << i
;
407 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
408 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
410 dst
->states
.enabled_mask
&= ~disable_mask
;
411 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
412 dst
->states
.enabled_mask
|= new_mask
;
413 dst
->states
.dirty_mask
|= new_mask
;
414 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
416 r600_sampler_states_dirty(rctx
, &dst
->states
);
418 /* Seamless cubemap state. */
419 if (rctx
->chip_class
<= R700
&&
420 seamless_cube_map
!= -1 &&
421 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
422 /* change in TA_CNTL_AUX need a pipeline flush */
423 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
424 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
425 rctx
->seamless_cube_map
.atom
.dirty
= true;
429 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
431 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
434 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
436 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
439 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
444 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
446 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
448 r600_release_command_buffer(&blend
->buffer
);
449 r600_release_command_buffer(&blend
->buffer_no_blend
);
453 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
455 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
457 r600_release_command_buffer(&dsa
->buffer
);
461 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
463 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
465 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
468 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
470 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
471 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
475 static void r600_set_index_buffer(struct pipe_context
*ctx
,
476 const struct pipe_index_buffer
*ib
)
478 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
481 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
482 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
484 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
488 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
490 if (rctx
->vertex_buffer_state
.dirty_mask
) {
491 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
492 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
493 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
494 rctx
->vertex_buffer_state
.atom
.dirty
= true;
498 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
499 unsigned start_slot
, unsigned count
,
500 const struct pipe_vertex_buffer
*input
)
502 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
503 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
504 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
506 uint32_t disable_mask
= 0;
507 /* These are the new buffers set by this function. */
508 uint32_t new_buffer_mask
= 0;
510 /* Set vertex buffers. */
512 for (i
= 0; i
< count
; i
++) {
513 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
514 if (input
[i
].buffer
) {
515 vb
[i
].stride
= input
[i
].stride
;
516 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
517 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
518 new_buffer_mask
|= 1 << i
;
520 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
521 disable_mask
|= 1 << i
;
526 for (i
= 0; i
< count
; i
++) {
527 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
529 disable_mask
= ((1ull << count
) - 1);
532 disable_mask
<<= start_slot
;
533 new_buffer_mask
<<= start_slot
;
535 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
536 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
537 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
538 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
540 r600_vertex_buffers_dirty(rctx
);
543 void r600_sampler_views_dirty(struct r600_context
*rctx
,
544 struct r600_samplerview_state
*state
)
546 if (state
->dirty_mask
) {
547 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
548 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
549 util_bitcount(state
->dirty_mask
);
550 state
->atom
.dirty
= true;
554 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
555 unsigned start
, unsigned count
,
556 struct pipe_sampler_view
**views
)
558 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
559 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
560 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
561 uint32_t dirty_sampler_states_mask
= 0;
563 /* This sets 1-bit for textures with index >= count. */
564 uint32_t disable_mask
= ~((1ull << count
) - 1);
565 /* These are the new textures set by this function. */
566 uint32_t new_mask
= 0;
568 /* Set textures with index >= count to NULL. */
569 uint32_t remaining_mask
;
571 assert(start
== 0); /* XXX fix below */
573 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
575 while (remaining_mask
) {
576 i
= u_bit_scan(&remaining_mask
);
577 assert(dst
->views
.views
[i
]);
579 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
582 for (i
= 0; i
< count
; i
++) {
583 if (rviews
[i
] == dst
->views
.views
[i
]) {
588 struct r600_texture
*rtex
=
589 (struct r600_texture
*)rviews
[i
]->base
.texture
;
591 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
592 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
593 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
595 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
598 /* Track compressed colorbuffers. */
599 if (rtex
->cmask_size
&& rtex
->fmask_size
) {
600 dst
->views
.compressed_colortex_mask
|= 1 << i
;
602 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
605 /* Changing from array to non-arrays textures and vice versa requires
606 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
607 if (rctx
->chip_class
<= R700
&&
608 (dst
->states
.enabled_mask
& (1 << i
)) &&
609 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
610 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
611 dirty_sampler_states_mask
|= 1 << i
;
614 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
617 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
618 disable_mask
|= 1 << i
;
622 dst
->views
.enabled_mask
&= ~disable_mask
;
623 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
624 dst
->views
.enabled_mask
|= new_mask
;
625 dst
->views
.dirty_mask
|= new_mask
;
626 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
627 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
628 dst
->views
.dirty_txq_constants
= TRUE
;
629 dst
->views
.dirty_buffer_constants
= TRUE
;
630 r600_sampler_views_dirty(rctx
, &dst
->views
);
632 if (dirty_sampler_states_mask
) {
633 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
634 r600_sampler_states_dirty(rctx
, &dst
->states
);
638 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
639 struct pipe_sampler_view
**views
)
641 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
644 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
645 struct pipe_sampler_view
**views
)
647 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
650 static void r600_set_viewport_state(struct pipe_context
*ctx
,
651 const struct pipe_viewport_state
*state
)
653 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
655 rctx
->viewport
.state
= *state
;
656 rctx
->viewport
.atom
.dirty
= true;
659 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
661 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
662 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
664 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
665 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
666 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
667 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
668 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
669 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
670 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
673 /* Compute the key for the hw shader variant */
674 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
675 struct r600_pipe_shader_selector
* sel
)
677 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
678 struct r600_shader_key key
;
679 memset(&key
, 0, sizeof(key
));
681 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
682 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
683 key
.alpha_to_one
= rctx
->alpha_to_one
&&
684 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
685 !rctx
->framebuffer
.cb0_is_integer
;
686 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
687 /* Dual-source blending only makes sense with nr_cbufs == 1. */
688 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
694 /* Select the hw shader variant depending on the current state.
695 * (*dirty) is set to 1 if current variant was changed */
696 static int r600_shader_select(struct pipe_context
*ctx
,
697 struct r600_pipe_shader_selector
* sel
,
700 struct r600_shader_key key
;
701 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
702 struct r600_pipe_shader
* shader
= NULL
;
705 key
= r600_shader_selector_key(ctx
, sel
);
707 /* Check if we don't need to change anything.
708 * This path is also used for most shaders that don't need multiple
709 * variants, it will cost just a computation of the key and this
711 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
715 /* lookup if we have other variants in the list */
716 if (sel
->num_shaders
> 1) {
717 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
719 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
725 p
->next_variant
= c
->next_variant
;
730 if (unlikely(!shader
)) {
731 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
732 shader
->selector
= sel
;
734 r
= r600_pipe_shader_create(ctx
, shader
, key
);
736 R600_ERR("Failed to build shader variant (type=%u) %d\n",
742 /* We don't know the value of nr_ps_max_color_exports until we built
743 * at least one variant, so we may need to recompute the key after
744 * building first variant. */
745 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
746 sel
->num_shaders
== 0) {
747 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
748 key
= r600_shader_selector_key(ctx
, sel
);
758 shader
->next_variant
= sel
->current
;
759 sel
->current
= shader
;
761 if (rctx
->ps_shader
&&
762 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
763 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
764 rctx
->cb_misc_state
.atom
.dirty
= true;
769 static void *r600_create_shader_state(struct pipe_context
*ctx
,
770 const struct pipe_shader_state
*state
,
771 unsigned pipe_shader_type
)
773 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
776 sel
->type
= pipe_shader_type
;
777 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
778 sel
->so
= state
->stream_output
;
780 r
= r600_shader_select(ctx
, sel
, NULL
);
787 static void *r600_create_ps_state(struct pipe_context
*ctx
,
788 const struct pipe_shader_state
*state
)
790 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
793 static void *r600_create_vs_state(struct pipe_context
*ctx
,
794 const struct pipe_shader_state
*state
)
796 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
799 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
801 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
804 state
= rctx
->dummy_pixel_shader
;
806 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
807 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
809 if (rctx
->chip_class
<= R700
) {
810 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
812 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
813 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
814 rctx
->cb_misc_state
.atom
.dirty
= true;
818 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
819 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
820 rctx
->cb_misc_state
.atom
.dirty
= true;
823 if (rctx
->chip_class
>= EVERGREEN
) {
824 evergreen_update_db_shader_control(rctx
);
826 r600_update_db_shader_control(rctx
);
830 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
832 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
834 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
836 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
838 /* Update clip misc state. */
839 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
840 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
841 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
842 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
843 rctx
->clip_misc_state
.atom
.dirty
= true;
848 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
849 struct r600_pipe_shader_selector
*sel
)
851 struct r600_pipe_shader
*p
= sel
->current
, *c
;
854 r600_pipe_shader_destroy(ctx
, p
);
864 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
866 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
867 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
869 if (rctx
->ps_shader
== sel
) {
870 rctx
->ps_shader
= NULL
;
873 r600_delete_shader_selector(ctx
, sel
);
876 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
878 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
879 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
881 if (rctx
->vs_shader
== sel
) {
882 rctx
->vs_shader
= NULL
;
885 r600_delete_shader_selector(ctx
, sel
);
888 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
890 if (state
->dirty_mask
) {
891 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
892 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
893 : util_bitcount(state
->dirty_mask
)*19;
894 state
->atom
.dirty
= true;
898 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
899 struct pipe_constant_buffer
*input
)
901 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
902 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
903 struct pipe_constant_buffer
*cb
;
906 /* Note that the state tracker can unbind constant buffers by
909 if (unlikely(!input
)) {
910 state
->enabled_mask
&= ~(1 << index
);
911 state
->dirty_mask
&= ~(1 << index
);
912 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
916 cb
= &state
->cb
[index
];
917 cb
->buffer_size
= input
->buffer_size
;
919 ptr
= input
->user_buffer
;
922 /* Upload the user buffer. */
923 if (R600_BIG_ENDIAN
) {
925 unsigned i
, size
= input
->buffer_size
;
927 if (!(tmpPtr
= malloc(size
))) {
928 R600_ERR("Failed to allocate BE swap buffer.\n");
932 for (i
= 0; i
< size
/ 4; ++i
) {
933 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
936 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
939 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
942 /* Setup the hw buffer. */
943 cb
->buffer_offset
= input
->buffer_offset
;
944 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
947 state
->enabled_mask
|= 1 << index
;
948 state
->dirty_mask
|= 1 << index
;
949 r600_constant_buffers_dirty(rctx
, state
);
952 static struct pipe_stream_output_target
*
953 r600_create_so_target(struct pipe_context
*ctx
,
954 struct pipe_resource
*buffer
,
955 unsigned buffer_offset
,
956 unsigned buffer_size
)
958 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
959 struct r600_so_target
*t
;
961 t
= CALLOC_STRUCT(r600_so_target
);
966 u_suballocator_alloc(rctx
->allocator_so_filled_size
, 4,
967 &t
->buf_filled_size_offset
,
968 (struct pipe_resource
**)&t
->buf_filled_size
);
969 if (!t
->buf_filled_size
) {
974 t
->b
.reference
.count
= 1;
976 pipe_resource_reference(&t
->b
.buffer
, buffer
);
977 t
->b
.buffer_offset
= buffer_offset
;
978 t
->b
.buffer_size
= buffer_size
;
982 static void r600_so_target_destroy(struct pipe_context
*ctx
,
983 struct pipe_stream_output_target
*target
)
985 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
986 pipe_resource_reference(&t
->b
.buffer
, NULL
);
987 pipe_resource_reference((struct pipe_resource
**)&t
->buf_filled_size
, NULL
);
991 static void r600_set_so_targets(struct pipe_context
*ctx
,
992 unsigned num_targets
,
993 struct pipe_stream_output_target
**targets
,
994 unsigned append_bitmask
)
996 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
999 /* Stop streamout. */
1000 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
1001 r600_context_streamout_end(rctx
);
1004 /* Set the new targets. */
1005 for (i
= 0; i
< num_targets
; i
++) {
1006 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
1008 for (; i
< rctx
->num_so_targets
; i
++) {
1009 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
1012 rctx
->num_so_targets
= num_targets
;
1013 rctx
->streamout_start
= num_targets
!= 0;
1014 rctx
->streamout_append_bitmask
= append_bitmask
;
1017 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1019 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1021 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1024 rctx
->sample_mask
.sample_mask
= sample_mask
;
1025 rctx
->sample_mask
.atom
.dirty
= true;
1029 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1030 * doesn't require full swizzles it does need masking and setting alpha
1031 * to one, so we setup a set of 5 constants with the masks + alpha value
1032 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1033 * then OR the alpha with the value given here.
1034 * We use a 6th constant to store the txq buffer size in
1036 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1038 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1040 uint32_t array_size
;
1041 struct pipe_constant_buffer cb
;
1044 if (!samplers
->views
.dirty_buffer_constants
)
1047 samplers
->views
.dirty_buffer_constants
= FALSE
;
1049 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1050 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1051 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1052 memset(samplers
->buffer_constants
, 0, array_size
);
1053 for (i
= 0; i
< bits
; i
++) {
1054 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1056 const struct util_format_description
*desc
;
1057 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1059 for (j
= 0; j
< 4; j
++)
1060 if (j
< desc
->nr_channels
)
1061 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1063 samplers
->buffer_constants
[offset
+j
] = 0x0;
1064 if (desc
->nr_channels
< 4) {
1065 if (desc
->channel
[0].pure_integer
)
1066 samplers
->buffer_constants
[offset
+4] = 1;
1068 samplers
->buffer_constants
[offset
+4] = 0x3f800000;
1070 samplers
->buffer_constants
[offset
+ 4] = 0;
1072 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1077 cb
.user_buffer
= samplers
->buffer_constants
;
1078 cb
.buffer_offset
= 0;
1079 cb
.buffer_size
= array_size
;
1080 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1081 pipe_resource_reference(&cb
.buffer
, NULL
);
1084 /* On evergreen we only need to store the buffer size for TXQ */
1085 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1087 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1089 uint32_t array_size
;
1090 struct pipe_constant_buffer cb
;
1093 if (!samplers
->views
.dirty_buffer_constants
)
1096 samplers
->views
.dirty_buffer_constants
= FALSE
;
1098 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1099 array_size
= bits
* sizeof(uint32_t) * 4;
1100 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1101 memset(samplers
->buffer_constants
, 0, array_size
);
1102 for (i
= 0; i
< bits
; i
++)
1103 if (samplers
->views
.enabled_mask
& (1 << i
))
1104 samplers
->buffer_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1107 cb
.user_buffer
= samplers
->buffer_constants
;
1108 cb
.buffer_offset
= 0;
1109 cb
.buffer_size
= array_size
;
1110 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1111 pipe_resource_reference(&cb
.buffer
, NULL
);
1114 static void r600_setup_txq_cube_array_constants(struct r600_context
*rctx
, int shader_type
)
1116 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1118 uint32_t array_size
;
1119 struct pipe_constant_buffer cb
;
1122 if (!samplers
->views
.dirty_txq_constants
)
1125 samplers
->views
.dirty_txq_constants
= FALSE
;
1127 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1128 array_size
= bits
* sizeof(uint32_t) * 4;
1129 samplers
->txq_constants
= realloc(samplers
->txq_constants
, array_size
);
1130 memset(samplers
->txq_constants
, 0, array_size
);
1131 for (i
= 0; i
< bits
; i
++)
1132 if (samplers
->views
.enabled_mask
& (1 << i
))
1133 samplers
->txq_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1136 cb
.user_buffer
= samplers
->txq_constants
;
1137 cb
.buffer_offset
= 0;
1138 cb
.buffer_size
= array_size
;
1139 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_TXQ_CONST_BUFFER
, &cb
);
1140 pipe_resource_reference(&cb
.buffer
, NULL
);
1143 static bool r600_update_derived_state(struct r600_context
*rctx
)
1145 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1146 unsigned ps_dirty
= 0;
1149 if (!rctx
->blitter
->running
) {
1152 /* Decompress textures if needed. */
1153 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1154 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1155 if (views
->compressed_depthtex_mask
) {
1156 r600_decompress_depth_textures(rctx
, views
);
1158 if (views
->compressed_colortex_mask
) {
1159 r600_decompress_color_textures(rctx
, views
);
1164 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1166 if (rctx
->ps_shader
&& rctx
->rasterizer
&&
1167 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1168 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1170 if (rctx
->chip_class
>= EVERGREEN
)
1171 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1173 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1179 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1181 /* on R600 we stuff masks + txq info into one constant buffer */
1182 /* on evergreen we only need a txq info one */
1183 if (rctx
->chip_class
< EVERGREEN
) {
1184 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1185 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1186 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1187 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1189 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1190 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1191 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1192 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1196 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1197 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1198 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1199 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_VERTEX
);
1201 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1202 if (!r600_adjust_gprs(rctx
)) {
1203 /* discard rendering */
1208 blend_disable
= (rctx
->dual_src_blend
&&
1209 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1211 if (blend_disable
!= rctx
->force_blend_disable
) {
1212 rctx
->force_blend_disable
= blend_disable
;
1213 r600_bind_blend_state_internal(rctx
,
1214 rctx
->blend_state
.cso
,
1220 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1222 static const int prim_conv
[] = {
1223 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1224 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1225 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1226 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1227 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1228 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1229 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1230 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1231 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1232 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1233 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1234 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1235 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1236 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1237 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1239 assert(mode
< Elements(prim_conv
));
1241 return prim_conv
[mode
];
1244 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1246 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1247 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1249 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1250 state
->pa_cl_clip_cntl
|
1251 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1252 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1253 state
->pa_cl_vs_out_cntl
|
1254 (state
->clip_plane_enable
& state
->clip_dist_write
));
1257 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1259 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1260 struct pipe_draw_info info
= *dinfo
;
1261 struct pipe_index_buffer ib
= {};
1263 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1264 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1266 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1271 if (!rctx
->vs_shader
) {
1276 /* make sure that the gfx ring is only one active */
1277 rctx
->rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
);
1279 if (!r600_update_derived_state(rctx
)) {
1280 /* useless to render because current rendering command
1287 /* Initialize the index buffer struct. */
1288 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1289 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1290 ib
.index_size
= rctx
->index_buffer
.index_size
;
1291 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1293 /* Translate 8-bit indices to 16-bit. */
1294 if (ib
.index_size
== 1) {
1295 struct pipe_resource
*out_buffer
= NULL
;
1296 unsigned out_offset
;
1299 u_upload_alloc(rctx
->uploader
, 0, info
.count
* 2,
1300 &out_offset
, &out_buffer
, &ptr
);
1302 util_shorten_ubyte_elts_to_userptr(
1303 &rctx
->context
, &ib
, 0, ib
.offset
, info
.count
, ptr
);
1305 pipe_resource_reference(&ib
.buffer
, NULL
);
1306 ib
.user_buffer
= NULL
;
1307 ib
.buffer
= out_buffer
;
1308 ib
.offset
= out_offset
;
1312 /* Upload the index buffer.
1313 * The upload is skipped for small index counts on little-endian machines
1314 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1315 * Note: Instanced rendering in combination with immediate indices hangs. */
1316 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.instance_count
> 1 ||
1317 info
.count
*ib
.index_size
> 20)) {
1318 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1319 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1320 ib
.user_buffer
= NULL
;
1323 info
.index_bias
= info
.start
;
1326 /* Enable stream out if needed. */
1327 if (rctx
->streamout_start
) {
1328 r600_context_streamout_begin(rctx
);
1329 rctx
->streamout_start
= FALSE
;
1332 /* Set the index offset and multi primitive */
1333 if (rctx
->vgt2_state
.vgt_indx_offset
!= info
.index_bias
) {
1334 rctx
->vgt2_state
.vgt_indx_offset
= info
.index_bias
;
1335 rctx
->vgt2_state
.atom
.dirty
= true;
1337 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1338 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
) {
1339 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1340 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1341 rctx
->vgt_state
.atom
.dirty
= true;
1345 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1346 r600_flush_emit(rctx
);
1348 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1349 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1352 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1354 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1355 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1357 rctx
->pm4_dirty_cdwords
= 0;
1359 /* Update start instance. */
1360 if (rctx
->last_start_instance
!= info
.start_instance
) {
1361 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1362 rctx
->last_start_instance
= info
.start_instance
;
1365 /* Update the primitive type. */
1366 if (rctx
->last_primitive_type
!= info
.mode
) {
1367 unsigned ls_mask
= 0;
1369 if (info
.mode
== PIPE_PRIM_LINES
)
1371 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1372 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1375 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1376 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1377 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1378 r600_write_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
1379 r600_conv_prim_to_gs_out(info
.mode
));
1380 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1381 r600_conv_pipe_prim(info
.mode
));
1383 rctx
->last_primitive_type
= info
.mode
;
1387 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1388 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1390 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1391 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1392 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1393 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1395 if (ib
.user_buffer
) {
1396 unsigned size_bytes
= info
.count
*ib
.index_size
;
1397 unsigned size_dw
= align(size_bytes
, 4) / 4;
1398 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->predicate_drawing
);
1399 cs
->buf
[cs
->cdw
++] = info
.count
;
1400 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1401 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1404 uint64_t va
= r600_resource_va(ctx
->screen
, ib
.buffer
) + ib
.offset
;
1405 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1406 cs
->buf
[cs
->cdw
++] = va
;
1407 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1408 cs
->buf
[cs
->cdw
++] = info
.count
;
1409 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1410 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1411 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1414 if (info
.count_from_stream_output
) {
1415 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1416 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->buf_filled_size
) + t
->buf_filled_size_offset
;
1418 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1420 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1421 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1422 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1423 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1424 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1425 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1427 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1428 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, t
->buf_filled_size
, RADEON_USAGE_READ
);
1431 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1432 cs
->buf
[cs
->cdw
++] = info
.count
;
1433 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1434 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1438 if (rctx
->screen
->trace_bo
) {
1439 r600_trace_emit(rctx
);
1443 /* Set the depth buffer as dirty. */
1444 if (rctx
->framebuffer
.state
.zsbuf
) {
1445 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1446 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1448 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1450 if (rctx
->framebuffer
.compressed_cb_mask
) {
1451 struct pipe_surface
*surf
;
1452 struct r600_texture
*rtex
;
1453 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1456 unsigned i
= u_bit_scan(&mask
);
1457 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1458 rtex
= (struct r600_texture
*)surf
->texture
;
1460 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1465 pipe_resource_reference(&ib
.buffer
, NULL
);
1468 void r600_draw_rectangle(struct blitter_context
*blitter
,
1469 int x1
, int y1
, int x2
, int y2
, float depth
,
1470 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1472 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1473 struct pipe_viewport_state viewport
;
1474 struct pipe_resource
*buf
= NULL
;
1475 unsigned offset
= 0;
1478 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1479 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1483 /* Some operations (like color resolve on r6xx) don't work
1484 * with the conventional primitive types.
1485 * One that works is PT_RECTLIST, which we use here. */
1487 /* setup viewport */
1488 viewport
.scale
[0] = 1.0f
;
1489 viewport
.scale
[1] = 1.0f
;
1490 viewport
.scale
[2] = 1.0f
;
1491 viewport
.scale
[3] = 1.0f
;
1492 viewport
.translate
[0] = 0.0f
;
1493 viewport
.translate
[1] = 0.0f
;
1494 viewport
.translate
[2] = 0.0f
;
1495 viewport
.translate
[3] = 0.0f
;
1496 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1498 /* Upload vertices. The hw rectangle has only 3 vertices,
1499 * I guess the 4th one is derived from the first 3.
1500 * The vertex specification should match u_blitter's vertex element state. */
1501 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1518 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1519 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1520 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1524 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, rctx
->blitter
->vb_slot
, offset
,
1525 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1526 pipe_resource_reference(&buf
, NULL
);
1529 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1530 struct r600_pipe_state
*state
,
1531 uint32_t offset
, uint32_t value
,
1532 uint32_t range_id
, uint32_t block_id
,
1533 struct r600_resource
*bo
,
1534 enum radeon_bo_usage usage
)
1537 struct r600_range
*range
;
1538 struct r600_block
*block
;
1540 if (bo
) assert(usage
);
1542 range
= &ctx
->range
[range_id
];
1543 block
= range
->blocks
[block_id
];
1544 state
->regs
[state
->nregs
].block
= block
;
1545 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1547 state
->regs
[state
->nregs
].value
= value
;
1548 state
->regs
[state
->nregs
].bo
= bo
;
1549 state
->regs
[state
->nregs
].bo_usage
= usage
;
1552 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1555 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1556 struct r600_pipe_state
*state
,
1557 uint32_t offset
, uint32_t value
,
1558 uint32_t range_id
, uint32_t block_id
)
1560 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1561 range_id
, block_id
, NULL
, 0);
1564 uint32_t r600_translate_stencil_op(int s_op
)
1567 case PIPE_STENCIL_OP_KEEP
:
1568 return V_028800_STENCIL_KEEP
;
1569 case PIPE_STENCIL_OP_ZERO
:
1570 return V_028800_STENCIL_ZERO
;
1571 case PIPE_STENCIL_OP_REPLACE
:
1572 return V_028800_STENCIL_REPLACE
;
1573 case PIPE_STENCIL_OP_INCR
:
1574 return V_028800_STENCIL_INCR
;
1575 case PIPE_STENCIL_OP_DECR
:
1576 return V_028800_STENCIL_DECR
;
1577 case PIPE_STENCIL_OP_INCR_WRAP
:
1578 return V_028800_STENCIL_INCR_WRAP
;
1579 case PIPE_STENCIL_OP_DECR_WRAP
:
1580 return V_028800_STENCIL_DECR_WRAP
;
1581 case PIPE_STENCIL_OP_INVERT
:
1582 return V_028800_STENCIL_INVERT
;
1584 R600_ERR("Unknown stencil op %d", s_op
);
1591 uint32_t r600_translate_fill(uint32_t func
)
1594 case PIPE_POLYGON_MODE_FILL
:
1596 case PIPE_POLYGON_MODE_LINE
:
1598 case PIPE_POLYGON_MODE_POINT
:
1606 unsigned r600_tex_wrap(unsigned wrap
)
1610 case PIPE_TEX_WRAP_REPEAT
:
1611 return V_03C000_SQ_TEX_WRAP
;
1612 case PIPE_TEX_WRAP_CLAMP
:
1613 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1614 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1615 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1616 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1617 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1618 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1619 return V_03C000_SQ_TEX_MIRROR
;
1620 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1621 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1622 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1623 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1624 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1625 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1629 unsigned r600_tex_filter(unsigned filter
)
1633 case PIPE_TEX_FILTER_NEAREST
:
1634 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1635 case PIPE_TEX_FILTER_LINEAR
:
1636 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1640 unsigned r600_tex_mipfilter(unsigned filter
)
1643 case PIPE_TEX_MIPFILTER_NEAREST
:
1644 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1645 case PIPE_TEX_MIPFILTER_LINEAR
:
1646 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1648 case PIPE_TEX_MIPFILTER_NONE
:
1649 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1653 unsigned r600_tex_compare(unsigned compare
)
1657 case PIPE_FUNC_NEVER
:
1658 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1659 case PIPE_FUNC_LESS
:
1660 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1661 case PIPE_FUNC_EQUAL
:
1662 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1663 case PIPE_FUNC_LEQUAL
:
1664 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1665 case PIPE_FUNC_GREATER
:
1666 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1667 case PIPE_FUNC_NOTEQUAL
:
1668 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1669 case PIPE_FUNC_GEQUAL
:
1670 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1671 case PIPE_FUNC_ALWAYS
:
1672 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1676 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1678 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1679 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1681 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1682 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1685 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1687 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1688 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1690 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1691 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1692 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1693 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1694 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1697 /* keep this at the end of this file, please */
1698 void r600_init_common_state_functions(struct r600_context
*rctx
)
1700 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1701 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1702 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
1703 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1704 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1705 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1706 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1707 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1708 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1709 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1710 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1711 rctx
->context
.delete_blend_state
= r600_delete_blend_state
;
1712 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
1713 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1714 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1715 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1716 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1717 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1718 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1719 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1720 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1721 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1722 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1723 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1724 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1725 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1726 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1727 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1728 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1729 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1730 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1731 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1732 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1733 rctx
->context
.draw_vbo
= r600_draw_vbo
;
1737 void r600_trace_emit(struct r600_context
*rctx
)
1739 struct r600_screen
*rscreen
= rctx
->screen
;
1740 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1744 va
= r600_resource_va(&rscreen
->screen
, (void*)rscreen
->trace_bo
);
1745 reloc
= r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rscreen
->trace_bo
, RADEON_USAGE_READWRITE
);
1746 r600_write_value(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
1747 r600_write_value(cs
, va
& 0xFFFFFFFFUL
);
1748 r600_write_value(cs
, (va
>> 32UL) & 0xFFUL
);
1749 r600_write_value(cs
, cs
->cdw
);
1750 r600_write_value(cs
, rscreen
->cs_count
);
1751 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1752 r600_write_value(cs
, reloc
);