2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
97 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
98 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
100 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
101 PIPE_BARRIER_SHADER_BUFFER
|
102 PIPE_BARRIER_TEXTURE
|
104 PIPE_BARRIER_STREAMOUT_BUFFER
|
105 PIPE_BARRIER_GLOBAL_BUFFER
)) {
106 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
|
107 R600_CONTEXT_INV_TEX_CACHE
;
110 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
112 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV
;
114 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
117 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
119 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
121 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
122 R600_CONTEXT_FLUSH_AND_INV_CB
|
123 R600_CONTEXT_FLUSH_AND_INV
|
124 R600_CONTEXT_WAIT_3D_IDLE
;
125 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
128 static unsigned r600_conv_pipe_prim(unsigned prim
)
130 static const unsigned prim_conv
[] = {
131 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
132 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
133 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
134 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
135 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
136 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
138 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
139 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
140 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
141 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
145 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
146 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
148 assert(prim
< ARRAY_SIZE(prim_conv
));
149 return prim_conv
[prim
];
152 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
154 static const int prim_conv
[] = {
155 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
156 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
157 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
158 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
159 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
160 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
161 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
162 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
163 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
164 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
165 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
166 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
167 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
168 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
169 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
170 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
172 assert(mode
< ARRAY_SIZE(prim_conv
));
174 return prim_conv
[mode
];
177 /* common state between evergreen and r600 */
179 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
180 struct r600_blend_state
*blend
, bool blend_disable
)
182 unsigned color_control
;
183 bool update_cb
= false;
185 rctx
->alpha_to_one
= blend
->alpha_to_one
;
186 rctx
->dual_src_blend
= blend
->dual_src_blend
;
188 if (!blend_disable
) {
189 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
190 color_control
= blend
->cb_color_control
;
192 /* Blending is disabled. */
193 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
194 color_control
= blend
->cb_color_control_no_blend
;
197 /* Update derived states. */
198 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
199 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
202 if (rctx
->b
.chip_class
<= R700
&&
203 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
204 rctx
->cb_misc_state
.cb_color_control
= color_control
;
207 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
208 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
212 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
214 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
215 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
216 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
220 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
222 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
223 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
226 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
230 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
233 static void r600_set_blend_color(struct pipe_context
*ctx
,
234 const struct pipe_blend_color
*state
)
236 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
238 rctx
->blend_color
.state
= *state
;
239 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
242 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
244 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
245 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
247 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
248 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
249 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
250 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
251 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
254 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
256 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
257 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
259 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
260 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
261 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
262 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
263 if (a
->last_draw_was_indirect
) {
264 a
->last_draw_was_indirect
= false;
265 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
269 static void r600_set_clip_state(struct pipe_context
*ctx
,
270 const struct pipe_clip_state
*state
)
272 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
274 rctx
->clip_state
.state
= *state
;
275 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
276 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
279 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
280 const struct r600_stencil_ref
*state
)
282 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
284 rctx
->stencil_ref
.state
= *state
;
285 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
288 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
290 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
291 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
293 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
294 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
295 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
296 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
297 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
298 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
299 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
300 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
301 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
304 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
305 const struct pipe_stencil_ref
*state
)
307 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
308 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
309 struct r600_stencil_ref ref
;
311 rctx
->stencil_ref
.pipe_state
= *state
;
316 ref
.ref_value
[0] = state
->ref_value
[0];
317 ref
.ref_value
[1] = state
->ref_value
[1];
318 ref
.valuemask
[0] = dsa
->valuemask
[0];
319 ref
.valuemask
[1] = dsa
->valuemask
[1];
320 ref
.writemask
[0] = dsa
->writemask
[0];
321 ref
.writemask
[1] = dsa
->writemask
[1];
323 r600_set_stencil_ref(ctx
, &ref
);
326 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
328 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
329 struct r600_dsa_state
*dsa
= state
;
330 struct r600_stencil_ref ref
;
333 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
337 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
339 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
340 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
341 ref
.valuemask
[0] = dsa
->valuemask
[0];
342 ref
.valuemask
[1] = dsa
->valuemask
[1];
343 ref
.writemask
[0] = dsa
->writemask
[0];
344 ref
.writemask
[1] = dsa
->writemask
[1];
345 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
346 rctx
->zwritemask
= dsa
->zwritemask
;
347 if (rctx
->b
.chip_class
>= EVERGREEN
) {
348 /* work around some issue when not writing to zbuffer
349 * we are having lockup on evergreen so do not enable
350 * hyperz when not writing zbuffer
352 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
356 r600_set_stencil_ref(ctx
, &ref
);
358 /* Update alphatest state. */
359 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
360 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
361 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
362 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
363 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
367 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
369 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
370 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
375 rctx
->rasterizer
= rs
;
377 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
379 if (rs
->offset_enable
&&
380 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
381 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
382 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
383 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
384 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
385 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
386 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
389 /* Update clip_misc_state. */
390 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
391 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
392 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
393 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
394 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
397 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
399 /* Re-emit PA_SC_LINE_STIPPLE. */
400 rctx
->last_primitive_type
= -1;
403 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
405 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
407 r600_release_command_buffer(&rs
->buffer
);
411 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
412 struct pipe_sampler_view
*state
)
414 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
416 if (view
->tex_resource
->gpu_address
&&
417 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
418 LIST_DELINIT(&view
->list
);
420 pipe_resource_reference(&state
->texture
, NULL
);
424 void r600_sampler_states_dirty(struct r600_context
*rctx
,
425 struct r600_sampler_states
*state
)
427 if (state
->dirty_mask
) {
428 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
429 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
432 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
433 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
434 r600_mark_atom_dirty(rctx
, &state
->atom
);
438 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
439 enum pipe_shader_type shader
,
441 unsigned count
, void **states
)
443 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
444 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
445 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
446 int seamless_cube_map
= -1;
448 /* This sets 1-bit for states with index >= count. */
449 uint32_t disable_mask
= ~((1ull << count
) - 1);
450 /* These are the new states set by this function. */
451 uint32_t new_mask
= 0;
453 assert(start
== 0); /* XXX fix below */
460 for (i
= 0; i
< count
; i
++) {
461 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
463 if (rstate
== dst
->states
.states
[i
]) {
468 if (rstate
->border_color_use
) {
469 dst
->states
.has_bordercolor_mask
|= 1 << i
;
471 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
473 seamless_cube_map
= rstate
->seamless_cube_map
;
477 disable_mask
|= 1 << i
;
481 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
482 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
484 dst
->states
.enabled_mask
&= ~disable_mask
;
485 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
486 dst
->states
.enabled_mask
|= new_mask
;
487 dst
->states
.dirty_mask
|= new_mask
;
488 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
490 r600_sampler_states_dirty(rctx
, &dst
->states
);
492 /* Seamless cubemap state. */
493 if (rctx
->b
.chip_class
<= R700
&&
494 seamless_cube_map
!= -1 &&
495 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
496 /* change in TA_CNTL_AUX need a pipeline flush */
497 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
498 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
499 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
503 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
508 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
510 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
511 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
513 if (rctx
->blend_state
.cso
== state
) {
514 ctx
->bind_blend_state(ctx
, NULL
);
517 r600_release_command_buffer(&blend
->buffer
);
518 r600_release_command_buffer(&blend
->buffer_no_blend
);
522 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
524 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
525 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
527 if (rctx
->dsa_state
.cso
== state
) {
528 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
531 r600_release_command_buffer(&dsa
->buffer
);
535 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
537 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
539 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
542 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
544 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
545 r600_resource_reference(&shader
->buffer
, NULL
);
549 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
551 if (rctx
->vertex_buffer_state
.dirty_mask
) {
552 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
553 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
554 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
558 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
559 unsigned start_slot
, unsigned count
,
560 const struct pipe_vertex_buffer
*input
)
562 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
563 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
564 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
566 uint32_t disable_mask
= 0;
567 /* These are the new buffers set by this function. */
568 uint32_t new_buffer_mask
= 0;
570 /* Set vertex buffers. */
572 for (i
= 0; i
< count
; i
++) {
573 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
574 if (input
[i
].buffer
.resource
) {
575 vb
[i
].stride
= input
[i
].stride
;
576 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
577 pipe_resource_reference(&vb
[i
].buffer
.resource
, input
[i
].buffer
.resource
);
578 new_buffer_mask
|= 1 << i
;
579 r600_context_add_resource_size(ctx
, input
[i
].buffer
.resource
);
581 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
582 disable_mask
|= 1 << i
;
587 for (i
= 0; i
< count
; i
++) {
588 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
590 disable_mask
= ((1ull << count
) - 1);
593 disable_mask
<<= start_slot
;
594 new_buffer_mask
<<= start_slot
;
596 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
597 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
598 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
599 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
601 r600_vertex_buffers_dirty(rctx
);
604 void r600_sampler_views_dirty(struct r600_context
*rctx
,
605 struct r600_samplerview_state
*state
)
607 if (state
->dirty_mask
) {
608 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
609 util_bitcount(state
->dirty_mask
);
610 r600_mark_atom_dirty(rctx
, &state
->atom
);
614 static void r600_set_sampler_views(struct pipe_context
*pipe
,
615 enum pipe_shader_type shader
,
616 unsigned start
, unsigned count
,
617 struct pipe_sampler_view
**views
)
619 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
620 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
621 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
622 uint32_t dirty_sampler_states_mask
= 0;
624 /* This sets 1-bit for textures with index >= count. */
625 uint32_t disable_mask
= ~((1ull << count
) - 1);
626 /* These are the new textures set by this function. */
627 uint32_t new_mask
= 0;
629 /* Set textures with index >= count to NULL. */
630 uint32_t remaining_mask
;
632 assert(start
== 0); /* XXX fix below */
639 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
641 while (remaining_mask
) {
642 i
= u_bit_scan(&remaining_mask
);
643 assert(dst
->views
.views
[i
]);
645 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
648 for (i
= 0; i
< count
; i
++) {
649 if (rviews
[i
] == dst
->views
.views
[i
]) {
654 struct r600_texture
*rtex
=
655 (struct r600_texture
*)rviews
[i
]->base
.texture
;
656 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
658 if (!is_buffer
&& rtex
->db_compatible
) {
659 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
661 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
664 /* Track compressed colorbuffers. */
665 if (!is_buffer
&& rtex
->cmask
.size
) {
666 dst
->views
.compressed_colortex_mask
|= 1 << i
;
668 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
671 /* Changing from array to non-arrays textures and vice versa requires
672 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
673 if (rctx
->b
.chip_class
<= R700
&&
674 (dst
->states
.enabled_mask
& (1 << i
)) &&
675 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
676 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
677 dirty_sampler_states_mask
|= 1 << i
;
680 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
682 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
684 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
685 disable_mask
|= 1 << i
;
689 dst
->views
.enabled_mask
&= ~disable_mask
;
690 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
691 dst
->views
.enabled_mask
|= new_mask
;
692 dst
->views
.dirty_mask
|= new_mask
;
693 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
694 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
695 dst
->views
.dirty_buffer_constants
= TRUE
;
696 r600_sampler_views_dirty(rctx
, &dst
->views
);
698 if (dirty_sampler_states_mask
) {
699 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
700 r600_sampler_states_dirty(rctx
, &dst
->states
);
704 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
706 uint32_t mask
= views
->enabled_mask
;
709 unsigned i
= u_bit_scan(&mask
);
710 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
712 if (res
&& res
->target
!= PIPE_BUFFER
) {
713 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
715 if (rtex
->cmask
.size
) {
716 views
->compressed_colortex_mask
|= 1 << i
;
718 views
->compressed_colortex_mask
&= ~(1 << i
);
724 static int r600_get_hw_atomic_count(const struct pipe_context
*ctx
,
725 enum pipe_shader_type shader
)
727 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
730 case PIPE_SHADER_FRAGMENT
:
731 case PIPE_SHADER_COMPUTE
:
734 case PIPE_SHADER_VERTEX
:
735 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
737 case PIPE_SHADER_GEOMETRY
:
738 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
739 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
741 case PIPE_SHADER_TESS_EVAL
:
742 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
743 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
744 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0);
746 case PIPE_SHADER_TESS_CTRL
:
747 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
748 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
749 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0) +
750 rctx
->tes_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
756 static void r600_update_compressed_colortex_mask_images(struct r600_image_state
*images
)
758 uint32_t mask
= images
->enabled_mask
;
761 unsigned i
= u_bit_scan(&mask
);
762 struct pipe_resource
*res
= images
->views
[i
].base
.resource
;
764 if (res
&& res
->target
!= PIPE_BUFFER
) {
765 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
767 if (rtex
->cmask
.size
) {
768 images
->compressed_colortex_mask
|= 1 << i
;
770 images
->compressed_colortex_mask
&= ~(1 << i
);
776 /* Compute the key for the hw shader variant */
777 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
778 const struct r600_pipe_shader_selector
*sel
,
779 union r600_shader_key
*key
)
781 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
782 memset(key
, 0, sizeof(*key
));
785 case PIPE_SHADER_VERTEX
: {
786 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
788 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
790 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
791 key
->vs
.as_gs_a
= true;
792 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
794 key
->vs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_VERTEX
);
797 case PIPE_SHADER_GEOMETRY
:
798 key
->gs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_GEOMETRY
);
799 key
->gs
.tri_strip_adj_fix
= rctx
->gs_tri_strip_adj_fix
;
801 case PIPE_SHADER_FRAGMENT
: {
802 if (rctx
->ps_shader
->info
.images_declared
)
803 key
->ps
.image_size_const_offset
= util_last_bit(rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.enabled_mask
);
804 key
->ps
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_FRAGMENT
);
805 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
806 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
807 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
808 !rctx
->framebuffer
.cb0_is_integer
;
809 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
810 /* Dual-source blending only makes sense with nr_cbufs == 1. */
811 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
812 key
->ps
.nr_cbufs
= 2;
815 case PIPE_SHADER_TESS_EVAL
:
816 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
817 key
->tes
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_EVAL
);
819 case PIPE_SHADER_TESS_CTRL
:
820 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
821 key
->tcs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_CTRL
);
828 /* Select the hw shader variant depending on the current state.
829 * (*dirty) is set to 1 if current variant was changed */
830 static int r600_shader_select(struct pipe_context
*ctx
,
831 struct r600_pipe_shader_selector
* sel
,
834 union r600_shader_key key
;
835 struct r600_pipe_shader
* shader
= NULL
;
838 r600_shader_selector_key(ctx
, sel
, &key
);
840 /* Check if we don't need to change anything.
841 * This path is also used for most shaders that don't need multiple
842 * variants, it will cost just a computation of the key and this
844 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
848 /* lookup if we have other variants in the list */
849 if (sel
->num_shaders
> 1) {
850 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
852 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
858 p
->next_variant
= c
->next_variant
;
863 if (unlikely(!shader
)) {
864 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
865 shader
->selector
= sel
;
867 r
= r600_pipe_shader_create(ctx
, shader
, key
);
869 R600_ERR("Failed to build shader variant (type=%u) %d\n",
876 /* We don't know the value of nr_ps_max_color_exports until we built
877 * at least one variant, so we may need to recompute the key after
878 * building first variant. */
879 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
880 sel
->num_shaders
== 0) {
881 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
882 r600_shader_selector_key(ctx
, sel
, &key
);
885 memcpy(&shader
->key
, &key
, sizeof(key
));
892 shader
->next_variant
= sel
->current
;
893 sel
->current
= shader
;
898 static void *r600_create_shader_state(struct pipe_context
*ctx
,
899 const struct pipe_shader_state
*state
,
900 unsigned pipe_shader_type
)
902 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
905 sel
->type
= pipe_shader_type
;
906 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
907 sel
->so
= state
->stream_output
;
908 tgsi_scan_shader(state
->tokens
, &sel
->info
);
910 switch (pipe_shader_type
) {
911 case PIPE_SHADER_GEOMETRY
:
912 sel
->gs_output_prim
=
913 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
914 sel
->gs_max_out_vertices
=
915 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
916 sel
->gs_num_invocations
=
917 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
919 case PIPE_SHADER_VERTEX
:
920 case PIPE_SHADER_TESS_CTRL
:
921 sel
->lds_patch_outputs_written_mask
= 0;
922 sel
->lds_outputs_written_mask
= 0;
924 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
925 unsigned name
= sel
->info
.output_semantic_name
[i
];
926 unsigned index
= sel
->info
.output_semantic_index
[i
];
929 case TGSI_SEMANTIC_TESSINNER
:
930 case TGSI_SEMANTIC_TESSOUTER
:
931 case TGSI_SEMANTIC_PATCH
:
932 sel
->lds_patch_outputs_written_mask
|=
933 1ull << r600_get_lds_unique_index(name
, index
);
936 sel
->lds_outputs_written_mask
|=
937 1ull << r600_get_lds_unique_index(name
, index
);
948 static void *r600_create_ps_state(struct pipe_context
*ctx
,
949 const struct pipe_shader_state
*state
)
951 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
954 static void *r600_create_vs_state(struct pipe_context
*ctx
,
955 const struct pipe_shader_state
*state
)
957 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
960 static void *r600_create_gs_state(struct pipe_context
*ctx
,
961 const struct pipe_shader_state
*state
)
963 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
966 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
967 const struct pipe_shader_state
*state
)
969 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
972 static void *r600_create_tes_state(struct pipe_context
*ctx
,
973 const struct pipe_shader_state
*state
)
975 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
978 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
980 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
983 state
= rctx
->dummy_pixel_shader
;
985 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
988 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
991 return &rctx
->gs_shader
->info
;
992 else if (rctx
->tes_shader
)
993 return &rctx
->tes_shader
->info
;
994 else if (rctx
->vs_shader
)
995 return &rctx
->vs_shader
->info
;
1000 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1002 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1004 if (!state
|| rctx
->vs_shader
== state
)
1007 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
1008 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1009 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
1012 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1014 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1016 if (state
== rctx
->gs_shader
)
1019 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
1020 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1024 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
1027 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1029 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1031 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
1034 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1036 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1038 if (state
== rctx
->tes_shader
)
1041 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
1042 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1046 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
1049 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
1050 struct r600_pipe_shader_selector
*sel
)
1052 struct r600_pipe_shader
*p
= sel
->current
, *c
;
1054 c
= p
->next_variant
;
1055 r600_pipe_shader_destroy(ctx
, p
);
1065 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
1067 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1068 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1070 if (rctx
->ps_shader
== sel
) {
1071 rctx
->ps_shader
= NULL
;
1074 r600_delete_shader_selector(ctx
, sel
);
1077 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1079 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1080 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1082 if (rctx
->vs_shader
== sel
) {
1083 rctx
->vs_shader
= NULL
;
1086 r600_delete_shader_selector(ctx
, sel
);
1090 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1092 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1093 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1095 if (rctx
->gs_shader
== sel
) {
1096 rctx
->gs_shader
= NULL
;
1099 r600_delete_shader_selector(ctx
, sel
);
1102 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1104 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1105 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1107 if (rctx
->tcs_shader
== sel
) {
1108 rctx
->tcs_shader
= NULL
;
1111 r600_delete_shader_selector(ctx
, sel
);
1114 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1116 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1117 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1119 if (rctx
->tes_shader
== sel
) {
1120 rctx
->tes_shader
= NULL
;
1123 r600_delete_shader_selector(ctx
, sel
);
1126 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1128 if (state
->dirty_mask
) {
1129 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1130 : util_bitcount(state
->dirty_mask
)*19;
1131 r600_mark_atom_dirty(rctx
, &state
->atom
);
1135 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1136 enum pipe_shader_type shader
, uint index
,
1137 const struct pipe_constant_buffer
*input
)
1139 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1140 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1141 struct pipe_constant_buffer
*cb
;
1144 /* Note that the state tracker can unbind constant buffers by
1145 * passing NULL here.
1147 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1148 state
->enabled_mask
&= ~(1 << index
);
1149 state
->dirty_mask
&= ~(1 << index
);
1150 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1154 cb
= &state
->cb
[index
];
1155 cb
->buffer_size
= input
->buffer_size
;
1157 ptr
= input
->user_buffer
;
1160 /* Upload the user buffer. */
1161 if (R600_BIG_ENDIAN
) {
1163 unsigned i
, size
= input
->buffer_size
;
1165 if (!(tmpPtr
= malloc(size
))) {
1166 R600_ERR("Failed to allocate BE swap buffer.\n");
1170 for (i
= 0; i
< size
/ 4; ++i
) {
1171 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1174 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1175 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1178 u_upload_data(ctx
->stream_uploader
, 0,
1179 input
->buffer_size
, 256, ptr
,
1180 &cb
->buffer_offset
, &cb
->buffer
);
1182 /* account it in gtt */
1183 rctx
->b
.gtt
+= input
->buffer_size
;
1185 /* Setup the hw buffer. */
1186 cb
->buffer_offset
= input
->buffer_offset
;
1187 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1188 r600_context_add_resource_size(ctx
, input
->buffer
);
1191 state
->enabled_mask
|= 1 << index
;
1192 state
->dirty_mask
|= 1 << index
;
1193 r600_constant_buffers_dirty(rctx
, state
);
1196 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1198 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1200 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1203 rctx
->sample_mask
.sample_mask
= sample_mask
;
1204 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1207 static void r600_update_driver_const_buffers(struct r600_context
*rctx
)
1211 struct pipe_constant_buffer cb
;
1212 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
1213 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1214 if (!info
->vs_ucp_dirty
&&
1215 !info
->texture_const_dirty
&&
1216 !info
->ps_sample_pos_dirty
)
1219 ptr
= info
->constants
;
1220 size
= info
->alloc_size
;
1221 if (info
->vs_ucp_dirty
) {
1222 assert(sh
== PIPE_SHADER_VERTEX
);
1224 ptr
= rctx
->clip_state
.state
.ucp
;
1225 size
= R600_UCP_SIZE
;
1227 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1229 info
->vs_ucp_dirty
= false;
1232 if (info
->ps_sample_pos_dirty
) {
1233 assert(sh
== PIPE_SHADER_FRAGMENT
);
1235 ptr
= rctx
->sample_positions
;
1236 size
= R600_UCP_SIZE
;
1238 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1240 info
->ps_sample_pos_dirty
= false;
1243 if (info
->texture_const_dirty
) {
1246 if (sh
== PIPE_SHADER_VERTEX
)
1247 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1248 if (sh
== PIPE_SHADER_FRAGMENT
)
1249 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1251 info
->texture_const_dirty
= false;
1254 cb
.user_buffer
= ptr
;
1255 cb
.buffer_offset
= 0;
1256 cb
.buffer_size
= size
;
1257 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1258 pipe_resource_reference(&cb
.buffer
, NULL
);
1262 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1263 int array_size
, uint32_t *base_offset
)
1265 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1266 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1267 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1268 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1270 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1271 info
->texture_const_dirty
= true;
1272 *base_offset
= R600_UCP_SIZE
;
1273 return info
->constants
;
1276 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1277 * doesn't require full swizzles it does need masking and setting alpha
1278 * to one, so we setup a set of 5 constants with the masks + alpha value
1279 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1280 * then OR the alpha with the value given here.
1281 * We use a 6th constant to store the txq buffer size in
1282 * we use 7th slot for number of cube layers in a cube map array.
1284 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1286 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1288 uint32_t array_size
;
1290 uint32_t *constants
;
1291 uint32_t base_offset
;
1292 if (!samplers
->views
.dirty_buffer_constants
)
1295 samplers
->views
.dirty_buffer_constants
= FALSE
;
1297 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1298 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1300 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1302 for (i
= 0; i
< bits
; i
++) {
1303 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1304 int offset
= (base_offset
/ 4) + i
* 8;
1305 const struct util_format_description
*desc
;
1306 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1308 for (j
= 0; j
< 4; j
++)
1309 if (j
< desc
->nr_channels
)
1310 constants
[offset
+j
] = 0xffffffff;
1312 constants
[offset
+j
] = 0x0;
1313 if (desc
->nr_channels
< 4) {
1314 if (desc
->channel
[0].pure_integer
)
1315 constants
[offset
+4] = 1;
1317 constants
[offset
+4] = fui(1.0);
1319 constants
[offset
+ 4] = 0;
1321 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1322 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1328 /* On evergreen we store two values
1329 * 1. buffer size for TXQ
1330 * 2. number of cube layers in a cube map array.
1332 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1334 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1335 struct r600_image_state
*images
= NULL
;
1336 int bits
, sview_bits
;
1337 uint32_t array_size
;
1339 uint32_t *constants
;
1340 uint32_t base_offset
;
1342 if (shader_type
== PIPE_SHADER_FRAGMENT
)
1343 images
= &rctx
->fragment_images
;
1345 if (!samplers
->views
.dirty_buffer_constants
&&
1346 (images
&& !images
->dirty_buffer_constants
))
1350 images
->dirty_buffer_constants
= FALSE
;
1351 samplers
->views
.dirty_buffer_constants
= FALSE
;
1353 bits
= sview_bits
= util_last_bit(samplers
->views
.enabled_mask
);
1355 bits
+= util_last_bit(images
->enabled_mask
);
1356 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1358 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1361 for (i
= 0; i
< sview_bits
; i
++) {
1362 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1363 uint32_t offset
= (base_offset
/ 4) + i
* 2;
1364 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1365 constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1369 for (i
= sview_bits
; i
< bits
; i
++) {
1370 int idx
= i
- sview_bits
;
1371 if (images
->enabled_mask
& (1 << idx
)) {
1372 uint32_t offset
= (base_offset
/ 4) + i
* 2;
1373 constants
[offset
] = images
->views
[i
].base
.resource
->width0
/ util_format_get_blocksize(images
->views
[i
].base
.format
);
1374 constants
[offset
+ 1] = images
->views
[i
].base
.resource
->array_size
/ 6;
1380 /* set sample xy locations as array of fragment shader constants */
1381 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1384 struct pipe_context
*ctx
= &rctx
->b
.b
;
1386 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1387 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1389 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1390 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1391 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1392 /* Also fill in center-zeroed positions used for interpolateAtSample */
1393 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1394 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1397 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1400 static void update_shader_atom(struct pipe_context
*ctx
,
1401 struct r600_shader_state
*state
,
1402 struct r600_pipe_shader
*shader
)
1404 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1406 state
->shader
= shader
;
1408 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1409 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1411 state
->atom
.num_dw
= 0;
1413 r600_mark_atom_dirty(rctx
, &state
->atom
);
1416 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1418 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1419 rctx
->shader_stages
.geom_enable
= enable
;
1420 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1423 if (rctx
->gs_rings
.enable
!= enable
) {
1424 rctx
->gs_rings
.enable
= enable
;
1425 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1427 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1428 unsigned size
= 0x1C000;
1429 rctx
->gs_rings
.esgs_ring
.buffer
=
1430 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1431 PIPE_USAGE_DEFAULT
, size
);
1432 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1436 rctx
->gs_rings
.gsvs_ring
.buffer
=
1437 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1438 PIPE_USAGE_DEFAULT
, size
);
1439 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1443 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1444 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1445 if (rctx
->tes_shader
) {
1446 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1447 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1449 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1450 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1453 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1454 R600_GS_RING_CONST_BUFFER
, NULL
);
1455 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1456 R600_GS_RING_CONST_BUFFER
, NULL
);
1457 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1458 R600_GS_RING_CONST_BUFFER
, NULL
);
1463 static void r600_update_clip_state(struct r600_context
*rctx
,
1464 struct r600_pipe_shader
*current
)
1466 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1467 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1468 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1469 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1470 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1471 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1472 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1473 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1474 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1478 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1480 struct ureg_src const0
, const1
;
1481 struct ureg_dst tessouter
, tessinner
;
1482 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1485 return; /* if we get here, we're screwed */
1487 assert(!rctx
->fixed_func_tcs_shader
);
1489 ureg_DECL_constant2D(ureg
, 0, 3, R600_LDS_INFO_CONST_BUFFER
);
1490 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 2),
1491 R600_LDS_INFO_CONST_BUFFER
);
1492 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 3),
1493 R600_LDS_INFO_CONST_BUFFER
);
1495 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1496 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1498 ureg_MOV(ureg
, tessouter
, const0
);
1499 ureg_MOV(ureg
, tessinner
, const1
);
1502 rctx
->fixed_func_tcs_shader
=
1503 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1506 static void r600_update_compressed_resource_state(struct r600_context
*rctx
)
1511 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1512 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1513 rctx
->b
.last_compressed_colortex_counter
= counter
;
1515 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1516 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1518 r600_update_compressed_colortex_mask_images(&rctx
->fragment_images
);
1521 /* Decompress textures if needed. */
1522 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1523 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1524 if (views
->compressed_depthtex_mask
) {
1525 r600_decompress_depth_textures(rctx
, views
);
1527 if (views
->compressed_colortex_mask
) {
1528 r600_decompress_color_textures(rctx
, views
);
1533 struct r600_image_state
*istate
;
1534 istate
= &rctx
->fragment_images
;
1535 if (istate
->compressed_depthtex_mask
)
1536 r600_decompress_depth_images(rctx
, istate
);
1537 if (istate
->compressed_colortex_mask
)
1538 r600_decompress_color_images(rctx
, istate
);
1542 #define SELECT_SHADER_OR_FAIL(x) do { \
1543 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1544 if (unlikely(!rctx->x##_shader->current)) \
1548 #define UPDATE_SHADER(hw, sw) do { \
1549 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1550 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1553 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1554 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1555 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1556 clip_so_current = rctx->sw##_shader->current; \
1560 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1561 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1562 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1563 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1564 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1568 #define SET_NULL_SHADER(hw) do { \
1569 if (rctx->hw_shader_stages[(hw)].shader) \
1570 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1573 static bool r600_update_derived_state(struct r600_context
*rctx
)
1575 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1576 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1577 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1579 bool need_buf_const
;
1580 struct r600_pipe_shader
*clip_so_current
= NULL
;
1582 if (!rctx
->blitter
->running
)
1583 r600_update_compressed_resource_state(rctx
);
1585 SELECT_SHADER_OR_FAIL(ps
);
1587 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1589 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1591 if (rctx
->gs_shader
)
1592 SELECT_SHADER_OR_FAIL(gs
);
1595 if (rctx
->tcs_shader
) {
1596 SELECT_SHADER_OR_FAIL(tcs
);
1598 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1599 } else if (rctx
->tes_shader
) {
1600 if (!rctx
->fixed_func_tcs_shader
) {
1601 r600_generate_fixed_func_tcs(rctx
);
1602 if (!rctx
->fixed_func_tcs_shader
)
1606 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1608 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1610 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1612 if (rctx
->tes_shader
) {
1613 SELECT_SHADER_OR_FAIL(tes
);
1616 SELECT_SHADER_OR_FAIL(vs
);
1618 if (rctx
->gs_shader
) {
1619 if (!rctx
->shader_stages
.geom_enable
) {
1620 rctx
->shader_stages
.geom_enable
= true;
1621 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1624 /* gs_shader provides GS and VS (copy shader) */
1625 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1627 /* vs_shader is used as ES */
1629 if (rctx
->tes_shader
) {
1630 /* VS goes to LS, TES goes to ES */
1631 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1632 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1634 /* vs_shader is used as ES */
1635 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1636 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1639 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1640 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1641 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1642 rctx
->shader_stages
.geom_enable
= false;
1643 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1646 if (rctx
->tes_shader
) {
1647 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1648 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1649 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1651 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1652 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1656 /* Update clip misc state. */
1657 if (clip_so_current
) {
1658 r600_update_clip_state(rctx
, clip_so_current
);
1659 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1662 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1663 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1664 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1666 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1667 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1668 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1671 if (rctx
->b
.chip_class
<= R700
) {
1672 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1674 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1675 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1676 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1680 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1681 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1682 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1684 if (rctx
->b
.chip_class
>= EVERGREEN
)
1685 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1687 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1690 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1692 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1694 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1695 evergreen_update_db_shader_control(rctx
);
1697 r600_update_db_shader_control(rctx
);
1700 /* on R600 we stuff masks + txq info into one constant buffer */
1701 /* on evergreen we only need a txq info one */
1702 if (rctx
->ps_shader
) {
1703 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1704 if (need_buf_const
) {
1705 if (rctx
->b
.chip_class
< EVERGREEN
)
1706 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1708 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1712 if (rctx
->vs_shader
) {
1713 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1714 if (need_buf_const
) {
1715 if (rctx
->b
.chip_class
< EVERGREEN
)
1716 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1718 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1722 if (rctx
->gs_shader
) {
1723 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1724 if (need_buf_const
) {
1725 if (rctx
->b
.chip_class
< EVERGREEN
)
1726 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1728 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1732 r600_update_driver_const_buffers(rctx
);
1734 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1735 if (!r600_adjust_gprs(rctx
)) {
1736 /* discard rendering */
1741 if (rctx
->b
.chip_class
== EVERGREEN
) {
1742 if (!evergreen_adjust_gprs(rctx
)) {
1743 /* discard rendering */
1748 blend_disable
= (rctx
->dual_src_blend
&&
1749 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1751 if (blend_disable
!= rctx
->force_blend_disable
) {
1752 rctx
->force_blend_disable
= blend_disable
;
1753 r600_bind_blend_state_internal(rctx
,
1754 rctx
->blend_state
.cso
,
1761 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1763 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1764 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1766 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1767 state
->pa_cl_clip_cntl
|
1768 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1769 S_028810_CLIP_DISABLE(state
->clip_disable
));
1770 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1771 state
->pa_cl_vs_out_cntl
|
1772 (state
->clip_plane_enable
& state
->clip_dist_write
));
1773 /* reuse needs to be set off if we write oViewport */
1774 if (rctx
->b
.chip_class
>= EVERGREEN
)
1775 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1776 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1779 /* rast_prim is the primitive type after GS. */
1780 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
1782 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1783 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
1785 /* Skip this if not rendering lines. */
1786 if (rast_prim
!= PIPE_PRIM_LINES
&&
1787 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
1788 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
1789 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
1790 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
1793 if (rast_prim
== rctx
->last_rast_prim
)
1796 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1797 * reset the stipple pattern at each packet (line strips, line loops).
1799 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1800 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
1801 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1802 rctx
->last_rast_prim
= rast_prim
;
1805 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1807 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1808 struct pipe_resource
*indexbuf
= info
->has_user_indices
? NULL
: info
->index
.resource
;
1809 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1810 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
1811 bool has_user_indices
= info
->has_user_indices
;
1813 unsigned num_patches
, dirty_tex_counter
, index_offset
= 0;
1814 unsigned index_size
= info
->index_size
;
1816 struct r600_shader_atomic combined_atomics
[8];
1817 uint8_t atomic_used_mask
;
1819 if (!info
->indirect
&& !info
->count
&& (index_size
|| !info
->count_from_stream_output
)) {
1823 if (unlikely(!rctx
->vs_shader
)) {
1827 if (unlikely(!rctx
->ps_shader
&&
1828 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
1833 /* make sure that the gfx ring is only one active */
1834 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
1835 rctx
->b
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1838 /* Re-emit the framebuffer state if needed. */
1839 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
1840 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
1841 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1842 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1843 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
1846 if (rctx
->gs_shader
) {
1847 /* Determine whether the GS triangle strip adjacency fix should
1848 * be applied. Rotate every other triangle if
1849 * - triangle strips with adjacency are fed to the GS and
1850 * - primitive restart is disabled (the rotation doesn't help
1851 * when the restart occurs after an odd number of triangles).
1853 bool gs_tri_strip_adj_fix
=
1854 !rctx
->tes_shader
&&
1855 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1856 !info
->primitive_restart
;
1857 if (gs_tri_strip_adj_fix
!= rctx
->gs_tri_strip_adj_fix
)
1858 rctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1860 if (!r600_update_derived_state(rctx
)) {
1861 /* useless to render because current rendering command
1867 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
1868 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
1871 if (rctx
->b
.chip_class
>= EVERGREEN
)
1872 evergreen_emit_atomic_buffer_setup(rctx
, combined_atomics
, &atomic_used_mask
);
1875 index_offset
+= info
->start
* index_size
;
1877 /* Translate 8-bit indices to 16-bit. */
1878 if (unlikely(index_size
== 1)) {
1879 struct pipe_resource
*out_buffer
= NULL
;
1880 unsigned out_offset
;
1882 unsigned start
, count
;
1884 if (likely(!info
->indirect
)) {
1886 count
= info
->count
;
1889 /* Have to get start/count from indirect buffer, slow path ahead... */
1890 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
->buffer
;
1891 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1892 PIPE_TRANSFER_READ
);
1894 data
+= info
->indirect
->offset
/ sizeof(unsigned);
1895 start
= data
[2] * index_size
;
1904 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
1905 256, &out_offset
, &out_buffer
, &ptr
);
1909 util_shorten_ubyte_elts_to_userptr(
1910 &rctx
->b
.b
, info
, 0, 0, index_offset
, count
, ptr
);
1912 indexbuf
= out_buffer
;
1913 index_offset
= out_offset
;
1915 has_user_indices
= false;
1918 /* Upload the index buffer.
1919 * The upload is skipped for small index counts on little-endian machines
1920 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1921 * Indirect draws never use immediate indices.
1922 * Note: Instanced rendering in combination with immediate indices hangs. */
1923 if (has_user_indices
&& (R600_BIG_ENDIAN
|| info
->indirect
||
1924 info
->instance_count
> 1 ||
1925 info
->count
*index_size
> 20)) {
1927 u_upload_data(ctx
->stream_uploader
, 0,
1928 info
->count
* index_size
, 256,
1929 info
->index
.user
, &index_offset
, &indexbuf
);
1930 has_user_indices
= false;
1932 index_bias
= info
->index_bias
;
1934 index_bias
= info
->start
;
1937 /* Set the index offset and primitive restart. */
1938 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
1939 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
1940 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
1941 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
1942 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
1943 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
1944 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
1945 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1948 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1949 if (rctx
->b
.chip_class
== R600
) {
1950 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1951 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1954 if (rctx
->b
.chip_class
>= EVERGREEN
)
1955 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
1958 r600_need_cs_space(rctx
, has_user_indices
? 5 : 0, TRUE
);
1959 r600_flush_emit(rctx
);
1961 mask
= rctx
->dirty_atoms
;
1963 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
1966 if (rctx
->b
.chip_class
== CAYMAN
) {
1967 /* Copied from radeonsi. */
1968 unsigned primgroup_size
= 128; /* recommended without a GS */
1969 bool ia_switch_on_eop
= false;
1970 bool partial_vs_wave
= false;
1972 if (rctx
->gs_shader
)
1973 primgroup_size
= 64; /* recommended with a GS */
1975 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1976 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1977 ia_switch_on_eop
= true;
1980 if (r600_get_strmout_en(&rctx
->b
))
1981 partial_vs_wave
= true;
1983 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1984 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1985 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1986 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1989 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1990 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
1993 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
1994 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
1997 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1998 * even though it should have no effect on those. */
1999 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
2000 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
2001 unsigned prim
= info
->mode
;
2003 if (rctx
->gs_shader
) {
2004 prim
= rctx
->gs_shader
->gs_output_prim
;
2006 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
2008 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
2009 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
2010 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
2011 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
2013 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
2016 /* Update start instance. */
2017 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
2018 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
2019 rctx
->last_start_instance
= info
->start_instance
;
2022 /* Update the primitive type. */
2023 if (rctx
->last_primitive_type
!= info
->mode
) {
2024 r600_emit_rasterizer_prim_state(rctx
);
2025 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
2026 r600_conv_pipe_prim(info
->mode
));
2028 rctx
->last_primitive_type
= info
->mode
;
2032 if (likely(!info
->indirect
)) {
2033 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2034 radeon_emit(cs
, info
->instance_count
);
2036 uint64_t va
= r600_resource(info
->indirect
->buffer
)->gpu_address
;
2037 assert(rctx
->b
.chip_class
>= EVERGREEN
);
2039 // Invalidate so non-indirect draw calls reset this state
2040 rctx
->vgt_state
.last_draw_was_indirect
= true;
2041 rctx
->last_start_instance
= -1;
2043 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
2044 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
2045 radeon_emit(cs
, va
);
2046 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2048 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2049 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2050 (struct r600_resource
*)info
->indirect
->buffer
,
2052 RADEON_PRIO_DRAW_INDIRECT
));
2056 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2057 radeon_emit(cs
, index_size
== 4 ?
2058 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
2059 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
2061 if (has_user_indices
) {
2062 unsigned size_bytes
= info
->count
*index_size
;
2063 unsigned size_dw
= align(size_bytes
, 4) / 4;
2064 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
2065 radeon_emit(cs
, info
->count
);
2066 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
2067 radeon_emit_array(cs
, info
->index
.user
, size_dw
);
2069 uint64_t va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
2071 if (likely(!info
->indirect
)) {
2072 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
2073 radeon_emit(cs
, va
);
2074 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2075 radeon_emit(cs
, info
->count
);
2076 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2077 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2078 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2079 (struct r600_resource
*)indexbuf
,
2081 RADEON_PRIO_INDEX_BUFFER
));
2084 uint32_t max_size
= (indexbuf
->width0
- index_offset
) / index_size
;
2086 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
2087 radeon_emit(cs
, va
);
2088 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2090 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2091 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2092 (struct r600_resource
*)indexbuf
,
2094 RADEON_PRIO_INDEX_BUFFER
));
2096 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2097 radeon_emit(cs
, max_size
);
2099 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
2100 radeon_emit(cs
, info
->indirect
->offset
);
2101 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2105 if (unlikely(info
->count_from_stream_output
)) {
2106 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
2107 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
2109 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
2111 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
2112 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
2113 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
2114 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
2115 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
2116 radeon_emit(cs
, 0); /* unused */
2118 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2119 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2120 t
->buf_filled_size
, RADEON_USAGE_READ
,
2121 RADEON_PRIO_SO_FILLED_SIZE
));
2124 if (likely(!info
->indirect
)) {
2125 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
2126 radeon_emit(cs
, info
->count
);
2129 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
2130 radeon_emit(cs
, info
->indirect
->offset
);
2132 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2133 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2136 /* SMX returns CONTEXT_DONE too early workaround */
2137 if (rctx
->b
.family
== CHIP_R600
||
2138 rctx
->b
.family
== CHIP_RV610
||
2139 rctx
->b
.family
== CHIP_RV630
||
2140 rctx
->b
.family
== CHIP_RV635
) {
2141 /* if we have gs shader or streamout
2142 we need to do a wait idle after every draw */
2143 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2144 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2148 /* ES ring rolling over at EOP - workaround */
2149 if (rctx
->b
.chip_class
== R600
) {
2150 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2151 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2155 if (rctx
->b
.chip_class
>= EVERGREEN
)
2156 evergreen_emit_atomic_buffer_save(rctx
, combined_atomics
, &atomic_used_mask
);
2158 if (rctx
->trace_buf
)
2159 eg_trace_emit(rctx
);
2161 if (rctx
->framebuffer
.do_update_surf_dirtiness
) {
2162 /* Set the depth buffer as dirty. */
2163 if (rctx
->framebuffer
.state
.zsbuf
) {
2164 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2165 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2167 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2169 if (rtex
->surface
.has_stencil
)
2170 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2172 if (rctx
->framebuffer
.compressed_cb_mask
) {
2173 struct pipe_surface
*surf
;
2174 struct r600_texture
*rtex
;
2175 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2178 unsigned i
= u_bit_scan(&mask
);
2179 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2180 rtex
= (struct r600_texture
*)surf
->texture
;
2182 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2186 rctx
->framebuffer
.do_update_surf_dirtiness
= false;
2189 if (index_size
&& indexbuf
!= info
->index
.resource
)
2190 pipe_resource_reference(&indexbuf
, NULL
);
2191 rctx
->b
.num_draw_calls
++;
2194 uint32_t r600_translate_stencil_op(int s_op
)
2197 case PIPE_STENCIL_OP_KEEP
:
2198 return V_028800_STENCIL_KEEP
;
2199 case PIPE_STENCIL_OP_ZERO
:
2200 return V_028800_STENCIL_ZERO
;
2201 case PIPE_STENCIL_OP_REPLACE
:
2202 return V_028800_STENCIL_REPLACE
;
2203 case PIPE_STENCIL_OP_INCR
:
2204 return V_028800_STENCIL_INCR
;
2205 case PIPE_STENCIL_OP_DECR
:
2206 return V_028800_STENCIL_DECR
;
2207 case PIPE_STENCIL_OP_INCR_WRAP
:
2208 return V_028800_STENCIL_INCR_WRAP
;
2209 case PIPE_STENCIL_OP_DECR_WRAP
:
2210 return V_028800_STENCIL_DECR_WRAP
;
2211 case PIPE_STENCIL_OP_INVERT
:
2212 return V_028800_STENCIL_INVERT
;
2214 R600_ERR("Unknown stencil op %d", s_op
);
2221 uint32_t r600_translate_fill(uint32_t func
)
2224 case PIPE_POLYGON_MODE_FILL
:
2226 case PIPE_POLYGON_MODE_LINE
:
2228 case PIPE_POLYGON_MODE_POINT
:
2236 unsigned r600_tex_wrap(unsigned wrap
)
2240 case PIPE_TEX_WRAP_REPEAT
:
2241 return V_03C000_SQ_TEX_WRAP
;
2242 case PIPE_TEX_WRAP_CLAMP
:
2243 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2244 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2245 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2246 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2247 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2248 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2249 return V_03C000_SQ_TEX_MIRROR
;
2250 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2251 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2252 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2253 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2254 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2255 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2259 unsigned r600_tex_mipfilter(unsigned filter
)
2262 case PIPE_TEX_MIPFILTER_NEAREST
:
2263 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2264 case PIPE_TEX_MIPFILTER_LINEAR
:
2265 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2267 case PIPE_TEX_MIPFILTER_NONE
:
2268 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2272 unsigned r600_tex_compare(unsigned compare
)
2276 case PIPE_FUNC_NEVER
:
2277 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2278 case PIPE_FUNC_LESS
:
2279 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2280 case PIPE_FUNC_EQUAL
:
2281 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2282 case PIPE_FUNC_LEQUAL
:
2283 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2284 case PIPE_FUNC_GREATER
:
2285 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2286 case PIPE_FUNC_NOTEQUAL
:
2287 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2288 case PIPE_FUNC_GEQUAL
:
2289 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2290 case PIPE_FUNC_ALWAYS
:
2291 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2295 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2297 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2298 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2300 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2301 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2304 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2306 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2307 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2309 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2310 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2311 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2312 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2313 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2316 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2319 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2320 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2325 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2326 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2327 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2328 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2331 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2332 const unsigned char *swizzle_view
,
2336 unsigned char swizzle
[4];
2337 unsigned result
= 0;
2338 const uint32_t tex_swizzle_shift
[4] = {
2341 const uint32_t vtx_swizzle_shift
[4] = {
2344 const uint32_t swizzle_bit
[4] = {
2347 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2350 swizzle_shift
= vtx_swizzle_shift
;
2353 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2355 memcpy(swizzle
, swizzle_format
, 4);
2359 for (i
= 0; i
< 4; i
++) {
2360 switch (swizzle
[i
]) {
2361 case PIPE_SWIZZLE_Y
:
2362 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2364 case PIPE_SWIZZLE_Z
:
2365 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2367 case PIPE_SWIZZLE_W
:
2368 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2370 case PIPE_SWIZZLE_0
:
2371 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2373 case PIPE_SWIZZLE_1
:
2374 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2376 default: /* PIPE_SWIZZLE_X */
2377 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2383 /* texture format translate */
2384 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2385 enum pipe_format format
,
2386 const unsigned char *swizzle_view
,
2387 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2388 bool do_endian_swap
)
2390 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2391 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2392 const struct util_format_description
*desc
;
2393 boolean uniform
= TRUE
;
2394 bool is_srgb_valid
= FALSE
;
2395 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2396 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2397 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2398 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2399 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2402 const uint32_t sign_bit
[4] = {
2403 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2404 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2405 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2406 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2409 /* Need to replace the specified texture formats in case of big-endian.
2410 * These formats are formats that have channels with number of bits
2411 * not divisible by 8.
2412 * Mesa conversion functions don't swap bits for those formats, and because
2413 * we transmit this over a serial bus to the GPU (PCIe), the
2414 * bit-endianess is important!!!
2415 * In case we have an "opposite" format, just use that for the swizzling
2416 * information. If we don't have such an "opposite" format, we need
2417 * to use a fixed swizzle info instead (see below)
2419 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2420 format
= PIPE_FORMAT_A4R4_UNORM
;
2422 desc
= util_format_description(format
);
2426 /* Depth and stencil swizzling is handled separately. */
2427 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2428 /* Need to check for specific texture formats that don't have
2429 * an "opposite" format we can use. For those formats, we directly
2430 * specify the swizzling, which is the LE swizzling as defined in
2433 if (do_endian_swap
) {
2434 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2435 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2436 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2437 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2438 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2439 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2441 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2443 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2447 /* Colorspace (return non-RGB formats directly). */
2448 switch (desc
->colorspace
) {
2449 /* Depth stencil formats */
2450 case UTIL_FORMAT_COLORSPACE_ZS
:
2452 /* Depth sampler formats. */
2453 case PIPE_FORMAT_Z16_UNORM
:
2454 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2457 case PIPE_FORMAT_Z24X8_UNORM
:
2458 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2459 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2462 case PIPE_FORMAT_X8Z24_UNORM
:
2463 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2464 if (rscreen
->b
.chip_class
< EVERGREEN
)
2466 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2469 case PIPE_FORMAT_Z32_FLOAT
:
2470 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2471 result
= FMT_32_FLOAT
;
2473 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2474 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2475 result
= FMT_X24_8_32_FLOAT
;
2477 /* Stencil sampler formats. */
2478 case PIPE_FORMAT_S8_UINT
:
2479 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2480 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2483 case PIPE_FORMAT_X24S8_UINT
:
2484 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2485 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2488 case PIPE_FORMAT_S8X24_UINT
:
2489 if (rscreen
->b
.chip_class
< EVERGREEN
)
2491 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2492 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2495 case PIPE_FORMAT_X32_S8X24_UINT
:
2496 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2497 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2498 result
= FMT_X24_8_32_FLOAT
;
2504 case UTIL_FORMAT_COLORSPACE_YUV
:
2505 yuv_format
|= (1 << 30);
2507 case PIPE_FORMAT_UYVY
:
2508 case PIPE_FORMAT_YUYV
:
2512 goto out_unknown
; /* XXX */
2514 case UTIL_FORMAT_COLORSPACE_SRGB
:
2515 word4
|= S_038010_FORCE_DEGAMMA(1);
2522 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2524 case PIPE_FORMAT_RGTC1_SNORM
:
2525 case PIPE_FORMAT_LATC1_SNORM
:
2526 word4
|= sign_bit
[0];
2527 case PIPE_FORMAT_RGTC1_UNORM
:
2528 case PIPE_FORMAT_LATC1_UNORM
:
2531 case PIPE_FORMAT_RGTC2_SNORM
:
2532 case PIPE_FORMAT_LATC2_SNORM
:
2533 word4
|= sign_bit
[0] | sign_bit
[1];
2534 case PIPE_FORMAT_RGTC2_UNORM
:
2535 case PIPE_FORMAT_LATC2_UNORM
:
2543 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2545 case PIPE_FORMAT_DXT1_RGB
:
2546 case PIPE_FORMAT_DXT1_RGBA
:
2547 case PIPE_FORMAT_DXT1_SRGB
:
2548 case PIPE_FORMAT_DXT1_SRGBA
:
2550 is_srgb_valid
= TRUE
;
2552 case PIPE_FORMAT_DXT3_RGBA
:
2553 case PIPE_FORMAT_DXT3_SRGBA
:
2555 is_srgb_valid
= TRUE
;
2557 case PIPE_FORMAT_DXT5_RGBA
:
2558 case PIPE_FORMAT_DXT5_SRGBA
:
2560 is_srgb_valid
= TRUE
;
2567 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2568 if (rscreen
->b
.chip_class
< EVERGREEN
)
2572 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2573 case PIPE_FORMAT_BPTC_SRGBA
:
2575 is_srgb_valid
= TRUE
;
2577 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2578 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2580 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2588 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2590 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2591 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2594 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2595 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2603 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2604 result
= FMT_5_9_9_9_SHAREDEXP
;
2606 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2607 result
= FMT_10_11_11_FLOAT
;
2612 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2613 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2614 word4
|= sign_bit
[i
];
2618 /* R8G8Bx_SNORM - XXX CxV8U8 */
2620 /* See whether the components are of the same size. */
2621 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2622 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2625 /* Non-uniform formats. */
2627 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2628 desc
->channel
[0].pure_integer
)
2629 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2630 switch(desc
->nr_channels
) {
2632 if (desc
->channel
[0].size
== 5 &&
2633 desc
->channel
[1].size
== 6 &&
2634 desc
->channel
[2].size
== 5) {
2640 if (desc
->channel
[0].size
== 5 &&
2641 desc
->channel
[1].size
== 5 &&
2642 desc
->channel
[2].size
== 5 &&
2643 desc
->channel
[3].size
== 1) {
2644 result
= FMT_1_5_5_5
;
2647 if (desc
->channel
[0].size
== 10 &&
2648 desc
->channel
[1].size
== 10 &&
2649 desc
->channel
[2].size
== 10 &&
2650 desc
->channel
[3].size
== 2) {
2651 result
= FMT_2_10_10_10
;
2659 /* Find the first non-VOID channel. */
2660 for (i
= 0; i
< 4; i
++) {
2661 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2669 /* uniform formats */
2670 switch (desc
->channel
[i
].type
) {
2671 case UTIL_FORMAT_TYPE_UNSIGNED
:
2672 case UTIL_FORMAT_TYPE_SIGNED
:
2674 if (!desc
->channel
[i
].normalized
&&
2675 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2679 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2680 desc
->channel
[i
].pure_integer
)
2681 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2683 switch (desc
->channel
[i
].size
) {
2685 switch (desc
->nr_channels
) {
2690 result
= FMT_4_4_4_4
;
2695 switch (desc
->nr_channels
) {
2703 result
= FMT_8_8_8_8
;
2704 is_srgb_valid
= TRUE
;
2709 switch (desc
->nr_channels
) {
2717 result
= FMT_16_16_16_16
;
2722 switch (desc
->nr_channels
) {
2730 result
= FMT_32_32_32_32
;
2736 case UTIL_FORMAT_TYPE_FLOAT
:
2737 switch (desc
->channel
[i
].size
) {
2739 switch (desc
->nr_channels
) {
2741 result
= FMT_16_FLOAT
;
2744 result
= FMT_16_16_FLOAT
;
2747 result
= FMT_16_16_16_16_FLOAT
;
2752 switch (desc
->nr_channels
) {
2754 result
= FMT_32_FLOAT
;
2757 result
= FMT_32_32_FLOAT
;
2760 result
= FMT_32_32_32_32_FLOAT
;
2769 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2774 *yuv_format_p
= yuv_format
;
2777 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2781 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
2782 bool do_endian_swap
)
2784 const struct util_format_description
*desc
= util_format_description(format
);
2785 int channel
= util_format_get_first_non_void_channel(format
);
2790 #define HAS_SIZE(x,y,z,w) \
2791 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2792 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2794 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2795 return V_0280A0_COLOR_10_11_11_FLOAT
;
2797 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2801 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2803 switch (desc
->nr_channels
) {
2805 switch (desc
->channel
[0].size
) {
2807 return V_0280A0_COLOR_8
;
2810 return V_0280A0_COLOR_16_FLOAT
;
2812 return V_0280A0_COLOR_16
;
2815 return V_0280A0_COLOR_32_FLOAT
;
2817 return V_0280A0_COLOR_32
;
2821 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2822 switch (desc
->channel
[0].size
) {
2825 return V_0280A0_COLOR_4_4
;
2827 return ~0U; /* removed on Evergreen */
2829 return V_0280A0_COLOR_8_8
;
2832 return V_0280A0_COLOR_16_16_FLOAT
;
2834 return V_0280A0_COLOR_16_16
;
2837 return V_0280A0_COLOR_32_32_FLOAT
;
2839 return V_0280A0_COLOR_32_32
;
2841 } else if (HAS_SIZE(8,24,0,0)) {
2842 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
2843 } else if (HAS_SIZE(24,8,0,0)) {
2844 return V_0280A0_COLOR_8_24
;
2848 if (HAS_SIZE(5,6,5,0)) {
2849 return V_0280A0_COLOR_5_6_5
;
2850 } else if (HAS_SIZE(32,8,24,0)) {
2851 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2855 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2856 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2857 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2858 switch (desc
->channel
[0].size
) {
2860 return V_0280A0_COLOR_4_4_4_4
;
2862 return V_0280A0_COLOR_8_8_8_8
;
2865 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2867 return V_0280A0_COLOR_16_16_16_16
;
2870 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2872 return V_0280A0_COLOR_32_32_32_32
;
2874 } else if (HAS_SIZE(5,5,5,1)) {
2875 return V_0280A0_COLOR_1_5_5_5
;
2876 } else if (HAS_SIZE(10,10,10,2)) {
2877 return V_0280A0_COLOR_2_10_10_10
;
2884 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
2886 if (R600_BIG_ENDIAN
) {
2887 switch(colorformat
) {
2888 /* 8-bit buffers. */
2889 case V_0280A0_COLOR_4_4
:
2890 case V_0280A0_COLOR_8
:
2893 /* 16-bit buffers. */
2894 case V_0280A0_COLOR_8_8
:
2896 * No need to do endian swaps on array formats,
2897 * as mesa<-->pipe formats conversion take into account
2902 case V_0280A0_COLOR_5_6_5
:
2903 case V_0280A0_COLOR_1_5_5_5
:
2904 case V_0280A0_COLOR_4_4_4_4
:
2905 case V_0280A0_COLOR_16
:
2906 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
2908 /* 32-bit buffers. */
2909 case V_0280A0_COLOR_8_8_8_8
:
2911 * No need to do endian swaps on array formats,
2912 * as mesa<-->pipe formats conversion take into account
2917 case V_0280A0_COLOR_2_10_10_10
:
2918 case V_0280A0_COLOR_8_24
:
2919 case V_0280A0_COLOR_24_8
:
2920 case V_0280A0_COLOR_32_FLOAT
:
2921 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
2923 case V_0280A0_COLOR_16_16_FLOAT
:
2924 case V_0280A0_COLOR_16_16
:
2925 return ENDIAN_8IN16
;
2927 /* 64-bit buffers. */
2928 case V_0280A0_COLOR_16_16_16_16
:
2929 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2930 return ENDIAN_8IN16
;
2932 case V_0280A0_COLOR_32_32_FLOAT
:
2933 case V_0280A0_COLOR_32_32
:
2934 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2935 return ENDIAN_8IN32
;
2937 /* 128-bit buffers. */
2938 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2939 case V_0280A0_COLOR_32_32_32_32
:
2940 return ENDIAN_8IN32
;
2942 return ENDIAN_NONE
; /* Unsupported. */
2949 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2951 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2952 struct r600_resource
*rbuffer
= r600_resource(buf
);
2953 unsigned i
, shader
, mask
;
2954 struct r600_pipe_sampler_view
*view
;
2956 /* Reallocate the buffer in the same pipe_resource. */
2957 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
2959 /* We changed the buffer, now we need to bind it where the old one was bound. */
2960 /* Vertex buffers. */
2961 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2963 i
= u_bit_scan(&mask
);
2964 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
.resource
== &rbuffer
->b
.b
) {
2965 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2966 r600_vertex_buffers_dirty(rctx
);
2969 /* Streamout buffers. */
2970 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2971 if (rctx
->b
.streamout
.targets
[i
] &&
2972 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2973 if (rctx
->b
.streamout
.begin_emitted
) {
2974 r600_emit_streamout_end(&rctx
->b
);
2976 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2977 r600_streamout_buffers_dirty(&rctx
->b
);
2981 /* Constant buffers. */
2982 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2983 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2985 uint32_t mask
= state
->enabled_mask
;
2988 unsigned i
= u_bit_scan(&mask
);
2989 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2991 state
->dirty_mask
|= 1 << i
;
2995 r600_constant_buffers_dirty(rctx
, state
);
2999 /* Texture buffer objects - update the virtual addresses in descriptors. */
3000 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
3001 if (view
->base
.texture
== &rbuffer
->b
.b
) {
3002 uint64_t offset
= view
->base
.u
.buf
.offset
;
3003 uint64_t va
= rbuffer
->gpu_address
+ offset
;
3005 view
->tex_resource_words
[0] = va
;
3006 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
3007 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
3010 /* Texture buffer objects - make bindings dirty if needed. */
3011 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3012 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
3014 uint32_t mask
= state
->enabled_mask
;
3017 unsigned i
= u_bit_scan(&mask
);
3018 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
3020 state
->dirty_mask
|= 1 << i
;
3024 r600_sampler_views_dirty(rctx
, state
);
3029 static void r600_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
3031 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3033 /* Pipeline stat & streamout queries. */
3035 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
3036 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
3038 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
3039 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
3042 /* Occlusion queries. */
3043 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
3044 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
3045 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3049 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3050 bool include_draw_vbo
)
3052 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
3055 /* keep this at the end of this file, please */
3056 void r600_init_common_state_functions(struct r600_context
*rctx
)
3058 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
3059 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
3060 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
3061 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
3062 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
3063 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
3064 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
3065 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
3066 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
3067 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
3068 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
3069 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
3070 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
3071 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
3072 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
3073 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
3074 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
3075 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
3076 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
3077 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
3078 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
3079 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
3080 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
3081 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
3082 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
3083 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
3084 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
3085 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
3086 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
3087 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
3088 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
3089 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
3090 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
3091 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
3092 rctx
->b
.b
.memory_barrier
= r600_memory_barrier
;
3093 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
3094 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
3095 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
3096 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
3097 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
3098 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;