2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "tgsi/tgsi_parse.h"
38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
42 cb
->buf
= CALLOC(1, 4 * num_dw
);
43 cb
->max_num_dw
= num_dw
;
46 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
51 void r600_init_atom(struct r600_context
*rctx
,
52 struct r600_atom
*atom
,
54 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
57 assert(id
< R600_NUM_ATOMS
);
58 assert(rctx
->atoms
[id
] == NULL
);
59 rctx
->atoms
[id
] = atom
;
62 atom
->num_dw
= num_dw
;
66 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
68 r600_emit_command_buffer(rctx
->rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
71 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
73 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
74 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
75 unsigned alpha_ref
= a
->sx_alpha_ref
;
77 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
81 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
82 a
->sx_alpha_test_control
|
83 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
84 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
87 static void r600_texture_barrier(struct pipe_context
*ctx
)
89 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
91 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
92 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
93 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
96 static unsigned r600_conv_pipe_prim(unsigned prim
)
98 static const unsigned prim_conv
[] = {
99 V_008958_DI_PT_POINTLIST
,
100 V_008958_DI_PT_LINELIST
,
101 V_008958_DI_PT_LINELOOP
,
102 V_008958_DI_PT_LINESTRIP
,
103 V_008958_DI_PT_TRILIST
,
104 V_008958_DI_PT_TRISTRIP
,
105 V_008958_DI_PT_TRIFAN
,
106 V_008958_DI_PT_QUADLIST
,
107 V_008958_DI_PT_QUADSTRIP
,
108 V_008958_DI_PT_POLYGON
,
109 V_008958_DI_PT_LINELIST_ADJ
,
110 V_008958_DI_PT_LINESTRIP_ADJ
,
111 V_008958_DI_PT_TRILIST_ADJ
,
112 V_008958_DI_PT_TRISTRIP_ADJ
,
113 V_008958_DI_PT_RECTLIST
115 return prim_conv
[prim
];
118 /* common state between evergreen and r600 */
120 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
121 struct r600_blend_state
*blend
, bool blend_disable
)
123 unsigned color_control
;
124 bool update_cb
= false;
126 rctx
->alpha_to_one
= blend
->alpha_to_one
;
127 rctx
->dual_src_blend
= blend
->dual_src_blend
;
129 if (!blend_disable
) {
130 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
131 color_control
= blend
->cb_color_control
;
133 /* Blending is disabled. */
134 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
135 color_control
= blend
->cb_color_control_no_blend
;
138 /* Update derived states. */
139 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
140 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
143 if (rctx
->chip_class
<= R700
&&
144 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
145 rctx
->cb_misc_state
.cb_color_control
= color_control
;
148 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
149 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
153 rctx
->cb_misc_state
.atom
.dirty
= true;
157 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
159 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
160 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
165 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
168 static void r600_set_blend_color(struct pipe_context
*ctx
,
169 const struct pipe_blend_color
*state
)
171 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
173 rctx
->blend_color
.state
= *state
;
174 rctx
->blend_color
.atom
.dirty
= true;
177 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
179 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
180 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
182 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
183 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
184 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
185 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
186 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
189 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
191 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
192 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
194 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
195 r600_write_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, a
->vgt_multi_prim_ib_reset_indx
);
198 void r600_emit_vgt2_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
200 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
201 struct r600_vgt2_state
*a
= (struct r600_vgt2_state
*)atom
;
203 r600_write_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, a
->vgt_indx_offset
);
206 static void r600_set_clip_state(struct pipe_context
*ctx
,
207 const struct pipe_clip_state
*state
)
209 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
210 struct pipe_constant_buffer cb
;
212 rctx
->clip_state
.state
= *state
;
213 rctx
->clip_state
.atom
.dirty
= true;
216 cb
.user_buffer
= state
->ucp
;
217 cb
.buffer_offset
= 0;
218 cb
.buffer_size
= 4*4*8;
219 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
220 pipe_resource_reference(&cb
.buffer
, NULL
);
223 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
224 const struct r600_stencil_ref
*state
)
226 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
228 rctx
->stencil_ref
.state
= *state
;
229 rctx
->stencil_ref
.atom
.dirty
= true;
232 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
234 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
235 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
237 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
238 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
239 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
240 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
241 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
242 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
243 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
244 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
245 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
248 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
249 const struct pipe_stencil_ref
*state
)
251 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
252 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
253 struct r600_stencil_ref ref
;
255 rctx
->stencil_ref
.pipe_state
= *state
;
260 ref
.ref_value
[0] = state
->ref_value
[0];
261 ref
.ref_value
[1] = state
->ref_value
[1];
262 ref
.valuemask
[0] = dsa
->valuemask
[0];
263 ref
.valuemask
[1] = dsa
->valuemask
[1];
264 ref
.writemask
[0] = dsa
->writemask
[0];
265 ref
.writemask
[1] = dsa
->writemask
[1];
267 r600_set_stencil_ref(ctx
, &ref
);
270 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
272 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
273 struct r600_dsa_state
*dsa
= state
;
274 struct r600_stencil_ref ref
;
279 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
281 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
282 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
283 ref
.valuemask
[0] = dsa
->valuemask
[0];
284 ref
.valuemask
[1] = dsa
->valuemask
[1];
285 ref
.writemask
[0] = dsa
->writemask
[0];
286 ref
.writemask
[1] = dsa
->writemask
[1];
287 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
288 rctx
->zwritemask
= dsa
->zwritemask
;
289 if (rctx
->chip_class
>= EVERGREEN
) {
290 /* work around some issue when not writting to zbuffer
291 * we are having lockup on evergreen so do not enable
292 * hyperz when not writting zbuffer
294 rctx
->db_misc_state
.atom
.dirty
= true;
298 r600_set_stencil_ref(ctx
, &ref
);
300 /* Update alphatest state. */
301 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
302 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
303 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
304 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
305 rctx
->alphatest_state
.atom
.dirty
= true;
306 if (rctx
->chip_class
>= EVERGREEN
) {
307 evergreen_update_db_shader_control(rctx
);
309 r600_update_db_shader_control(rctx
);
314 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
316 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
317 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
322 rctx
->rasterizer
= rs
;
324 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
326 if (rs
->offset_enable
&&
327 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
328 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
329 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
330 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
331 rctx
->poly_offset_state
.atom
.dirty
= true;
334 /* Update clip_misc_state. */
335 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
336 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
337 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
338 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
339 rctx
->clip_misc_state
.atom
.dirty
= true;
342 /* Workaround for a missing scissor enable on r600. */
343 if (rctx
->chip_class
== R600
&&
344 rs
->scissor_enable
!= rctx
->scissor
.enable
) {
345 rctx
->scissor
.enable
= rs
->scissor_enable
;
346 rctx
->scissor
.atom
.dirty
= true;
349 /* Re-emit PA_SC_LINE_STIPPLE. */
350 rctx
->last_primitive_type
= -1;
353 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
355 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
357 r600_release_command_buffer(&rs
->buffer
);
361 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
362 struct pipe_sampler_view
*state
)
364 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
366 pipe_resource_reference(&state
->texture
, NULL
);
370 void r600_sampler_states_dirty(struct r600_context
*rctx
,
371 struct r600_sampler_states
*state
)
373 if (state
->dirty_mask
) {
374 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
375 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
378 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
379 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
380 state
->atom
.dirty
= true;
384 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
387 unsigned count
, void **states
)
389 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
390 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
391 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
392 int seamless_cube_map
= -1;
394 /* This sets 1-bit for states with index >= count. */
395 uint32_t disable_mask
= ~((1ull << count
) - 1);
396 /* These are the new states set by this function. */
397 uint32_t new_mask
= 0;
399 assert(start
== 0); /* XXX fix below */
401 for (i
= 0; i
< count
; i
++) {
402 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
404 if (rstate
== dst
->states
.states
[i
]) {
409 if (rstate
->border_color_use
) {
410 dst
->states
.has_bordercolor_mask
|= 1 << i
;
412 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
414 seamless_cube_map
= rstate
->seamless_cube_map
;
418 disable_mask
|= 1 << i
;
422 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
423 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
425 dst
->states
.enabled_mask
&= ~disable_mask
;
426 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
427 dst
->states
.enabled_mask
|= new_mask
;
428 dst
->states
.dirty_mask
|= new_mask
;
429 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
431 r600_sampler_states_dirty(rctx
, &dst
->states
);
433 /* Seamless cubemap state. */
434 if (rctx
->chip_class
<= R700
&&
435 seamless_cube_map
!= -1 &&
436 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
437 /* change in TA_CNTL_AUX need a pipeline flush */
438 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
439 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
440 rctx
->seamless_cube_map
.atom
.dirty
= true;
444 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
446 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
449 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
451 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
454 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
459 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
461 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
463 r600_release_command_buffer(&blend
->buffer
);
464 r600_release_command_buffer(&blend
->buffer_no_blend
);
468 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
470 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
472 r600_release_command_buffer(&dsa
->buffer
);
476 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
478 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
480 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
483 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
485 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
486 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
490 static void r600_set_index_buffer(struct pipe_context
*ctx
,
491 const struct pipe_index_buffer
*ib
)
493 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
496 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
497 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
498 r600_context_add_resource_size(ctx
, ib
->buffer
);
500 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
504 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
506 if (rctx
->vertex_buffer_state
.dirty_mask
) {
507 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
508 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
509 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
510 rctx
->vertex_buffer_state
.atom
.dirty
= true;
514 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
515 unsigned start_slot
, unsigned count
,
516 const struct pipe_vertex_buffer
*input
)
518 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
519 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
520 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
522 uint32_t disable_mask
= 0;
523 /* These are the new buffers set by this function. */
524 uint32_t new_buffer_mask
= 0;
526 /* Set vertex buffers. */
528 for (i
= 0; i
< count
; i
++) {
529 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
530 if (input
[i
].buffer
) {
531 vb
[i
].stride
= input
[i
].stride
;
532 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
533 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
534 new_buffer_mask
|= 1 << i
;
535 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
537 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
538 disable_mask
|= 1 << i
;
543 for (i
= 0; i
< count
; i
++) {
544 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
546 disable_mask
= ((1ull << count
) - 1);
549 disable_mask
<<= start_slot
;
550 new_buffer_mask
<<= start_slot
;
552 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
553 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
554 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
555 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
557 r600_vertex_buffers_dirty(rctx
);
560 void r600_sampler_views_dirty(struct r600_context
*rctx
,
561 struct r600_samplerview_state
*state
)
563 if (state
->dirty_mask
) {
564 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
565 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
566 util_bitcount(state
->dirty_mask
);
567 state
->atom
.dirty
= true;
571 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
572 unsigned start
, unsigned count
,
573 struct pipe_sampler_view
**views
)
575 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
576 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
577 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
578 uint32_t dirty_sampler_states_mask
= 0;
580 /* This sets 1-bit for textures with index >= count. */
581 uint32_t disable_mask
= ~((1ull << count
) - 1);
582 /* These are the new textures set by this function. */
583 uint32_t new_mask
= 0;
585 /* Set textures with index >= count to NULL. */
586 uint32_t remaining_mask
;
588 assert(start
== 0); /* XXX fix below */
590 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
592 while (remaining_mask
) {
593 i
= u_bit_scan(&remaining_mask
);
594 assert(dst
->views
.views
[i
]);
596 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
599 for (i
= 0; i
< count
; i
++) {
600 if (rviews
[i
] == dst
->views
.views
[i
]) {
605 struct r600_texture
*rtex
=
606 (struct r600_texture
*)rviews
[i
]->base
.texture
;
608 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
609 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
610 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
612 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
615 /* Track compressed colorbuffers. */
616 if (rtex
->cmask_size
&& rtex
->fmask_size
) {
617 dst
->views
.compressed_colortex_mask
|= 1 << i
;
619 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
622 /* Changing from array to non-arrays textures and vice versa requires
623 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
624 if (rctx
->chip_class
<= R700
&&
625 (dst
->states
.enabled_mask
& (1 << i
)) &&
626 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
627 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
628 dirty_sampler_states_mask
|= 1 << i
;
631 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
633 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
635 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
636 disable_mask
|= 1 << i
;
640 dst
->views
.enabled_mask
&= ~disable_mask
;
641 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
642 dst
->views
.enabled_mask
|= new_mask
;
643 dst
->views
.dirty_mask
|= new_mask
;
644 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
645 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
646 dst
->views
.dirty_txq_constants
= TRUE
;
647 dst
->views
.dirty_buffer_constants
= TRUE
;
648 r600_sampler_views_dirty(rctx
, &dst
->views
);
650 if (dirty_sampler_states_mask
) {
651 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
652 r600_sampler_states_dirty(rctx
, &dst
->states
);
656 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
657 struct pipe_sampler_view
**views
)
659 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
662 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
663 struct pipe_sampler_view
**views
)
665 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
668 static void r600_set_viewport_state(struct pipe_context
*ctx
,
669 const struct pipe_viewport_state
*state
)
671 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
673 rctx
->viewport
.state
= *state
;
674 rctx
->viewport
.atom
.dirty
= true;
677 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
679 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
680 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
682 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
683 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
684 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
685 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
686 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
687 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
688 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
691 /* Compute the key for the hw shader variant */
692 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
693 struct r600_pipe_shader_selector
* sel
)
695 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
696 struct r600_shader_key key
;
697 memset(&key
, 0, sizeof(key
));
699 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
700 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
701 key
.alpha_to_one
= rctx
->alpha_to_one
&&
702 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
703 !rctx
->framebuffer
.cb0_is_integer
;
704 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
705 /* Dual-source blending only makes sense with nr_cbufs == 1. */
706 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
712 /* Select the hw shader variant depending on the current state.
713 * (*dirty) is set to 1 if current variant was changed */
714 static int r600_shader_select(struct pipe_context
*ctx
,
715 struct r600_pipe_shader_selector
* sel
,
718 struct r600_shader_key key
;
719 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
720 struct r600_pipe_shader
* shader
= NULL
;
723 key
= r600_shader_selector_key(ctx
, sel
);
725 /* Check if we don't need to change anything.
726 * This path is also used for most shaders that don't need multiple
727 * variants, it will cost just a computation of the key and this
729 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
733 /* lookup if we have other variants in the list */
734 if (sel
->num_shaders
> 1) {
735 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
737 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
743 p
->next_variant
= c
->next_variant
;
748 if (unlikely(!shader
)) {
749 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
750 shader
->selector
= sel
;
752 r
= r600_pipe_shader_create(ctx
, shader
, key
);
754 R600_ERR("Failed to build shader variant (type=%u) %d\n",
761 /* We don't know the value of nr_ps_max_color_exports until we built
762 * at least one variant, so we may need to recompute the key after
763 * building first variant. */
764 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
765 sel
->num_shaders
== 0) {
766 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
767 key
= r600_shader_selector_key(ctx
, sel
);
777 shader
->next_variant
= sel
->current
;
778 sel
->current
= shader
;
780 if (rctx
->ps_shader
&&
781 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
782 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
783 rctx
->cb_misc_state
.atom
.dirty
= true;
788 static void *r600_create_shader_state(struct pipe_context
*ctx
,
789 const struct pipe_shader_state
*state
,
790 unsigned pipe_shader_type
)
792 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
795 sel
->type
= pipe_shader_type
;
796 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
797 sel
->so
= state
->stream_output
;
799 r
= r600_shader_select(ctx
, sel
, NULL
);
806 static void *r600_create_ps_state(struct pipe_context
*ctx
,
807 const struct pipe_shader_state
*state
)
809 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
812 static void *r600_create_vs_state(struct pipe_context
*ctx
,
813 const struct pipe_shader_state
*state
)
815 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
818 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
820 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
823 state
= rctx
->dummy_pixel_shader
;
825 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
826 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
828 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)rctx
->ps_shader
->current
->bo
);
830 if (rctx
->chip_class
<= R700
) {
831 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
833 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
834 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
835 rctx
->cb_misc_state
.atom
.dirty
= true;
839 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
840 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
841 rctx
->cb_misc_state
.atom
.dirty
= true;
844 if (rctx
->chip_class
>= EVERGREEN
) {
845 evergreen_update_db_shader_control(rctx
);
847 r600_update_db_shader_control(rctx
);
851 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
853 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
855 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
857 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
859 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)rctx
->vs_shader
->current
->bo
);
861 /* Update clip misc state. */
862 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
863 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
864 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
865 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
866 rctx
->clip_misc_state
.atom
.dirty
= true;
871 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
872 struct r600_pipe_shader_selector
*sel
)
874 struct r600_pipe_shader
*p
= sel
->current
, *c
;
877 r600_pipe_shader_destroy(ctx
, p
);
887 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
889 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
890 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
892 if (rctx
->ps_shader
== sel
) {
893 rctx
->ps_shader
= NULL
;
896 r600_delete_shader_selector(ctx
, sel
);
899 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
901 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
902 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
904 if (rctx
->vs_shader
== sel
) {
905 rctx
->vs_shader
= NULL
;
908 r600_delete_shader_selector(ctx
, sel
);
911 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
913 if (state
->dirty_mask
) {
914 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
915 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
916 : util_bitcount(state
->dirty_mask
)*19;
917 state
->atom
.dirty
= true;
921 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
922 struct pipe_constant_buffer
*input
)
924 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
925 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
926 struct pipe_constant_buffer
*cb
;
929 /* Note that the state tracker can unbind constant buffers by
932 if (unlikely(!input
)) {
933 state
->enabled_mask
&= ~(1 << index
);
934 state
->dirty_mask
&= ~(1 << index
);
935 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
939 cb
= &state
->cb
[index
];
940 cb
->buffer_size
= input
->buffer_size
;
942 ptr
= input
->user_buffer
;
945 /* Upload the user buffer. */
946 if (R600_BIG_ENDIAN
) {
948 unsigned i
, size
= input
->buffer_size
;
950 if (!(tmpPtr
= malloc(size
))) {
951 R600_ERR("Failed to allocate BE swap buffer.\n");
955 for (i
= 0; i
< size
/ 4; ++i
) {
956 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
959 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
962 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
964 /* account it in gtt */
965 rctx
->gtt
+= input
->buffer_size
;
967 /* Setup the hw buffer. */
968 cb
->buffer_offset
= input
->buffer_offset
;
969 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
970 r600_context_add_resource_size(ctx
, input
->buffer
);
973 state
->enabled_mask
|= 1 << index
;
974 state
->dirty_mask
|= 1 << index
;
975 r600_constant_buffers_dirty(rctx
, state
);
978 static struct pipe_stream_output_target
*
979 r600_create_so_target(struct pipe_context
*ctx
,
980 struct pipe_resource
*buffer
,
981 unsigned buffer_offset
,
982 unsigned buffer_size
)
984 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
985 struct r600_so_target
*t
;
987 t
= CALLOC_STRUCT(r600_so_target
);
992 u_suballocator_alloc(rctx
->allocator_so_filled_size
, 4,
993 &t
->buf_filled_size_offset
,
994 (struct pipe_resource
**)&t
->buf_filled_size
);
995 if (!t
->buf_filled_size
) {
1000 t
->b
.reference
.count
= 1;
1002 pipe_resource_reference(&t
->b
.buffer
, buffer
);
1003 t
->b
.buffer_offset
= buffer_offset
;
1004 t
->b
.buffer_size
= buffer_size
;
1008 static void r600_so_target_destroy(struct pipe_context
*ctx
,
1009 struct pipe_stream_output_target
*target
)
1011 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
1012 pipe_resource_reference(&t
->b
.buffer
, NULL
);
1013 pipe_resource_reference((struct pipe_resource
**)&t
->buf_filled_size
, NULL
);
1017 void r600_streamout_buffers_dirty(struct r600_context
*rctx
)
1019 rctx
->streamout
.num_dw_for_end
=
1020 12 + /* flush_vgt_streamout */
1021 util_bitcount(rctx
->streamout
.enabled_mask
) * 8 + /* STRMOUT_BUFFER_UPDATE */
1022 3 /* set_streamout_enable(0) */;
1024 rctx
->streamout
.begin_atom
.num_dw
=
1025 12 + /* flush_vgt_streamout */
1026 6 + /* set_streamout_enable */
1027 util_bitcount(rctx
->streamout
.enabled_mask
) * 7 + /* SET_CONTEXT_REG */
1028 (rctx
->family
>= CHIP_RS780
&&
1029 rctx
->family
<= CHIP_RV740
? util_bitcount(rctx
->streamout
.enabled_mask
) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1030 util_bitcount(rctx
->streamout
.enabled_mask
& rctx
->streamout
.append_bitmask
) * 8 + /* STRMOUT_BUFFER_UPDATE */
1031 util_bitcount(rctx
->streamout
.enabled_mask
& ~rctx
->streamout
.append_bitmask
) * 6 + /* STRMOUT_BUFFER_UPDATE */
1032 (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RS780
? 2 : 0) + /* SURFACE_BASE_UPDATE */
1033 rctx
->streamout
.num_dw_for_end
;
1035 rctx
->streamout
.begin_atom
.dirty
= true;
1038 static void r600_set_streamout_targets(struct pipe_context
*ctx
,
1039 unsigned num_targets
,
1040 struct pipe_stream_output_target
**targets
,
1041 unsigned append_bitmask
)
1043 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1046 /* Stop streamout. */
1047 if (rctx
->streamout
.num_targets
&& rctx
->streamout
.begin_emitted
) {
1048 r600_emit_streamout_end(rctx
);
1051 /* Set the new targets. */
1052 for (i
= 0; i
< num_targets
; i
++) {
1053 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->streamout
.targets
[i
], targets
[i
]);
1054 r600_context_add_resource_size(ctx
, targets
[i
]->buffer
);
1056 for (; i
< rctx
->streamout
.num_targets
; i
++) {
1057 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->streamout
.targets
[i
], NULL
);
1060 rctx
->streamout
.enabled_mask
= (num_targets
>= 1 && targets
[0] ? 1 : 0) |
1061 (num_targets
>= 2 && targets
[1] ? 2 : 0) |
1062 (num_targets
>= 3 && targets
[2] ? 4 : 0) |
1063 (num_targets
>= 4 && targets
[3] ? 8 : 0);
1065 rctx
->streamout
.num_targets
= num_targets
;
1066 rctx
->streamout
.append_bitmask
= append_bitmask
;
1069 r600_streamout_buffers_dirty(rctx
);
1073 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1075 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1077 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1080 rctx
->sample_mask
.sample_mask
= sample_mask
;
1081 rctx
->sample_mask
.atom
.dirty
= true;
1085 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1086 * doesn't require full swizzles it does need masking and setting alpha
1087 * to one, so we setup a set of 5 constants with the masks + alpha value
1088 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1089 * then OR the alpha with the value given here.
1090 * We use a 6th constant to store the txq buffer size in
1092 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1094 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1096 uint32_t array_size
;
1097 struct pipe_constant_buffer cb
;
1100 if (!samplers
->views
.dirty_buffer_constants
)
1103 samplers
->views
.dirty_buffer_constants
= FALSE
;
1105 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1106 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1107 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1108 memset(samplers
->buffer_constants
, 0, array_size
);
1109 for (i
= 0; i
< bits
; i
++) {
1110 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1112 const struct util_format_description
*desc
;
1113 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1115 for (j
= 0; j
< 4; j
++)
1116 if (j
< desc
->nr_channels
)
1117 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1119 samplers
->buffer_constants
[offset
+j
] = 0x0;
1120 if (desc
->nr_channels
< 4) {
1121 if (desc
->channel
[0].pure_integer
)
1122 samplers
->buffer_constants
[offset
+4] = 1;
1124 samplers
->buffer_constants
[offset
+4] = 0x3f800000;
1126 samplers
->buffer_constants
[offset
+ 4] = 0;
1128 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1133 cb
.user_buffer
= samplers
->buffer_constants
;
1134 cb
.buffer_offset
= 0;
1135 cb
.buffer_size
= array_size
;
1136 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1137 pipe_resource_reference(&cb
.buffer
, NULL
);
1140 /* On evergreen we only need to store the buffer size for TXQ */
1141 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1143 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1145 uint32_t array_size
;
1146 struct pipe_constant_buffer cb
;
1149 if (!samplers
->views
.dirty_buffer_constants
)
1152 samplers
->views
.dirty_buffer_constants
= FALSE
;
1154 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1155 array_size
= bits
* sizeof(uint32_t) * 4;
1156 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1157 memset(samplers
->buffer_constants
, 0, array_size
);
1158 for (i
= 0; i
< bits
; i
++)
1159 if (samplers
->views
.enabled_mask
& (1 << i
))
1160 samplers
->buffer_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1163 cb
.user_buffer
= samplers
->buffer_constants
;
1164 cb
.buffer_offset
= 0;
1165 cb
.buffer_size
= array_size
;
1166 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1167 pipe_resource_reference(&cb
.buffer
, NULL
);
1170 static void r600_setup_txq_cube_array_constants(struct r600_context
*rctx
, int shader_type
)
1172 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1174 uint32_t array_size
;
1175 struct pipe_constant_buffer cb
;
1178 if (!samplers
->views
.dirty_txq_constants
)
1181 samplers
->views
.dirty_txq_constants
= FALSE
;
1183 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1184 array_size
= bits
* sizeof(uint32_t) * 4;
1185 samplers
->txq_constants
= realloc(samplers
->txq_constants
, array_size
);
1186 memset(samplers
->txq_constants
, 0, array_size
);
1187 for (i
= 0; i
< bits
; i
++)
1188 if (samplers
->views
.enabled_mask
& (1 << i
))
1189 samplers
->txq_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1192 cb
.user_buffer
= samplers
->txq_constants
;
1193 cb
.buffer_offset
= 0;
1194 cb
.buffer_size
= array_size
;
1195 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_TXQ_CONST_BUFFER
, &cb
);
1196 pipe_resource_reference(&cb
.buffer
, NULL
);
1199 static bool r600_update_derived_state(struct r600_context
*rctx
)
1201 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1202 unsigned ps_dirty
= 0;
1205 if (!rctx
->blitter
->running
) {
1208 /* Decompress textures if needed. */
1209 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1210 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1211 if (views
->compressed_depthtex_mask
) {
1212 r600_decompress_depth_textures(rctx
, views
);
1214 if (views
->compressed_colortex_mask
) {
1215 r600_decompress_color_textures(rctx
, views
);
1220 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1222 if (rctx
->ps_shader
&& rctx
->rasterizer
&&
1223 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1224 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1226 if (rctx
->chip_class
>= EVERGREEN
)
1227 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1229 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1235 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1237 /* on R600 we stuff masks + txq info into one constant buffer */
1238 /* on evergreen we only need a txq info one */
1239 if (rctx
->chip_class
< EVERGREEN
) {
1240 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1241 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1242 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1243 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1245 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1246 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1247 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1248 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1252 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1253 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1254 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1255 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_VERTEX
);
1257 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1258 if (!r600_adjust_gprs(rctx
)) {
1259 /* discard rendering */
1264 blend_disable
= (rctx
->dual_src_blend
&&
1265 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1267 if (blend_disable
!= rctx
->force_blend_disable
) {
1268 rctx
->force_blend_disable
= blend_disable
;
1269 r600_bind_blend_state_internal(rctx
,
1270 rctx
->blend_state
.cso
,
1276 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1278 static const int prim_conv
[] = {
1279 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1280 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1281 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1282 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1283 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1284 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1285 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1286 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1287 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1288 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1289 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1290 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1291 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1292 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1293 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1295 assert(mode
< Elements(prim_conv
));
1297 return prim_conv
[mode
];
1300 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1302 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1303 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1305 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1306 state
->pa_cl_clip_cntl
|
1307 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1308 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1309 state
->pa_cl_vs_out_cntl
|
1310 (state
->clip_plane_enable
& state
->clip_dist_write
));
1313 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1315 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1316 struct pipe_draw_info info
= *dinfo
;
1317 struct pipe_index_buffer ib
= {};
1319 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1320 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1322 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1327 if (!rctx
->vs_shader
) {
1332 /* make sure that the gfx ring is only one active */
1333 if (rctx
->rings
.dma
.cs
) {
1334 rctx
->rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
);
1337 if (!r600_update_derived_state(rctx
)) {
1338 /* useless to render because current rendering command
1345 /* Initialize the index buffer struct. */
1346 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1347 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1348 ib
.index_size
= rctx
->index_buffer
.index_size
;
1349 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1351 /* Translate 8-bit indices to 16-bit. */
1352 if (ib
.index_size
== 1) {
1353 struct pipe_resource
*out_buffer
= NULL
;
1354 unsigned out_offset
;
1357 u_upload_alloc(rctx
->uploader
, 0, info
.count
* 2,
1358 &out_offset
, &out_buffer
, &ptr
);
1360 util_shorten_ubyte_elts_to_userptr(
1361 &rctx
->context
, &ib
, 0, ib
.offset
, info
.count
, ptr
);
1363 pipe_resource_reference(&ib
.buffer
, NULL
);
1364 ib
.user_buffer
= NULL
;
1365 ib
.buffer
= out_buffer
;
1366 ib
.offset
= out_offset
;
1370 /* Upload the index buffer.
1371 * The upload is skipped for small index counts on little-endian machines
1372 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1373 * Note: Instanced rendering in combination with immediate indices hangs. */
1374 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.instance_count
> 1 ||
1375 info
.count
*ib
.index_size
> 20)) {
1376 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1377 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1378 ib
.user_buffer
= NULL
;
1381 info
.index_bias
= info
.start
;
1384 /* Set the index offset and multi primitive */
1385 if (rctx
->vgt2_state
.vgt_indx_offset
!= info
.index_bias
) {
1386 rctx
->vgt2_state
.vgt_indx_offset
= info
.index_bias
;
1387 rctx
->vgt2_state
.atom
.dirty
= true;
1389 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1390 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
) {
1391 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1392 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1393 rctx
->vgt_state
.atom
.dirty
= true;
1396 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1397 if (rctx
->chip_class
== R600
) {
1398 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1399 rctx
->cb_misc_state
.atom
.dirty
= true;
1403 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1404 r600_flush_emit(rctx
);
1406 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1407 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1410 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1412 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1413 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1415 rctx
->pm4_dirty_cdwords
= 0;
1417 /* Update start instance. */
1418 if (rctx
->last_start_instance
!= info
.start_instance
) {
1419 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1420 rctx
->last_start_instance
= info
.start_instance
;
1423 /* Update the primitive type. */
1424 if (rctx
->last_primitive_type
!= info
.mode
) {
1425 unsigned ls_mask
= 0;
1427 if (info
.mode
== PIPE_PRIM_LINES
)
1429 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1430 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1433 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1434 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1435 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1436 r600_write_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
1437 r600_conv_prim_to_gs_out(info
.mode
));
1438 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1439 r600_conv_pipe_prim(info
.mode
));
1441 rctx
->last_primitive_type
= info
.mode
;
1445 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1446 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1448 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1449 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1450 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1451 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1453 if (ib
.user_buffer
) {
1454 unsigned size_bytes
= info
.count
*ib
.index_size
;
1455 unsigned size_dw
= align(size_bytes
, 4) / 4;
1456 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->predicate_drawing
);
1457 cs
->buf
[cs
->cdw
++] = info
.count
;
1458 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1459 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1462 uint64_t va
= r600_resource_va(ctx
->screen
, ib
.buffer
) + ib
.offset
;
1463 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1464 cs
->buf
[cs
->cdw
++] = va
;
1465 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1466 cs
->buf
[cs
->cdw
++] = info
.count
;
1467 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1468 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1469 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1472 if (info
.count_from_stream_output
) {
1473 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1474 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->buf_filled_size
) + t
->buf_filled_size_offset
;
1476 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1478 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1479 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1480 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1481 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1482 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1483 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1485 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1486 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, t
->buf_filled_size
, RADEON_USAGE_READ
);
1489 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1490 cs
->buf
[cs
->cdw
++] = info
.count
;
1491 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1492 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1496 if (rctx
->screen
->trace_bo
) {
1497 r600_trace_emit(rctx
);
1501 /* Set the depth buffer as dirty. */
1502 if (rctx
->framebuffer
.state
.zsbuf
) {
1503 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1504 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1506 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1508 if (rctx
->framebuffer
.compressed_cb_mask
) {
1509 struct pipe_surface
*surf
;
1510 struct r600_texture
*rtex
;
1511 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1514 unsigned i
= u_bit_scan(&mask
);
1515 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1516 rtex
= (struct r600_texture
*)surf
->texture
;
1518 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1523 pipe_resource_reference(&ib
.buffer
, NULL
);
1526 void r600_draw_rectangle(struct blitter_context
*blitter
,
1527 int x1
, int y1
, int x2
, int y2
, float depth
,
1528 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1530 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1531 struct pipe_viewport_state viewport
;
1532 struct pipe_resource
*buf
= NULL
;
1533 unsigned offset
= 0;
1536 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1537 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1541 /* Some operations (like color resolve on r6xx) don't work
1542 * with the conventional primitive types.
1543 * One that works is PT_RECTLIST, which we use here. */
1545 /* setup viewport */
1546 viewport
.scale
[0] = 1.0f
;
1547 viewport
.scale
[1] = 1.0f
;
1548 viewport
.scale
[2] = 1.0f
;
1549 viewport
.scale
[3] = 1.0f
;
1550 viewport
.translate
[0] = 0.0f
;
1551 viewport
.translate
[1] = 0.0f
;
1552 viewport
.translate
[2] = 0.0f
;
1553 viewport
.translate
[3] = 0.0f
;
1554 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1556 /* Upload vertices. The hw rectangle has only 3 vertices,
1557 * I guess the 4th one is derived from the first 3.
1558 * The vertex specification should match u_blitter's vertex element state. */
1559 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1576 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1577 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1578 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1582 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, rctx
->blitter
->vb_slot
, offset
,
1583 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1584 pipe_resource_reference(&buf
, NULL
);
1587 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1588 struct r600_pipe_state
*state
,
1589 uint32_t offset
, uint32_t value
,
1590 uint32_t range_id
, uint32_t block_id
,
1591 struct r600_resource
*bo
,
1592 enum radeon_bo_usage usage
)
1595 struct r600_range
*range
;
1596 struct r600_block
*block
;
1598 if (bo
) assert(usage
);
1600 range
= &ctx
->range
[range_id
];
1601 block
= range
->blocks
[block_id
];
1602 state
->regs
[state
->nregs
].block
= block
;
1603 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1605 state
->regs
[state
->nregs
].value
= value
;
1606 state
->regs
[state
->nregs
].bo
= bo
;
1607 state
->regs
[state
->nregs
].bo_usage
= usage
;
1610 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1613 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1614 struct r600_pipe_state
*state
,
1615 uint32_t offset
, uint32_t value
,
1616 uint32_t range_id
, uint32_t block_id
)
1618 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1619 range_id
, block_id
, NULL
, 0);
1622 uint32_t r600_translate_stencil_op(int s_op
)
1625 case PIPE_STENCIL_OP_KEEP
:
1626 return V_028800_STENCIL_KEEP
;
1627 case PIPE_STENCIL_OP_ZERO
:
1628 return V_028800_STENCIL_ZERO
;
1629 case PIPE_STENCIL_OP_REPLACE
:
1630 return V_028800_STENCIL_REPLACE
;
1631 case PIPE_STENCIL_OP_INCR
:
1632 return V_028800_STENCIL_INCR
;
1633 case PIPE_STENCIL_OP_DECR
:
1634 return V_028800_STENCIL_DECR
;
1635 case PIPE_STENCIL_OP_INCR_WRAP
:
1636 return V_028800_STENCIL_INCR_WRAP
;
1637 case PIPE_STENCIL_OP_DECR_WRAP
:
1638 return V_028800_STENCIL_DECR_WRAP
;
1639 case PIPE_STENCIL_OP_INVERT
:
1640 return V_028800_STENCIL_INVERT
;
1642 R600_ERR("Unknown stencil op %d", s_op
);
1649 uint32_t r600_translate_fill(uint32_t func
)
1652 case PIPE_POLYGON_MODE_FILL
:
1654 case PIPE_POLYGON_MODE_LINE
:
1656 case PIPE_POLYGON_MODE_POINT
:
1664 unsigned r600_tex_wrap(unsigned wrap
)
1668 case PIPE_TEX_WRAP_REPEAT
:
1669 return V_03C000_SQ_TEX_WRAP
;
1670 case PIPE_TEX_WRAP_CLAMP
:
1671 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1672 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1673 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1674 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1675 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1676 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1677 return V_03C000_SQ_TEX_MIRROR
;
1678 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1679 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1680 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1681 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1682 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1683 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1687 unsigned r600_tex_filter(unsigned filter
)
1691 case PIPE_TEX_FILTER_NEAREST
:
1692 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1693 case PIPE_TEX_FILTER_LINEAR
:
1694 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1698 unsigned r600_tex_mipfilter(unsigned filter
)
1701 case PIPE_TEX_MIPFILTER_NEAREST
:
1702 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1703 case PIPE_TEX_MIPFILTER_LINEAR
:
1704 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1706 case PIPE_TEX_MIPFILTER_NONE
:
1707 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1711 unsigned r600_tex_compare(unsigned compare
)
1715 case PIPE_FUNC_NEVER
:
1716 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1717 case PIPE_FUNC_LESS
:
1718 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1719 case PIPE_FUNC_EQUAL
:
1720 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1721 case PIPE_FUNC_LEQUAL
:
1722 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1723 case PIPE_FUNC_GREATER
:
1724 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1725 case PIPE_FUNC_NOTEQUAL
:
1726 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1727 case PIPE_FUNC_GEQUAL
:
1728 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1729 case PIPE_FUNC_ALWAYS
:
1730 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1734 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1736 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1737 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1739 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1740 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1743 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1745 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1746 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1748 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1749 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1750 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1751 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1752 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1755 /* keep this at the end of this file, please */
1756 void r600_init_common_state_functions(struct r600_context
*rctx
)
1758 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1759 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1760 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
1761 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1762 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1763 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1764 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1765 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1766 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1767 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1768 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1769 rctx
->context
.delete_blend_state
= r600_delete_blend_state
;
1770 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
1771 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1772 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1773 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1774 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1775 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1776 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1777 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1778 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1779 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1780 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1781 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1782 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1783 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1784 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1785 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1786 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1787 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1788 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1789 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1790 rctx
->context
.set_stream_output_targets
= r600_set_streamout_targets
;
1791 rctx
->context
.draw_vbo
= r600_draw_vbo
;
1795 void r600_trace_emit(struct r600_context
*rctx
)
1797 struct r600_screen
*rscreen
= rctx
->screen
;
1798 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1802 va
= r600_resource_va(&rscreen
->screen
, (void*)rscreen
->trace_bo
);
1803 reloc
= r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rscreen
->trace_bo
, RADEON_USAGE_READWRITE
);
1804 r600_write_value(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
1805 r600_write_value(cs
, va
& 0xFFFFFFFFUL
);
1806 r600_write_value(cs
, (va
>> 32UL) & 0xFFUL
);
1807 r600_write_value(cs
, cs
->cdw
);
1808 r600_write_value(cs
, rscreen
->cs_count
);
1809 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1810 r600_write_value(cs
, reloc
);