2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
39 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
41 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
44 cb
->buf
= CALLOC(1, 4 * num_dw
);
45 cb
->max_num_dw
= num_dw
;
48 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
53 void r600_init_atom(struct r600_context
*rctx
,
54 struct r600_atom
*atom
,
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
59 assert(id
< R600_NUM_ATOMS
);
60 assert(rctx
->atoms
[id
] == NULL
);
61 rctx
->atoms
[id
] = atom
;
62 atom
->emit
= (void*)emit
;
63 atom
->num_dw
= num_dw
;
67 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
69 r600_emit_command_buffer(rctx
->b
.rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
72 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
74 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
75 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
76 unsigned alpha_ref
= a
->sx_alpha_ref
;
78 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
82 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
83 a
->sx_alpha_test_control
|
84 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
85 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
88 static void r600_texture_barrier(struct pipe_context
*ctx
)
90 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
92 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
93 R600_CONTEXT_FLUSH_AND_INV_CB
|
94 R600_CONTEXT_FLUSH_AND_INV
|
95 R600_CONTEXT_WAIT_3D_IDLE
;
98 static unsigned r600_conv_pipe_prim(unsigned prim
)
100 static const unsigned prim_conv
[] = {
101 V_008958_DI_PT_POINTLIST
,
102 V_008958_DI_PT_LINELIST
,
103 V_008958_DI_PT_LINELOOP
,
104 V_008958_DI_PT_LINESTRIP
,
105 V_008958_DI_PT_TRILIST
,
106 V_008958_DI_PT_TRISTRIP
,
107 V_008958_DI_PT_TRIFAN
,
108 V_008958_DI_PT_QUADLIST
,
109 V_008958_DI_PT_QUADSTRIP
,
110 V_008958_DI_PT_POLYGON
,
111 V_008958_DI_PT_LINELIST_ADJ
,
112 V_008958_DI_PT_LINESTRIP_ADJ
,
113 V_008958_DI_PT_TRILIST_ADJ
,
114 V_008958_DI_PT_TRISTRIP_ADJ
,
115 V_008958_DI_PT_RECTLIST
117 return prim_conv
[prim
];
120 /* common state between evergreen and r600 */
122 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
123 struct r600_blend_state
*blend
, bool blend_disable
)
125 unsigned color_control
;
126 bool update_cb
= false;
128 rctx
->alpha_to_one
= blend
->alpha_to_one
;
129 rctx
->dual_src_blend
= blend
->dual_src_blend
;
131 if (!blend_disable
) {
132 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
133 color_control
= blend
->cb_color_control
;
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
137 color_control
= blend
->cb_color_control_no_blend
;
140 /* Update derived states. */
141 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
142 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
145 if (rctx
->b
.chip_class
<= R700
&&
146 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
147 rctx
->cb_misc_state
.cb_color_control
= color_control
;
150 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
151 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
155 rctx
->cb_misc_state
.atom
.dirty
= true;
159 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
161 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
162 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
167 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
170 static void r600_set_blend_color(struct pipe_context
*ctx
,
171 const struct pipe_blend_color
*state
)
173 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
175 rctx
->blend_color
.state
= *state
;
176 rctx
->blend_color
.atom
.dirty
= true;
179 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
181 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
182 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
184 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
185 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
186 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
187 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
188 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
191 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
193 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
194 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
196 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
197 r600_write_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
198 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
199 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
202 static void r600_set_clip_state(struct pipe_context
*ctx
,
203 const struct pipe_clip_state
*state
)
205 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
206 struct pipe_constant_buffer cb
;
208 rctx
->clip_state
.state
= *state
;
209 rctx
->clip_state
.atom
.dirty
= true;
212 cb
.user_buffer
= state
->ucp
;
213 cb
.buffer_offset
= 0;
214 cb
.buffer_size
= 4*4*8;
215 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
216 pipe_resource_reference(&cb
.buffer
, NULL
);
219 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
220 const struct r600_stencil_ref
*state
)
222 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
224 rctx
->stencil_ref
.state
= *state
;
225 rctx
->stencil_ref
.atom
.dirty
= true;
228 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
230 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
231 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
233 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
234 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
235 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
236 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
237 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
238 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
239 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
240 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
241 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
244 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
245 const struct pipe_stencil_ref
*state
)
247 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
248 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
249 struct r600_stencil_ref ref
;
251 rctx
->stencil_ref
.pipe_state
= *state
;
256 ref
.ref_value
[0] = state
->ref_value
[0];
257 ref
.ref_value
[1] = state
->ref_value
[1];
258 ref
.valuemask
[0] = dsa
->valuemask
[0];
259 ref
.valuemask
[1] = dsa
->valuemask
[1];
260 ref
.writemask
[0] = dsa
->writemask
[0];
261 ref
.writemask
[1] = dsa
->writemask
[1];
263 r600_set_stencil_ref(ctx
, &ref
);
266 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
268 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
269 struct r600_dsa_state
*dsa
= state
;
270 struct r600_stencil_ref ref
;
273 r600_set_cso_state_with_cb(&rctx
->dsa_state
, NULL
, NULL
);
277 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
279 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
280 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
281 ref
.valuemask
[0] = dsa
->valuemask
[0];
282 ref
.valuemask
[1] = dsa
->valuemask
[1];
283 ref
.writemask
[0] = dsa
->writemask
[0];
284 ref
.writemask
[1] = dsa
->writemask
[1];
285 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
286 rctx
->zwritemask
= dsa
->zwritemask
;
287 if (rctx
->b
.chip_class
>= EVERGREEN
) {
288 /* work around some issue when not writting to zbuffer
289 * we are having lockup on evergreen so do not enable
290 * hyperz when not writting zbuffer
292 rctx
->db_misc_state
.atom
.dirty
= true;
296 r600_set_stencil_ref(ctx
, &ref
);
298 /* Update alphatest state. */
299 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
300 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
301 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
302 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
303 rctx
->alphatest_state
.atom
.dirty
= true;
307 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
309 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
310 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
315 rctx
->rasterizer
= rs
;
317 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
319 if (rs
->offset_enable
&&
320 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
321 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
322 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
323 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
324 rctx
->poly_offset_state
.atom
.dirty
= true;
327 /* Update clip_misc_state. */
328 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
329 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
330 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
331 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
332 rctx
->clip_misc_state
.atom
.dirty
= true;
335 /* Workaround for a missing scissor enable on r600. */
336 if (rctx
->b
.chip_class
== R600
&&
337 rs
->scissor_enable
!= rctx
->scissor
.enable
) {
338 rctx
->scissor
.enable
= rs
->scissor_enable
;
339 rctx
->scissor
.atom
.dirty
= true;
342 /* Re-emit PA_SC_LINE_STIPPLE. */
343 rctx
->last_primitive_type
= -1;
346 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
348 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
350 r600_release_command_buffer(&rs
->buffer
);
354 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
355 struct pipe_sampler_view
*state
)
357 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
359 pipe_resource_reference(&state
->texture
, NULL
);
363 void r600_sampler_states_dirty(struct r600_context
*rctx
,
364 struct r600_sampler_states
*state
)
366 if (state
->dirty_mask
) {
367 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
368 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
371 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
372 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
373 state
->atom
.dirty
= true;
377 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
380 unsigned count
, void **states
)
382 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
383 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
384 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
385 int seamless_cube_map
= -1;
387 /* This sets 1-bit for states with index >= count. */
388 uint32_t disable_mask
= ~((1ull << count
) - 1);
389 /* These are the new states set by this function. */
390 uint32_t new_mask
= 0;
392 assert(start
== 0); /* XXX fix below */
394 if (shader
!= PIPE_SHADER_VERTEX
&&
395 shader
!= PIPE_SHADER_FRAGMENT
) {
399 for (i
= 0; i
< count
; i
++) {
400 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
402 if (rstate
== dst
->states
.states
[i
]) {
407 if (rstate
->border_color_use
) {
408 dst
->states
.has_bordercolor_mask
|= 1 << i
;
410 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
412 seamless_cube_map
= rstate
->seamless_cube_map
;
416 disable_mask
|= 1 << i
;
420 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
421 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
423 dst
->states
.enabled_mask
&= ~disable_mask
;
424 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
425 dst
->states
.enabled_mask
|= new_mask
;
426 dst
->states
.dirty_mask
|= new_mask
;
427 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
429 r600_sampler_states_dirty(rctx
, &dst
->states
);
431 /* Seamless cubemap state. */
432 if (rctx
->b
.chip_class
<= R700
&&
433 seamless_cube_map
!= -1 &&
434 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
435 /* change in TA_CNTL_AUX need a pipeline flush */
436 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
437 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
438 rctx
->seamless_cube_map
.atom
.dirty
= true;
442 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
447 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
449 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
451 r600_release_command_buffer(&blend
->buffer
);
452 r600_release_command_buffer(&blend
->buffer_no_blend
);
456 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
458 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
459 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
461 if (rctx
->dsa_state
.cso
== state
) {
462 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
465 r600_release_command_buffer(&dsa
->buffer
);
469 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
471 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
473 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
476 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
478 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
479 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
483 static void r600_set_index_buffer(struct pipe_context
*ctx
,
484 const struct pipe_index_buffer
*ib
)
486 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
489 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
490 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
491 r600_context_add_resource_size(ctx
, ib
->buffer
);
493 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
497 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
499 if (rctx
->vertex_buffer_state
.dirty_mask
) {
500 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
;
501 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
502 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
503 rctx
->vertex_buffer_state
.atom
.dirty
= true;
507 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
508 unsigned start_slot
, unsigned count
,
509 const struct pipe_vertex_buffer
*input
)
511 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
512 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
513 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
515 uint32_t disable_mask
= 0;
516 /* These are the new buffers set by this function. */
517 uint32_t new_buffer_mask
= 0;
519 /* Set vertex buffers. */
521 for (i
= 0; i
< count
; i
++) {
522 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
523 if (input
[i
].buffer
) {
524 vb
[i
].stride
= input
[i
].stride
;
525 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
526 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
527 new_buffer_mask
|= 1 << i
;
528 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
530 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
531 disable_mask
|= 1 << i
;
536 for (i
= 0; i
< count
; i
++) {
537 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
539 disable_mask
= ((1ull << count
) - 1);
542 disable_mask
<<= start_slot
;
543 new_buffer_mask
<<= start_slot
;
545 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
546 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
547 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
548 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
550 r600_vertex_buffers_dirty(rctx
);
553 void r600_sampler_views_dirty(struct r600_context
*rctx
,
554 struct r600_samplerview_state
*state
)
556 if (state
->dirty_mask
) {
557 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
558 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
559 util_bitcount(state
->dirty_mask
);
560 state
->atom
.dirty
= true;
564 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
565 unsigned start
, unsigned count
,
566 struct pipe_sampler_view
**views
)
568 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
569 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
570 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
571 uint32_t dirty_sampler_states_mask
= 0;
573 /* This sets 1-bit for textures with index >= count. */
574 uint32_t disable_mask
= ~((1ull << count
) - 1);
575 /* These are the new textures set by this function. */
576 uint32_t new_mask
= 0;
578 /* Set textures with index >= count to NULL. */
579 uint32_t remaining_mask
;
581 assert(start
== 0); /* XXX fix below */
583 if (shader
== PIPE_SHADER_COMPUTE
) {
584 evergreen_set_cs_sampler_view(pipe
, start
, count
, views
);
588 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
590 while (remaining_mask
) {
591 i
= u_bit_scan(&remaining_mask
);
592 assert(dst
->views
.views
[i
]);
594 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
597 for (i
= 0; i
< count
; i
++) {
598 if (rviews
[i
] == dst
->views
.views
[i
]) {
603 struct r600_texture
*rtex
=
604 (struct r600_texture
*)rviews
[i
]->base
.texture
;
606 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
607 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
608 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
610 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
613 /* Track compressed colorbuffers. */
614 if (rtex
->cmask
.size
) {
615 dst
->views
.compressed_colortex_mask
|= 1 << i
;
617 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
620 /* Changing from array to non-arrays textures and vice versa requires
621 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
622 if (rctx
->b
.chip_class
<= R700
&&
623 (dst
->states
.enabled_mask
& (1 << i
)) &&
624 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
625 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
626 dirty_sampler_states_mask
|= 1 << i
;
629 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
631 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
633 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
634 disable_mask
|= 1 << i
;
638 dst
->views
.enabled_mask
&= ~disable_mask
;
639 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
640 dst
->views
.enabled_mask
|= new_mask
;
641 dst
->views
.dirty_mask
|= new_mask
;
642 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
643 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
644 dst
->views
.dirty_txq_constants
= TRUE
;
645 dst
->views
.dirty_buffer_constants
= TRUE
;
646 r600_sampler_views_dirty(rctx
, &dst
->views
);
648 if (dirty_sampler_states_mask
) {
649 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
650 r600_sampler_states_dirty(rctx
, &dst
->states
);
654 static void r600_set_viewport_states(struct pipe_context
*ctx
,
656 unsigned num_viewports
,
657 const struct pipe_viewport_state
*state
)
659 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
661 rctx
->viewport
.state
= *state
;
662 rctx
->viewport
.atom
.dirty
= true;
665 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
667 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
668 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
670 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
671 radeon_emit(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
672 radeon_emit(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
673 radeon_emit(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
674 radeon_emit(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
675 radeon_emit(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
676 radeon_emit(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
679 /* Compute the key for the hw shader variant */
680 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
681 struct r600_pipe_shader_selector
* sel
)
683 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
684 struct r600_shader_key key
;
685 memset(&key
, 0, sizeof(key
));
687 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
688 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
689 key
.alpha_to_one
= rctx
->alpha_to_one
&&
690 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
691 !rctx
->framebuffer
.cb0_is_integer
;
692 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
693 /* Dual-source blending only makes sense with nr_cbufs == 1. */
694 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
696 } else if (sel
->type
== PIPE_SHADER_VERTEX
) {
697 key
.vs_as_es
= (rctx
->gs_shader
!= NULL
);
702 /* Select the hw shader variant depending on the current state.
703 * (*dirty) is set to 1 if current variant was changed */
704 static int r600_shader_select(struct pipe_context
*ctx
,
705 struct r600_pipe_shader_selector
* sel
,
708 struct r600_shader_key key
;
709 struct r600_pipe_shader
* shader
= NULL
;
712 memset(&key
, 0, sizeof(key
));
713 key
= r600_shader_selector_key(ctx
, sel
);
715 /* Check if we don't need to change anything.
716 * This path is also used for most shaders that don't need multiple
717 * variants, it will cost just a computation of the key and this
719 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
723 /* lookup if we have other variants in the list */
724 if (sel
->num_shaders
> 1) {
725 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
727 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
733 p
->next_variant
= c
->next_variant
;
738 if (unlikely(!shader
)) {
739 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
740 shader
->selector
= sel
;
742 r
= r600_pipe_shader_create(ctx
, shader
, key
);
744 R600_ERR("Failed to build shader variant (type=%u) %d\n",
751 /* We don't know the value of nr_ps_max_color_exports until we built
752 * at least one variant, so we may need to recompute the key after
753 * building first variant. */
754 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
755 sel
->num_shaders
== 0) {
756 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
757 key
= r600_shader_selector_key(ctx
, sel
);
760 memcpy(&shader
->key
, &key
, sizeof(key
));
767 shader
->next_variant
= sel
->current
;
768 sel
->current
= shader
;
773 static void *r600_create_shader_state(struct pipe_context
*ctx
,
774 const struct pipe_shader_state
*state
,
775 unsigned pipe_shader_type
)
777 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
779 sel
->type
= pipe_shader_type
;
780 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
781 sel
->so
= state
->stream_output
;
785 static void *r600_create_ps_state(struct pipe_context
*ctx
,
786 const struct pipe_shader_state
*state
)
788 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
791 static void *r600_create_vs_state(struct pipe_context
*ctx
,
792 const struct pipe_shader_state
*state
)
794 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
797 static void *r600_create_gs_state(struct pipe_context
*ctx
,
798 const struct pipe_shader_state
*state
)
800 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
803 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
805 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
808 state
= rctx
->dummy_pixel_shader
;
810 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
813 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
815 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
820 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
821 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
824 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
826 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
828 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
832 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
835 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
836 struct r600_pipe_shader_selector
*sel
)
838 struct r600_pipe_shader
*p
= sel
->current
, *c
;
841 r600_pipe_shader_destroy(ctx
, p
);
851 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
853 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
854 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
856 if (rctx
->ps_shader
== sel
) {
857 rctx
->ps_shader
= NULL
;
860 r600_delete_shader_selector(ctx
, sel
);
863 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
865 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
866 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
868 if (rctx
->vs_shader
== sel
) {
869 rctx
->vs_shader
= NULL
;
872 r600_delete_shader_selector(ctx
, sel
);
876 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
878 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
879 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
881 if (rctx
->gs_shader
== sel
) {
882 rctx
->gs_shader
= NULL
;
885 r600_delete_shader_selector(ctx
, sel
);
889 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
891 if (state
->dirty_mask
) {
892 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
893 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
894 : util_bitcount(state
->dirty_mask
)*19;
895 state
->atom
.dirty
= true;
899 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
900 struct pipe_constant_buffer
*input
)
902 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
903 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
904 struct pipe_constant_buffer
*cb
;
907 /* Note that the state tracker can unbind constant buffers by
910 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
911 state
->enabled_mask
&= ~(1 << index
);
912 state
->dirty_mask
&= ~(1 << index
);
913 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
917 cb
= &state
->cb
[index
];
918 cb
->buffer_size
= input
->buffer_size
;
920 ptr
= input
->user_buffer
;
923 /* Upload the user buffer. */
924 if (R600_BIG_ENDIAN
) {
926 unsigned i
, size
= input
->buffer_size
;
928 if (!(tmpPtr
= malloc(size
))) {
929 R600_ERR("Failed to allocate BE swap buffer.\n");
933 for (i
= 0; i
< size
/ 4; ++i
) {
934 tmpPtr
[i
] = util_bswap32(((uint32_t *)ptr
)[i
]);
937 u_upload_data(rctx
->b
.uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
940 u_upload_data(rctx
->b
.uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
942 /* account it in gtt */
943 rctx
->b
.gtt
+= input
->buffer_size
;
945 /* Setup the hw buffer. */
946 cb
->buffer_offset
= input
->buffer_offset
;
947 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
948 r600_context_add_resource_size(ctx
, input
->buffer
);
951 state
->enabled_mask
|= 1 << index
;
952 state
->dirty_mask
|= 1 << index
;
953 r600_constant_buffers_dirty(rctx
, state
);
956 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
958 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
960 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
963 rctx
->sample_mask
.sample_mask
= sample_mask
;
964 rctx
->sample_mask
.atom
.dirty
= true;
968 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
969 * doesn't require full swizzles it does need masking and setting alpha
970 * to one, so we setup a set of 5 constants with the masks + alpha value
971 * then in the shader, we AND the 4 components with 0xffffffff or 0,
972 * then OR the alpha with the value given here.
973 * We use a 6th constant to store the txq buffer size in
975 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
977 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
980 struct pipe_constant_buffer cb
;
983 if (!samplers
->views
.dirty_buffer_constants
)
986 samplers
->views
.dirty_buffer_constants
= FALSE
;
988 bits
= util_last_bit(samplers
->views
.enabled_mask
);
989 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
990 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
991 memset(samplers
->buffer_constants
, 0, array_size
);
992 for (i
= 0; i
< bits
; i
++) {
993 if (samplers
->views
.enabled_mask
& (1 << i
)) {
995 const struct util_format_description
*desc
;
996 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
998 for (j
= 0; j
< 4; j
++)
999 if (j
< desc
->nr_channels
)
1000 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1002 samplers
->buffer_constants
[offset
+j
] = 0x0;
1003 if (desc
->nr_channels
< 4) {
1004 if (desc
->channel
[0].pure_integer
)
1005 samplers
->buffer_constants
[offset
+4] = 1;
1007 samplers
->buffer_constants
[offset
+4] = 0x3f800000;
1009 samplers
->buffer_constants
[offset
+ 4] = 0;
1011 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1016 cb
.user_buffer
= samplers
->buffer_constants
;
1017 cb
.buffer_offset
= 0;
1018 cb
.buffer_size
= array_size
;
1019 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1020 pipe_resource_reference(&cb
.buffer
, NULL
);
1023 /* On evergreen we only need to store the buffer size for TXQ */
1024 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1026 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1028 uint32_t array_size
;
1029 struct pipe_constant_buffer cb
;
1032 if (!samplers
->views
.dirty_buffer_constants
)
1035 samplers
->views
.dirty_buffer_constants
= FALSE
;
1037 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1038 array_size
= bits
* sizeof(uint32_t) * 4;
1039 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1040 memset(samplers
->buffer_constants
, 0, array_size
);
1041 for (i
= 0; i
< bits
; i
++)
1042 if (samplers
->views
.enabled_mask
& (1 << i
))
1043 samplers
->buffer_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1046 cb
.user_buffer
= samplers
->buffer_constants
;
1047 cb
.buffer_offset
= 0;
1048 cb
.buffer_size
= array_size
;
1049 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1050 pipe_resource_reference(&cb
.buffer
, NULL
);
1053 static void r600_setup_txq_cube_array_constants(struct r600_context
*rctx
, int shader_type
)
1055 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1057 uint32_t array_size
;
1058 struct pipe_constant_buffer cb
;
1061 if (!samplers
->views
.dirty_txq_constants
)
1064 samplers
->views
.dirty_txq_constants
= FALSE
;
1066 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1067 array_size
= bits
* sizeof(uint32_t) * 4;
1068 samplers
->txq_constants
= realloc(samplers
->txq_constants
, array_size
);
1069 memset(samplers
->txq_constants
, 0, array_size
);
1070 for (i
= 0; i
< bits
; i
++)
1071 if (samplers
->views
.enabled_mask
& (1 << i
))
1072 samplers
->txq_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1075 cb
.user_buffer
= samplers
->txq_constants
;
1076 cb
.buffer_offset
= 0;
1077 cb
.buffer_size
= array_size
;
1078 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_TXQ_CONST_BUFFER
, &cb
);
1079 pipe_resource_reference(&cb
.buffer
, NULL
);
1082 static void update_shader_atom(struct pipe_context
*ctx
,
1083 struct r600_shader_state
*state
,
1084 struct r600_pipe_shader
*shader
)
1086 state
->shader
= shader
;
1088 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1089 state
->atom
.dirty
= true;
1090 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1092 state
->atom
.num_dw
= 0;
1093 state
->atom
.dirty
= false;
1097 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1099 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1100 rctx
->shader_stages
.geom_enable
= enable
;
1101 rctx
->shader_stages
.atom
.dirty
= true;
1104 if (rctx
->gs_rings
.enable
!= enable
) {
1105 rctx
->gs_rings
.enable
= enable
;
1106 rctx
->gs_rings
.atom
.dirty
= true;
1108 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1109 unsigned size
= 0x1C000;
1110 rctx
->gs_rings
.esgs_ring
.buffer
=
1111 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1112 PIPE_USAGE_STATIC
, size
);
1113 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1117 rctx
->gs_rings
.gsvs_ring
.buffer
=
1118 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1119 PIPE_USAGE_STATIC
, size
);
1120 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1124 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1125 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1126 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1127 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1129 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1130 R600_GS_RING_CONST_BUFFER
, NULL
);
1131 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1132 R600_GS_RING_CONST_BUFFER
, NULL
);
1137 static bool r600_update_derived_state(struct r600_context
*rctx
)
1139 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1140 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1143 if (!rctx
->blitter
->running
) {
1146 /* Decompress textures if needed. */
1147 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1148 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1149 if (views
->compressed_depthtex_mask
) {
1150 r600_decompress_depth_textures(rctx
, views
);
1152 if (views
->compressed_colortex_mask
) {
1153 r600_decompress_color_textures(rctx
, views
);
1158 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1160 if (rctx
->gs_shader
) {
1161 r600_shader_select(ctx
, rctx
->gs_shader
, &gs_dirty
);
1162 if (unlikely(!rctx
->gs_shader
->current
))
1165 if (!rctx
->shader_stages
.geom_enable
) {
1166 rctx
->shader_stages
.geom_enable
= true;
1167 rctx
->shader_stages
.atom
.dirty
= true;
1170 /* gs_shader provides GS and VS (copy shader) */
1171 if (unlikely(rctx
->geometry_shader
.shader
!= rctx
->gs_shader
->current
)) {
1172 update_shader_atom(ctx
, &rctx
->geometry_shader
, rctx
->gs_shader
->current
);
1173 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->gs_shader
->current
->gs_copy_shader
);
1174 /* Update clip misc state. */
1175 if (rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1176 rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
1177 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
;
1178 rctx
->clip_misc_state
.clip_dist_write
= rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
;
1179 rctx
->clip_misc_state
.atom
.dirty
= true;
1183 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1184 if (unlikely(!rctx
->vs_shader
->current
))
1187 /* vs_shader is used as ES */
1188 if (unlikely(vs_dirty
|| rctx
->export_shader
.shader
!= rctx
->vs_shader
->current
)) {
1189 update_shader_atom(ctx
, &rctx
->export_shader
, rctx
->vs_shader
->current
);
1192 if (unlikely(rctx
->geometry_shader
.shader
)) {
1193 update_shader_atom(ctx
, &rctx
->geometry_shader
, NULL
);
1194 update_shader_atom(ctx
, &rctx
->export_shader
, NULL
);
1195 rctx
->shader_stages
.geom_enable
= false;
1196 rctx
->shader_stages
.atom
.dirty
= true;
1199 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1200 if (unlikely(!rctx
->vs_shader
->current
))
1203 if (unlikely(vs_dirty
|| rctx
->vertex_shader
.shader
!= rctx
->vs_shader
->current
)) {
1204 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->vs_shader
->current
);
1206 /* Update clip misc state. */
1207 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1208 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
1209 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
1210 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
1211 rctx
->clip_misc_state
.atom
.dirty
= true;
1216 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1217 if (unlikely(!rctx
->ps_shader
->current
))
1220 if (unlikely(ps_dirty
|| rctx
->pixel_shader
.shader
!= rctx
->ps_shader
->current
)) {
1222 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1223 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1224 rctx
->cb_misc_state
.atom
.dirty
= true;
1227 if (rctx
->b
.chip_class
<= R700
) {
1228 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1230 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1231 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1232 rctx
->cb_misc_state
.atom
.dirty
= true;
1236 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1237 evergreen_update_db_shader_control(rctx
);
1239 r600_update_db_shader_control(rctx
);
1242 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1243 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1244 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1246 if (rctx
->b
.chip_class
>= EVERGREEN
)
1247 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1249 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1252 update_shader_atom(ctx
, &rctx
->pixel_shader
, rctx
->ps_shader
->current
);
1255 /* on R600 we stuff masks + txq info into one constant buffer */
1256 /* on evergreen we only need a txq info one */
1257 if (rctx
->b
.chip_class
< EVERGREEN
) {
1258 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1259 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1260 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1261 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1262 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.uses_tex_buffers
)
1263 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1265 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1266 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1267 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1268 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1269 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.uses_tex_buffers
)
1270 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1274 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1275 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1276 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1277 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_VERTEX
);
1278 if (rctx
->gs_shader
&& rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1279 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1281 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1282 if (!r600_adjust_gprs(rctx
)) {
1283 /* discard rendering */
1288 blend_disable
= (rctx
->dual_src_blend
&&
1289 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1291 if (blend_disable
!= rctx
->force_blend_disable
) {
1292 rctx
->force_blend_disable
= blend_disable
;
1293 r600_bind_blend_state_internal(rctx
,
1294 rctx
->blend_state
.cso
,
1301 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1303 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1304 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1306 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1307 state
->pa_cl_clip_cntl
|
1308 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1309 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1310 state
->pa_cl_vs_out_cntl
|
1311 (state
->clip_plane_enable
& state
->clip_dist_write
));
1314 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1316 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1317 struct pipe_draw_info info
= *dinfo
;
1318 struct pipe_index_buffer ib
= {};
1320 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1322 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1327 if (!rctx
->vs_shader
|| !rctx
->ps_shader
) {
1332 /* make sure that the gfx ring is only one active */
1333 if (rctx
->b
.rings
.dma
.cs
) {
1334 rctx
->b
.rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
);
1337 if (!r600_update_derived_state(rctx
)) {
1338 /* useless to render because current rendering command
1345 /* Initialize the index buffer struct. */
1346 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1347 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1348 ib
.index_size
= rctx
->index_buffer
.index_size
;
1349 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1351 /* Translate 8-bit indices to 16-bit. */
1352 if (ib
.index_size
== 1) {
1353 struct pipe_resource
*out_buffer
= NULL
;
1354 unsigned out_offset
;
1357 u_upload_alloc(rctx
->b
.uploader
, 0, info
.count
* 2,
1358 &out_offset
, &out_buffer
, &ptr
);
1360 util_shorten_ubyte_elts_to_userptr(
1361 &rctx
->b
.b
, &ib
, 0, ib
.offset
, info
.count
, ptr
);
1363 pipe_resource_reference(&ib
.buffer
, NULL
);
1364 ib
.user_buffer
= NULL
;
1365 ib
.buffer
= out_buffer
;
1366 ib
.offset
= out_offset
;
1370 /* Upload the index buffer.
1371 * The upload is skipped for small index counts on little-endian machines
1372 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1373 * Note: Instanced rendering in combination with immediate indices hangs. */
1374 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.instance_count
> 1 ||
1375 info
.count
*ib
.index_size
> 20)) {
1376 u_upload_data(rctx
->b
.uploader
, 0, info
.count
* ib
.index_size
,
1377 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1378 ib
.user_buffer
= NULL
;
1381 info
.index_bias
= info
.start
;
1384 /* Set the index offset and primitive restart. */
1385 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1386 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1387 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
) {
1388 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1389 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1390 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1391 rctx
->vgt_state
.atom
.dirty
= true;
1394 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1395 if (rctx
->b
.chip_class
== R600
) {
1396 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1397 rctx
->cb_misc_state
.atom
.dirty
= true;
1401 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1402 r600_flush_emit(rctx
);
1404 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1405 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1408 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1411 /* Update start instance. */
1412 if (rctx
->last_start_instance
!= info
.start_instance
) {
1413 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1414 rctx
->last_start_instance
= info
.start_instance
;
1417 /* Update the primitive type. */
1418 if (rctx
->last_primitive_type
!= info
.mode
) {
1419 unsigned ls_mask
= 0;
1421 if (info
.mode
== PIPE_PRIM_LINES
)
1423 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1424 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1427 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1428 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1429 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1430 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1431 r600_conv_pipe_prim(info
.mode
));
1433 rctx
->last_primitive_type
= info
.mode
;
1437 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->b
.predicate_drawing
);
1438 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1440 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->b
.predicate_drawing
);
1441 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1442 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1443 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1445 if (ib
.user_buffer
) {
1446 unsigned size_bytes
= info
.count
*ib
.index_size
;
1447 unsigned size_dw
= align(size_bytes
, 4) / 4;
1448 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->b
.predicate_drawing
);
1449 cs
->buf
[cs
->cdw
++] = info
.count
;
1450 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1451 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1454 uint64_t va
= r600_resource_va(ctx
->screen
, ib
.buffer
) + ib
.offset
;
1455 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->b
.predicate_drawing
);
1456 cs
->buf
[cs
->cdw
++] = va
;
1457 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1458 cs
->buf
[cs
->cdw
++] = info
.count
;
1459 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1460 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1461 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1464 if (info
.count_from_stream_output
) {
1465 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1466 uint64_t va
= r600_resource_va(&rctx
->screen
->b
.b
, (void*)t
->buf_filled_size
) + t
->buf_filled_size_offset
;
1468 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1470 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1471 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1472 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1473 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1474 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1475 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1477 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1478 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, t
->buf_filled_size
, RADEON_USAGE_READ
);
1481 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->b
.predicate_drawing
);
1482 cs
->buf
[cs
->cdw
++] = info
.count
;
1483 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1484 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1487 if (rctx
->screen
->b
.trace_bo
) {
1488 r600_trace_emit(rctx
);
1491 /* Set the depth buffer as dirty. */
1492 if (rctx
->framebuffer
.state
.zsbuf
) {
1493 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1494 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1496 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1498 if (rctx
->framebuffer
.compressed_cb_mask
) {
1499 struct pipe_surface
*surf
;
1500 struct r600_texture
*rtex
;
1501 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1504 unsigned i
= u_bit_scan(&mask
);
1505 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1506 rtex
= (struct r600_texture
*)surf
->texture
;
1508 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1513 pipe_resource_reference(&ib
.buffer
, NULL
);
1514 rctx
->b
.num_draw_calls
++;
1517 void r600_draw_rectangle(struct blitter_context
*blitter
,
1518 int x1
, int y1
, int x2
, int y2
, float depth
,
1519 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1521 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1522 struct pipe_viewport_state viewport
;
1523 struct pipe_resource
*buf
= NULL
;
1524 unsigned offset
= 0;
1527 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1528 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1532 /* Some operations (like color resolve on r6xx) don't work
1533 * with the conventional primitive types.
1534 * One that works is PT_RECTLIST, which we use here. */
1536 /* setup viewport */
1537 viewport
.scale
[0] = 1.0f
;
1538 viewport
.scale
[1] = 1.0f
;
1539 viewport
.scale
[2] = 1.0f
;
1540 viewport
.scale
[3] = 1.0f
;
1541 viewport
.translate
[0] = 0.0f
;
1542 viewport
.translate
[1] = 0.0f
;
1543 viewport
.translate
[2] = 0.0f
;
1544 viewport
.translate
[3] = 0.0f
;
1545 rctx
->b
.b
.set_viewport_states(&rctx
->b
.b
, 0, 1, &viewport
);
1547 /* Upload vertices. The hw rectangle has only 3 vertices,
1548 * I guess the 4th one is derived from the first 3.
1549 * The vertex specification should match u_blitter's vertex element state. */
1550 u_upload_alloc(rctx
->b
.uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1567 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1568 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1569 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1573 util_draw_vertex_buffer(&rctx
->b
.b
, NULL
, buf
, rctx
->blitter
->vb_slot
, offset
,
1574 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1575 pipe_resource_reference(&buf
, NULL
);
1578 uint32_t r600_translate_stencil_op(int s_op
)
1581 case PIPE_STENCIL_OP_KEEP
:
1582 return V_028800_STENCIL_KEEP
;
1583 case PIPE_STENCIL_OP_ZERO
:
1584 return V_028800_STENCIL_ZERO
;
1585 case PIPE_STENCIL_OP_REPLACE
:
1586 return V_028800_STENCIL_REPLACE
;
1587 case PIPE_STENCIL_OP_INCR
:
1588 return V_028800_STENCIL_INCR
;
1589 case PIPE_STENCIL_OP_DECR
:
1590 return V_028800_STENCIL_DECR
;
1591 case PIPE_STENCIL_OP_INCR_WRAP
:
1592 return V_028800_STENCIL_INCR_WRAP
;
1593 case PIPE_STENCIL_OP_DECR_WRAP
:
1594 return V_028800_STENCIL_DECR_WRAP
;
1595 case PIPE_STENCIL_OP_INVERT
:
1596 return V_028800_STENCIL_INVERT
;
1598 R600_ERR("Unknown stencil op %d", s_op
);
1605 uint32_t r600_translate_fill(uint32_t func
)
1608 case PIPE_POLYGON_MODE_FILL
:
1610 case PIPE_POLYGON_MODE_LINE
:
1612 case PIPE_POLYGON_MODE_POINT
:
1620 unsigned r600_tex_wrap(unsigned wrap
)
1624 case PIPE_TEX_WRAP_REPEAT
:
1625 return V_03C000_SQ_TEX_WRAP
;
1626 case PIPE_TEX_WRAP_CLAMP
:
1627 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1628 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1629 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1630 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1631 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1632 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1633 return V_03C000_SQ_TEX_MIRROR
;
1634 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1635 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1636 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1637 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1638 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1639 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1643 unsigned r600_tex_filter(unsigned filter
)
1647 case PIPE_TEX_FILTER_NEAREST
:
1648 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1649 case PIPE_TEX_FILTER_LINEAR
:
1650 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1654 unsigned r600_tex_mipfilter(unsigned filter
)
1657 case PIPE_TEX_MIPFILTER_NEAREST
:
1658 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1659 case PIPE_TEX_MIPFILTER_LINEAR
:
1660 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1662 case PIPE_TEX_MIPFILTER_NONE
:
1663 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1667 unsigned r600_tex_compare(unsigned compare
)
1671 case PIPE_FUNC_NEVER
:
1672 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1673 case PIPE_FUNC_LESS
:
1674 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1675 case PIPE_FUNC_EQUAL
:
1676 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1677 case PIPE_FUNC_LEQUAL
:
1678 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1679 case PIPE_FUNC_GREATER
:
1680 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1681 case PIPE_FUNC_NOTEQUAL
:
1682 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1683 case PIPE_FUNC_GEQUAL
:
1684 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1685 case PIPE_FUNC_ALWAYS
:
1686 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1690 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1692 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1693 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1695 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1696 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1699 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1701 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1702 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1704 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1705 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1706 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1707 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1708 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1711 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1714 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1715 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
1720 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
1721 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1722 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->bo
, RADEON_USAGE_READ
));
1725 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1726 struct pipe_resource
*texture
,
1727 const struct pipe_surface
*templ
,
1728 unsigned width
, unsigned height
)
1730 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1732 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1733 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1734 if (surface
== NULL
)
1736 pipe_reference_init(&surface
->base
.reference
, 1);
1737 pipe_resource_reference(&surface
->base
.texture
, texture
);
1738 surface
->base
.context
= pipe
;
1739 surface
->base
.format
= templ
->format
;
1740 surface
->base
.width
= width
;
1741 surface
->base
.height
= height
;
1742 surface
->base
.u
= templ
->u
;
1743 return &surface
->base
;
1746 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1747 struct pipe_resource
*tex
,
1748 const struct pipe_surface
*templ
)
1750 unsigned level
= templ
->u
.tex
.level
;
1752 return r600_create_surface_custom(pipe
, tex
, templ
,
1753 u_minify(tex
->width0
, level
),
1754 u_minify(tex
->height0
, level
));
1757 static void r600_surface_destroy(struct pipe_context
*pipe
,
1758 struct pipe_surface
*surface
)
1760 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1761 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
1762 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
1763 pipe_resource_reference(&surface
->texture
, NULL
);
1767 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
1768 const unsigned char *swizzle_view
,
1772 unsigned char swizzle
[4];
1773 unsigned result
= 0;
1774 const uint32_t tex_swizzle_shift
[4] = {
1777 const uint32_t vtx_swizzle_shift
[4] = {
1780 const uint32_t swizzle_bit
[4] = {
1783 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
1786 swizzle_shift
= vtx_swizzle_shift
;
1789 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1791 memcpy(swizzle
, swizzle_format
, 4);
1795 for (i
= 0; i
< 4; i
++) {
1796 switch (swizzle
[i
]) {
1797 case UTIL_FORMAT_SWIZZLE_Y
:
1798 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1800 case UTIL_FORMAT_SWIZZLE_Z
:
1801 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1803 case UTIL_FORMAT_SWIZZLE_W
:
1804 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1806 case UTIL_FORMAT_SWIZZLE_0
:
1807 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1809 case UTIL_FORMAT_SWIZZLE_1
:
1810 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1812 default: /* UTIL_FORMAT_SWIZZLE_X */
1813 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1819 /* texture format translate */
1820 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1821 enum pipe_format format
,
1822 const unsigned char *swizzle_view
,
1823 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1825 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1826 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1827 const struct util_format_description
*desc
;
1828 boolean uniform
= TRUE
;
1829 bool enable_s3tc
= rscreen
->b
.info
.drm_minor
>= 9;
1830 bool is_srgb_valid
= FALSE
;
1831 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
1832 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
1835 const uint32_t sign_bit
[4] = {
1836 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1837 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1838 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1839 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1841 desc
= util_format_description(format
);
1843 /* Depth and stencil swizzling is handled separately. */
1844 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
1845 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
1848 /* Colorspace (return non-RGB formats directly). */
1849 switch (desc
->colorspace
) {
1850 /* Depth stencil formats */
1851 case UTIL_FORMAT_COLORSPACE_ZS
:
1853 /* Depth sampler formats. */
1854 case PIPE_FORMAT_Z16_UNORM
:
1855 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1858 case PIPE_FORMAT_Z24X8_UNORM
:
1859 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1860 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1863 case PIPE_FORMAT_X8Z24_UNORM
:
1864 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1865 if (rscreen
->b
.chip_class
< EVERGREEN
)
1867 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1870 case PIPE_FORMAT_Z32_FLOAT
:
1871 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1872 result
= FMT_32_FLOAT
;
1874 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1875 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1876 result
= FMT_X24_8_32_FLOAT
;
1878 /* Stencil sampler formats. */
1879 case PIPE_FORMAT_S8_UINT
:
1880 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1881 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1884 case PIPE_FORMAT_X24S8_UINT
:
1885 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1886 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1889 case PIPE_FORMAT_S8X24_UINT
:
1890 if (rscreen
->b
.chip_class
< EVERGREEN
)
1892 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1893 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1896 case PIPE_FORMAT_X32_S8X24_UINT
:
1897 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1898 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1899 result
= FMT_X24_8_32_FLOAT
;
1905 case UTIL_FORMAT_COLORSPACE_YUV
:
1906 yuv_format
|= (1 << 30);
1908 case PIPE_FORMAT_UYVY
:
1909 case PIPE_FORMAT_YUYV
:
1913 goto out_unknown
; /* XXX */
1915 case UTIL_FORMAT_COLORSPACE_SRGB
:
1916 word4
|= S_038010_FORCE_DEGAMMA(1);
1923 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1928 case PIPE_FORMAT_RGTC1_SNORM
:
1929 case PIPE_FORMAT_LATC1_SNORM
:
1930 word4
|= sign_bit
[0];
1931 case PIPE_FORMAT_RGTC1_UNORM
:
1932 case PIPE_FORMAT_LATC1_UNORM
:
1935 case PIPE_FORMAT_RGTC2_SNORM
:
1936 case PIPE_FORMAT_LATC2_SNORM
:
1937 word4
|= sign_bit
[0] | sign_bit
[1];
1938 case PIPE_FORMAT_RGTC2_UNORM
:
1939 case PIPE_FORMAT_LATC2_UNORM
:
1947 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1952 if (!util_format_s3tc_enabled
) {
1957 case PIPE_FORMAT_DXT1_RGB
:
1958 case PIPE_FORMAT_DXT1_RGBA
:
1959 case PIPE_FORMAT_DXT1_SRGB
:
1960 case PIPE_FORMAT_DXT1_SRGBA
:
1962 is_srgb_valid
= TRUE
;
1964 case PIPE_FORMAT_DXT3_RGBA
:
1965 case PIPE_FORMAT_DXT3_SRGBA
:
1967 is_srgb_valid
= TRUE
;
1969 case PIPE_FORMAT_DXT5_RGBA
:
1970 case PIPE_FORMAT_DXT5_SRGBA
:
1972 is_srgb_valid
= TRUE
;
1979 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1981 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1982 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1985 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1986 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1994 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1995 result
= FMT_5_9_9_9_SHAREDEXP
;
1997 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1998 result
= FMT_10_11_11_FLOAT
;
2003 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2004 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2005 word4
|= sign_bit
[i
];
2009 /* R8G8Bx_SNORM - XXX CxV8U8 */
2011 /* See whether the components are of the same size. */
2012 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2013 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2016 /* Non-uniform formats. */
2018 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2019 desc
->channel
[0].pure_integer
)
2020 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2021 switch(desc
->nr_channels
) {
2023 if (desc
->channel
[0].size
== 5 &&
2024 desc
->channel
[1].size
== 6 &&
2025 desc
->channel
[2].size
== 5) {
2031 if (desc
->channel
[0].size
== 5 &&
2032 desc
->channel
[1].size
== 5 &&
2033 desc
->channel
[2].size
== 5 &&
2034 desc
->channel
[3].size
== 1) {
2035 result
= FMT_1_5_5_5
;
2038 if (desc
->channel
[0].size
== 10 &&
2039 desc
->channel
[1].size
== 10 &&
2040 desc
->channel
[2].size
== 10 &&
2041 desc
->channel
[3].size
== 2) {
2042 result
= FMT_2_10_10_10
;
2050 /* Find the first non-VOID channel. */
2051 for (i
= 0; i
< 4; i
++) {
2052 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2060 /* uniform formats */
2061 switch (desc
->channel
[i
].type
) {
2062 case UTIL_FORMAT_TYPE_UNSIGNED
:
2063 case UTIL_FORMAT_TYPE_SIGNED
:
2065 if (!desc
->channel
[i
].normalized
&&
2066 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2070 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2071 desc
->channel
[i
].pure_integer
)
2072 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2074 switch (desc
->channel
[i
].size
) {
2076 switch (desc
->nr_channels
) {
2081 result
= FMT_4_4_4_4
;
2086 switch (desc
->nr_channels
) {
2094 result
= FMT_8_8_8_8
;
2095 is_srgb_valid
= TRUE
;
2100 switch (desc
->nr_channels
) {
2108 result
= FMT_16_16_16_16
;
2113 switch (desc
->nr_channels
) {
2121 result
= FMT_32_32_32_32
;
2127 case UTIL_FORMAT_TYPE_FLOAT
:
2128 switch (desc
->channel
[i
].size
) {
2130 switch (desc
->nr_channels
) {
2132 result
= FMT_16_FLOAT
;
2135 result
= FMT_16_16_FLOAT
;
2138 result
= FMT_16_16_16_16_FLOAT
;
2143 switch (desc
->nr_channels
) {
2145 result
= FMT_32_FLOAT
;
2148 result
= FMT_32_32_FLOAT
;
2151 result
= FMT_32_32_32_32_FLOAT
;
2160 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2165 *yuv_format_p
= yuv_format
;
2168 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2172 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2174 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2175 struct r600_resource
*rbuffer
= r600_resource(buf
);
2176 unsigned i
, shader
, mask
, alignment
= rbuffer
->buf
->alignment
;
2178 /* Discard the buffer. */
2179 pb_reference(&rbuffer
->buf
, NULL
);
2181 /* Create a new one in the same pipe_resource. */
2182 r600_init_resource(&rctx
->screen
->b
, rbuffer
, rbuffer
->b
.b
.width0
, alignment
,
2183 TRUE
, rbuffer
->b
.b
.usage
);
2185 /* We changed the buffer, now we need to bind it where the old one was bound. */
2186 /* Vertex buffers. */
2187 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2189 i
= u_bit_scan(&mask
);
2190 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2191 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2192 r600_vertex_buffers_dirty(rctx
);
2195 /* Streamout buffers. */
2196 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2197 if (rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2198 if (rctx
->b
.streamout
.begin_emitted
) {
2199 r600_emit_streamout_end(&rctx
->b
);
2201 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2202 r600_streamout_buffers_dirty(&rctx
->b
);
2206 /* Constant buffers. */
2207 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2208 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2210 uint32_t mask
= state
->enabled_mask
;
2213 unsigned i
= u_bit_scan(&mask
);
2214 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2216 state
->dirty_mask
|= 1 << i
;
2220 r600_constant_buffers_dirty(rctx
, state
);
2224 /* XXX TODO: texture buffer objects */
2227 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2229 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2231 if (rctx
->db_misc_state
.occlusion_query_enabled
!= enable
) {
2232 rctx
->db_misc_state
.occlusion_query_enabled
= enable
;
2233 rctx
->db_misc_state
.atom
.dirty
= true;
2237 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2238 bool include_draw_vbo
)
2240 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2243 /* keep this at the end of this file, please */
2244 void r600_init_common_state_functions(struct r600_context
*rctx
)
2246 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2247 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2248 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2249 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2250 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2251 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2252 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2253 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2254 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2255 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2256 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2257 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2258 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2259 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2260 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2261 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2262 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2263 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2264 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2265 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2266 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2267 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2268 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2269 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2270 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2271 rctx
->b
.b
.set_viewport_states
= r600_set_viewport_states
;
2272 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2273 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2274 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2275 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2276 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2277 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2278 rctx
->b
.b
.create_surface
= r600_create_surface
;
2279 rctx
->b
.b
.surface_destroy
= r600_surface_destroy
;
2280 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2281 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2282 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2283 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;
2286 void r600_trace_emit(struct r600_context
*rctx
)
2288 struct r600_screen
*rscreen
= rctx
->screen
;
2289 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2293 va
= r600_resource_va(&rscreen
->b
.b
, (void*)rscreen
->b
.trace_bo
);
2294 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rscreen
->b
.trace_bo
, RADEON_USAGE_READWRITE
);
2295 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
2296 radeon_emit(cs
, va
& 0xFFFFFFFFUL
);
2297 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
);
2298 radeon_emit(cs
, cs
->cdw
);
2299 radeon_emit(cs
, rscreen
->b
.cs_count
);
2300 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2301 radeon_emit(cs
, reloc
);