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Merge branch 'gallium-userbuf'
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
36 {
37 struct radeon_winsys_cs *cs = rctx->cs;
38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
39
40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
42 cs->cdw += cb->atom.num_dw;
43 }
44
45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
46 {
47 cb->atom.emit = r600_emit_command_buffer;
48 cb->atom.num_dw = 0;
49 cb->atom.flags = flags;
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
60 {
61 struct radeon_winsys_cs *cs = rctx->cs;
62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
63
64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
69
70 a->flush_flags = 0;
71 }
72
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 struct radeon_winsys_cs *cs = rctx->cs;
76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
78 }
79
80 void r600_init_atom(struct r600_atom *atom,
81 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
82 unsigned num_dw, enum r600_atom_flags flags)
83 {
84 atom->emit = emit;
85 atom->num_dw = num_dw;
86 atom->flags = flags;
87 }
88
89 void r600_init_common_atoms(struct r600_context *rctx)
90 {
91 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
92 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
93 }
94
95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
96 {
97 unsigned flags = 0;
98
99 if (rctx->framebuffer.nr_cbufs) {
100 flags |= S_0085F0_CB_ACTION_ENA(1) |
101 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
102 }
103
104 /* Workaround for broken flushing on some R6xx chipsets. */
105 if (rctx->family == CHIP_RV670 ||
106 rctx->family == CHIP_RS780 ||
107 rctx->family == CHIP_RS880) {
108 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
109 S_0085F0_DEST_BASE_0_ENA(1);
110 }
111 return flags;
112 }
113
114 void r600_texture_barrier(struct pipe_context *ctx)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117
118 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
119 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
120 }
121
122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
123 {
124 static const int prim_conv[] = {
125 V_008958_DI_PT_POINTLIST,
126 V_008958_DI_PT_LINELIST,
127 V_008958_DI_PT_LINELOOP,
128 V_008958_DI_PT_LINESTRIP,
129 V_008958_DI_PT_TRILIST,
130 V_008958_DI_PT_TRISTRIP,
131 V_008958_DI_PT_TRIFAN,
132 V_008958_DI_PT_QUADLIST,
133 V_008958_DI_PT_QUADSTRIP,
134 V_008958_DI_PT_POLYGON,
135 -1,
136 -1,
137 -1,
138 -1
139 };
140
141 *prim = prim_conv[pprim];
142 if (*prim == -1) {
143 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
144 return false;
145 }
146 return true;
147 }
148
149 /* common state between evergreen and r600 */
150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
151 {
152 struct r600_context *rctx = (struct r600_context *)ctx;
153 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
154 struct r600_pipe_state *rstate;
155
156 if (state == NULL)
157 return;
158 rstate = &blend->rstate;
159 rctx->states[rstate->id] = rstate;
160 rctx->cb_target_mask = blend->cb_target_mask;
161 /* Replace every bit except MULTIWRITE_ENABLE. */
162 rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
163 rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
164 rctx->dual_src_blend = blend->dual_src_blend;
165 r600_context_pipe_state_set(rctx, rstate);
166 }
167
168 void r600_set_blend_color(struct pipe_context *ctx,
169 const struct pipe_blend_color *state)
170 {
171 struct r600_context *rctx = (struct r600_context *)ctx;
172 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
173
174 if (rstate == NULL)
175 return;
176
177 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
178 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
179 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
180 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
181 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
182
183 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
184 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
185 r600_context_pipe_state_set(rctx, rstate);
186 }
187
188 static void r600_set_stencil_ref(struct pipe_context *ctx,
189 const struct r600_stencil_ref *state)
190 {
191 struct r600_context *rctx = (struct r600_context *)ctx;
192 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
193
194 if (rstate == NULL)
195 return;
196
197 rstate->id = R600_PIPE_STATE_STENCIL_REF;
198 r600_pipe_state_add_reg(rstate,
199 R_028430_DB_STENCILREFMASK,
200 S_028430_STENCILREF(state->ref_value[0]) |
201 S_028430_STENCILMASK(state->valuemask[0]) |
202 S_028430_STENCILWRITEMASK(state->writemask[0]));
203 r600_pipe_state_add_reg(rstate,
204 R_028434_DB_STENCILREFMASK_BF,
205 S_028434_STENCILREF_BF(state->ref_value[1]) |
206 S_028434_STENCILMASK_BF(state->valuemask[1]) |
207 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
208
209 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
210 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
211 r600_context_pipe_state_set(rctx, rstate);
212 }
213
214 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
215 const struct pipe_stencil_ref *state)
216 {
217 struct r600_context *rctx = (struct r600_context *)ctx;
218 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
219 struct r600_stencil_ref ref;
220
221 rctx->stencil_ref = *state;
222
223 if (!dsa)
224 return;
225
226 ref.ref_value[0] = state->ref_value[0];
227 ref.ref_value[1] = state->ref_value[1];
228 ref.valuemask[0] = dsa->valuemask[0];
229 ref.valuemask[1] = dsa->valuemask[1];
230 ref.writemask[0] = dsa->writemask[0];
231 ref.writemask[1] = dsa->writemask[1];
232
233 r600_set_stencil_ref(ctx, &ref);
234 }
235
236 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
237 {
238 struct r600_context *rctx = (struct r600_context *)ctx;
239 struct r600_pipe_dsa *dsa = state;
240 struct r600_pipe_state *rstate;
241 struct r600_stencil_ref ref;
242
243 if (state == NULL)
244 return;
245 rstate = &dsa->rstate;
246 rctx->states[rstate->id] = rstate;
247 rctx->sx_alpha_test_control &= ~0xff;
248 rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
249 rctx->alpha_ref = dsa->alpha_ref;
250 rctx->alpha_ref_dirty = true;
251 r600_context_pipe_state_set(rctx, rstate);
252
253 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
254 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
255 ref.valuemask[0] = dsa->valuemask[0];
256 ref.valuemask[1] = dsa->valuemask[1];
257 ref.writemask[0] = dsa->writemask[0];
258 ref.writemask[1] = dsa->writemask[1];
259
260 r600_set_stencil_ref(ctx, &ref);
261
262 if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
263 rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
264 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
265 }
266 }
267
268 void r600_set_max_scissor(struct r600_context *rctx)
269 {
270 /* Set a scissor state such that it doesn't do anything. */
271 struct pipe_scissor_state scissor;
272 scissor.minx = 0;
273 scissor.miny = 0;
274 scissor.maxx = 8192;
275 scissor.maxy = 8192;
276
277 r600_set_scissor_state(rctx, &scissor);
278 }
279
280 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
281 {
282 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
283 struct r600_context *rctx = (struct r600_context *)ctx;
284
285 if (state == NULL)
286 return;
287
288 rctx->sprite_coord_enable = rs->sprite_coord_enable;
289 rctx->two_side = rs->two_side;
290 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
291 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
292
293 rctx->rasterizer = rs;
294
295 rctx->states[rs->rstate.id] = &rs->rstate;
296 r600_context_pipe_state_set(rctx, &rs->rstate);
297
298 if (rctx->chip_class >= EVERGREEN) {
299 evergreen_polygon_offset_update(rctx);
300 } else {
301 r600_polygon_offset_update(rctx);
302 }
303
304 /* Workaround for a missing scissor enable on r600. */
305 if (rctx->chip_class == R600) {
306 if (rs->scissor_enable != rctx->scissor_enable) {
307 rctx->scissor_enable = rs->scissor_enable;
308
309 if (rs->scissor_enable) {
310 r600_set_scissor_state(rctx, &rctx->scissor_state);
311 } else {
312 r600_set_max_scissor(rctx);
313 }
314 }
315 }
316 }
317
318 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
319 {
320 struct r600_context *rctx = (struct r600_context *)ctx;
321 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
322
323 if (rctx->rasterizer == rs) {
324 rctx->rasterizer = NULL;
325 }
326 if (rctx->states[rs->rstate.id] == &rs->rstate) {
327 rctx->states[rs->rstate.id] = NULL;
328 }
329 free(rs);
330 }
331
332 void r600_sampler_view_destroy(struct pipe_context *ctx,
333 struct pipe_sampler_view *state)
334 {
335 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
336
337 pipe_resource_reference(&state->texture, NULL);
338 FREE(resource);
339 }
340
341 void r600_delete_state(struct pipe_context *ctx, void *state)
342 {
343 struct r600_context *rctx = (struct r600_context *)ctx;
344 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
345
346 if (rctx->states[rstate->id] == rstate) {
347 rctx->states[rstate->id] = NULL;
348 }
349 for (int i = 0; i < rstate->nregs; i++) {
350 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
351 }
352 free(rstate);
353 }
354
355 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
356 {
357 struct r600_context *rctx = (struct r600_context *)ctx;
358 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
359
360 rctx->vertex_elements = v;
361 if (v) {
362 r600_inval_shader_cache(rctx);
363
364 rctx->states[v->rstate.id] = &v->rstate;
365 r600_context_pipe_state_set(rctx, &v->rstate);
366 }
367 }
368
369 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
370 {
371 struct r600_context *rctx = (struct r600_context *)ctx;
372 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
373
374 if (rctx->states[v->rstate.id] == &v->rstate) {
375 rctx->states[v->rstate.id] = NULL;
376 }
377 if (rctx->vertex_elements == state)
378 rctx->vertex_elements = NULL;
379
380 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
381 FREE(state);
382 }
383
384 void r600_set_index_buffer(struct pipe_context *ctx,
385 const struct pipe_index_buffer *ib)
386 {
387 struct r600_context *rctx = (struct r600_context *)ctx;
388
389 if (ib) {
390 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
391 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
392 } else {
393 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
394 }
395 }
396
397 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
398 const struct pipe_vertex_buffer *buffers)
399 {
400 struct r600_context *rctx = (struct r600_context *)ctx;
401
402 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
403
404 r600_inval_vertex_cache(rctx);
405 rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
406 rctx->nr_vertex_buffers;
407 r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
408 }
409
410 void *r600_create_vertex_elements(struct pipe_context *ctx,
411 unsigned count,
412 const struct pipe_vertex_element *elements)
413 {
414 struct r600_context *rctx = (struct r600_context *)ctx;
415 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
416
417 assert(count < 32);
418 if (!v)
419 return NULL;
420
421 v->count = count;
422 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
423
424 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
425 FREE(v);
426 return NULL;
427 }
428
429 return v;
430 }
431
432 void *r600_create_shader_state(struct pipe_context *ctx,
433 const struct pipe_shader_state *state)
434 {
435 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
436 int r;
437
438 shader->tokens = tgsi_dup_tokens(state->tokens);
439 shader->so = state->stream_output;
440
441 r = r600_pipe_shader_create(ctx, shader);
442 if (r) {
443 return NULL;
444 }
445 return shader;
446 }
447
448 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
449 {
450 struct r600_context *rctx = (struct r600_context *)ctx;
451
452 if (!state) {
453 state = rctx->dummy_pixel_shader;
454 }
455
456 rctx->ps_shader = (struct r600_pipe_shader *)state;
457
458 r600_inval_shader_cache(rctx);
459 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
460
461 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
462 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
463
464 if (rctx->ps_shader && rctx->vs_shader) {
465 r600_adjust_gprs(rctx);
466 }
467 }
468
469 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
470 {
471 struct r600_context *rctx = (struct r600_context *)ctx;
472
473 rctx->vs_shader = (struct r600_pipe_shader *)state;
474 if (state) {
475 r600_inval_shader_cache(rctx);
476 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
477 }
478 if (rctx->ps_shader && rctx->vs_shader) {
479 r600_adjust_gprs(rctx);
480 }
481 }
482
483 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
484 {
485 struct r600_context *rctx = (struct r600_context *)ctx;
486 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
487
488 if (rctx->ps_shader == shader) {
489 rctx->ps_shader = NULL;
490 }
491
492 free(shader->tokens);
493 r600_pipe_shader_destroy(ctx, shader);
494 free(shader);
495 }
496
497 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
498 {
499 struct r600_context *rctx = (struct r600_context *)ctx;
500 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
501
502 if (rctx->vs_shader == shader) {
503 rctx->vs_shader = NULL;
504 }
505
506 free(shader->tokens);
507 r600_pipe_shader_destroy(ctx, shader);
508 free(shader);
509 }
510
511 static void r600_update_alpha_ref(struct r600_context *rctx)
512 {
513 unsigned alpha_ref;
514 struct r600_pipe_state rstate;
515
516 alpha_ref = rctx->alpha_ref;
517 rstate.nregs = 0;
518 if (rctx->export_16bpc)
519 alpha_ref &= ~0x1FFF;
520 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
521
522 r600_context_pipe_state_set(rctx, &rstate);
523 rctx->alpha_ref_dirty = false;
524 }
525
526 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
527 {
528 r600_inval_shader_cache(rctx);
529 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
530 : util_bitcount(state->dirty_mask)*19;
531 r600_atom_dirty(rctx, &state->atom);
532 }
533
534 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
535 struct pipe_constant_buffer *input)
536 {
537 struct r600_context *rctx = (struct r600_context *)ctx;
538 struct r600_constbuf_state *state;
539 struct pipe_constant_buffer *cb;
540 const uint8_t *ptr;
541
542 switch (shader) {
543 case PIPE_SHADER_VERTEX:
544 state = &rctx->vs_constbuf_state;
545 break;
546 case PIPE_SHADER_FRAGMENT:
547 state = &rctx->ps_constbuf_state;
548 break;
549 default:
550 return;
551 }
552
553 /* Note that the state tracker can unbind constant buffers by
554 * passing NULL here.
555 */
556 if (unlikely(!input)) {
557 state->enabled_mask &= ~(1 << index);
558 state->dirty_mask &= ~(1 << index);
559 pipe_resource_reference(&state->cb[index].buffer, NULL);
560 return;
561 }
562
563 cb = &state->cb[index];
564 cb->buffer_size = input->buffer_size;
565
566 ptr = input->user_buffer;
567
568 if (ptr) {
569 /* Upload the user buffer. */
570 if (R600_BIG_ENDIAN) {
571 uint32_t *tmpPtr;
572 unsigned i, size = input->buffer_size;
573
574 if (!(tmpPtr = malloc(size))) {
575 R600_ERR("Failed to allocate BE swap buffer.\n");
576 return;
577 }
578
579 for (i = 0; i < size / 4; ++i) {
580 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
581 }
582
583 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
584 free(tmpPtr);
585 } else {
586 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
587 }
588 } else {
589 /* Setup the hw buffer. */
590 cb->buffer_offset = input->buffer_offset;
591 pipe_resource_reference(&cb->buffer, input->buffer);
592 }
593
594 state->enabled_mask |= 1 << index;
595 state->dirty_mask |= 1 << index;
596 r600_constant_buffers_dirty(rctx, state);
597 }
598
599 struct pipe_stream_output_target *
600 r600_create_so_target(struct pipe_context *ctx,
601 struct pipe_resource *buffer,
602 unsigned buffer_offset,
603 unsigned buffer_size)
604 {
605 struct r600_context *rctx = (struct r600_context *)ctx;
606 struct r600_so_target *t;
607 void *ptr;
608
609 t = CALLOC_STRUCT(r600_so_target);
610 if (!t) {
611 return NULL;
612 }
613
614 t->b.reference.count = 1;
615 t->b.context = ctx;
616 pipe_resource_reference(&t->b.buffer, buffer);
617 t->b.buffer_offset = buffer_offset;
618 t->b.buffer_size = buffer_size;
619
620 t->filled_size = (struct r600_resource*)
621 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
622 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
623 memset(ptr, 0, t->filled_size->buf->size);
624 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
625
626 return &t->b;
627 }
628
629 void r600_so_target_destroy(struct pipe_context *ctx,
630 struct pipe_stream_output_target *target)
631 {
632 struct r600_so_target *t = (struct r600_so_target*)target;
633 pipe_resource_reference(&t->b.buffer, NULL);
634 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
635 FREE(t);
636 }
637
638 void r600_set_so_targets(struct pipe_context *ctx,
639 unsigned num_targets,
640 struct pipe_stream_output_target **targets,
641 unsigned append_bitmask)
642 {
643 struct r600_context *rctx = (struct r600_context *)ctx;
644 unsigned i;
645
646 /* Stop streamout. */
647 if (rctx->num_so_targets) {
648 r600_context_streamout_end(rctx);
649 }
650
651 /* Set the new targets. */
652 for (i = 0; i < num_targets; i++) {
653 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
654 }
655 for (; i < rctx->num_so_targets; i++) {
656 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
657 }
658
659 rctx->num_so_targets = num_targets;
660 rctx->streamout_start = num_targets != 0;
661 rctx->streamout_append_bitmask = append_bitmask;
662 }
663
664 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
665 {
666 struct r600_context *rctx = (struct r600_context *)ctx;
667 int r;
668
669 r600_pipe_shader_destroy(ctx, shader);
670 r = r600_pipe_shader_create(ctx, shader);
671 if (r) {
672 return r;
673 }
674 r600_context_pipe_state_set(rctx, &shader->rstate);
675
676 return 0;
677 }
678
679 static void r600_update_derived_state(struct r600_context *rctx)
680 {
681 struct pipe_context * ctx = (struct pipe_context*)rctx;
682
683 if (!rctx->blitter->running) {
684 if (rctx->have_depth_fb || rctx->have_depth_texture)
685 r600_flush_depth_textures(rctx);
686 }
687
688 if (rctx->chip_class < EVERGREEN) {
689 r600_update_sampler_states(rctx);
690 }
691
692 if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
693 ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
694 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
695 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
696 }
697
698 if (rctx->alpha_ref_dirty) {
699 r600_update_alpha_ref(rctx);
700 }
701
702 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
703 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
704 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
705
706 if (rctx->chip_class >= EVERGREEN)
707 evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
708 else
709 r600_pipe_shader_ps(ctx, rctx->ps_shader);
710
711 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
712 }
713
714 if (rctx->dual_src_blend)
715 rctx->cb_shader_mask = rctx->ps_shader->ps_cb_shader_mask | rctx->fb_cb_shader_mask;
716 else
717 rctx->cb_shader_mask = rctx->fb_cb_shader_mask;
718 }
719
720 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
721 {
722 static const int prim_conv[] = {
723 V_028A6C_OUTPRIM_TYPE_POINTLIST,
724 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
725 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
726 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
727 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
728 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
729 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
730 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
731 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
732 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
733 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
734 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
735 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
736 V_028A6C_OUTPRIM_TYPE_TRISTRIP
737 };
738 assert(mode < Elements(prim_conv));
739
740 return prim_conv[mode];
741 }
742
743 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
744 {
745 struct r600_context *rctx = (struct r600_context *)ctx;
746 struct pipe_draw_info info = *dinfo;
747 struct pipe_index_buffer ib = {};
748 unsigned prim, mask, ls_mask = 0;
749 struct r600_block *dirty_block = NULL, *next_block = NULL;
750 struct r600_atom *state = NULL, *next_state = NULL;
751 struct radeon_winsys_cs *cs = rctx->cs;
752 uint64_t va;
753 uint8_t *ptr;
754
755 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
756 !r600_conv_pipe_prim(info.mode, &prim)) {
757 assert(0);
758 return;
759 }
760
761 if (!rctx->vs_shader) {
762 assert(0);
763 return;
764 }
765
766 r600_update_derived_state(rctx);
767
768 if (info.indexed) {
769 /* Initialize the index buffer struct. */
770 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
771 ib.user_buffer = rctx->index_buffer.user_buffer;
772 ib.index_size = rctx->index_buffer.index_size;
773 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
774
775 /* Translate or upload, if needed. */
776 r600_translate_index_buffer(rctx, &ib, info.count);
777
778 ptr = (uint8_t*)ib.user_buffer;
779 if (!ib.buffer && ptr) {
780 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
781 ptr, &ib.offset, &ib.buffer);
782 }
783 } else {
784 info.index_bias = info.start;
785 if (info.count_from_stream_output) {
786 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
787 }
788 }
789
790 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
791
792 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
793 rctx->vgt.id = R600_PIPE_STATE_VGT;
794 rctx->vgt.nregs = 0;
795 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
796 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
797 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask);
798 r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0);
799 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
800 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
801 r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
802 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
803 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
804 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
805 if (rctx->chip_class <= R700)
806 r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
807 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
808 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
809
810 if (rctx->chip_class <= R700)
811 r600_pipe_state_add_reg(&rctx->vgt, R_0280A4_CB_COLOR1_INFO, 0);
812 else
813 r600_pipe_state_add_reg(&rctx->vgt, 0x28CAC, 0);
814 }
815
816 rctx->vgt.nregs = 0;
817 r600_pipe_state_mod_reg(&rctx->vgt, prim);
818 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
819 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
820 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
821 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
822 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
823 r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
824 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
825 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
826
827 if (prim == V_008958_DI_PT_LINELIST)
828 ls_mask = 1;
829 else if (prim == V_008958_DI_PT_LINESTRIP)
830 ls_mask = 2;
831 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
832 if (rctx->chip_class <= R700)
833 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
834 r600_pipe_state_mod_reg(&rctx->vgt,
835 rctx->vs_shader->pa_cl_vs_out_cntl |
836 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
837 r600_pipe_state_mod_reg(&rctx->vgt,
838 rctx->pa_cl_clip_cntl |
839 (rctx->vs_shader->shader.clip_dist_write ||
840 rctx->vs_shader->shader.vs_prohibit_ucps ?
841 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
842
843 if (rctx->dual_src_blend) {
844 r600_pipe_state_mod_reg(&rctx->vgt,
845 rctx->color0_format);
846 }
847
848 r600_context_pipe_state_set(rctx, &rctx->vgt);
849
850 /* Emit states (the function expects that we emit at most 17 dwords here). */
851 r600_need_cs_space(rctx, 0, TRUE);
852
853 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
854 r600_emit_atom(rctx, state);
855 }
856 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
857 r600_context_block_emit_dirty(rctx, dirty_block);
858 }
859 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
860 r600_context_block_resource_emit_dirty(rctx, dirty_block);
861 }
862 rctx->pm4_dirty_cdwords = 0;
863
864 /* Enable stream out if needed. */
865 if (rctx->streamout_start) {
866 r600_context_streamout_begin(rctx);
867 rctx->streamout_start = FALSE;
868 }
869
870 /* draw packet */
871 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
872 cs->buf[cs->cdw++] = ib.index_size == 4 ?
873 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
874 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
875 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
876 cs->buf[cs->cdw++] = info.instance_count;
877 if (info.indexed) {
878 va = r600_resource_va(ctx->screen, ib.buffer);
879 va += ib.offset;
880 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
881 cs->buf[cs->cdw++] = va;
882 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
883 cs->buf[cs->cdw++] = info.count;
884 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
885 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
886 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
887 } else {
888 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
889 cs->buf[cs->cdw++] = info.count;
890 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
891 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
892 }
893
894 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
895
896 if (rctx->framebuffer.zsbuf)
897 {
898 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
899 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
900 }
901
902 pipe_resource_reference(&ib.buffer, NULL);
903 }
904
905 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
906 struct r600_pipe_state *state,
907 uint32_t offset, uint32_t value,
908 uint32_t range_id, uint32_t block_id,
909 struct r600_resource *bo,
910 enum radeon_bo_usage usage)
911
912 {
913 struct r600_range *range;
914 struct r600_block *block;
915
916 if (bo) assert(usage);
917
918 range = &ctx->range[range_id];
919 block = range->blocks[block_id];
920 state->regs[state->nregs].block = block;
921 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
922
923 state->regs[state->nregs].value = value;
924 state->regs[state->nregs].bo = bo;
925 state->regs[state->nregs].bo_usage = usage;
926
927 state->nregs++;
928 assert(state->nregs < R600_BLOCK_MAX_REG);
929 }
930
931 void _r600_pipe_state_add_reg(struct r600_context *ctx,
932 struct r600_pipe_state *state,
933 uint32_t offset, uint32_t value,
934 uint32_t range_id, uint32_t block_id)
935 {
936 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
937 range_id, block_id, NULL, 0);
938 }
939
940 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
941 uint32_t offset, uint32_t value,
942 struct r600_resource *bo,
943 enum radeon_bo_usage usage)
944 {
945 if (bo) assert(usage);
946
947 state->regs[state->nregs].id = offset;
948 state->regs[state->nregs].block = NULL;
949 state->regs[state->nregs].value = value;
950 state->regs[state->nregs].bo = bo;
951 state->regs[state->nregs].bo_usage = usage;
952
953 state->nregs++;
954 assert(state->nregs < R600_BLOCK_MAX_REG);
955 }
956
957 uint32_t r600_translate_stencil_op(int s_op)
958 {
959 switch (s_op) {
960 case PIPE_STENCIL_OP_KEEP:
961 return V_028800_STENCIL_KEEP;
962 case PIPE_STENCIL_OP_ZERO:
963 return V_028800_STENCIL_ZERO;
964 case PIPE_STENCIL_OP_REPLACE:
965 return V_028800_STENCIL_REPLACE;
966 case PIPE_STENCIL_OP_INCR:
967 return V_028800_STENCIL_INCR;
968 case PIPE_STENCIL_OP_DECR:
969 return V_028800_STENCIL_DECR;
970 case PIPE_STENCIL_OP_INCR_WRAP:
971 return V_028800_STENCIL_INCR_WRAP;
972 case PIPE_STENCIL_OP_DECR_WRAP:
973 return V_028800_STENCIL_DECR_WRAP;
974 case PIPE_STENCIL_OP_INVERT:
975 return V_028800_STENCIL_INVERT;
976 default:
977 R600_ERR("Unknown stencil op %d", s_op);
978 assert(0);
979 break;
980 }
981 return 0;
982 }
983
984 uint32_t r600_translate_fill(uint32_t func)
985 {
986 switch(func) {
987 case PIPE_POLYGON_MODE_FILL:
988 return 2;
989 case PIPE_POLYGON_MODE_LINE:
990 return 1;
991 case PIPE_POLYGON_MODE_POINT:
992 return 0;
993 default:
994 assert(0);
995 return 0;
996 }
997 }
998
999 unsigned r600_tex_wrap(unsigned wrap)
1000 {
1001 switch (wrap) {
1002 default:
1003 case PIPE_TEX_WRAP_REPEAT:
1004 return V_03C000_SQ_TEX_WRAP;
1005 case PIPE_TEX_WRAP_CLAMP:
1006 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1007 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1008 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1009 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1010 return V_03C000_SQ_TEX_CLAMP_BORDER;
1011 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1012 return V_03C000_SQ_TEX_MIRROR;
1013 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1014 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1015 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1016 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1017 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1018 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1019 }
1020 }
1021
1022 unsigned r600_tex_filter(unsigned filter)
1023 {
1024 switch (filter) {
1025 default:
1026 case PIPE_TEX_FILTER_NEAREST:
1027 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1028 case PIPE_TEX_FILTER_LINEAR:
1029 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1030 }
1031 }
1032
1033 unsigned r600_tex_mipfilter(unsigned filter)
1034 {
1035 switch (filter) {
1036 case PIPE_TEX_MIPFILTER_NEAREST:
1037 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1038 case PIPE_TEX_MIPFILTER_LINEAR:
1039 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1040 default:
1041 case PIPE_TEX_MIPFILTER_NONE:
1042 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1043 }
1044 }
1045
1046 unsigned r600_tex_compare(unsigned compare)
1047 {
1048 switch (compare) {
1049 default:
1050 case PIPE_FUNC_NEVER:
1051 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1052 case PIPE_FUNC_LESS:
1053 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1054 case PIPE_FUNC_EQUAL:
1055 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1056 case PIPE_FUNC_LEQUAL:
1057 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1058 case PIPE_FUNC_GREATER:
1059 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1060 case PIPE_FUNC_NOTEQUAL:
1061 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1062 case PIPE_FUNC_GEQUAL:
1063 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1064 case PIPE_FUNC_ALWAYS:
1065 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1066 }
1067 }