2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
97 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
98 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
100 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
101 PIPE_BARRIER_SHADER_BUFFER
|
102 PIPE_BARRIER_TEXTURE
|
104 PIPE_BARRIER_STREAMOUT_BUFFER
|
105 PIPE_BARRIER_GLOBAL_BUFFER
)) {
106 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
|
107 R600_CONTEXT_INV_TEX_CACHE
;
110 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
112 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV
;
114 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
117 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
119 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
121 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
122 R600_CONTEXT_FLUSH_AND_INV_CB
|
123 R600_CONTEXT_FLUSH_AND_INV
|
124 R600_CONTEXT_WAIT_3D_IDLE
;
125 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
128 static unsigned r600_conv_pipe_prim(unsigned prim
)
130 static const unsigned prim_conv
[] = {
131 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
132 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
133 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
134 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
135 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
136 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
138 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
139 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
140 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
141 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
145 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
146 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
148 assert(prim
< ARRAY_SIZE(prim_conv
));
149 return prim_conv
[prim
];
152 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
154 static const int prim_conv
[] = {
155 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
156 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
157 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
158 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
159 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
160 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
161 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
162 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
163 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
164 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
165 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
166 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
167 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
168 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
169 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
170 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
172 assert(mode
< ARRAY_SIZE(prim_conv
));
174 return prim_conv
[mode
];
177 /* common state between evergreen and r600 */
179 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
180 struct r600_blend_state
*blend
, bool blend_disable
)
182 unsigned color_control
;
183 bool update_cb
= false;
185 rctx
->alpha_to_one
= blend
->alpha_to_one
;
186 rctx
->dual_src_blend
= blend
->dual_src_blend
;
188 if (!blend_disable
) {
189 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
190 color_control
= blend
->cb_color_control
;
192 /* Blending is disabled. */
193 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
194 color_control
= blend
->cb_color_control_no_blend
;
197 /* Update derived states. */
198 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
199 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
202 if (rctx
->b
.chip_class
<= R700
&&
203 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
204 rctx
->cb_misc_state
.cb_color_control
= color_control
;
207 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
208 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
212 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
214 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
215 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
216 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
220 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
222 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
223 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
226 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
230 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
233 static void r600_set_blend_color(struct pipe_context
*ctx
,
234 const struct pipe_blend_color
*state
)
236 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
238 rctx
->blend_color
.state
= *state
;
239 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
242 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
244 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
245 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
247 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
248 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
249 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
250 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
251 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
254 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
256 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
257 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
259 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
260 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
261 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
262 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
263 if (a
->last_draw_was_indirect
) {
264 a
->last_draw_was_indirect
= false;
265 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
269 static void r600_set_clip_state(struct pipe_context
*ctx
,
270 const struct pipe_clip_state
*state
)
272 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
274 rctx
->clip_state
.state
= *state
;
275 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
276 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
279 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
280 const struct r600_stencil_ref
*state
)
282 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
284 rctx
->stencil_ref
.state
= *state
;
285 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
288 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
290 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
291 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
293 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
294 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
295 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
296 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
297 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
298 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
299 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
300 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
301 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
304 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
305 const struct pipe_stencil_ref
*state
)
307 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
308 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
309 struct r600_stencil_ref ref
;
311 rctx
->stencil_ref
.pipe_state
= *state
;
316 ref
.ref_value
[0] = state
->ref_value
[0];
317 ref
.ref_value
[1] = state
->ref_value
[1];
318 ref
.valuemask
[0] = dsa
->valuemask
[0];
319 ref
.valuemask
[1] = dsa
->valuemask
[1];
320 ref
.writemask
[0] = dsa
->writemask
[0];
321 ref
.writemask
[1] = dsa
->writemask
[1];
323 r600_set_stencil_ref(ctx
, &ref
);
326 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
328 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
329 struct r600_dsa_state
*dsa
= state
;
330 struct r600_stencil_ref ref
;
333 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
337 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
339 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
340 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
341 ref
.valuemask
[0] = dsa
->valuemask
[0];
342 ref
.valuemask
[1] = dsa
->valuemask
[1];
343 ref
.writemask
[0] = dsa
->writemask
[0];
344 ref
.writemask
[1] = dsa
->writemask
[1];
345 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
346 rctx
->zwritemask
= dsa
->zwritemask
;
347 if (rctx
->b
.chip_class
>= EVERGREEN
) {
348 /* work around some issue when not writing to zbuffer
349 * we are having lockup on evergreen so do not enable
350 * hyperz when not writing zbuffer
352 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
356 r600_set_stencil_ref(ctx
, &ref
);
358 /* Update alphatest state. */
359 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
360 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
361 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
362 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
363 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
367 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
369 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
370 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
375 rctx
->rasterizer
= rs
;
377 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
379 if (rs
->offset_enable
&&
380 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
381 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
382 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
383 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
384 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
385 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
386 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
389 /* Update clip_misc_state. */
390 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
391 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
392 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
393 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
394 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
397 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
399 /* Re-emit PA_SC_LINE_STIPPLE. */
400 rctx
->last_primitive_type
= -1;
403 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
405 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
407 r600_release_command_buffer(&rs
->buffer
);
411 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
412 struct pipe_sampler_view
*state
)
414 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
416 if (view
->tex_resource
->gpu_address
&&
417 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
418 LIST_DELINIT(&view
->list
);
420 pipe_resource_reference(&state
->texture
, NULL
);
424 void r600_sampler_states_dirty(struct r600_context
*rctx
,
425 struct r600_sampler_states
*state
)
427 if (state
->dirty_mask
) {
428 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
429 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
432 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
433 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
434 r600_mark_atom_dirty(rctx
, &state
->atom
);
438 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
439 enum pipe_shader_type shader
,
441 unsigned count
, void **states
)
443 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
444 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
445 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
446 int seamless_cube_map
= -1;
448 /* This sets 1-bit for states with index >= count. */
449 uint32_t disable_mask
= ~((1ull << count
) - 1);
450 /* These are the new states set by this function. */
451 uint32_t new_mask
= 0;
453 assert(start
== 0); /* XXX fix below */
460 for (i
= 0; i
< count
; i
++) {
461 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
463 if (rstate
== dst
->states
.states
[i
]) {
468 if (rstate
->border_color_use
) {
469 dst
->states
.has_bordercolor_mask
|= 1 << i
;
471 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
473 seamless_cube_map
= rstate
->seamless_cube_map
;
477 disable_mask
|= 1 << i
;
481 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
482 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
484 dst
->states
.enabled_mask
&= ~disable_mask
;
485 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
486 dst
->states
.enabled_mask
|= new_mask
;
487 dst
->states
.dirty_mask
|= new_mask
;
488 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
490 r600_sampler_states_dirty(rctx
, &dst
->states
);
492 /* Seamless cubemap state. */
493 if (rctx
->b
.chip_class
<= R700
&&
494 seamless_cube_map
!= -1 &&
495 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
496 /* change in TA_CNTL_AUX need a pipeline flush */
497 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
498 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
499 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
503 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
508 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
510 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
511 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
513 if (rctx
->blend_state
.cso
== state
) {
514 ctx
->bind_blend_state(ctx
, NULL
);
517 r600_release_command_buffer(&blend
->buffer
);
518 r600_release_command_buffer(&blend
->buffer_no_blend
);
522 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
524 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
525 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
527 if (rctx
->dsa_state
.cso
== state
) {
528 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
531 r600_release_command_buffer(&dsa
->buffer
);
535 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
537 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
539 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
542 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
544 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
545 r600_resource_reference(&shader
->buffer
, NULL
);
549 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
551 if (rctx
->vertex_buffer_state
.dirty_mask
) {
552 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
553 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
554 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
558 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
559 unsigned start_slot
, unsigned count
,
560 const struct pipe_vertex_buffer
*input
)
562 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
563 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
564 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
566 uint32_t disable_mask
= 0;
567 /* These are the new buffers set by this function. */
568 uint32_t new_buffer_mask
= 0;
570 /* Set vertex buffers. */
572 for (i
= 0; i
< count
; i
++) {
573 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
574 if (input
[i
].buffer
.resource
) {
575 vb
[i
].stride
= input
[i
].stride
;
576 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
577 pipe_resource_reference(&vb
[i
].buffer
.resource
, input
[i
].buffer
.resource
);
578 new_buffer_mask
|= 1 << i
;
579 r600_context_add_resource_size(ctx
, input
[i
].buffer
.resource
);
581 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
582 disable_mask
|= 1 << i
;
587 for (i
= 0; i
< count
; i
++) {
588 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
590 disable_mask
= ((1ull << count
) - 1);
593 disable_mask
<<= start_slot
;
594 new_buffer_mask
<<= start_slot
;
596 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
597 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
598 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
599 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
601 r600_vertex_buffers_dirty(rctx
);
604 void r600_sampler_views_dirty(struct r600_context
*rctx
,
605 struct r600_samplerview_state
*state
)
607 if (state
->dirty_mask
) {
608 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
609 util_bitcount(state
->dirty_mask
);
610 r600_mark_atom_dirty(rctx
, &state
->atom
);
614 static void r600_set_sampler_views(struct pipe_context
*pipe
,
615 enum pipe_shader_type shader
,
616 unsigned start
, unsigned count
,
617 struct pipe_sampler_view
**views
)
619 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
620 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
621 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
622 uint32_t dirty_sampler_states_mask
= 0;
624 /* This sets 1-bit for textures with index >= count. */
625 uint32_t disable_mask
= ~((1ull << count
) - 1);
626 /* These are the new textures set by this function. */
627 uint32_t new_mask
= 0;
629 /* Set textures with index >= count to NULL. */
630 uint32_t remaining_mask
;
632 assert(start
== 0); /* XXX fix below */
639 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
641 while (remaining_mask
) {
642 i
= u_bit_scan(&remaining_mask
);
643 assert(dst
->views
.views
[i
]);
645 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
648 for (i
= 0; i
< count
; i
++) {
649 if (rviews
[i
] == dst
->views
.views
[i
]) {
654 struct r600_texture
*rtex
=
655 (struct r600_texture
*)rviews
[i
]->base
.texture
;
656 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
658 if (!is_buffer
&& rtex
->db_compatible
) {
659 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
661 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
664 /* Track compressed colorbuffers. */
665 if (!is_buffer
&& rtex
->cmask
.size
) {
666 dst
->views
.compressed_colortex_mask
|= 1 << i
;
668 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
671 /* Changing from array to non-arrays textures and vice versa requires
672 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
673 if (rctx
->b
.chip_class
<= R700
&&
674 (dst
->states
.enabled_mask
& (1 << i
)) &&
675 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
676 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
677 dirty_sampler_states_mask
|= 1 << i
;
680 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
682 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
684 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
685 disable_mask
|= 1 << i
;
689 dst
->views
.enabled_mask
&= ~disable_mask
;
690 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
691 dst
->views
.enabled_mask
|= new_mask
;
692 dst
->views
.dirty_mask
|= new_mask
;
693 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
694 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
695 dst
->views
.dirty_buffer_constants
= TRUE
;
696 r600_sampler_views_dirty(rctx
, &dst
->views
);
698 if (dirty_sampler_states_mask
) {
699 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
700 r600_sampler_states_dirty(rctx
, &dst
->states
);
704 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
706 uint32_t mask
= views
->enabled_mask
;
709 unsigned i
= u_bit_scan(&mask
);
710 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
712 if (res
&& res
->target
!= PIPE_BUFFER
) {
713 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
715 if (rtex
->cmask
.size
) {
716 views
->compressed_colortex_mask
|= 1 << i
;
718 views
->compressed_colortex_mask
&= ~(1 << i
);
724 static int r600_get_hw_atomic_count(const struct pipe_context
*ctx
,
725 enum pipe_shader_type shader
)
727 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
730 case PIPE_SHADER_FRAGMENT
:
731 case PIPE_SHADER_COMPUTE
:
734 case PIPE_SHADER_VERTEX
:
735 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
737 case PIPE_SHADER_GEOMETRY
:
738 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
739 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
741 case PIPE_SHADER_TESS_EVAL
:
742 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
743 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
744 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0);
746 case PIPE_SHADER_TESS_CTRL
:
747 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
748 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
749 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0) +
750 rctx
->tes_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
756 static void r600_update_compressed_colortex_mask_images(struct r600_image_state
*images
)
758 uint32_t mask
= images
->enabled_mask
;
761 unsigned i
= u_bit_scan(&mask
);
762 struct pipe_resource
*res
= images
->views
[i
].base
.resource
;
764 if (res
&& res
->target
!= PIPE_BUFFER
) {
765 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
767 if (rtex
->cmask
.size
) {
768 images
->compressed_colortex_mask
|= 1 << i
;
770 images
->compressed_colortex_mask
&= ~(1 << i
);
776 /* Compute the key for the hw shader variant */
777 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
778 const struct r600_pipe_shader_selector
*sel
,
779 union r600_shader_key
*key
)
781 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
782 memset(key
, 0, sizeof(*key
));
785 case PIPE_SHADER_VERTEX
: {
786 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
788 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
790 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
791 key
->vs
.as_gs_a
= true;
792 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
794 key
->vs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_VERTEX
);
797 case PIPE_SHADER_GEOMETRY
:
798 key
->gs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_GEOMETRY
);
799 key
->gs
.tri_strip_adj_fix
= rctx
->gs_tri_strip_adj_fix
;
801 case PIPE_SHADER_FRAGMENT
: {
802 if (rctx
->ps_shader
->info
.images_declared
)
803 key
->ps
.image_size_const_offset
= util_last_bit(rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.enabled_mask
);
804 key
->ps
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_FRAGMENT
);
805 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
806 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
807 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
808 !rctx
->framebuffer
.cb0_is_integer
;
809 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
810 /* Dual-source blending only makes sense with nr_cbufs == 1. */
811 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
812 key
->ps
.nr_cbufs
= 2;
815 case PIPE_SHADER_TESS_EVAL
:
816 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
817 key
->tes
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_EVAL
);
819 case PIPE_SHADER_TESS_CTRL
:
820 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
821 key
->tcs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_CTRL
);
823 case PIPE_SHADER_COMPUTE
:
830 /* Select the hw shader variant depending on the current state.
831 * (*dirty) is set to 1 if current variant was changed */
832 int r600_shader_select(struct pipe_context
*ctx
,
833 struct r600_pipe_shader_selector
* sel
,
836 union r600_shader_key key
;
837 struct r600_pipe_shader
* shader
= NULL
;
840 r600_shader_selector_key(ctx
, sel
, &key
);
842 /* Check if we don't need to change anything.
843 * This path is also used for most shaders that don't need multiple
844 * variants, it will cost just a computation of the key and this
846 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
850 /* lookup if we have other variants in the list */
851 if (sel
->num_shaders
> 1) {
852 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
854 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
860 p
->next_variant
= c
->next_variant
;
865 if (unlikely(!shader
)) {
866 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
867 shader
->selector
= sel
;
869 r
= r600_pipe_shader_create(ctx
, shader
, key
);
871 R600_ERR("Failed to build shader variant (type=%u) %d\n",
878 /* We don't know the value of nr_ps_max_color_exports until we built
879 * at least one variant, so we may need to recompute the key after
880 * building first variant. */
881 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
882 sel
->num_shaders
== 0) {
883 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
884 r600_shader_selector_key(ctx
, sel
, &key
);
887 memcpy(&shader
->key
, &key
, sizeof(key
));
894 shader
->next_variant
= sel
->current
;
895 sel
->current
= shader
;
900 struct r600_pipe_shader_selector
*r600_create_shader_state_tokens(struct pipe_context
*ctx
,
901 const struct tgsi_token
*tokens
,
902 unsigned pipe_shader_type
)
904 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
906 sel
->type
= pipe_shader_type
;
907 sel
->tokens
= tgsi_dup_tokens(tokens
);
908 tgsi_scan_shader(tokens
, &sel
->info
);
912 static void *r600_create_shader_state(struct pipe_context
*ctx
,
913 const struct pipe_shader_state
*state
,
914 unsigned pipe_shader_type
)
917 struct r600_pipe_shader_selector
*sel
= r600_create_shader_state_tokens(ctx
, state
->tokens
, pipe_shader_type
);
919 sel
->so
= state
->stream_output
;
921 switch (pipe_shader_type
) {
922 case PIPE_SHADER_GEOMETRY
:
923 sel
->gs_output_prim
=
924 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
925 sel
->gs_max_out_vertices
=
926 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
927 sel
->gs_num_invocations
=
928 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
930 case PIPE_SHADER_VERTEX
:
931 case PIPE_SHADER_TESS_CTRL
:
932 sel
->lds_patch_outputs_written_mask
= 0;
933 sel
->lds_outputs_written_mask
= 0;
935 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
936 unsigned name
= sel
->info
.output_semantic_name
[i
];
937 unsigned index
= sel
->info
.output_semantic_index
[i
];
940 case TGSI_SEMANTIC_TESSINNER
:
941 case TGSI_SEMANTIC_TESSOUTER
:
942 case TGSI_SEMANTIC_PATCH
:
943 sel
->lds_patch_outputs_written_mask
|=
944 1ull << r600_get_lds_unique_index(name
, index
);
947 sel
->lds_outputs_written_mask
|=
948 1ull << r600_get_lds_unique_index(name
, index
);
959 static void *r600_create_ps_state(struct pipe_context
*ctx
,
960 const struct pipe_shader_state
*state
)
962 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
965 static void *r600_create_vs_state(struct pipe_context
*ctx
,
966 const struct pipe_shader_state
*state
)
968 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
971 static void *r600_create_gs_state(struct pipe_context
*ctx
,
972 const struct pipe_shader_state
*state
)
974 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
977 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
978 const struct pipe_shader_state
*state
)
980 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
983 static void *r600_create_tes_state(struct pipe_context
*ctx
,
984 const struct pipe_shader_state
*state
)
986 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
989 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
991 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
994 state
= rctx
->dummy_pixel_shader
;
996 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
999 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
1001 if (rctx
->gs_shader
)
1002 return &rctx
->gs_shader
->info
;
1003 else if (rctx
->tes_shader
)
1004 return &rctx
->tes_shader
->info
;
1005 else if (rctx
->vs_shader
)
1006 return &rctx
->vs_shader
->info
;
1011 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1013 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1015 if (!state
|| rctx
->vs_shader
== state
)
1018 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
1019 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1020 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
1023 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1025 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1027 if (state
== rctx
->gs_shader
)
1030 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
1031 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1035 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
1038 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1040 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1042 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
1045 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1047 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1049 if (state
== rctx
->tes_shader
)
1052 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
1053 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1057 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
1060 void r600_delete_shader_selector(struct pipe_context
*ctx
,
1061 struct r600_pipe_shader_selector
*sel
)
1063 struct r600_pipe_shader
*p
= sel
->current
, *c
;
1065 c
= p
->next_variant
;
1066 r600_pipe_shader_destroy(ctx
, p
);
1076 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
1078 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1079 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1081 if (rctx
->ps_shader
== sel
) {
1082 rctx
->ps_shader
= NULL
;
1085 r600_delete_shader_selector(ctx
, sel
);
1088 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1090 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1091 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1093 if (rctx
->vs_shader
== sel
) {
1094 rctx
->vs_shader
= NULL
;
1097 r600_delete_shader_selector(ctx
, sel
);
1101 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1103 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1104 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1106 if (rctx
->gs_shader
== sel
) {
1107 rctx
->gs_shader
= NULL
;
1110 r600_delete_shader_selector(ctx
, sel
);
1113 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1115 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1116 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1118 if (rctx
->tcs_shader
== sel
) {
1119 rctx
->tcs_shader
= NULL
;
1122 r600_delete_shader_selector(ctx
, sel
);
1125 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1127 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1128 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1130 if (rctx
->tes_shader
== sel
) {
1131 rctx
->tes_shader
= NULL
;
1134 r600_delete_shader_selector(ctx
, sel
);
1137 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1139 if (state
->dirty_mask
) {
1140 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1141 : util_bitcount(state
->dirty_mask
)*19;
1142 r600_mark_atom_dirty(rctx
, &state
->atom
);
1146 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1147 enum pipe_shader_type shader
, uint index
,
1148 const struct pipe_constant_buffer
*input
)
1150 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1151 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1152 struct pipe_constant_buffer
*cb
;
1155 /* Note that the state tracker can unbind constant buffers by
1156 * passing NULL here.
1158 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1159 state
->enabled_mask
&= ~(1 << index
);
1160 state
->dirty_mask
&= ~(1 << index
);
1161 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1165 cb
= &state
->cb
[index
];
1166 cb
->buffer_size
= input
->buffer_size
;
1168 ptr
= input
->user_buffer
;
1171 /* Upload the user buffer. */
1172 if (R600_BIG_ENDIAN
) {
1174 unsigned i
, size
= input
->buffer_size
;
1176 if (!(tmpPtr
= malloc(size
))) {
1177 R600_ERR("Failed to allocate BE swap buffer.\n");
1181 for (i
= 0; i
< size
/ 4; ++i
) {
1182 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1185 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1186 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1189 u_upload_data(ctx
->stream_uploader
, 0,
1190 input
->buffer_size
, 256, ptr
,
1191 &cb
->buffer_offset
, &cb
->buffer
);
1193 /* account it in gtt */
1194 rctx
->b
.gtt
+= input
->buffer_size
;
1196 /* Setup the hw buffer. */
1197 cb
->buffer_offset
= input
->buffer_offset
;
1198 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1199 r600_context_add_resource_size(ctx
, input
->buffer
);
1202 state
->enabled_mask
|= 1 << index
;
1203 state
->dirty_mask
|= 1 << index
;
1204 r600_constant_buffers_dirty(rctx
, state
);
1207 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1209 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1211 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1214 rctx
->sample_mask
.sample_mask
= sample_mask
;
1215 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1218 void r600_update_driver_const_buffers(struct r600_context
*rctx
, bool compute_only
)
1222 struct pipe_constant_buffer cb
;
1225 start
= compute_only
? PIPE_SHADER_COMPUTE
: 0;
1226 end
= compute_only
? PIPE_SHADER_TYPES
: PIPE_SHADER_COMPUTE
;
1228 for (sh
= start
; sh
< end
; sh
++) {
1229 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1230 if (!info
->vs_ucp_dirty
&&
1231 !info
->texture_const_dirty
&&
1232 !info
->ps_sample_pos_dirty
&&
1233 !info
->tcs_default_levels_dirty
&&
1234 !info
->cs_block_grid_size_dirty
)
1237 ptr
= info
->constants
;
1238 size
= info
->alloc_size
;
1239 if (info
->vs_ucp_dirty
) {
1240 assert(sh
== PIPE_SHADER_VERTEX
);
1242 ptr
= rctx
->clip_state
.state
.ucp
;
1243 size
= R600_UCP_SIZE
;
1245 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1247 info
->vs_ucp_dirty
= false;
1250 else if (info
->ps_sample_pos_dirty
) {
1251 assert(sh
== PIPE_SHADER_FRAGMENT
);
1253 ptr
= rctx
->sample_positions
;
1254 size
= R600_UCP_SIZE
;
1256 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1258 info
->ps_sample_pos_dirty
= false;
1261 else if (info
->cs_block_grid_size_dirty
) {
1262 assert(sh
== PIPE_SHADER_COMPUTE
);
1264 ptr
= rctx
->cs_block_grid_sizes
;
1265 size
= R600_CS_BLOCK_GRID_SIZE
;
1267 memcpy(ptr
, rctx
->cs_block_grid_sizes
, R600_CS_BLOCK_GRID_SIZE
);
1269 info
->cs_block_grid_size_dirty
= false;
1272 else if (info
->tcs_default_levels_dirty
) {
1274 * We'd only really need this for default tcs shader.
1276 assert(sh
== PIPE_SHADER_TESS_CTRL
);
1278 ptr
= rctx
->tess_state
;
1279 size
= R600_TCS_DEFAULT_LEVELS_SIZE
;
1281 memcpy(ptr
, rctx
->tess_state
, R600_TCS_DEFAULT_LEVELS_SIZE
);
1283 info
->tcs_default_levels_dirty
= false;
1286 if (info
->texture_const_dirty
) {
1289 if (sh
== PIPE_SHADER_VERTEX
)
1290 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1291 if (sh
== PIPE_SHADER_FRAGMENT
)
1292 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1293 if (sh
== PIPE_SHADER_COMPUTE
)
1294 memcpy(ptr
, rctx
->cs_block_grid_sizes
, R600_CS_BLOCK_GRID_SIZE
);
1295 if (sh
== PIPE_SHADER_TESS_CTRL
)
1296 memcpy(ptr
, rctx
->tess_state
, R600_TCS_DEFAULT_LEVELS_SIZE
);
1298 info
->texture_const_dirty
= false;
1301 cb
.user_buffer
= ptr
;
1302 cb
.buffer_offset
= 0;
1303 cb
.buffer_size
= size
;
1304 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1305 pipe_resource_reference(&cb
.buffer
, NULL
);
1309 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1310 int array_size
, uint32_t *base_offset
)
1312 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1313 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1314 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1315 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1317 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1318 info
->texture_const_dirty
= true;
1319 *base_offset
= R600_UCP_SIZE
;
1320 return info
->constants
;
1323 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1324 * doesn't require full swizzles it does need masking and setting alpha
1325 * to one, so we setup a set of 5 constants with the masks + alpha value
1326 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1327 * then OR the alpha with the value given here.
1328 * We use a 6th constant to store the txq buffer size in
1329 * we use 7th slot for number of cube layers in a cube map array.
1331 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1333 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1335 uint32_t array_size
;
1337 uint32_t *constants
;
1338 uint32_t base_offset
;
1339 if (!samplers
->views
.dirty_buffer_constants
)
1342 samplers
->views
.dirty_buffer_constants
= FALSE
;
1344 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1345 array_size
= bits
* 8 * sizeof(uint32_t);
1347 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1349 for (i
= 0; i
< bits
; i
++) {
1350 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1351 int offset
= (base_offset
/ 4) + i
* 8;
1352 const struct util_format_description
*desc
;
1353 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1355 for (j
= 0; j
< 4; j
++)
1356 if (j
< desc
->nr_channels
)
1357 constants
[offset
+j
] = 0xffffffff;
1359 constants
[offset
+j
] = 0x0;
1360 if (desc
->nr_channels
< 4) {
1361 if (desc
->channel
[0].pure_integer
)
1362 constants
[offset
+4] = 1;
1364 constants
[offset
+4] = fui(1.0);
1366 constants
[offset
+ 4] = 0;
1368 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.u
.buf
.size
/
1369 util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1370 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1376 /* On evergreen we store one value
1377 * 1. number of cube layers in a cube map array.
1379 void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1381 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1382 struct r600_image_state
*images
= NULL
;
1383 int bits
, sview_bits
, img_bits
;
1384 uint32_t array_size
;
1386 uint32_t *constants
;
1387 uint32_t base_offset
;
1389 if (shader_type
== PIPE_SHADER_FRAGMENT
) {
1390 images
= &rctx
->fragment_images
;
1391 } else if (shader_type
== PIPE_SHADER_COMPUTE
) {
1392 images
= &rctx
->compute_images
;
1395 if (!samplers
->views
.dirty_buffer_constants
&&
1396 !(images
&& images
->dirty_buffer_constants
))
1400 images
->dirty_buffer_constants
= FALSE
;
1401 samplers
->views
.dirty_buffer_constants
= FALSE
;
1403 bits
= sview_bits
= util_last_bit(samplers
->views
.enabled_mask
);
1405 bits
+= util_last_bit(images
->enabled_mask
);
1408 array_size
= bits
* sizeof(uint32_t);
1410 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1413 for (i
= 0; i
< sview_bits
; i
++) {
1414 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1415 uint32_t offset
= (base_offset
/ 4) + i
;
1416 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1420 for (i
= sview_bits
; i
< img_bits
; i
++) {
1421 int idx
= i
- sview_bits
;
1422 if (images
->enabled_mask
& (1 << idx
)) {
1423 uint32_t offset
= (base_offset
/ 4) + i
;
1424 constants
[offset
] = images
->views
[i
].base
.resource
->array_size
/ 6;
1430 /* set sample xy locations as array of fragment shader constants */
1431 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1434 struct pipe_context
*ctx
= &rctx
->b
.b
;
1436 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1437 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1439 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1440 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1441 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1442 /* Also fill in center-zeroed positions used for interpolateAtSample */
1443 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1444 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1447 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1450 static void update_shader_atom(struct pipe_context
*ctx
,
1451 struct r600_shader_state
*state
,
1452 struct r600_pipe_shader
*shader
)
1454 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1456 state
->shader
= shader
;
1458 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1459 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1461 state
->atom
.num_dw
= 0;
1463 r600_mark_atom_dirty(rctx
, &state
->atom
);
1466 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1468 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1469 rctx
->shader_stages
.geom_enable
= enable
;
1470 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1473 if (rctx
->gs_rings
.enable
!= enable
) {
1474 rctx
->gs_rings
.enable
= enable
;
1475 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1477 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1478 unsigned size
= 0x1C000;
1479 rctx
->gs_rings
.esgs_ring
.buffer
=
1480 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1481 PIPE_USAGE_DEFAULT
, size
);
1482 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1486 rctx
->gs_rings
.gsvs_ring
.buffer
=
1487 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1488 PIPE_USAGE_DEFAULT
, size
);
1489 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1493 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1494 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1495 if (rctx
->tes_shader
) {
1496 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1497 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1499 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1500 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1503 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1504 R600_GS_RING_CONST_BUFFER
, NULL
);
1505 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1506 R600_GS_RING_CONST_BUFFER
, NULL
);
1507 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1508 R600_GS_RING_CONST_BUFFER
, NULL
);
1513 static void r600_update_clip_state(struct r600_context
*rctx
,
1514 struct r600_pipe_shader
*current
)
1516 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1517 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1518 current
->shader
.cull_dist_write
!= rctx
->clip_misc_state
.cull_dist_write
||
1519 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1520 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1521 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1522 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1523 rctx
->clip_misc_state
.cull_dist_write
= current
->shader
.cull_dist_write
;
1524 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1525 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1526 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1530 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1532 struct ureg_src const0
, const1
;
1533 struct ureg_dst tessouter
, tessinner
;
1534 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1537 return; /* if we get here, we're screwed */
1539 assert(!rctx
->fixed_func_tcs_shader
);
1541 ureg_DECL_constant2D(ureg
, 0, 1, R600_BUFFER_INFO_CONST_BUFFER
);
1542 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 0),
1543 R600_BUFFER_INFO_CONST_BUFFER
);
1544 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 1),
1545 R600_BUFFER_INFO_CONST_BUFFER
);
1547 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1548 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1550 ureg_MOV(ureg
, tessouter
, const0
);
1551 ureg_MOV(ureg
, tessinner
, const1
);
1554 rctx
->fixed_func_tcs_shader
=
1555 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1558 void r600_update_compressed_resource_state(struct r600_context
*rctx
, bool compute_only
)
1563 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1564 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1565 rctx
->b
.last_compressed_colortex_counter
= counter
;
1568 r600_update_compressed_colortex_mask(&rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
);
1570 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1571 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1575 r600_update_compressed_colortex_mask_images(&rctx
->fragment_images
);
1576 r600_update_compressed_colortex_mask_images(&rctx
->compute_images
);
1579 /* Decompress textures if needed. */
1580 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1581 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1584 if (i
!= PIPE_SHADER_COMPUTE
)
1586 if (views
->compressed_depthtex_mask
) {
1587 r600_decompress_depth_textures(rctx
, views
);
1589 if (views
->compressed_colortex_mask
) {
1590 r600_decompress_color_textures(rctx
, views
);
1595 struct r600_image_state
*istate
;
1597 if (!compute_only
) {
1598 istate
= &rctx
->fragment_images
;
1599 if (istate
->compressed_depthtex_mask
)
1600 r600_decompress_depth_images(rctx
, istate
);
1601 if (istate
->compressed_colortex_mask
)
1602 r600_decompress_color_images(rctx
, istate
);
1605 istate
= &rctx
->compute_images
;
1606 if (istate
->compressed_depthtex_mask
)
1607 r600_decompress_depth_images(rctx
, istate
);
1608 if (istate
->compressed_colortex_mask
)
1609 r600_decompress_color_images(rctx
, istate
);
1613 #define SELECT_SHADER_OR_FAIL(x) do { \
1614 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1615 if (unlikely(!rctx->x##_shader->current)) \
1619 #define UPDATE_SHADER(hw, sw) do { \
1620 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1621 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1624 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1625 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1626 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1627 clip_so_current = rctx->sw##_shader->current; \
1631 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1632 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1633 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1634 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1635 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1639 #define SET_NULL_SHADER(hw) do { \
1640 if (rctx->hw_shader_stages[(hw)].shader) \
1641 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1644 static bool r600_update_derived_state(struct r600_context
*rctx
)
1646 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1647 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1648 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1650 bool need_buf_const
;
1651 struct r600_pipe_shader
*clip_so_current
= NULL
;
1653 if (!rctx
->blitter
->running
)
1654 r600_update_compressed_resource_state(rctx
, false);
1656 SELECT_SHADER_OR_FAIL(ps
);
1658 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1660 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1662 if (rctx
->gs_shader
)
1663 SELECT_SHADER_OR_FAIL(gs
);
1666 if (rctx
->tcs_shader
) {
1667 SELECT_SHADER_OR_FAIL(tcs
);
1669 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1670 } else if (rctx
->tes_shader
) {
1671 if (!rctx
->fixed_func_tcs_shader
) {
1672 r600_generate_fixed_func_tcs(rctx
);
1673 if (!rctx
->fixed_func_tcs_shader
)
1677 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1679 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1681 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1683 if (rctx
->tes_shader
) {
1684 SELECT_SHADER_OR_FAIL(tes
);
1687 SELECT_SHADER_OR_FAIL(vs
);
1689 if (rctx
->gs_shader
) {
1690 if (!rctx
->shader_stages
.geom_enable
) {
1691 rctx
->shader_stages
.geom_enable
= true;
1692 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1695 /* gs_shader provides GS and VS (copy shader) */
1696 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1698 /* vs_shader is used as ES */
1700 if (rctx
->tes_shader
) {
1701 /* VS goes to LS, TES goes to ES */
1702 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1703 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1705 /* vs_shader is used as ES */
1706 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1707 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1710 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1711 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1712 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1713 rctx
->shader_stages
.geom_enable
= false;
1714 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1717 if (rctx
->tes_shader
) {
1718 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1719 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1720 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1722 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1723 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1728 * XXX: I believe there's some fatal flaw in the dirty state logic when
1729 * enabling/disabling tes.
1730 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1731 * it will therefore overwrite the VS slots. If it now gets disabled,
1732 * the VS needs to rebind all buffer/resource/sampler slots - not only
1733 * has TES overwritten the corresponding slots, but when the VS was
1734 * operating as LS the things with correpsonding dirty bits got bound
1735 * to LS slots and won't reflect what is dirty as VS stage even if the
1736 * TES didn't overwrite it. The story for re-enabled TES is similar.
1737 * In any case, we're not allowed to submit any TES state when
1738 * TES is disabled (the state tracker may not do this but this looks
1739 * like an optimization to me, not something which can be relied on).
1742 /* Update clip misc state. */
1743 if (clip_so_current
) {
1744 r600_update_clip_state(rctx
, clip_so_current
);
1745 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1748 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1749 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1750 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1752 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1753 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1754 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1757 if (rctx
->b
.chip_class
<= R700
) {
1758 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1760 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1761 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1762 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1766 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1767 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1768 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1770 if (rctx
->b
.chip_class
>= EVERGREEN
)
1771 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1773 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1776 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1778 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1780 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1781 evergreen_update_db_shader_control(rctx
);
1783 r600_update_db_shader_control(rctx
);
1786 /* on R600 we stuff masks + txq info into one constant buffer */
1787 /* on evergreen we only need a txq info one */
1788 if (rctx
->ps_shader
) {
1789 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1790 if (need_buf_const
) {
1791 if (rctx
->b
.chip_class
< EVERGREEN
)
1792 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1794 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1798 if (rctx
->vs_shader
) {
1799 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1800 if (need_buf_const
) {
1801 if (rctx
->b
.chip_class
< EVERGREEN
)
1802 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1804 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1808 if (rctx
->gs_shader
) {
1809 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1810 if (need_buf_const
) {
1811 if (rctx
->b
.chip_class
< EVERGREEN
)
1812 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1814 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1818 if (rctx
->tes_shader
) {
1819 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1820 need_buf_const
= rctx
->tes_shader
->current
->shader
.uses_tex_buffers
||
1821 rctx
->tes_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1822 if (need_buf_const
) {
1823 eg_setup_buffer_constants(rctx
, PIPE_SHADER_TESS_EVAL
);
1825 if (rctx
->tcs_shader
) {
1826 need_buf_const
= rctx
->tcs_shader
->current
->shader
.uses_tex_buffers
||
1827 rctx
->tcs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1828 if (need_buf_const
) {
1829 eg_setup_buffer_constants(rctx
, PIPE_SHADER_TESS_CTRL
);
1834 r600_update_driver_const_buffers(rctx
, false);
1836 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1837 if (!r600_adjust_gprs(rctx
)) {
1838 /* discard rendering */
1843 if (rctx
->b
.chip_class
== EVERGREEN
) {
1844 if (!evergreen_adjust_gprs(rctx
)) {
1845 /* discard rendering */
1850 blend_disable
= (rctx
->dual_src_blend
&&
1851 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1853 if (blend_disable
!= rctx
->force_blend_disable
) {
1854 rctx
->force_blend_disable
= blend_disable
;
1855 r600_bind_blend_state_internal(rctx
,
1856 rctx
->blend_state
.cso
,
1863 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1865 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1866 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1868 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1869 state
->pa_cl_clip_cntl
|
1870 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1871 S_028810_CLIP_DISABLE(state
->clip_disable
));
1872 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1873 state
->pa_cl_vs_out_cntl
|
1874 (state
->clip_plane_enable
& state
->clip_dist_write
) |
1875 (state
->cull_dist_write
<< 8));
1876 /* reuse needs to be set off if we write oViewport */
1877 if (rctx
->b
.chip_class
>= EVERGREEN
)
1878 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1879 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1882 /* rast_prim is the primitive type after GS. */
1883 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
1885 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1886 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
1888 /* Skip this if not rendering lines. */
1889 if (rast_prim
!= PIPE_PRIM_LINES
&&
1890 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
1891 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
1892 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
1893 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
1896 if (rast_prim
== rctx
->last_rast_prim
)
1899 /* For lines, reset the stipple pattern at each primitive. Otherwise,
1900 * reset the stipple pattern at each packet (line strips, line loops).
1902 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1903 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
1904 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1905 rctx
->last_rast_prim
= rast_prim
;
1908 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1910 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1911 struct pipe_resource
*indexbuf
= info
->has_user_indices
? NULL
: info
->index
.resource
;
1912 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1913 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
1914 bool has_user_indices
= info
->has_user_indices
;
1916 unsigned num_patches
, dirty_tex_counter
, index_offset
= 0;
1917 unsigned index_size
= info
->index_size
;
1919 struct r600_shader_atomic combined_atomics
[8];
1920 uint8_t atomic_used_mask
;
1922 if (!info
->indirect
&& !info
->count
&& (index_size
|| !info
->count_from_stream_output
)) {
1926 if (unlikely(!rctx
->vs_shader
)) {
1930 if (unlikely(!rctx
->ps_shader
&&
1931 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
1936 /* make sure that the gfx ring is only one active */
1937 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
1938 rctx
->b
.dma
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
1941 if (rctx
->cmd_buf_is_compute
) {
1942 rctx
->b
.gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
1943 rctx
->cmd_buf_is_compute
= false;
1946 /* Re-emit the framebuffer state if needed. */
1947 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
1948 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
1949 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1950 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1951 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
1954 if (rctx
->gs_shader
) {
1955 /* Determine whether the GS triangle strip adjacency fix should
1956 * be applied. Rotate every other triangle if
1957 * - triangle strips with adjacency are fed to the GS and
1958 * - primitive restart is disabled (the rotation doesn't help
1959 * when the restart occurs after an odd number of triangles).
1961 bool gs_tri_strip_adj_fix
=
1962 !rctx
->tes_shader
&&
1963 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1964 !info
->primitive_restart
;
1965 if (gs_tri_strip_adj_fix
!= rctx
->gs_tri_strip_adj_fix
)
1966 rctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1968 if (!r600_update_derived_state(rctx
)) {
1969 /* useless to render because current rendering command
1975 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
1976 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
1979 if (rctx
->b
.chip_class
>= EVERGREEN
)
1980 evergreen_emit_atomic_buffer_setup(rctx
, NULL
, combined_atomics
, &atomic_used_mask
);
1983 index_offset
+= info
->start
* index_size
;
1985 /* Translate 8-bit indices to 16-bit. */
1986 if (unlikely(index_size
== 1)) {
1987 struct pipe_resource
*out_buffer
= NULL
;
1988 unsigned out_offset
;
1990 unsigned start
, count
;
1992 if (likely(!info
->indirect
)) {
1994 count
= info
->count
;
1997 /* Have to get start/count from indirect buffer, slow path ahead... */
1998 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
->buffer
;
1999 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
2000 PIPE_TRANSFER_READ
);
2002 data
+= info
->indirect
->offset
/ sizeof(unsigned);
2003 start
= data
[2] * index_size
;
2012 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
2013 256, &out_offset
, &out_buffer
, &ptr
);
2017 util_shorten_ubyte_elts_to_userptr(
2018 &rctx
->b
.b
, info
, 0, 0, index_offset
, count
, ptr
);
2020 indexbuf
= out_buffer
;
2021 index_offset
= out_offset
;
2023 has_user_indices
= false;
2026 /* Upload the index buffer.
2027 * The upload is skipped for small index counts on little-endian machines
2028 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2029 * Indirect draws never use immediate indices.
2030 * Note: Instanced rendering in combination with immediate indices hangs. */
2031 if (has_user_indices
&& (R600_BIG_ENDIAN
|| info
->indirect
||
2032 info
->instance_count
> 1 ||
2033 info
->count
*index_size
> 20)) {
2035 u_upload_data(ctx
->stream_uploader
, 0,
2036 info
->count
* index_size
, 256,
2037 info
->index
.user
, &index_offset
, &indexbuf
);
2038 has_user_indices
= false;
2040 index_bias
= info
->index_bias
;
2042 index_bias
= info
->start
;
2045 /* Set the index offset and primitive restart. */
2046 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
2047 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
2048 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
2049 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
2050 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
2051 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
2052 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
2053 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
2056 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2057 if (rctx
->b
.chip_class
== R600
) {
2058 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
2059 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
2062 if (rctx
->b
.chip_class
>= EVERGREEN
)
2063 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
2066 r600_need_cs_space(rctx
, has_user_indices
? 5 : 0, TRUE
);
2067 r600_flush_emit(rctx
);
2069 mask
= rctx
->dirty_atoms
;
2071 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
2074 if (rctx
->b
.chip_class
== CAYMAN
) {
2075 /* Copied from radeonsi. */
2076 unsigned primgroup_size
= 128; /* recommended without a GS */
2077 bool ia_switch_on_eop
= false;
2078 bool partial_vs_wave
= false;
2080 if (rctx
->gs_shader
)
2081 primgroup_size
= 64; /* recommended with a GS */
2083 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
2084 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
2085 ia_switch_on_eop
= true;
2088 if (r600_get_strmout_en(&rctx
->b
))
2089 partial_vs_wave
= true;
2091 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
2092 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
2093 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
2094 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
2097 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2098 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
2101 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
2102 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
2105 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2106 * even though it should have no effect on those. */
2107 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
2108 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
2109 unsigned prim
= info
->mode
;
2111 if (rctx
->gs_shader
) {
2112 prim
= rctx
->gs_shader
->gs_output_prim
;
2114 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
2116 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
2117 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
2118 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
2119 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
2121 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
2124 /* Update start instance. */
2125 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
2126 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
2127 rctx
->last_start_instance
= info
->start_instance
;
2130 /* Update the primitive type. */
2131 if (rctx
->last_primitive_type
!= info
->mode
) {
2132 r600_emit_rasterizer_prim_state(rctx
);
2133 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
2134 r600_conv_pipe_prim(info
->mode
));
2136 rctx
->last_primitive_type
= info
->mode
;
2140 if (likely(!info
->indirect
)) {
2141 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2142 radeon_emit(cs
, info
->instance_count
);
2144 uint64_t va
= r600_resource(info
->indirect
->buffer
)->gpu_address
;
2145 assert(rctx
->b
.chip_class
>= EVERGREEN
);
2147 // Invalidate so non-indirect draw calls reset this state
2148 rctx
->vgt_state
.last_draw_was_indirect
= true;
2149 rctx
->last_start_instance
= -1;
2151 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
2152 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
2153 radeon_emit(cs
, va
);
2154 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2156 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2157 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2158 (struct r600_resource
*)info
->indirect
->buffer
,
2160 RADEON_PRIO_DRAW_INDIRECT
));
2164 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2165 radeon_emit(cs
, index_size
== 4 ?
2166 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
2167 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
2169 if (has_user_indices
) {
2170 unsigned size_bytes
= info
->count
*index_size
;
2171 unsigned size_dw
= align(size_bytes
, 4) / 4;
2172 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
2173 radeon_emit(cs
, info
->count
);
2174 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
2175 radeon_emit_array(cs
, info
->index
.user
, size_dw
);
2177 uint64_t va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
2179 if (likely(!info
->indirect
)) {
2180 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
2181 radeon_emit(cs
, va
);
2182 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2183 radeon_emit(cs
, info
->count
);
2184 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2185 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2186 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2187 (struct r600_resource
*)indexbuf
,
2189 RADEON_PRIO_INDEX_BUFFER
));
2192 uint32_t max_size
= (indexbuf
->width0
- index_offset
) / index_size
;
2194 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
2195 radeon_emit(cs
, va
);
2196 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2198 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2199 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2200 (struct r600_resource
*)indexbuf
,
2202 RADEON_PRIO_INDEX_BUFFER
));
2204 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2205 radeon_emit(cs
, max_size
);
2207 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
2208 radeon_emit(cs
, info
->indirect
->offset
);
2209 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2213 if (unlikely(info
->count_from_stream_output
)) {
2214 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
2215 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
2217 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
2219 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
2220 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
2221 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
2222 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
2223 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
2224 radeon_emit(cs
, 0); /* unused */
2226 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2227 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2228 t
->buf_filled_size
, RADEON_USAGE_READ
,
2229 RADEON_PRIO_SO_FILLED_SIZE
));
2232 if (likely(!info
->indirect
)) {
2233 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
2234 radeon_emit(cs
, info
->count
);
2237 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
2238 radeon_emit(cs
, info
->indirect
->offset
);
2240 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2241 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2244 /* SMX returns CONTEXT_DONE too early workaround */
2245 if (rctx
->b
.family
== CHIP_R600
||
2246 rctx
->b
.family
== CHIP_RV610
||
2247 rctx
->b
.family
== CHIP_RV630
||
2248 rctx
->b
.family
== CHIP_RV635
) {
2249 /* if we have gs shader or streamout
2250 we need to do a wait idle after every draw */
2251 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2252 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2256 /* ES ring rolling over at EOP - workaround */
2257 if (rctx
->b
.chip_class
== R600
) {
2258 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2259 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2263 if (rctx
->b
.chip_class
>= EVERGREEN
)
2264 evergreen_emit_atomic_buffer_save(rctx
, false, combined_atomics
, &atomic_used_mask
);
2266 if (rctx
->trace_buf
)
2267 eg_trace_emit(rctx
);
2269 if (rctx
->framebuffer
.do_update_surf_dirtiness
) {
2270 /* Set the depth buffer as dirty. */
2271 if (rctx
->framebuffer
.state
.zsbuf
) {
2272 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2273 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2275 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2277 if (rtex
->surface
.has_stencil
)
2278 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2280 if (rctx
->framebuffer
.compressed_cb_mask
) {
2281 struct pipe_surface
*surf
;
2282 struct r600_texture
*rtex
;
2283 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2286 unsigned i
= u_bit_scan(&mask
);
2287 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2288 rtex
= (struct r600_texture
*)surf
->texture
;
2290 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2294 rctx
->framebuffer
.do_update_surf_dirtiness
= false;
2297 if (index_size
&& indexbuf
!= info
->index
.resource
)
2298 pipe_resource_reference(&indexbuf
, NULL
);
2299 rctx
->b
.num_draw_calls
++;
2302 uint32_t r600_translate_stencil_op(int s_op
)
2305 case PIPE_STENCIL_OP_KEEP
:
2306 return V_028800_STENCIL_KEEP
;
2307 case PIPE_STENCIL_OP_ZERO
:
2308 return V_028800_STENCIL_ZERO
;
2309 case PIPE_STENCIL_OP_REPLACE
:
2310 return V_028800_STENCIL_REPLACE
;
2311 case PIPE_STENCIL_OP_INCR
:
2312 return V_028800_STENCIL_INCR
;
2313 case PIPE_STENCIL_OP_DECR
:
2314 return V_028800_STENCIL_DECR
;
2315 case PIPE_STENCIL_OP_INCR_WRAP
:
2316 return V_028800_STENCIL_INCR_WRAP
;
2317 case PIPE_STENCIL_OP_DECR_WRAP
:
2318 return V_028800_STENCIL_DECR_WRAP
;
2319 case PIPE_STENCIL_OP_INVERT
:
2320 return V_028800_STENCIL_INVERT
;
2322 R600_ERR("Unknown stencil op %d", s_op
);
2329 uint32_t r600_translate_fill(uint32_t func
)
2332 case PIPE_POLYGON_MODE_FILL
:
2334 case PIPE_POLYGON_MODE_LINE
:
2336 case PIPE_POLYGON_MODE_POINT
:
2344 unsigned r600_tex_wrap(unsigned wrap
)
2348 case PIPE_TEX_WRAP_REPEAT
:
2349 return V_03C000_SQ_TEX_WRAP
;
2350 case PIPE_TEX_WRAP_CLAMP
:
2351 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2352 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2353 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2354 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2355 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2356 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2357 return V_03C000_SQ_TEX_MIRROR
;
2358 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2359 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2360 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2361 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2362 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2363 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2367 unsigned r600_tex_mipfilter(unsigned filter
)
2370 case PIPE_TEX_MIPFILTER_NEAREST
:
2371 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2372 case PIPE_TEX_MIPFILTER_LINEAR
:
2373 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2375 case PIPE_TEX_MIPFILTER_NONE
:
2376 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2380 unsigned r600_tex_compare(unsigned compare
)
2384 case PIPE_FUNC_NEVER
:
2385 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2386 case PIPE_FUNC_LESS
:
2387 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2388 case PIPE_FUNC_EQUAL
:
2389 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2390 case PIPE_FUNC_LEQUAL
:
2391 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2392 case PIPE_FUNC_GREATER
:
2393 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2394 case PIPE_FUNC_NOTEQUAL
:
2395 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2396 case PIPE_FUNC_GEQUAL
:
2397 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2398 case PIPE_FUNC_ALWAYS
:
2399 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2403 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2405 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2406 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2408 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2409 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2412 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2414 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2415 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2417 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2418 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2419 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2420 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2421 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2424 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2427 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2428 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2433 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2434 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2435 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2436 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2439 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2440 const unsigned char *swizzle_view
,
2444 unsigned char swizzle
[4];
2445 unsigned result
= 0;
2446 const uint32_t tex_swizzle_shift
[4] = {
2449 const uint32_t vtx_swizzle_shift
[4] = {
2452 const uint32_t swizzle_bit
[4] = {
2455 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2458 swizzle_shift
= vtx_swizzle_shift
;
2461 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2463 memcpy(swizzle
, swizzle_format
, 4);
2467 for (i
= 0; i
< 4; i
++) {
2468 switch (swizzle
[i
]) {
2469 case PIPE_SWIZZLE_Y
:
2470 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2472 case PIPE_SWIZZLE_Z
:
2473 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2475 case PIPE_SWIZZLE_W
:
2476 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2478 case PIPE_SWIZZLE_0
:
2479 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2481 case PIPE_SWIZZLE_1
:
2482 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2484 default: /* PIPE_SWIZZLE_X */
2485 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2491 /* texture format translate */
2492 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2493 enum pipe_format format
,
2494 const unsigned char *swizzle_view
,
2495 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2496 bool do_endian_swap
)
2498 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2499 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2500 const struct util_format_description
*desc
;
2501 boolean uniform
= TRUE
;
2502 bool is_srgb_valid
= FALSE
;
2503 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2504 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2505 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2506 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2507 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2510 const uint32_t sign_bit
[4] = {
2511 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2512 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2513 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2514 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2517 /* Need to replace the specified texture formats in case of big-endian.
2518 * These formats are formats that have channels with number of bits
2519 * not divisible by 8.
2520 * Mesa conversion functions don't swap bits for those formats, and because
2521 * we transmit this over a serial bus to the GPU (PCIe), the
2522 * bit-endianess is important!!!
2523 * In case we have an "opposite" format, just use that for the swizzling
2524 * information. If we don't have such an "opposite" format, we need
2525 * to use a fixed swizzle info instead (see below)
2527 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2528 format
= PIPE_FORMAT_A4R4_UNORM
;
2530 desc
= util_format_description(format
);
2534 /* Depth and stencil swizzling is handled separately. */
2535 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2536 /* Need to check for specific texture formats that don't have
2537 * an "opposite" format we can use. For those formats, we directly
2538 * specify the swizzling, which is the LE swizzling as defined in
2541 if (do_endian_swap
) {
2542 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2543 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2544 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2545 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2546 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2547 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2549 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2551 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2555 /* Colorspace (return non-RGB formats directly). */
2556 switch (desc
->colorspace
) {
2557 /* Depth stencil formats */
2558 case UTIL_FORMAT_COLORSPACE_ZS
:
2560 /* Depth sampler formats. */
2561 case PIPE_FORMAT_Z16_UNORM
:
2562 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2565 case PIPE_FORMAT_Z24X8_UNORM
:
2566 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2567 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2570 case PIPE_FORMAT_X8Z24_UNORM
:
2571 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2572 if (rscreen
->b
.chip_class
< EVERGREEN
)
2574 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2577 case PIPE_FORMAT_Z32_FLOAT
:
2578 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2579 result
= FMT_32_FLOAT
;
2581 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2582 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2583 result
= FMT_X24_8_32_FLOAT
;
2585 /* Stencil sampler formats. */
2586 case PIPE_FORMAT_S8_UINT
:
2587 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2588 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2591 case PIPE_FORMAT_X24S8_UINT
:
2592 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2593 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2596 case PIPE_FORMAT_S8X24_UINT
:
2597 if (rscreen
->b
.chip_class
< EVERGREEN
)
2599 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2600 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2603 case PIPE_FORMAT_X32_S8X24_UINT
:
2604 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2605 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2606 result
= FMT_X24_8_32_FLOAT
;
2612 case UTIL_FORMAT_COLORSPACE_YUV
:
2613 yuv_format
|= (1 << 30);
2615 case PIPE_FORMAT_UYVY
:
2616 case PIPE_FORMAT_YUYV
:
2620 goto out_unknown
; /* XXX */
2622 case UTIL_FORMAT_COLORSPACE_SRGB
:
2623 word4
|= S_038010_FORCE_DEGAMMA(1);
2630 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2632 case PIPE_FORMAT_RGTC1_SNORM
:
2633 case PIPE_FORMAT_LATC1_SNORM
:
2634 word4
|= sign_bit
[0];
2635 case PIPE_FORMAT_RGTC1_UNORM
:
2636 case PIPE_FORMAT_LATC1_UNORM
:
2639 case PIPE_FORMAT_RGTC2_SNORM
:
2640 case PIPE_FORMAT_LATC2_SNORM
:
2641 word4
|= sign_bit
[0] | sign_bit
[1];
2642 case PIPE_FORMAT_RGTC2_UNORM
:
2643 case PIPE_FORMAT_LATC2_UNORM
:
2651 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2653 case PIPE_FORMAT_DXT1_RGB
:
2654 case PIPE_FORMAT_DXT1_RGBA
:
2655 case PIPE_FORMAT_DXT1_SRGB
:
2656 case PIPE_FORMAT_DXT1_SRGBA
:
2658 is_srgb_valid
= TRUE
;
2660 case PIPE_FORMAT_DXT3_RGBA
:
2661 case PIPE_FORMAT_DXT3_SRGBA
:
2663 is_srgb_valid
= TRUE
;
2665 case PIPE_FORMAT_DXT5_RGBA
:
2666 case PIPE_FORMAT_DXT5_SRGBA
:
2668 is_srgb_valid
= TRUE
;
2675 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2676 if (rscreen
->b
.chip_class
< EVERGREEN
)
2680 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2681 case PIPE_FORMAT_BPTC_SRGBA
:
2683 is_srgb_valid
= TRUE
;
2685 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2686 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2688 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2696 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2698 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2699 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2702 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2703 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2711 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2712 result
= FMT_5_9_9_9_SHAREDEXP
;
2714 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2715 result
= FMT_10_11_11_FLOAT
;
2720 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2721 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2722 word4
|= sign_bit
[i
];
2726 /* R8G8Bx_SNORM - XXX CxV8U8 */
2728 /* See whether the components are of the same size. */
2729 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2730 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2733 /* Non-uniform formats. */
2735 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2736 desc
->channel
[0].pure_integer
)
2737 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2738 switch(desc
->nr_channels
) {
2740 if (desc
->channel
[0].size
== 5 &&
2741 desc
->channel
[1].size
== 6 &&
2742 desc
->channel
[2].size
== 5) {
2748 if (desc
->channel
[0].size
== 5 &&
2749 desc
->channel
[1].size
== 5 &&
2750 desc
->channel
[2].size
== 5 &&
2751 desc
->channel
[3].size
== 1) {
2752 result
= FMT_1_5_5_5
;
2755 if (desc
->channel
[0].size
== 10 &&
2756 desc
->channel
[1].size
== 10 &&
2757 desc
->channel
[2].size
== 10 &&
2758 desc
->channel
[3].size
== 2) {
2759 result
= FMT_2_10_10_10
;
2767 /* Find the first non-VOID channel. */
2768 for (i
= 0; i
< 4; i
++) {
2769 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2777 /* uniform formats */
2778 switch (desc
->channel
[i
].type
) {
2779 case UTIL_FORMAT_TYPE_UNSIGNED
:
2780 case UTIL_FORMAT_TYPE_SIGNED
:
2782 if (!desc
->channel
[i
].normalized
&&
2783 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2787 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2788 desc
->channel
[i
].pure_integer
)
2789 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2791 switch (desc
->channel
[i
].size
) {
2793 switch (desc
->nr_channels
) {
2798 result
= FMT_4_4_4_4
;
2803 switch (desc
->nr_channels
) {
2811 result
= FMT_8_8_8_8
;
2812 is_srgb_valid
= TRUE
;
2817 switch (desc
->nr_channels
) {
2825 result
= FMT_16_16_16_16
;
2830 switch (desc
->nr_channels
) {
2838 result
= FMT_32_32_32_32
;
2844 case UTIL_FORMAT_TYPE_FLOAT
:
2845 switch (desc
->channel
[i
].size
) {
2847 switch (desc
->nr_channels
) {
2849 result
= FMT_16_FLOAT
;
2852 result
= FMT_16_16_FLOAT
;
2855 result
= FMT_16_16_16_16_FLOAT
;
2860 switch (desc
->nr_channels
) {
2862 result
= FMT_32_FLOAT
;
2865 result
= FMT_32_32_FLOAT
;
2868 result
= FMT_32_32_32_32_FLOAT
;
2877 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2882 *yuv_format_p
= yuv_format
;
2885 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2889 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
2890 bool do_endian_swap
)
2892 const struct util_format_description
*desc
= util_format_description(format
);
2893 int channel
= util_format_get_first_non_void_channel(format
);
2898 #define HAS_SIZE(x,y,z,w) \
2899 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2900 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2902 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2903 return V_0280A0_COLOR_10_11_11_FLOAT
;
2905 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2909 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2911 switch (desc
->nr_channels
) {
2913 switch (desc
->channel
[0].size
) {
2915 return V_0280A0_COLOR_8
;
2918 return V_0280A0_COLOR_16_FLOAT
;
2920 return V_0280A0_COLOR_16
;
2923 return V_0280A0_COLOR_32_FLOAT
;
2925 return V_0280A0_COLOR_32
;
2929 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2930 switch (desc
->channel
[0].size
) {
2933 return V_0280A0_COLOR_4_4
;
2935 return ~0U; /* removed on Evergreen */
2937 return V_0280A0_COLOR_8_8
;
2940 return V_0280A0_COLOR_16_16_FLOAT
;
2942 return V_0280A0_COLOR_16_16
;
2945 return V_0280A0_COLOR_32_32_FLOAT
;
2947 return V_0280A0_COLOR_32_32
;
2949 } else if (HAS_SIZE(8,24,0,0)) {
2950 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
2951 } else if (HAS_SIZE(24,8,0,0)) {
2952 return V_0280A0_COLOR_8_24
;
2956 if (HAS_SIZE(5,6,5,0)) {
2957 return V_0280A0_COLOR_5_6_5
;
2958 } else if (HAS_SIZE(32,8,24,0)) {
2959 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2963 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2964 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2965 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2966 switch (desc
->channel
[0].size
) {
2968 return V_0280A0_COLOR_4_4_4_4
;
2970 return V_0280A0_COLOR_8_8_8_8
;
2973 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2975 return V_0280A0_COLOR_16_16_16_16
;
2978 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2980 return V_0280A0_COLOR_32_32_32_32
;
2982 } else if (HAS_SIZE(5,5,5,1)) {
2983 return V_0280A0_COLOR_1_5_5_5
;
2984 } else if (HAS_SIZE(10,10,10,2)) {
2985 return V_0280A0_COLOR_2_10_10_10
;
2992 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
2994 if (R600_BIG_ENDIAN
) {
2995 switch(colorformat
) {
2996 /* 8-bit buffers. */
2997 case V_0280A0_COLOR_4_4
:
2998 case V_0280A0_COLOR_8
:
3001 /* 16-bit buffers. */
3002 case V_0280A0_COLOR_8_8
:
3004 * No need to do endian swaps on array formats,
3005 * as mesa<-->pipe formats conversion take into account
3010 case V_0280A0_COLOR_5_6_5
:
3011 case V_0280A0_COLOR_1_5_5_5
:
3012 case V_0280A0_COLOR_4_4_4_4
:
3013 case V_0280A0_COLOR_16
:
3014 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
3016 /* 32-bit buffers. */
3017 case V_0280A0_COLOR_8_8_8_8
:
3019 * No need to do endian swaps on array formats,
3020 * as mesa<-->pipe formats conversion take into account
3025 case V_0280A0_COLOR_2_10_10_10
:
3026 case V_0280A0_COLOR_8_24
:
3027 case V_0280A0_COLOR_24_8
:
3028 case V_0280A0_COLOR_32_FLOAT
:
3029 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
3031 case V_0280A0_COLOR_16_16_FLOAT
:
3032 case V_0280A0_COLOR_16_16
:
3033 return ENDIAN_8IN16
;
3035 /* 64-bit buffers. */
3036 case V_0280A0_COLOR_16_16_16_16
:
3037 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
3038 return ENDIAN_8IN16
;
3040 case V_0280A0_COLOR_32_32_FLOAT
:
3041 case V_0280A0_COLOR_32_32
:
3042 case V_0280A0_COLOR_X24_8_32_FLOAT
:
3043 return ENDIAN_8IN32
;
3045 /* 128-bit buffers. */
3046 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
3047 case V_0280A0_COLOR_32_32_32_32
:
3048 return ENDIAN_8IN32
;
3050 return ENDIAN_NONE
; /* Unsupported. */
3057 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
3059 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3060 struct r600_resource
*rbuffer
= r600_resource(buf
);
3061 unsigned i
, shader
, mask
;
3062 struct r600_pipe_sampler_view
*view
;
3064 /* Reallocate the buffer in the same pipe_resource. */
3065 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
3067 /* We changed the buffer, now we need to bind it where the old one was bound. */
3068 /* Vertex buffers. */
3069 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
3071 i
= u_bit_scan(&mask
);
3072 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
.resource
== &rbuffer
->b
.b
) {
3073 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
3074 r600_vertex_buffers_dirty(rctx
);
3077 /* Streamout buffers. */
3078 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
3079 if (rctx
->b
.streamout
.targets
[i
] &&
3080 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
3081 if (rctx
->b
.streamout
.begin_emitted
) {
3082 r600_emit_streamout_end(&rctx
->b
);
3084 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
3085 r600_streamout_buffers_dirty(&rctx
->b
);
3089 /* Constant buffers. */
3090 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3091 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
3093 uint32_t mask
= state
->enabled_mask
;
3096 unsigned i
= u_bit_scan(&mask
);
3097 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
3099 state
->dirty_mask
|= 1 << i
;
3103 r600_constant_buffers_dirty(rctx
, state
);
3107 /* Texture buffer objects - update the virtual addresses in descriptors. */
3108 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
3109 if (view
->base
.texture
== &rbuffer
->b
.b
) {
3110 uint64_t offset
= view
->base
.u
.buf
.offset
;
3111 uint64_t va
= rbuffer
->gpu_address
+ offset
;
3113 view
->tex_resource_words
[0] = va
;
3114 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
3115 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
3118 /* Texture buffer objects - make bindings dirty if needed. */
3119 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3120 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
3122 uint32_t mask
= state
->enabled_mask
;
3125 unsigned i
= u_bit_scan(&mask
);
3126 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
3128 state
->dirty_mask
|= 1 << i
;
3132 r600_sampler_views_dirty(rctx
, state
);
3137 struct r600_image_state
*istate
= &rctx
->fragment_buffers
;
3139 uint32_t mask
= istate
->enabled_mask
;
3142 unsigned i
= u_bit_scan(&mask
);
3143 if (istate
->views
[i
].base
.resource
== &rbuffer
->b
.b
) {
3145 istate
->dirty_mask
|= 1 << i
;
3149 r600_mark_atom_dirty(rctx
, &istate
->atom
);
3155 static void r600_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
3157 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3159 /* Pipeline stat & streamout queries. */
3161 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
3162 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
3164 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
3165 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
3168 /* Occlusion queries. */
3169 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
3170 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
3171 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3175 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3176 bool include_draw_vbo
)
3178 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
3181 /* keep this at the end of this file, please */
3182 void r600_init_common_state_functions(struct r600_context
*rctx
)
3184 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
3185 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
3186 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
3187 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
3188 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
3189 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
3190 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
3191 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
3192 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
3193 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
3194 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
3195 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
3196 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
3197 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
3198 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
3199 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
3200 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
3201 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
3202 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
3203 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
3204 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
3205 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
3206 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
3207 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
3208 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
3209 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
3210 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
3211 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
3212 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
3213 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
3214 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
3215 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
3216 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
3217 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
3218 rctx
->b
.b
.memory_barrier
= r600_memory_barrier
;
3219 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
3220 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
3221 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
3223 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
3224 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
3225 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;