2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
37 struct radeon_winsys_cs
*cs
= rctx
->cs
;
38 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
40 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
41 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
42 cs
->cdw
+= cb
->atom
.num_dw
;
45 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
)
47 cb
->atom
.emit
= r600_emit_command_buffer
;
49 cb
->atom
.flags
= flags
;
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 static void r600_emit_surface_sync(struct r600_context
*rctx
, struct r600_atom
*atom
)
61 struct radeon_winsys_cs
*cs
= rctx
->cs
;
62 struct r600_surface_sync_cmd
*a
= (struct r600_surface_sync_cmd
*)atom
;
64 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SURFACE_SYNC
, 3, 0);
65 cs
->buf
[cs
->cdw
++] = a
->flush_flags
; /* CP_COHER_CNTL */
66 cs
->buf
[cs
->cdw
++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs
->buf
[cs
->cdw
++] = 0; /* CP_COHER_BASE */
68 cs
->buf
[cs
->cdw
++] = 0x0000000A; /* POLL_INTERVAL */
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 struct radeon_winsys_cs
*cs
= rctx
->cs
;
76 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
77 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0);
80 void r600_init_atom(struct r600_atom
*atom
,
81 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
82 unsigned num_dw
, enum r600_atom_flags flags
)
85 atom
->num_dw
= num_dw
;
89 void r600_init_common_atoms(struct r600_context
*rctx
)
91 r600_init_atom(&rctx
->surface_sync_cmd
.atom
, r600_emit_surface_sync
, 5, EMIT_EARLY
);
92 r600_init_atom(&rctx
->r6xx_flush_and_inv_cmd
, r600_emit_r6xx_flush_and_inv
, 2, EMIT_EARLY
);
95 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
)
99 if (rctx
->framebuffer
.nr_cbufs
) {
100 flags
|= S_0085F0_CB_ACTION_ENA(1) |
101 (((1 << rctx
->framebuffer
.nr_cbufs
) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT
);
104 /* Workaround for broken flushing on some R6xx chipsets. */
105 if (rctx
->family
== CHIP_RV670
||
106 rctx
->family
== CHIP_RS780
||
107 rctx
->family
== CHIP_RS880
) {
108 flags
|= S_0085F0_CB1_DEST_BASE_ENA(1) |
109 S_0085F0_DEST_BASE_0_ENA(1);
114 void r600_texture_barrier(struct pipe_context
*ctx
)
116 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
118 rctx
->surface_sync_cmd
.flush_flags
|= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx
);
119 r600_atom_dirty(rctx
, &rctx
->surface_sync_cmd
.atom
);
122 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
124 static const int prim_conv
[] = {
125 V_008958_DI_PT_POINTLIST
,
126 V_008958_DI_PT_LINELIST
,
127 V_008958_DI_PT_LINELOOP
,
128 V_008958_DI_PT_LINESTRIP
,
129 V_008958_DI_PT_TRILIST
,
130 V_008958_DI_PT_TRISTRIP
,
131 V_008958_DI_PT_TRIFAN
,
132 V_008958_DI_PT_QUADLIST
,
133 V_008958_DI_PT_QUADSTRIP
,
134 V_008958_DI_PT_POLYGON
,
141 *prim
= prim_conv
[pprim
];
143 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
149 /* common state between evergreen and r600 */
150 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
152 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
153 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
154 struct r600_pipe_state
*rstate
;
155 bool update_cb
= false;
159 rstate
= &blend
->rstate
;
160 rctx
->states
[rstate
->id
] = rstate
;
161 rctx
->dual_src_blend
= blend
->dual_src_blend
;
162 r600_context_pipe_state_set(rctx
, rstate
);
164 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
165 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
168 if (rctx
->chip_class
<= R700
&&
169 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
170 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
173 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
174 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
178 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
182 void r600_set_blend_color(struct pipe_context
*ctx
,
183 const struct pipe_blend_color
*state
)
185 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
186 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
191 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
192 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
193 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
194 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
195 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
197 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
198 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
199 r600_context_pipe_state_set(rctx
, rstate
);
202 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
203 const struct r600_stencil_ref
*state
)
205 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
206 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
211 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
212 r600_pipe_state_add_reg(rstate
,
213 R_028430_DB_STENCILREFMASK
,
214 S_028430_STENCILREF(state
->ref_value
[0]) |
215 S_028430_STENCILMASK(state
->valuemask
[0]) |
216 S_028430_STENCILWRITEMASK(state
->writemask
[0]));
217 r600_pipe_state_add_reg(rstate
,
218 R_028434_DB_STENCILREFMASK_BF
,
219 S_028434_STENCILREF_BF(state
->ref_value
[1]) |
220 S_028434_STENCILMASK_BF(state
->valuemask
[1]) |
221 S_028434_STENCILWRITEMASK_BF(state
->writemask
[1]));
223 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
224 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
225 r600_context_pipe_state_set(rctx
, rstate
);
228 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
229 const struct pipe_stencil_ref
*state
)
231 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
232 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
233 struct r600_stencil_ref ref
;
235 rctx
->stencil_ref
= *state
;
240 ref
.ref_value
[0] = state
->ref_value
[0];
241 ref
.ref_value
[1] = state
->ref_value
[1];
242 ref
.valuemask
[0] = dsa
->valuemask
[0];
243 ref
.valuemask
[1] = dsa
->valuemask
[1];
244 ref
.writemask
[0] = dsa
->writemask
[0];
245 ref
.writemask
[1] = dsa
->writemask
[1];
247 r600_set_stencil_ref(ctx
, &ref
);
250 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
252 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
253 struct r600_pipe_dsa
*dsa
= state
;
254 struct r600_pipe_state
*rstate
;
255 struct r600_stencil_ref ref
;
259 rstate
= &dsa
->rstate
;
260 rctx
->states
[rstate
->id
] = rstate
;
261 rctx
->sx_alpha_test_control
&= ~0xff;
262 rctx
->sx_alpha_test_control
|= dsa
->sx_alpha_test_control
;
263 rctx
->alpha_ref
= dsa
->alpha_ref
;
264 rctx
->alpha_ref_dirty
= true;
265 r600_context_pipe_state_set(rctx
, rstate
);
267 ref
.ref_value
[0] = rctx
->stencil_ref
.ref_value
[0];
268 ref
.ref_value
[1] = rctx
->stencil_ref
.ref_value
[1];
269 ref
.valuemask
[0] = dsa
->valuemask
[0];
270 ref
.valuemask
[1] = dsa
->valuemask
[1];
271 ref
.writemask
[0] = dsa
->writemask
[0];
272 ref
.writemask
[1] = dsa
->writemask
[1];
274 r600_set_stencil_ref(ctx
, &ref
);
277 void r600_set_max_scissor(struct r600_context
*rctx
)
279 /* Set a scissor state such that it doesn't do anything. */
280 struct pipe_scissor_state scissor
;
286 r600_set_scissor_state(rctx
, &scissor
);
289 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
291 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
292 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
297 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
298 rctx
->two_side
= rs
->two_side
;
299 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
300 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
302 rctx
->rasterizer
= rs
;
304 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
305 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
307 if (rctx
->chip_class
>= EVERGREEN
) {
308 evergreen_polygon_offset_update(rctx
);
310 r600_polygon_offset_update(rctx
);
313 /* Workaround for a missing scissor enable on r600. */
314 if (rctx
->chip_class
== R600
) {
315 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
316 rctx
->scissor_enable
= rs
->scissor_enable
;
318 if (rs
->scissor_enable
) {
319 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
321 r600_set_max_scissor(rctx
);
327 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
329 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
330 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
332 if (rctx
->rasterizer
== rs
) {
333 rctx
->rasterizer
= NULL
;
335 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
336 rctx
->states
[rs
->rstate
.id
] = NULL
;
341 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
342 struct pipe_sampler_view
*state
)
344 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
346 pipe_resource_reference(&state
->texture
, NULL
);
350 void r600_delete_state(struct pipe_context
*ctx
, void *state
)
352 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
353 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
355 if (rctx
->states
[rstate
->id
] == rstate
) {
356 rctx
->states
[rstate
->id
] = NULL
;
358 for (int i
= 0; i
< rstate
->nregs
; i
++) {
359 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
364 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
366 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
367 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
369 rctx
->vertex_elements
= v
;
371 r600_inval_shader_cache(rctx
);
373 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
374 r600_context_pipe_state_set(rctx
, &v
->rstate
);
378 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
380 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
381 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
383 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
384 rctx
->states
[v
->rstate
.id
] = NULL
;
386 if (rctx
->vertex_elements
== state
)
387 rctx
->vertex_elements
= NULL
;
389 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
393 void r600_set_index_buffer(struct pipe_context
*ctx
,
394 const struct pipe_index_buffer
*ib
)
396 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
399 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
400 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
402 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
406 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
407 const struct pipe_vertex_buffer
*buffers
)
409 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
411 util_copy_vertex_buffers(rctx
->vertex_buffer
, &rctx
->nr_vertex_buffers
, buffers
, count
);
413 r600_inval_vertex_cache(rctx
);
414 rctx
->vertex_buffer_state
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 10) *
415 rctx
->nr_vertex_buffers
;
416 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
);
419 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
421 const struct pipe_vertex_element
*elements
)
423 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
424 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
431 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
433 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
441 /* Compute the key for the hw shader variant */
442 static INLINE
unsigned r600_shader_selector_key(struct pipe_context
* ctx
,
443 struct r600_pipe_shader_selector
* sel
)
445 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
448 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
449 key
= rctx
->two_side
|
450 MIN2(sel
->nr_ps_max_color_exports
, rctx
->nr_cbufs
+ rctx
->dual_src_blend
) << 1;
457 /* Select the hw shader variant depending on the current state.
458 * (*dirty) is set to 1 if current variant was changed */
459 static int r600_shader_select(struct pipe_context
*ctx
,
460 struct r600_pipe_shader_selector
* sel
,
464 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
465 struct r600_pipe_shader
* shader
= NULL
;
468 key
= r600_shader_selector_key(ctx
, sel
);
470 /* Check if we don't need to change anything.
471 * This path is also used for most shaders that don't need multiple
472 * variants, it will cost just a computation of the key and this
474 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
478 /* lookup if we have other variants in the list */
479 if (sel
->num_shaders
> 1) {
480 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
482 while (c
&& c
->key
!= key
) {
488 p
->next_variant
= c
->next_variant
;
493 if (unlikely(!shader
)) {
494 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
495 shader
->selector
= sel
;
497 r
= r600_pipe_shader_create(ctx
, shader
);
499 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
505 /* We don't know the value of nr_ps_max_color_exports until we built
506 * at least one variant, so we may need to recompute the key after
507 * building first variant. */
508 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
509 sel
->num_shaders
== 0) {
510 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
511 key
= r600_shader_selector_key(ctx
, sel
);
521 shader
->next_variant
= sel
->current
;
522 sel
->current
= shader
;
524 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
525 r600_adjust_gprs(rctx
);
528 if (rctx
->ps_shader
&&
529 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
530 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
531 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
536 static void *r600_create_shader_state(struct pipe_context
*ctx
,
537 const struct pipe_shader_state
*state
,
538 unsigned pipe_shader_type
)
540 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
543 sel
->type
= pipe_shader_type
;
544 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
545 sel
->so
= state
->stream_output
;
547 r
= r600_shader_select(ctx
, sel
, NULL
);
554 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
555 const struct pipe_shader_state
*state
)
557 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
560 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
561 const struct pipe_shader_state
*state
)
563 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
566 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
568 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
571 state
= rctx
->dummy_pixel_shader
;
573 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
574 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
576 if (rctx
->chip_class
<= R700
) {
577 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
579 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
580 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
581 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
585 r600_adjust_gprs(rctx
);
588 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
589 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
590 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
594 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
596 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
598 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
600 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
602 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
603 r600_adjust_gprs(rctx
);
607 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
608 struct r600_pipe_shader_selector
*sel
)
610 struct r600_pipe_shader
*p
= sel
->current
, *c
;
613 r600_pipe_shader_destroy(ctx
, p
);
623 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
625 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
626 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
628 if (rctx
->ps_shader
== sel
) {
629 rctx
->ps_shader
= NULL
;
632 r600_delete_shader_selector(ctx
, sel
);
635 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
637 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
638 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
640 if (rctx
->vs_shader
== sel
) {
641 rctx
->vs_shader
= NULL
;
644 r600_delete_shader_selector(ctx
, sel
);
647 static void r600_update_alpha_ref(struct r600_context
*rctx
)
650 struct r600_pipe_state rstate
;
652 alpha_ref
= rctx
->alpha_ref
;
654 if (rctx
->export_16bpc
&& rctx
->chip_class
>= EVERGREEN
) {
655 alpha_ref
&= ~0x1FFF;
657 r600_pipe_state_add_reg(&rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
);
659 r600_context_pipe_state_set(rctx
, &rstate
);
660 rctx
->alpha_ref_dirty
= false;
663 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
665 r600_inval_shader_cache(rctx
);
666 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
667 : util_bitcount(state
->dirty_mask
)*19;
668 r600_atom_dirty(rctx
, &state
->atom
);
671 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
672 struct pipe_constant_buffer
*input
)
674 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
675 struct r600_constbuf_state
*state
;
676 struct pipe_constant_buffer
*cb
;
680 case PIPE_SHADER_VERTEX
:
681 state
= &rctx
->vs_constbuf_state
;
683 case PIPE_SHADER_FRAGMENT
:
684 state
= &rctx
->ps_constbuf_state
;
690 /* Note that the state tracker can unbind constant buffers by
693 if (unlikely(!input
)) {
694 state
->enabled_mask
&= ~(1 << index
);
695 state
->dirty_mask
&= ~(1 << index
);
696 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
700 cb
= &state
->cb
[index
];
701 cb
->buffer_size
= input
->buffer_size
;
703 ptr
= input
->user_buffer
;
706 /* Upload the user buffer. */
707 if (R600_BIG_ENDIAN
) {
709 unsigned i
, size
= input
->buffer_size
;
711 if (!(tmpPtr
= malloc(size
))) {
712 R600_ERR("Failed to allocate BE swap buffer.\n");
716 for (i
= 0; i
< size
/ 4; ++i
) {
717 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
720 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
723 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
726 /* Setup the hw buffer. */
727 cb
->buffer_offset
= input
->buffer_offset
;
728 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
731 state
->enabled_mask
|= 1 << index
;
732 state
->dirty_mask
|= 1 << index
;
733 r600_constant_buffers_dirty(rctx
, state
);
736 struct pipe_stream_output_target
*
737 r600_create_so_target(struct pipe_context
*ctx
,
738 struct pipe_resource
*buffer
,
739 unsigned buffer_offset
,
740 unsigned buffer_size
)
742 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
743 struct r600_so_target
*t
;
746 t
= CALLOC_STRUCT(r600_so_target
);
751 t
->b
.reference
.count
= 1;
753 pipe_resource_reference(&t
->b
.buffer
, buffer
);
754 t
->b
.buffer_offset
= buffer_offset
;
755 t
->b
.buffer_size
= buffer_size
;
757 t
->filled_size
= (struct r600_resource
*)
758 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
759 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
760 memset(ptr
, 0, t
->filled_size
->buf
->size
);
761 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
766 void r600_so_target_destroy(struct pipe_context
*ctx
,
767 struct pipe_stream_output_target
*target
)
769 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
770 pipe_resource_reference(&t
->b
.buffer
, NULL
);
771 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
775 void r600_set_so_targets(struct pipe_context
*ctx
,
776 unsigned num_targets
,
777 struct pipe_stream_output_target
**targets
,
778 unsigned append_bitmask
)
780 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
783 /* Stop streamout. */
784 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
785 r600_context_streamout_end(rctx
);
788 /* Set the new targets. */
789 for (i
= 0; i
< num_targets
; i
++) {
790 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
792 for (; i
< rctx
->num_so_targets
; i
++) {
793 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
796 rctx
->num_so_targets
= num_targets
;
797 rctx
->streamout_start
= num_targets
!= 0;
798 rctx
->streamout_append_bitmask
= append_bitmask
;
801 static void r600_update_derived_state(struct r600_context
*rctx
)
803 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
804 unsigned ps_dirty
= 0;
806 if (!rctx
->blitter
->running
) {
807 if (rctx
->have_depth_fb
|| rctx
->have_depth_texture
)
808 r600_flush_depth_textures(rctx
);
811 if (rctx
->chip_class
< EVERGREEN
) {
812 r600_update_sampler_states(rctx
);
815 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
817 if (rctx
->alpha_ref_dirty
) {
818 r600_update_alpha_ref(rctx
);
821 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
822 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
823 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
825 if (rctx
->chip_class
>= EVERGREEN
)
826 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
828 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
834 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
836 if (rctx
->chip_class
>= EVERGREEN
) {
837 evergreen_update_dual_export_state(rctx
);
839 r600_update_dual_export_state(rctx
);
843 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
845 static const int prim_conv
[] = {
846 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
847 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
848 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
849 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
850 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
851 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
852 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
853 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
854 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
855 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
856 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
857 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
858 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
859 V_028A6C_OUTPRIM_TYPE_TRISTRIP
861 assert(mode
< Elements(prim_conv
));
863 return prim_conv
[mode
];
866 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
868 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
869 struct pipe_draw_info info
= *dinfo
;
870 struct pipe_index_buffer ib
= {};
871 unsigned prim
, ls_mask
= 0;
872 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
873 struct r600_atom
*state
= NULL
, *next_state
= NULL
;
874 struct radeon_winsys_cs
*cs
= rctx
->cs
;
878 if ((!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) ||
879 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
884 if (!rctx
->vs_shader
) {
889 r600_update_derived_state(rctx
);
892 /* Initialize the index buffer struct. */
893 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
894 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
895 ib
.index_size
= rctx
->index_buffer
.index_size
;
896 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
898 /* Translate or upload, if needed. */
899 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
901 ptr
= (uint8_t*)ib
.user_buffer
;
902 if (!ib
.buffer
&& ptr
) {
903 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
904 ptr
, &ib
.offset
, &ib
.buffer
);
907 info
.index_bias
= info
.start
;
908 if (info
.count_from_stream_output
) {
909 r600_context_draw_opaque_count(rctx
, (struct r600_so_target
*)info
.count_from_stream_output
);
913 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
914 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
916 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
917 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0);
918 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
);
919 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
);
920 r600_pipe_state_add_reg(&rctx
->vgt
, R_028410_SX_ALPHA_TEST_CONTROL
, 0);
921 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
);
922 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
923 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A0C_PA_SC_LINE_STIPPLE
, 0);
924 r600_pipe_state_add_reg(&rctx
->vgt
, R_02881C_PA_CL_VS_OUT_CNTL
, 0);
925 r600_pipe_state_add_reg(&rctx
->vgt
, R_028810_PA_CL_CLIP_CNTL
, 0);
929 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
930 r600_pipe_state_mod_reg(&rctx
->vgt
, r600_conv_prim_to_gs_out(info
.mode
));
931 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
932 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
933 r600_pipe_state_mod_reg(&rctx
->vgt
, rctx
->sx_alpha_test_control
);
934 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
935 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
937 if (prim
== V_008958_DI_PT_LINELIST
)
939 else if (prim
== V_008958_DI_PT_LINESTRIP
)
941 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
942 r600_pipe_state_mod_reg(&rctx
->vgt
,
943 rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
|
944 (rctx
->rasterizer
->clip_plane_enable
& rctx
->vs_shader
->current
->shader
.clip_dist_write
));
945 r600_pipe_state_mod_reg(&rctx
->vgt
,
946 rctx
->pa_cl_clip_cntl
|
947 (rctx
->vs_shader
->current
->shader
.clip_dist_write
||
948 rctx
->vs_shader
->current
->shader
.vs_prohibit_ucps
?
949 0 : rctx
->rasterizer
->clip_plane_enable
& 0x3F));
951 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
953 /* Emit states (the function expects that we emit at most 17 dwords here). */
954 r600_need_cs_space(rctx
, 0, TRUE
);
956 LIST_FOR_EACH_ENTRY_SAFE(state
, next_state
, &rctx
->dirty_states
, head
) {
957 r600_emit_atom(rctx
, state
);
959 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
960 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
962 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->resource_dirty
,list
) {
963 r600_context_block_resource_emit_dirty(rctx
, dirty_block
);
965 rctx
->pm4_dirty_cdwords
= 0;
967 /* Enable stream out if needed. */
968 if (rctx
->streamout_start
) {
969 r600_context_streamout_begin(rctx
);
970 rctx
->streamout_start
= FALSE
;
974 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
975 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
976 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
977 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
978 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
979 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
981 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
983 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
984 cs
->buf
[cs
->cdw
++] = va
;
985 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
986 cs
->buf
[cs
->cdw
++] = info
.count
;
987 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
988 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
989 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
991 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
992 cs
->buf
[cs
->cdw
++] = info
.count
;
993 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
994 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
997 rctx
->flags
|= R600_CONTEXT_DST_CACHES_DIRTY
| R600_CONTEXT_DRAW_PENDING
;
999 /* Set the depth buffer as dirty. */
1000 if (rctx
->framebuffer
.zsbuf
) {
1001 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
1002 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)surf
->texture
;
1004 rtex
->dirty_db_mask
|= 1 << surf
->u
.tex
.level
;
1007 pipe_resource_reference(&ib
.buffer
, NULL
);
1010 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1011 struct r600_pipe_state
*state
,
1012 uint32_t offset
, uint32_t value
,
1013 uint32_t range_id
, uint32_t block_id
,
1014 struct r600_resource
*bo
,
1015 enum radeon_bo_usage usage
)
1018 struct r600_range
*range
;
1019 struct r600_block
*block
;
1021 if (bo
) assert(usage
);
1023 range
= &ctx
->range
[range_id
];
1024 block
= range
->blocks
[block_id
];
1025 state
->regs
[state
->nregs
].block
= block
;
1026 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1028 state
->regs
[state
->nregs
].value
= value
;
1029 state
->regs
[state
->nregs
].bo
= bo
;
1030 state
->regs
[state
->nregs
].bo_usage
= usage
;
1033 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1036 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1037 struct r600_pipe_state
*state
,
1038 uint32_t offset
, uint32_t value
,
1039 uint32_t range_id
, uint32_t block_id
)
1041 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1042 range_id
, block_id
, NULL
, 0);
1045 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state
*state
,
1046 uint32_t offset
, uint32_t value
,
1047 struct r600_resource
*bo
,
1048 enum radeon_bo_usage usage
)
1050 if (bo
) assert(usage
);
1052 state
->regs
[state
->nregs
].id
= offset
;
1053 state
->regs
[state
->nregs
].block
= NULL
;
1054 state
->regs
[state
->nregs
].value
= value
;
1055 state
->regs
[state
->nregs
].bo
= bo
;
1056 state
->regs
[state
->nregs
].bo_usage
= usage
;
1059 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1062 uint32_t r600_translate_stencil_op(int s_op
)
1065 case PIPE_STENCIL_OP_KEEP
:
1066 return V_028800_STENCIL_KEEP
;
1067 case PIPE_STENCIL_OP_ZERO
:
1068 return V_028800_STENCIL_ZERO
;
1069 case PIPE_STENCIL_OP_REPLACE
:
1070 return V_028800_STENCIL_REPLACE
;
1071 case PIPE_STENCIL_OP_INCR
:
1072 return V_028800_STENCIL_INCR
;
1073 case PIPE_STENCIL_OP_DECR
:
1074 return V_028800_STENCIL_DECR
;
1075 case PIPE_STENCIL_OP_INCR_WRAP
:
1076 return V_028800_STENCIL_INCR_WRAP
;
1077 case PIPE_STENCIL_OP_DECR_WRAP
:
1078 return V_028800_STENCIL_DECR_WRAP
;
1079 case PIPE_STENCIL_OP_INVERT
:
1080 return V_028800_STENCIL_INVERT
;
1082 R600_ERR("Unknown stencil op %d", s_op
);
1089 uint32_t r600_translate_fill(uint32_t func
)
1092 case PIPE_POLYGON_MODE_FILL
:
1094 case PIPE_POLYGON_MODE_LINE
:
1096 case PIPE_POLYGON_MODE_POINT
:
1104 unsigned r600_tex_wrap(unsigned wrap
)
1108 case PIPE_TEX_WRAP_REPEAT
:
1109 return V_03C000_SQ_TEX_WRAP
;
1110 case PIPE_TEX_WRAP_CLAMP
:
1111 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1112 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1113 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1114 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1115 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1116 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1117 return V_03C000_SQ_TEX_MIRROR
;
1118 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1119 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1120 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1121 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1122 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1123 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1127 unsigned r600_tex_filter(unsigned filter
)
1131 case PIPE_TEX_FILTER_NEAREST
:
1132 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1133 case PIPE_TEX_FILTER_LINEAR
:
1134 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1138 unsigned r600_tex_mipfilter(unsigned filter
)
1141 case PIPE_TEX_MIPFILTER_NEAREST
:
1142 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1143 case PIPE_TEX_MIPFILTER_LINEAR
:
1144 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1146 case PIPE_TEX_MIPFILTER_NONE
:
1147 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1151 unsigned r600_tex_compare(unsigned compare
)
1155 case PIPE_FUNC_NEVER
:
1156 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1157 case PIPE_FUNC_LESS
:
1158 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1159 case PIPE_FUNC_EQUAL
:
1160 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1161 case PIPE_FUNC_LEQUAL
:
1162 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1163 case PIPE_FUNC_GREATER
:
1164 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1165 case PIPE_FUNC_NOTEQUAL
:
1166 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1167 case PIPE_FUNC_GEQUAL
:
1168 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1169 case PIPE_FUNC_ALWAYS
:
1170 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;