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r600g: allow setting geometry shader sampler states
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37
38 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
39 {
40 assert(!cb->buf);
41 cb->buf = CALLOC(1, 4 * num_dw);
42 cb->max_num_dw = num_dw;
43 }
44
45 void r600_release_command_buffer(struct r600_command_buffer *cb)
46 {
47 FREE(cb->buf);
48 }
49
50 void r600_add_atom(struct r600_context *rctx,
51 struct r600_atom *atom,
52 unsigned id)
53 {
54 assert(id < R600_NUM_ATOMS);
55 assert(rctx->atoms[id] == NULL);
56 rctx->atoms[id] = atom;
57 atom->id = id;
58 atom->dirty = false;
59 }
60
61 void r600_init_atom(struct r600_context *rctx,
62 struct r600_atom *atom,
63 unsigned id,
64 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
65 unsigned num_dw)
66 {
67 atom->emit = (void*)emit;
68 atom->num_dw = num_dw;
69 r600_add_atom(rctx, atom, id);
70 }
71
72 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
73 {
74 r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
75 }
76
77 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
78 {
79 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
80 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
81 unsigned alpha_ref = a->sx_alpha_ref;
82
83 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
84 alpha_ref &= ~0x1FFF;
85 }
86
87 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
88 a->sx_alpha_test_control |
89 S_028410_ALPHA_TEST_BYPASS(a->bypass));
90 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
91 }
92
93 static void r600_texture_barrier(struct pipe_context *ctx)
94 {
95 struct r600_context *rctx = (struct r600_context *)ctx;
96
97 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
98 R600_CONTEXT_FLUSH_AND_INV_CB |
99 R600_CONTEXT_FLUSH_AND_INV |
100 R600_CONTEXT_WAIT_3D_IDLE;
101 }
102
103 static unsigned r600_conv_pipe_prim(unsigned prim)
104 {
105 static const unsigned prim_conv[] = {
106 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
107 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
108 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
109 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
110 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
111 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
112 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
113 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
114 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
115 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
116 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
117 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
118 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
119 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
120 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
121 };
122 assert(prim < Elements(prim_conv));
123 return prim_conv[prim];
124 }
125
126 /* common state between evergreen and r600 */
127
128 static void r600_bind_blend_state_internal(struct r600_context *rctx,
129 struct r600_blend_state *blend, bool blend_disable)
130 {
131 unsigned color_control;
132 bool update_cb = false;
133
134 rctx->alpha_to_one = blend->alpha_to_one;
135 rctx->dual_src_blend = blend->dual_src_blend;
136
137 if (!blend_disable) {
138 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
139 color_control = blend->cb_color_control;
140 } else {
141 /* Blending is disabled. */
142 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
143 color_control = blend->cb_color_control_no_blend;
144 }
145
146 /* Update derived states. */
147 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
148 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
149 update_cb = true;
150 }
151 if (rctx->b.chip_class <= R700 &&
152 rctx->cb_misc_state.cb_color_control != color_control) {
153 rctx->cb_misc_state.cb_color_control = color_control;
154 update_cb = true;
155 }
156 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
157 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
158 update_cb = true;
159 }
160 if (update_cb) {
161 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
162 }
163 }
164
165 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
166 {
167 struct r600_context *rctx = (struct r600_context *)ctx;
168 struct r600_blend_state *blend = (struct r600_blend_state *)state;
169
170 if (blend == NULL) {
171 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
172 return;
173 }
174
175 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
176 }
177
178 static void r600_set_blend_color(struct pipe_context *ctx,
179 const struct pipe_blend_color *state)
180 {
181 struct r600_context *rctx = (struct r600_context *)ctx;
182
183 rctx->blend_color.state = *state;
184 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
185 }
186
187 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
188 {
189 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
190 struct pipe_blend_color *state = &rctx->blend_color.state;
191
192 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
193 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
194 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
195 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
196 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
197 }
198
199 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
200 {
201 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
202 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
203
204 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
205 r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
206 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
207 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
208 if (a->last_draw_was_indirect) {
209 a->last_draw_was_indirect = false;
210 r600_write_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
211 }
212 }
213
214 static void r600_set_clip_state(struct pipe_context *ctx,
215 const struct pipe_clip_state *state)
216 {
217 struct r600_context *rctx = (struct r600_context *)ctx;
218 struct pipe_constant_buffer cb;
219
220 rctx->clip_state.state = *state;
221 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
222
223 cb.buffer = NULL;
224 cb.user_buffer = state->ucp;
225 cb.buffer_offset = 0;
226 cb.buffer_size = 4*4*8;
227 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
228 pipe_resource_reference(&cb.buffer, NULL);
229 }
230
231 static void r600_set_stencil_ref(struct pipe_context *ctx,
232 const struct r600_stencil_ref *state)
233 {
234 struct r600_context *rctx = (struct r600_context *)ctx;
235
236 rctx->stencil_ref.state = *state;
237 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
238 }
239
240 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
241 {
242 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
243 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
244
245 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
246 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
247 S_028430_STENCILREF(a->state.ref_value[0]) |
248 S_028430_STENCILMASK(a->state.valuemask[0]) |
249 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
250 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
251 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
252 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
253 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
254 }
255
256 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
257 const struct pipe_stencil_ref *state)
258 {
259 struct r600_context *rctx = (struct r600_context *)ctx;
260 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
261 struct r600_stencil_ref ref;
262
263 rctx->stencil_ref.pipe_state = *state;
264
265 if (!dsa)
266 return;
267
268 ref.ref_value[0] = state->ref_value[0];
269 ref.ref_value[1] = state->ref_value[1];
270 ref.valuemask[0] = dsa->valuemask[0];
271 ref.valuemask[1] = dsa->valuemask[1];
272 ref.writemask[0] = dsa->writemask[0];
273 ref.writemask[1] = dsa->writemask[1];
274
275 r600_set_stencil_ref(ctx, &ref);
276 }
277
278 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
279 {
280 struct r600_context *rctx = (struct r600_context *)ctx;
281 struct r600_dsa_state *dsa = state;
282 struct r600_stencil_ref ref;
283
284 if (state == NULL) {
285 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
286 return;
287 }
288
289 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
290
291 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
292 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
293 ref.valuemask[0] = dsa->valuemask[0];
294 ref.valuemask[1] = dsa->valuemask[1];
295 ref.writemask[0] = dsa->writemask[0];
296 ref.writemask[1] = dsa->writemask[1];
297 if (rctx->zwritemask != dsa->zwritemask) {
298 rctx->zwritemask = dsa->zwritemask;
299 if (rctx->b.chip_class >= EVERGREEN) {
300 /* work around some issue when not writing to zbuffer
301 * we are having lockup on evergreen so do not enable
302 * hyperz when not writing zbuffer
303 */
304 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
305 }
306 }
307
308 r600_set_stencil_ref(ctx, &ref);
309
310 /* Update alphatest state. */
311 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
312 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
313 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
314 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
315 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
316 }
317 }
318
319 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
320 {
321 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
322 struct r600_context *rctx = (struct r600_context *)ctx;
323
324 if (state == NULL)
325 return;
326
327 rctx->rasterizer = rs;
328
329 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
330
331 if (rs->offset_enable &&
332 (rs->offset_units != rctx->poly_offset_state.offset_units ||
333 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
334 rctx->poly_offset_state.offset_units = rs->offset_units;
335 rctx->poly_offset_state.offset_scale = rs->offset_scale;
336 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
337 }
338
339 /* Update clip_misc_state. */
340 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
341 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
342 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
343 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
344 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
345 }
346
347 /* Workaround for a missing scissor enable on r600. */
348 if (rctx->b.chip_class == R600 &&
349 rs->scissor_enable != rctx->scissor[0].enable) {
350 rctx->scissor[0].enable = rs->scissor_enable;
351 r600_mark_atom_dirty(rctx, &rctx->scissor[0].atom);
352 }
353
354 /* Re-emit PA_SC_LINE_STIPPLE. */
355 rctx->last_primitive_type = -1;
356 }
357
358 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
359 {
360 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
361
362 r600_release_command_buffer(&rs->buffer);
363 FREE(rs);
364 }
365
366 static void r600_sampler_view_destroy(struct pipe_context *ctx,
367 struct pipe_sampler_view *state)
368 {
369 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
370
371 if (view->tex_resource->gpu_address &&
372 view->tex_resource->b.b.target == PIPE_BUFFER)
373 LIST_DELINIT(&view->list);
374
375 pipe_resource_reference(&state->texture, NULL);
376 FREE(view);
377 }
378
379 void r600_sampler_states_dirty(struct r600_context *rctx,
380 struct r600_sampler_states *state)
381 {
382 if (state->dirty_mask) {
383 if (state->dirty_mask & state->has_bordercolor_mask) {
384 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
385 }
386 state->atom.num_dw =
387 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
388 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
389 r600_mark_atom_dirty(rctx, &state->atom);
390 }
391 }
392
393 static void r600_bind_sampler_states(struct pipe_context *pipe,
394 unsigned shader,
395 unsigned start,
396 unsigned count, void **states)
397 {
398 struct r600_context *rctx = (struct r600_context *)pipe;
399 struct r600_textures_info *dst = &rctx->samplers[shader];
400 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
401 int seamless_cube_map = -1;
402 unsigned i;
403 /* This sets 1-bit for states with index >= count. */
404 uint32_t disable_mask = ~((1ull << count) - 1);
405 /* These are the new states set by this function. */
406 uint32_t new_mask = 0;
407
408 assert(start == 0); /* XXX fix below */
409
410 for (i = 0; i < count; i++) {
411 struct r600_pipe_sampler_state *rstate = rstates[i];
412
413 if (rstate == dst->states.states[i]) {
414 continue;
415 }
416
417 if (rstate) {
418 if (rstate->border_color_use) {
419 dst->states.has_bordercolor_mask |= 1 << i;
420 } else {
421 dst->states.has_bordercolor_mask &= ~(1 << i);
422 }
423 seamless_cube_map = rstate->seamless_cube_map;
424
425 new_mask |= 1 << i;
426 } else {
427 disable_mask |= 1 << i;
428 }
429 }
430
431 memcpy(dst->states.states, rstates, sizeof(void*) * count);
432 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
433
434 dst->states.enabled_mask &= ~disable_mask;
435 dst->states.dirty_mask &= dst->states.enabled_mask;
436 dst->states.enabled_mask |= new_mask;
437 dst->states.dirty_mask |= new_mask;
438 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
439
440 r600_sampler_states_dirty(rctx, &dst->states);
441
442 /* Seamless cubemap state. */
443 if (rctx->b.chip_class <= R700 &&
444 seamless_cube_map != -1 &&
445 seamless_cube_map != rctx->seamless_cube_map.enabled) {
446 /* change in TA_CNTL_AUX need a pipeline flush */
447 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
448 rctx->seamless_cube_map.enabled = seamless_cube_map;
449 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
450 }
451 }
452
453 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
454 {
455 free(state);
456 }
457
458 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
459 {
460 struct r600_context *rctx = (struct r600_context *)ctx;
461 struct r600_blend_state *blend = (struct r600_blend_state*)state;
462
463 if (rctx->blend_state.cso == state) {
464 ctx->bind_blend_state(ctx, NULL);
465 }
466
467 r600_release_command_buffer(&blend->buffer);
468 r600_release_command_buffer(&blend->buffer_no_blend);
469 FREE(blend);
470 }
471
472 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
473 {
474 struct r600_context *rctx = (struct r600_context *)ctx;
475 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
476
477 if (rctx->dsa_state.cso == state) {
478 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
479 }
480
481 r600_release_command_buffer(&dsa->buffer);
482 free(dsa);
483 }
484
485 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
486 {
487 struct r600_context *rctx = (struct r600_context *)ctx;
488
489 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
490 }
491
492 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
493 {
494 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
495 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
496 FREE(shader);
497 }
498
499 static void r600_set_index_buffer(struct pipe_context *ctx,
500 const struct pipe_index_buffer *ib)
501 {
502 struct r600_context *rctx = (struct r600_context *)ctx;
503
504 if (ib) {
505 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
506 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
507 r600_context_add_resource_size(ctx, ib->buffer);
508 } else {
509 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
510 }
511 }
512
513 void r600_vertex_buffers_dirty(struct r600_context *rctx)
514 {
515 if (rctx->vertex_buffer_state.dirty_mask) {
516 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
517 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
518 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
519 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
520 }
521 }
522
523 static void r600_set_vertex_buffers(struct pipe_context *ctx,
524 unsigned start_slot, unsigned count,
525 const struct pipe_vertex_buffer *input)
526 {
527 struct r600_context *rctx = (struct r600_context *)ctx;
528 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
529 struct pipe_vertex_buffer *vb = state->vb + start_slot;
530 unsigned i;
531 uint32_t disable_mask = 0;
532 /* These are the new buffers set by this function. */
533 uint32_t new_buffer_mask = 0;
534
535 /* Set vertex buffers. */
536 if (input) {
537 for (i = 0; i < count; i++) {
538 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
539 if (input[i].buffer) {
540 vb[i].stride = input[i].stride;
541 vb[i].buffer_offset = input[i].buffer_offset;
542 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
543 new_buffer_mask |= 1 << i;
544 r600_context_add_resource_size(ctx, input[i].buffer);
545 } else {
546 pipe_resource_reference(&vb[i].buffer, NULL);
547 disable_mask |= 1 << i;
548 }
549 }
550 }
551 } else {
552 for (i = 0; i < count; i++) {
553 pipe_resource_reference(&vb[i].buffer, NULL);
554 }
555 disable_mask = ((1ull << count) - 1);
556 }
557
558 disable_mask <<= start_slot;
559 new_buffer_mask <<= start_slot;
560
561 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
562 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
563 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
564 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
565
566 r600_vertex_buffers_dirty(rctx);
567 }
568
569 void r600_sampler_views_dirty(struct r600_context *rctx,
570 struct r600_samplerview_state *state)
571 {
572 if (state->dirty_mask) {
573 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
574 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
575 util_bitcount(state->dirty_mask);
576 r600_mark_atom_dirty(rctx, &state->atom);
577 }
578 }
579
580 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
581 unsigned start, unsigned count,
582 struct pipe_sampler_view **views)
583 {
584 struct r600_context *rctx = (struct r600_context *) pipe;
585 struct r600_textures_info *dst = &rctx->samplers[shader];
586 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
587 uint32_t dirty_sampler_states_mask = 0;
588 unsigned i;
589 /* This sets 1-bit for textures with index >= count. */
590 uint32_t disable_mask = ~((1ull << count) - 1);
591 /* These are the new textures set by this function. */
592 uint32_t new_mask = 0;
593
594 /* Set textures with index >= count to NULL. */
595 uint32_t remaining_mask;
596
597 assert(start == 0); /* XXX fix below */
598
599 if (shader == PIPE_SHADER_COMPUTE) {
600 evergreen_set_cs_sampler_view(pipe, start, count, views);
601 return;
602 }
603
604 remaining_mask = dst->views.enabled_mask & disable_mask;
605
606 while (remaining_mask) {
607 i = u_bit_scan(&remaining_mask);
608 assert(dst->views.views[i]);
609
610 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
611 }
612
613 for (i = 0; i < count; i++) {
614 if (rviews[i] == dst->views.views[i]) {
615 continue;
616 }
617
618 if (rviews[i]) {
619 struct r600_texture *rtex =
620 (struct r600_texture*)rviews[i]->base.texture;
621
622 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
623 if (rtex->is_depth && !rtex->is_flushing_texture) {
624 dst->views.compressed_depthtex_mask |= 1 << i;
625 } else {
626 dst->views.compressed_depthtex_mask &= ~(1 << i);
627 }
628
629 /* Track compressed colorbuffers. */
630 if (rtex->cmask.size) {
631 dst->views.compressed_colortex_mask |= 1 << i;
632 } else {
633 dst->views.compressed_colortex_mask &= ~(1 << i);
634 }
635 }
636 /* Changing from array to non-arrays textures and vice versa requires
637 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
638 if (rctx->b.chip_class <= R700 &&
639 (dst->states.enabled_mask & (1 << i)) &&
640 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
641 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
642 dirty_sampler_states_mask |= 1 << i;
643 }
644
645 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
646 new_mask |= 1 << i;
647 r600_context_add_resource_size(pipe, views[i]->texture);
648 } else {
649 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
650 disable_mask |= 1 << i;
651 }
652 }
653
654 dst->views.enabled_mask &= ~disable_mask;
655 dst->views.dirty_mask &= dst->views.enabled_mask;
656 dst->views.enabled_mask |= new_mask;
657 dst->views.dirty_mask |= new_mask;
658 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
659 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
660 dst->views.dirty_buffer_constants = TRUE;
661 r600_sampler_views_dirty(rctx, &dst->views);
662
663 if (dirty_sampler_states_mask) {
664 dst->states.dirty_mask |= dirty_sampler_states_mask;
665 r600_sampler_states_dirty(rctx, &dst->states);
666 }
667 }
668
669 static void r600_set_viewport_states(struct pipe_context *ctx,
670 unsigned start_slot,
671 unsigned num_viewports,
672 const struct pipe_viewport_state *state)
673 {
674 struct r600_context *rctx = (struct r600_context *)ctx;
675 int i;
676
677 for (i = start_slot; i < start_slot + num_viewports; i++) {
678 rctx->viewport[i].state = state[i - start_slot];
679 r600_mark_atom_dirty(rctx, &rctx->viewport[i].atom);
680 }
681 }
682
683 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
684 {
685 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
686 struct r600_viewport_state *rstate = (struct r600_viewport_state *)atom;
687 struct pipe_viewport_state *state = &rstate->state;
688 int offset = rstate->idx * 6 * 4;
689
690 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
691 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
692 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
693 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
694 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
695 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
696 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
697 }
698
699 /* Compute the key for the hw shader variant */
700 static inline struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
701 struct r600_pipe_shader_selector * sel)
702 {
703 struct r600_context *rctx = (struct r600_context *)ctx;
704 struct r600_shader_key key;
705 memset(&key, 0, sizeof(key));
706
707 if (sel->type == PIPE_SHADER_FRAGMENT) {
708 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
709 key.alpha_to_one = rctx->alpha_to_one &&
710 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
711 !rctx->framebuffer.cb0_is_integer;
712 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
713 /* Dual-source blending only makes sense with nr_cbufs == 1. */
714 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
715 key.nr_cbufs = 2;
716 } else if (sel->type == PIPE_SHADER_VERTEX) {
717 key.vs_as_es = (rctx->gs_shader != NULL);
718 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
719 key.vs_as_gs_a = true;
720 key.vs_prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
721 }
722 }
723 return key;
724 }
725
726 /* Select the hw shader variant depending on the current state.
727 * (*dirty) is set to 1 if current variant was changed */
728 static int r600_shader_select(struct pipe_context *ctx,
729 struct r600_pipe_shader_selector* sel,
730 bool *dirty)
731 {
732 struct r600_shader_key key;
733 struct r600_pipe_shader * shader = NULL;
734 int r;
735
736 memset(&key, 0, sizeof(key));
737 key = r600_shader_selector_key(ctx, sel);
738
739 /* Check if we don't need to change anything.
740 * This path is also used for most shaders that don't need multiple
741 * variants, it will cost just a computation of the key and this
742 * test. */
743 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
744 return 0;
745 }
746
747 /* lookup if we have other variants in the list */
748 if (sel->num_shaders > 1) {
749 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
750
751 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
752 p = c;
753 c = c->next_variant;
754 }
755
756 if (c) {
757 p->next_variant = c->next_variant;
758 shader = c;
759 }
760 }
761
762 if (unlikely(!shader)) {
763 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
764 shader->selector = sel;
765
766 r = r600_pipe_shader_create(ctx, shader, key);
767 if (unlikely(r)) {
768 R600_ERR("Failed to build shader variant (type=%u) %d\n",
769 sel->type, r);
770 sel->current = NULL;
771 FREE(shader);
772 return r;
773 }
774
775 /* We don't know the value of nr_ps_max_color_exports until we built
776 * at least one variant, so we may need to recompute the key after
777 * building first variant. */
778 if (sel->type == PIPE_SHADER_FRAGMENT &&
779 sel->num_shaders == 0) {
780 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
781 key = r600_shader_selector_key(ctx, sel);
782 }
783
784 memcpy(&shader->key, &key, sizeof(key));
785 sel->num_shaders++;
786 }
787
788 if (dirty)
789 *dirty = true;
790
791 shader->next_variant = sel->current;
792 sel->current = shader;
793
794 return 0;
795 }
796
797 static void *r600_create_shader_state(struct pipe_context *ctx,
798 const struct pipe_shader_state *state,
799 unsigned pipe_shader_type)
800 {
801 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
802
803 sel->type = pipe_shader_type;
804 sel->tokens = tgsi_dup_tokens(state->tokens);
805 sel->so = state->stream_output;
806 return sel;
807 }
808
809 static void *r600_create_ps_state(struct pipe_context *ctx,
810 const struct pipe_shader_state *state)
811 {
812 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
813 }
814
815 static void *r600_create_vs_state(struct pipe_context *ctx,
816 const struct pipe_shader_state *state)
817 {
818 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
819 }
820
821 static void *r600_create_gs_state(struct pipe_context *ctx,
822 const struct pipe_shader_state *state)
823 {
824 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
825 }
826
827 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
828 {
829 struct r600_context *rctx = (struct r600_context *)ctx;
830
831 if (!state)
832 state = rctx->dummy_pixel_shader;
833
834 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
835 }
836
837 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
838 {
839 struct r600_context *rctx = (struct r600_context *)ctx;
840
841 if (!state)
842 return;
843
844 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
845 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
846 }
847
848 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
849 {
850 struct r600_context *rctx = (struct r600_context *)ctx;
851
852 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
853
854 if (!state)
855 return;
856 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
857 }
858
859 static void r600_delete_shader_selector(struct pipe_context *ctx,
860 struct r600_pipe_shader_selector *sel)
861 {
862 struct r600_pipe_shader *p = sel->current, *c;
863 while (p) {
864 c = p->next_variant;
865 r600_pipe_shader_destroy(ctx, p);
866 free(p);
867 p = c;
868 }
869
870 free(sel->tokens);
871 free(sel);
872 }
873
874
875 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
876 {
877 struct r600_context *rctx = (struct r600_context *)ctx;
878 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
879
880 if (rctx->ps_shader == sel) {
881 rctx->ps_shader = NULL;
882 }
883
884 r600_delete_shader_selector(ctx, sel);
885 }
886
887 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
888 {
889 struct r600_context *rctx = (struct r600_context *)ctx;
890 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
891
892 if (rctx->vs_shader == sel) {
893 rctx->vs_shader = NULL;
894 }
895
896 r600_delete_shader_selector(ctx, sel);
897 }
898
899
900 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
901 {
902 struct r600_context *rctx = (struct r600_context *)ctx;
903 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
904
905 if (rctx->gs_shader == sel) {
906 rctx->gs_shader = NULL;
907 }
908
909 r600_delete_shader_selector(ctx, sel);
910 }
911
912
913 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
914 {
915 if (state->dirty_mask) {
916 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
917 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
918 : util_bitcount(state->dirty_mask)*19;
919 r600_mark_atom_dirty(rctx, &state->atom);
920 }
921 }
922
923 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
924 struct pipe_constant_buffer *input)
925 {
926 struct r600_context *rctx = (struct r600_context *)ctx;
927 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
928 struct pipe_constant_buffer *cb;
929 const uint8_t *ptr;
930
931 /* Note that the state tracker can unbind constant buffers by
932 * passing NULL here.
933 */
934 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
935 state->enabled_mask &= ~(1 << index);
936 state->dirty_mask &= ~(1 << index);
937 pipe_resource_reference(&state->cb[index].buffer, NULL);
938 return;
939 }
940
941 cb = &state->cb[index];
942 cb->buffer_size = input->buffer_size;
943
944 ptr = input->user_buffer;
945
946 if (ptr) {
947 /* Upload the user buffer. */
948 if (R600_BIG_ENDIAN) {
949 uint32_t *tmpPtr;
950 unsigned i, size = input->buffer_size;
951
952 if (!(tmpPtr = malloc(size))) {
953 R600_ERR("Failed to allocate BE swap buffer.\n");
954 return;
955 }
956
957 for (i = 0; i < size / 4; ++i) {
958 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
959 }
960
961 u_upload_data(rctx->b.uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
962 free(tmpPtr);
963 } else {
964 u_upload_data(rctx->b.uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
965 }
966 /* account it in gtt */
967 rctx->b.gtt += input->buffer_size;
968 } else {
969 /* Setup the hw buffer. */
970 cb->buffer_offset = input->buffer_offset;
971 pipe_resource_reference(&cb->buffer, input->buffer);
972 r600_context_add_resource_size(ctx, input->buffer);
973 }
974
975 state->enabled_mask |= 1 << index;
976 state->dirty_mask |= 1 << index;
977 r600_constant_buffers_dirty(rctx, state);
978 }
979
980 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
981 {
982 struct r600_context *rctx = (struct r600_context*)pipe;
983
984 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
985 return;
986
987 rctx->sample_mask.sample_mask = sample_mask;
988 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
989 }
990
991 /*
992 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
993 * doesn't require full swizzles it does need masking and setting alpha
994 * to one, so we setup a set of 5 constants with the masks + alpha value
995 * then in the shader, we AND the 4 components with 0xffffffff or 0,
996 * then OR the alpha with the value given here.
997 * We use a 6th constant to store the txq buffer size in
998 * we use 7th slot for number of cube layers in a cube map array.
999 */
1000 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1001 {
1002 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1003 int bits;
1004 uint32_t array_size;
1005 struct pipe_constant_buffer cb;
1006 int i, j;
1007
1008 if (!samplers->views.dirty_buffer_constants)
1009 return;
1010
1011 samplers->views.dirty_buffer_constants = FALSE;
1012
1013 bits = util_last_bit(samplers->views.enabled_mask);
1014 array_size = bits * 8 * sizeof(uint32_t) * 4;
1015 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1016 memset(samplers->buffer_constants, 0, array_size);
1017 for (i = 0; i < bits; i++) {
1018 if (samplers->views.enabled_mask & (1 << i)) {
1019 int offset = i * 8;
1020 const struct util_format_description *desc;
1021 desc = util_format_description(samplers->views.views[i]->base.format);
1022
1023 for (j = 0; j < 4; j++)
1024 if (j < desc->nr_channels)
1025 samplers->buffer_constants[offset+j] = 0xffffffff;
1026 else
1027 samplers->buffer_constants[offset+j] = 0x0;
1028 if (desc->nr_channels < 4) {
1029 if (desc->channel[0].pure_integer)
1030 samplers->buffer_constants[offset+4] = 1;
1031 else
1032 samplers->buffer_constants[offset+4] = fui(1.0);
1033 } else
1034 samplers->buffer_constants[offset + 4] = 0;
1035
1036 samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1037 samplers->buffer_constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1038 }
1039 }
1040
1041 cb.buffer = NULL;
1042 cb.user_buffer = samplers->buffer_constants;
1043 cb.buffer_offset = 0;
1044 cb.buffer_size = array_size;
1045 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1046 pipe_resource_reference(&cb.buffer, NULL);
1047 }
1048
1049 /* On evergreen we store two values
1050 * 1. buffer size for TXQ
1051 * 2. number of cube layers in a cube map array.
1052 */
1053 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1054 {
1055 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1056 int bits;
1057 uint32_t array_size;
1058 struct pipe_constant_buffer cb;
1059 int i;
1060
1061 if (!samplers->views.dirty_buffer_constants)
1062 return;
1063
1064 samplers->views.dirty_buffer_constants = FALSE;
1065
1066 bits = util_last_bit(samplers->views.enabled_mask);
1067 array_size = bits * 2 * sizeof(uint32_t) * 4;
1068 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1069 memset(samplers->buffer_constants, 0, array_size);
1070 for (i = 0; i < bits; i++) {
1071 if (samplers->views.enabled_mask & (1 << i)) {
1072 uint32_t offset = i * 2;
1073 samplers->buffer_constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1074 samplers->buffer_constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
1075 }
1076 }
1077
1078 cb.buffer = NULL;
1079 cb.user_buffer = samplers->buffer_constants;
1080 cb.buffer_offset = 0;
1081 cb.buffer_size = array_size;
1082 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1083 pipe_resource_reference(&cb.buffer, NULL);
1084 }
1085
1086 /* set sample xy locations as array of fragment shader constants */
1087 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1088 {
1089 struct pipe_constant_buffer constbuf = {0};
1090 float values[4*16] = {0.0f};
1091 int i;
1092 struct pipe_context *ctx = &rctx->b.b;
1093
1094 assert(rctx->framebuffer.nr_samples <= Elements(values)/4);
1095 for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
1096 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &values[4*i]);
1097 /* Also fill in center-zeroed positions used for interpolateAtSample */
1098 values[4*i + 2] = values[4*i + 0] - 0.5f;
1099 values[4*i + 3] = values[4*i + 1] - 0.5f;
1100 }
1101
1102 constbuf.user_buffer = values;
1103 constbuf.buffer_size = rctx->framebuffer.nr_samples * 4 * 4;
1104 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
1105 R600_SAMPLE_POSITIONS_CONST_BUFFER, &constbuf);
1106 pipe_resource_reference(&constbuf.buffer, NULL);
1107 }
1108
1109 static void update_shader_atom(struct pipe_context *ctx,
1110 struct r600_shader_state *state,
1111 struct r600_pipe_shader *shader)
1112 {
1113 struct r600_context *rctx = (struct r600_context *)ctx;
1114
1115 state->shader = shader;
1116 if (shader) {
1117 state->atom.num_dw = shader->command_buffer.num_dw;
1118 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1119 } else {
1120 state->atom.num_dw = 0;
1121 }
1122 r600_mark_atom_dirty(rctx, &state->atom);
1123 }
1124
1125 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1126 {
1127 if (rctx->shader_stages.geom_enable != enable) {
1128 rctx->shader_stages.geom_enable = enable;
1129 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1130 }
1131
1132 if (rctx->gs_rings.enable != enable) {
1133 rctx->gs_rings.enable = enable;
1134 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1135
1136 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1137 unsigned size = 0x1C000;
1138 rctx->gs_rings.esgs_ring.buffer =
1139 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1140 PIPE_USAGE_DEFAULT, size);
1141 rctx->gs_rings.esgs_ring.buffer_size = size;
1142
1143 size = 0x4000000;
1144
1145 rctx->gs_rings.gsvs_ring.buffer =
1146 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1147 PIPE_USAGE_DEFAULT, size);
1148 rctx->gs_rings.gsvs_ring.buffer_size = size;
1149 }
1150
1151 if (enable) {
1152 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1153 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
1154 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1155 R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
1156 } else {
1157 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1158 R600_GS_RING_CONST_BUFFER, NULL);
1159 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1160 R600_GS_RING_CONST_BUFFER, NULL);
1161 }
1162 }
1163 }
1164
1165 static bool r600_update_derived_state(struct r600_context *rctx)
1166 {
1167 struct pipe_context * ctx = (struct pipe_context*)rctx;
1168 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1169 bool blend_disable;
1170 bool need_buf_const;
1171 if (!rctx->blitter->running) {
1172 unsigned i;
1173
1174 /* Decompress textures if needed. */
1175 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1176 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1177 if (views->compressed_depthtex_mask) {
1178 r600_decompress_depth_textures(rctx, views);
1179 }
1180 if (views->compressed_colortex_mask) {
1181 r600_decompress_color_textures(rctx, views);
1182 }
1183 }
1184 }
1185
1186 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1187 if (unlikely(!rctx->ps_shader->current))
1188 return false;
1189
1190 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1191
1192 if (rctx->gs_shader) {
1193 r600_shader_select(ctx, rctx->gs_shader, &gs_dirty);
1194 if (unlikely(!rctx->gs_shader->current))
1195 return false;
1196
1197 if (!rctx->shader_stages.geom_enable) {
1198 rctx->shader_stages.geom_enable = true;
1199 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1200 }
1201
1202 /* gs_shader provides GS and VS (copy shader) */
1203 if (unlikely(rctx->geometry_shader.shader != rctx->gs_shader->current)) {
1204 update_shader_atom(ctx, &rctx->geometry_shader, rctx->gs_shader->current);
1205 update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
1206 /* Update clip misc state. */
1207 if (rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1208 rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1209 rctx->clip_misc_state.clip_disable != rctx->gs_shader->current->shader.vs_position_window_space) {
1210 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl;
1211 rctx->clip_misc_state.clip_dist_write = rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write;
1212 rctx->clip_misc_state.clip_disable = rctx->gs_shader->current->shader.vs_position_window_space;
1213 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1214 }
1215 rctx->b.streamout.enabled_stream_buffers_mask = rctx->gs_shader->current->gs_copy_shader->enabled_stream_buffers_mask;
1216 }
1217
1218 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1219 if (unlikely(!rctx->vs_shader->current))
1220 return false;
1221
1222 /* vs_shader is used as ES */
1223 if (unlikely(vs_dirty || rctx->export_shader.shader != rctx->vs_shader->current)) {
1224 update_shader_atom(ctx, &rctx->export_shader, rctx->vs_shader->current);
1225 }
1226 } else {
1227 if (unlikely(rctx->geometry_shader.shader)) {
1228 update_shader_atom(ctx, &rctx->geometry_shader, NULL);
1229 update_shader_atom(ctx, &rctx->export_shader, NULL);
1230 rctx->shader_stages.geom_enable = false;
1231 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1232 }
1233
1234 r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
1235 if (unlikely(!rctx->vs_shader->current))
1236 return false;
1237
1238 if (unlikely(vs_dirty || rctx->vertex_shader.shader != rctx->vs_shader->current)) {
1239 update_shader_atom(ctx, &rctx->vertex_shader, rctx->vs_shader->current);
1240
1241 /* Update clip misc state. */
1242 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1243 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1244 rctx->clip_misc_state.clip_disable != rctx->vs_shader->current->shader.vs_position_window_space) {
1245 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
1246 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
1247 rctx->clip_misc_state.clip_disable = rctx->vs_shader->current->shader.vs_position_window_space;
1248 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1249 }
1250 rctx->b.streamout.enabled_stream_buffers_mask = rctx->vs_shader->current->enabled_stream_buffers_mask;
1251 }
1252 }
1253
1254
1255 if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader->current ||
1256 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1257 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1258
1259 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
1260 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1261 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1262 }
1263
1264 if (rctx->b.chip_class <= R700) {
1265 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1266
1267 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1268 rctx->cb_misc_state.multiwrite = multiwrite;
1269 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1270 }
1271 }
1272
1273 if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
1274 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1275 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
1276
1277 if (rctx->b.chip_class >= EVERGREEN)
1278 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1279 else
1280 r600_update_ps_state(ctx, rctx->ps_shader->current);
1281 }
1282
1283 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1284 update_shader_atom(ctx, &rctx->pixel_shader, rctx->ps_shader->current);
1285 }
1286
1287 if (rctx->b.chip_class >= EVERGREEN) {
1288 evergreen_update_db_shader_control(rctx);
1289 } else {
1290 r600_update_db_shader_control(rctx);
1291 }
1292
1293 /* on R600 we stuff masks + txq info into one constant buffer */
1294 /* on evergreen we only need a txq info one */
1295 if (rctx->ps_shader) {
1296 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
1297 if (need_buf_const) {
1298 if (rctx->b.chip_class < EVERGREEN)
1299 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1300 else
1301 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1302 }
1303 }
1304
1305 if (rctx->vs_shader) {
1306 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
1307 if (need_buf_const) {
1308 if (rctx->b.chip_class < EVERGREEN)
1309 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1310 else
1311 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1312 }
1313 }
1314
1315 if (rctx->gs_shader) {
1316 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
1317 if (need_buf_const) {
1318 if (rctx->b.chip_class < EVERGREEN)
1319 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1320 else
1321 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
1322 }
1323 }
1324
1325 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1326 if (!r600_adjust_gprs(rctx)) {
1327 /* discard rendering */
1328 return false;
1329 }
1330 }
1331
1332 blend_disable = (rctx->dual_src_blend &&
1333 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1334
1335 if (blend_disable != rctx->force_blend_disable) {
1336 rctx->force_blend_disable = blend_disable;
1337 r600_bind_blend_state_internal(rctx,
1338 rctx->blend_state.cso,
1339 blend_disable);
1340 }
1341
1342 return true;
1343 }
1344
1345 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1346 {
1347 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1348 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1349
1350 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1351 state->pa_cl_clip_cntl |
1352 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
1353 S_028810_CLIP_DISABLE(state->clip_disable));
1354 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1355 state->pa_cl_vs_out_cntl |
1356 (state->clip_plane_enable & state->clip_dist_write));
1357 }
1358
1359 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1360 {
1361 struct r600_context *rctx = (struct r600_context *)ctx;
1362 struct pipe_draw_info info = *dinfo;
1363 struct pipe_index_buffer ib = {};
1364 unsigned i;
1365 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1366
1367 if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
1368 return;
1369 }
1370
1371 if (!rctx->vs_shader || !rctx->ps_shader) {
1372 assert(0);
1373 return;
1374 }
1375
1376 /* make sure that the gfx ring is only one active */
1377 if (rctx->b.rings.dma.cs && rctx->b.rings.dma.cs->cdw) {
1378 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1379 }
1380
1381 if (!r600_update_derived_state(rctx)) {
1382 /* useless to render because current rendering command
1383 * can't be achieved
1384 */
1385 return;
1386 }
1387
1388 if (info.indexed) {
1389 /* Initialize the index buffer struct. */
1390 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1391 ib.user_buffer = rctx->index_buffer.user_buffer;
1392 ib.index_size = rctx->index_buffer.index_size;
1393 ib.offset = rctx->index_buffer.offset;
1394 if (!info.indirect) {
1395 ib.offset += info.start * ib.index_size;
1396 }
1397
1398 /* Translate 8-bit indices to 16-bit. */
1399 if (unlikely(ib.index_size == 1)) {
1400 struct pipe_resource *out_buffer = NULL;
1401 unsigned out_offset;
1402 void *ptr;
1403 unsigned start, count;
1404
1405 if (likely(!info.indirect)) {
1406 start = 0;
1407 count = info.count;
1408 }
1409 else {
1410 /* Have to get start/count from indirect buffer, slow path ahead... */
1411 struct r600_resource *indirect_resource = (struct r600_resource *)info.indirect;
1412 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
1413 PIPE_TRANSFER_READ);
1414 if (data) {
1415 data += info.indirect_offset / sizeof(unsigned);
1416 start = data[2] * ib.index_size;
1417 count = data[0];
1418 }
1419 else {
1420 start = 0;
1421 count = 0;
1422 }
1423 }
1424
1425 u_upload_alloc(rctx->b.uploader, start, count * 2,
1426 &out_offset, &out_buffer, &ptr);
1427
1428 util_shorten_ubyte_elts_to_userptr(
1429 &rctx->b.b, &ib, 0, ib.offset + start, count, ptr);
1430
1431 pipe_resource_reference(&ib.buffer, NULL);
1432 ib.user_buffer = NULL;
1433 ib.buffer = out_buffer;
1434 ib.offset = out_offset;
1435 ib.index_size = 2;
1436 }
1437
1438 /* Upload the index buffer.
1439 * The upload is skipped for small index counts on little-endian machines
1440 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1441 * Indirect draws never use immediate indices.
1442 * Note: Instanced rendering in combination with immediate indices hangs. */
1443 if (ib.user_buffer && (R600_BIG_ENDIAN || info.indirect ||
1444 info.instance_count > 1 ||
1445 info.count*ib.index_size > 20)) {
1446 u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size,
1447 ib.user_buffer, &ib.offset, &ib.buffer);
1448 ib.user_buffer = NULL;
1449 }
1450 } else {
1451 info.index_bias = info.start;
1452 }
1453
1454 /* Set the index offset and primitive restart. */
1455 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1456 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1457 rctx->vgt_state.vgt_indx_offset != info.index_bias ||
1458 (rctx->vgt_state.last_draw_was_indirect && !info.indirect)) {
1459 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1460 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1461 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1462 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
1463 }
1464
1465 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1466 if (rctx->b.chip_class == R600) {
1467 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1468 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1469 }
1470
1471 /* Emit states. */
1472 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1473 r600_flush_emit(rctx);
1474
1475 i = r600_next_dirty_atom(rctx, 0);
1476 while (i < R600_NUM_ATOMS) {
1477 r600_emit_atom(rctx, rctx->atoms[i]);
1478 i = r600_next_dirty_atom(rctx, i + 1);
1479 }
1480
1481 if (rctx->b.chip_class == CAYMAN) {
1482 /* Copied from radeonsi. */
1483 unsigned primgroup_size = 128; /* recommended without a GS */
1484 bool ia_switch_on_eop = false;
1485 bool partial_vs_wave = false;
1486
1487 if (rctx->gs_shader)
1488 primgroup_size = 64; /* recommended with a GS */
1489
1490 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
1491 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
1492 ia_switch_on_eop = true;
1493 }
1494
1495 if (rctx->b.streamout.streamout_enabled ||
1496 rctx->b.streamout.prims_gen_query_enabled)
1497 partial_vs_wave = true;
1498
1499 r600_write_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
1500 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
1501 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
1502 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
1503 }
1504
1505 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1506 * even though it should have no effect on those. */
1507 if (rctx->b.chip_class == R600 && rctx->rasterizer) {
1508 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
1509 unsigned prim = info.mode;
1510
1511 if (rctx->gs_shader) {
1512 prim = rctx->gs_shader->current->shader.gs_output_prim;
1513 }
1514 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
1515
1516 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
1517 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
1518 info.mode == R600_PRIM_RECTANGLE_LIST) {
1519 su_sc_mode_cntl &= C_028814_CULL_FRONT;
1520 }
1521 r600_write_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
1522 }
1523
1524 /* Update start instance. */
1525 if (!info.indirect && rctx->last_start_instance != info.start_instance) {
1526 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1527 rctx->last_start_instance = info.start_instance;
1528 }
1529
1530 /* Update the primitive type. */
1531 if (rctx->last_primitive_type != info.mode) {
1532 unsigned ls_mask = 0;
1533
1534 if (info.mode == PIPE_PRIM_LINES)
1535 ls_mask = 1;
1536 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1537 info.mode == PIPE_PRIM_LINE_LOOP)
1538 ls_mask = 2;
1539
1540 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1541 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1542 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1543 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1544 r600_conv_pipe_prim(info.mode));
1545
1546 rctx->last_primitive_type = info.mode;
1547 }
1548
1549 /* Draw packets. */
1550 if (!info.indirect) {
1551 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->b.predicate_drawing);
1552 cs->buf[cs->cdw++] = info.instance_count;
1553 }
1554
1555 if (unlikely(info.indirect)) {
1556 uint64_t va = r600_resource(info.indirect)->gpu_address;
1557 assert(rctx->b.chip_class >= EVERGREEN);
1558
1559 // Invalidate so non-indirect draw calls reset this state
1560 rctx->vgt_state.last_draw_was_indirect = true;
1561 rctx->last_start_instance = -1;
1562
1563 cs->buf[cs->cdw++] = PKT3(EG_PKT3_SET_BASE, 2, rctx->b.predicate_drawing);
1564 cs->buf[cs->cdw++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE;
1565 cs->buf[cs->cdw++] = va;
1566 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1567
1568 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1569 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1570 (struct r600_resource*)info.indirect,
1571 RADEON_USAGE_READ, RADEON_PRIO_MIN);
1572 }
1573
1574 if (info.indexed) {
1575 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->b.predicate_drawing);
1576 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1577 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1578 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1579
1580 if (ib.user_buffer) {
1581 unsigned size_bytes = info.count*ib.index_size;
1582 unsigned size_dw = align(size_bytes, 4) / 4;
1583 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->b.predicate_drawing);
1584 cs->buf[cs->cdw++] = info.count;
1585 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1586 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1587 cs->cdw += size_dw;
1588 } else {
1589 uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
1590
1591 if (likely(!info.indirect)) {
1592 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
1593 cs->buf[cs->cdw++] = va;
1594 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1595 cs->buf[cs->cdw++] = info.count;
1596 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1597 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1598 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1599 (struct r600_resource*)ib.buffer,
1600 RADEON_USAGE_READ, RADEON_PRIO_MIN);
1601 }
1602 else {
1603 uint32_t max_size = (ib.buffer->width0 - ib.offset) / ib.index_size;
1604
1605 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BASE, 1, rctx->b.predicate_drawing);
1606 cs->buf[cs->cdw++] = va;
1607 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1608
1609 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
1610 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1611 (struct r600_resource*)ib.buffer,
1612 RADEON_USAGE_READ, RADEON_PRIO_MIN);
1613
1614 cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, rctx->b.predicate_drawing);
1615 cs->buf[cs->cdw++] = max_size;
1616
1617 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, rctx->b.predicate_drawing);
1618 cs->buf[cs->cdw++] = info.indirect_offset;
1619 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1620 }
1621 }
1622 } else {
1623 if (unlikely(info.count_from_stream_output)) {
1624 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1625 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
1626
1627 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1628
1629 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1630 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1631 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1632 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1633 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1634 cs->buf[cs->cdw++] = 0; /* unused */
1635
1636 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1637 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
1638 t->buf_filled_size, RADEON_USAGE_READ,
1639 RADEON_PRIO_MIN);
1640 }
1641
1642 if (likely(!info.indirect)) {
1643 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
1644 cs->buf[cs->cdw++] = info.count;
1645 }
1646 else {
1647 cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDIRECT, 1, rctx->b.predicate_drawing);
1648 cs->buf[cs->cdw++] = info.indirect_offset;
1649 }
1650 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1651 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1652 }
1653
1654 if (rctx->screen->b.trace_bo) {
1655 r600_trace_emit(rctx);
1656 }
1657
1658 /* Set the depth buffer as dirty. */
1659 if (rctx->framebuffer.state.zsbuf) {
1660 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1661 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1662
1663 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1664 }
1665 if (rctx->framebuffer.compressed_cb_mask) {
1666 struct pipe_surface *surf;
1667 struct r600_texture *rtex;
1668 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1669
1670 do {
1671 unsigned i = u_bit_scan(&mask);
1672 surf = rctx->framebuffer.state.cbufs[i];
1673 rtex = (struct r600_texture*)surf->texture;
1674
1675 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1676
1677 } while (mask);
1678 }
1679
1680 pipe_resource_reference(&ib.buffer, NULL);
1681 rctx->b.num_draw_calls++;
1682 }
1683
1684 uint32_t r600_translate_stencil_op(int s_op)
1685 {
1686 switch (s_op) {
1687 case PIPE_STENCIL_OP_KEEP:
1688 return V_028800_STENCIL_KEEP;
1689 case PIPE_STENCIL_OP_ZERO:
1690 return V_028800_STENCIL_ZERO;
1691 case PIPE_STENCIL_OP_REPLACE:
1692 return V_028800_STENCIL_REPLACE;
1693 case PIPE_STENCIL_OP_INCR:
1694 return V_028800_STENCIL_INCR;
1695 case PIPE_STENCIL_OP_DECR:
1696 return V_028800_STENCIL_DECR;
1697 case PIPE_STENCIL_OP_INCR_WRAP:
1698 return V_028800_STENCIL_INCR_WRAP;
1699 case PIPE_STENCIL_OP_DECR_WRAP:
1700 return V_028800_STENCIL_DECR_WRAP;
1701 case PIPE_STENCIL_OP_INVERT:
1702 return V_028800_STENCIL_INVERT;
1703 default:
1704 R600_ERR("Unknown stencil op %d", s_op);
1705 assert(0);
1706 break;
1707 }
1708 return 0;
1709 }
1710
1711 uint32_t r600_translate_fill(uint32_t func)
1712 {
1713 switch(func) {
1714 case PIPE_POLYGON_MODE_FILL:
1715 return 2;
1716 case PIPE_POLYGON_MODE_LINE:
1717 return 1;
1718 case PIPE_POLYGON_MODE_POINT:
1719 return 0;
1720 default:
1721 assert(0);
1722 return 0;
1723 }
1724 }
1725
1726 unsigned r600_tex_wrap(unsigned wrap)
1727 {
1728 switch (wrap) {
1729 default:
1730 case PIPE_TEX_WRAP_REPEAT:
1731 return V_03C000_SQ_TEX_WRAP;
1732 case PIPE_TEX_WRAP_CLAMP:
1733 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1734 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1735 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1736 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1737 return V_03C000_SQ_TEX_CLAMP_BORDER;
1738 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1739 return V_03C000_SQ_TEX_MIRROR;
1740 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1741 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1742 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1743 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1744 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1745 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1746 }
1747 }
1748
1749 unsigned r600_tex_filter(unsigned filter)
1750 {
1751 switch (filter) {
1752 default:
1753 case PIPE_TEX_FILTER_NEAREST:
1754 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1755 case PIPE_TEX_FILTER_LINEAR:
1756 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1757 }
1758 }
1759
1760 unsigned r600_tex_mipfilter(unsigned filter)
1761 {
1762 switch (filter) {
1763 case PIPE_TEX_MIPFILTER_NEAREST:
1764 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1765 case PIPE_TEX_MIPFILTER_LINEAR:
1766 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1767 default:
1768 case PIPE_TEX_MIPFILTER_NONE:
1769 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1770 }
1771 }
1772
1773 unsigned r600_tex_compare(unsigned compare)
1774 {
1775 switch (compare) {
1776 default:
1777 case PIPE_FUNC_NEVER:
1778 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1779 case PIPE_FUNC_LESS:
1780 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1781 case PIPE_FUNC_EQUAL:
1782 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1783 case PIPE_FUNC_LEQUAL:
1784 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1785 case PIPE_FUNC_GREATER:
1786 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1787 case PIPE_FUNC_NOTEQUAL:
1788 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1789 case PIPE_FUNC_GEQUAL:
1790 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1791 case PIPE_FUNC_ALWAYS:
1792 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1793 }
1794 }
1795
1796 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1797 {
1798 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1799 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1800 (linear_filter &&
1801 (wrap == PIPE_TEX_WRAP_CLAMP ||
1802 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1803 }
1804
1805 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1806 {
1807 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1808 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1809
1810 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1811 state->border_color.ui[2] || state->border_color.ui[3]) &&
1812 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1813 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1814 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1815 }
1816
1817 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1818 {
1819
1820 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1821 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
1822
1823 if (!shader)
1824 return;
1825
1826 r600_emit_command_buffer(cs, &shader->command_buffer);
1827 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1828 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo,
1829 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1830 }
1831
1832 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1833 const unsigned char *swizzle_view,
1834 boolean vtx)
1835 {
1836 unsigned i;
1837 unsigned char swizzle[4];
1838 unsigned result = 0;
1839 const uint32_t tex_swizzle_shift[4] = {
1840 16, 19, 22, 25,
1841 };
1842 const uint32_t vtx_swizzle_shift[4] = {
1843 3, 6, 9, 12,
1844 };
1845 const uint32_t swizzle_bit[4] = {
1846 0, 1, 2, 3,
1847 };
1848 const uint32_t *swizzle_shift = tex_swizzle_shift;
1849
1850 if (vtx)
1851 swizzle_shift = vtx_swizzle_shift;
1852
1853 if (swizzle_view) {
1854 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1855 } else {
1856 memcpy(swizzle, swizzle_format, 4);
1857 }
1858
1859 /* Get swizzle. */
1860 for (i = 0; i < 4; i++) {
1861 switch (swizzle[i]) {
1862 case UTIL_FORMAT_SWIZZLE_Y:
1863 result |= swizzle_bit[1] << swizzle_shift[i];
1864 break;
1865 case UTIL_FORMAT_SWIZZLE_Z:
1866 result |= swizzle_bit[2] << swizzle_shift[i];
1867 break;
1868 case UTIL_FORMAT_SWIZZLE_W:
1869 result |= swizzle_bit[3] << swizzle_shift[i];
1870 break;
1871 case UTIL_FORMAT_SWIZZLE_0:
1872 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1873 break;
1874 case UTIL_FORMAT_SWIZZLE_1:
1875 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1876 break;
1877 default: /* UTIL_FORMAT_SWIZZLE_X */
1878 result |= swizzle_bit[0] << swizzle_shift[i];
1879 }
1880 }
1881 return result;
1882 }
1883
1884 /* texture format translate */
1885 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1886 enum pipe_format format,
1887 const unsigned char *swizzle_view,
1888 uint32_t *word4_p, uint32_t *yuv_format_p)
1889 {
1890 struct r600_screen *rscreen = (struct r600_screen *)screen;
1891 uint32_t result = 0, word4 = 0, yuv_format = 0;
1892 const struct util_format_description *desc;
1893 boolean uniform = TRUE;
1894 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1895 bool is_srgb_valid = FALSE;
1896 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1897 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1898
1899 int i;
1900 const uint32_t sign_bit[4] = {
1901 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1902 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1903 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1904 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1905 };
1906 desc = util_format_description(format);
1907
1908 /* Depth and stencil swizzling is handled separately. */
1909 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1910 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1911 }
1912
1913 /* Colorspace (return non-RGB formats directly). */
1914 switch (desc->colorspace) {
1915 /* Depth stencil formats */
1916 case UTIL_FORMAT_COLORSPACE_ZS:
1917 switch (format) {
1918 /* Depth sampler formats. */
1919 case PIPE_FORMAT_Z16_UNORM:
1920 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1921 result = FMT_16;
1922 goto out_word4;
1923 case PIPE_FORMAT_Z24X8_UNORM:
1924 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1925 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1926 result = FMT_8_24;
1927 goto out_word4;
1928 case PIPE_FORMAT_X8Z24_UNORM:
1929 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1930 if (rscreen->b.chip_class < EVERGREEN)
1931 goto out_unknown;
1932 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1933 result = FMT_24_8;
1934 goto out_word4;
1935 case PIPE_FORMAT_Z32_FLOAT:
1936 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1937 result = FMT_32_FLOAT;
1938 goto out_word4;
1939 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1940 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1941 result = FMT_X24_8_32_FLOAT;
1942 goto out_word4;
1943 /* Stencil sampler formats. */
1944 case PIPE_FORMAT_S8_UINT:
1945 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1946 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1947 result = FMT_8;
1948 goto out_word4;
1949 case PIPE_FORMAT_X24S8_UINT:
1950 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1951 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1952 result = FMT_8_24;
1953 goto out_word4;
1954 case PIPE_FORMAT_S8X24_UINT:
1955 if (rscreen->b.chip_class < EVERGREEN)
1956 goto out_unknown;
1957 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1958 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1959 result = FMT_24_8;
1960 goto out_word4;
1961 case PIPE_FORMAT_X32_S8X24_UINT:
1962 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1963 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1964 result = FMT_X24_8_32_FLOAT;
1965 goto out_word4;
1966 default:
1967 goto out_unknown;
1968 }
1969
1970 case UTIL_FORMAT_COLORSPACE_YUV:
1971 yuv_format |= (1 << 30);
1972 switch (format) {
1973 case PIPE_FORMAT_UYVY:
1974 case PIPE_FORMAT_YUYV:
1975 default:
1976 break;
1977 }
1978 goto out_unknown; /* XXX */
1979
1980 case UTIL_FORMAT_COLORSPACE_SRGB:
1981 word4 |= S_038010_FORCE_DEGAMMA(1);
1982 break;
1983
1984 default:
1985 break;
1986 }
1987
1988 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1989 if (!enable_s3tc)
1990 goto out_unknown;
1991
1992 switch (format) {
1993 case PIPE_FORMAT_RGTC1_SNORM:
1994 case PIPE_FORMAT_LATC1_SNORM:
1995 word4 |= sign_bit[0];
1996 case PIPE_FORMAT_RGTC1_UNORM:
1997 case PIPE_FORMAT_LATC1_UNORM:
1998 result = FMT_BC4;
1999 goto out_word4;
2000 case PIPE_FORMAT_RGTC2_SNORM:
2001 case PIPE_FORMAT_LATC2_SNORM:
2002 word4 |= sign_bit[0] | sign_bit[1];
2003 case PIPE_FORMAT_RGTC2_UNORM:
2004 case PIPE_FORMAT_LATC2_UNORM:
2005 result = FMT_BC5;
2006 goto out_word4;
2007 default:
2008 goto out_unknown;
2009 }
2010 }
2011
2012 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2013
2014 if (!enable_s3tc)
2015 goto out_unknown;
2016
2017 if (!util_format_s3tc_enabled) {
2018 goto out_unknown;
2019 }
2020
2021 switch (format) {
2022 case PIPE_FORMAT_DXT1_RGB:
2023 case PIPE_FORMAT_DXT1_RGBA:
2024 case PIPE_FORMAT_DXT1_SRGB:
2025 case PIPE_FORMAT_DXT1_SRGBA:
2026 result = FMT_BC1;
2027 is_srgb_valid = TRUE;
2028 goto out_word4;
2029 case PIPE_FORMAT_DXT3_RGBA:
2030 case PIPE_FORMAT_DXT3_SRGBA:
2031 result = FMT_BC2;
2032 is_srgb_valid = TRUE;
2033 goto out_word4;
2034 case PIPE_FORMAT_DXT5_RGBA:
2035 case PIPE_FORMAT_DXT5_SRGBA:
2036 result = FMT_BC3;
2037 is_srgb_valid = TRUE;
2038 goto out_word4;
2039 default:
2040 goto out_unknown;
2041 }
2042 }
2043
2044 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2045 if (!enable_s3tc)
2046 goto out_unknown;
2047
2048 if (rscreen->b.chip_class < EVERGREEN)
2049 goto out_unknown;
2050
2051 switch (format) {
2052 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2053 case PIPE_FORMAT_BPTC_SRGBA:
2054 result = FMT_BC7;
2055 is_srgb_valid = TRUE;
2056 goto out_word4;
2057 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2058 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2059 /* fall through */
2060 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2061 result = FMT_BC6;
2062 goto out_word4;
2063 default:
2064 goto out_unknown;
2065 }
2066 }
2067
2068 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2069 switch (format) {
2070 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2071 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2072 result = FMT_GB_GR;
2073 goto out_word4;
2074 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2075 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2076 result = FMT_BG_RG;
2077 goto out_word4;
2078 default:
2079 goto out_unknown;
2080 }
2081 }
2082
2083 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2084 result = FMT_5_9_9_9_SHAREDEXP;
2085 goto out_word4;
2086 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2087 result = FMT_10_11_11_FLOAT;
2088 goto out_word4;
2089 }
2090
2091
2092 for (i = 0; i < desc->nr_channels; i++) {
2093 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2094 word4 |= sign_bit[i];
2095 }
2096 }
2097
2098 /* R8G8Bx_SNORM - XXX CxV8U8 */
2099
2100 /* See whether the components are of the same size. */
2101 for (i = 1; i < desc->nr_channels; i++) {
2102 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2103 }
2104
2105 /* Non-uniform formats. */
2106 if (!uniform) {
2107 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2108 desc->channel[0].pure_integer)
2109 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2110 switch(desc->nr_channels) {
2111 case 3:
2112 if (desc->channel[0].size == 5 &&
2113 desc->channel[1].size == 6 &&
2114 desc->channel[2].size == 5) {
2115 result = FMT_5_6_5;
2116 goto out_word4;
2117 }
2118 goto out_unknown;
2119 case 4:
2120 if (desc->channel[0].size == 5 &&
2121 desc->channel[1].size == 5 &&
2122 desc->channel[2].size == 5 &&
2123 desc->channel[3].size == 1) {
2124 result = FMT_1_5_5_5;
2125 goto out_word4;
2126 }
2127 if (desc->channel[0].size == 10 &&
2128 desc->channel[1].size == 10 &&
2129 desc->channel[2].size == 10 &&
2130 desc->channel[3].size == 2) {
2131 result = FMT_2_10_10_10;
2132 goto out_word4;
2133 }
2134 goto out_unknown;
2135 }
2136 goto out_unknown;
2137 }
2138
2139 /* Find the first non-VOID channel. */
2140 for (i = 0; i < 4; i++) {
2141 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2142 break;
2143 }
2144 }
2145
2146 if (i == 4)
2147 goto out_unknown;
2148
2149 /* uniform formats */
2150 switch (desc->channel[i].type) {
2151 case UTIL_FORMAT_TYPE_UNSIGNED:
2152 case UTIL_FORMAT_TYPE_SIGNED:
2153 #if 0
2154 if (!desc->channel[i].normalized &&
2155 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
2156 goto out_unknown;
2157 }
2158 #endif
2159 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2160 desc->channel[i].pure_integer)
2161 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2162
2163 switch (desc->channel[i].size) {
2164 case 4:
2165 switch (desc->nr_channels) {
2166 case 2:
2167 result = FMT_4_4;
2168 goto out_word4;
2169 case 4:
2170 result = FMT_4_4_4_4;
2171 goto out_word4;
2172 }
2173 goto out_unknown;
2174 case 8:
2175 switch (desc->nr_channels) {
2176 case 1:
2177 result = FMT_8;
2178 goto out_word4;
2179 case 2:
2180 result = FMT_8_8;
2181 goto out_word4;
2182 case 4:
2183 result = FMT_8_8_8_8;
2184 is_srgb_valid = TRUE;
2185 goto out_word4;
2186 }
2187 goto out_unknown;
2188 case 16:
2189 switch (desc->nr_channels) {
2190 case 1:
2191 result = FMT_16;
2192 goto out_word4;
2193 case 2:
2194 result = FMT_16_16;
2195 goto out_word4;
2196 case 4:
2197 result = FMT_16_16_16_16;
2198 goto out_word4;
2199 }
2200 goto out_unknown;
2201 case 32:
2202 switch (desc->nr_channels) {
2203 case 1:
2204 result = FMT_32;
2205 goto out_word4;
2206 case 2:
2207 result = FMT_32_32;
2208 goto out_word4;
2209 case 4:
2210 result = FMT_32_32_32_32;
2211 goto out_word4;
2212 }
2213 }
2214 goto out_unknown;
2215
2216 case UTIL_FORMAT_TYPE_FLOAT:
2217 switch (desc->channel[i].size) {
2218 case 16:
2219 switch (desc->nr_channels) {
2220 case 1:
2221 result = FMT_16_FLOAT;
2222 goto out_word4;
2223 case 2:
2224 result = FMT_16_16_FLOAT;
2225 goto out_word4;
2226 case 4:
2227 result = FMT_16_16_16_16_FLOAT;
2228 goto out_word4;
2229 }
2230 goto out_unknown;
2231 case 32:
2232 switch (desc->nr_channels) {
2233 case 1:
2234 result = FMT_32_FLOAT;
2235 goto out_word4;
2236 case 2:
2237 result = FMT_32_32_FLOAT;
2238 goto out_word4;
2239 case 4:
2240 result = FMT_32_32_32_32_FLOAT;
2241 goto out_word4;
2242 }
2243 }
2244 goto out_unknown;
2245 }
2246
2247 out_word4:
2248
2249 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2250 return ~0;
2251 if (word4_p)
2252 *word4_p = word4;
2253 if (yuv_format_p)
2254 *yuv_format_p = yuv_format;
2255 return result;
2256 out_unknown:
2257 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2258 return ~0;
2259 }
2260
2261 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format)
2262 {
2263 const struct util_format_description *desc = util_format_description(format);
2264 int channel = util_format_get_first_non_void_channel(format);
2265 bool is_float;
2266
2267 #define HAS_SIZE(x,y,z,w) \
2268 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2269 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2270
2271 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
2272 return V_0280A0_COLOR_10_11_11_FLOAT;
2273
2274 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
2275 channel == -1)
2276 return ~0U;
2277
2278 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
2279
2280 switch (desc->nr_channels) {
2281 case 1:
2282 switch (desc->channel[0].size) {
2283 case 8:
2284 return V_0280A0_COLOR_8;
2285 case 16:
2286 if (is_float)
2287 return V_0280A0_COLOR_16_FLOAT;
2288 else
2289 return V_0280A0_COLOR_16;
2290 case 32:
2291 if (is_float)
2292 return V_0280A0_COLOR_32_FLOAT;
2293 else
2294 return V_0280A0_COLOR_32;
2295 }
2296 break;
2297 case 2:
2298 if (desc->channel[0].size == desc->channel[1].size) {
2299 switch (desc->channel[0].size) {
2300 case 4:
2301 if (chip <= R700)
2302 return V_0280A0_COLOR_4_4;
2303 else
2304 return ~0U; /* removed on Evergreen */
2305 case 8:
2306 return V_0280A0_COLOR_8_8;
2307 case 16:
2308 if (is_float)
2309 return V_0280A0_COLOR_16_16_FLOAT;
2310 else
2311 return V_0280A0_COLOR_16_16;
2312 case 32:
2313 if (is_float)
2314 return V_0280A0_COLOR_32_32_FLOAT;
2315 else
2316 return V_0280A0_COLOR_32_32;
2317 }
2318 } else if (HAS_SIZE(8,24,0,0)) {
2319 return V_0280A0_COLOR_24_8;
2320 } else if (HAS_SIZE(24,8,0,0)) {
2321 return V_0280A0_COLOR_8_24;
2322 }
2323 break;
2324 case 3:
2325 if (HAS_SIZE(5,6,5,0)) {
2326 return V_0280A0_COLOR_5_6_5;
2327 } else if (HAS_SIZE(32,8,24,0)) {
2328 return V_0280A0_COLOR_X24_8_32_FLOAT;
2329 }
2330 break;
2331 case 4:
2332 if (desc->channel[0].size == desc->channel[1].size &&
2333 desc->channel[0].size == desc->channel[2].size &&
2334 desc->channel[0].size == desc->channel[3].size) {
2335 switch (desc->channel[0].size) {
2336 case 4:
2337 return V_0280A0_COLOR_4_4_4_4;
2338 case 8:
2339 return V_0280A0_COLOR_8_8_8_8;
2340 case 16:
2341 if (is_float)
2342 return V_0280A0_COLOR_16_16_16_16_FLOAT;
2343 else
2344 return V_0280A0_COLOR_16_16_16_16;
2345 case 32:
2346 if (is_float)
2347 return V_0280A0_COLOR_32_32_32_32_FLOAT;
2348 else
2349 return V_0280A0_COLOR_32_32_32_32;
2350 }
2351 } else if (HAS_SIZE(5,5,5,1)) {
2352 return V_0280A0_COLOR_1_5_5_5;
2353 } else if (HAS_SIZE(10,10,10,2)) {
2354 return V_0280A0_COLOR_2_10_10_10;
2355 }
2356 break;
2357 }
2358 return ~0U;
2359 }
2360
2361 uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
2362 {
2363 if (R600_BIG_ENDIAN) {
2364 switch(colorformat) {
2365 /* 8-bit buffers. */
2366 case V_0280A0_COLOR_4_4:
2367 case V_0280A0_COLOR_8:
2368 return ENDIAN_NONE;
2369
2370 /* 16-bit buffers. */
2371 case V_0280A0_COLOR_5_6_5:
2372 case V_0280A0_COLOR_1_5_5_5:
2373 case V_0280A0_COLOR_4_4_4_4:
2374 case V_0280A0_COLOR_16:
2375 case V_0280A0_COLOR_8_8:
2376 return ENDIAN_8IN16;
2377
2378 /* 32-bit buffers. */
2379 case V_0280A0_COLOR_8_8_8_8:
2380 case V_0280A0_COLOR_2_10_10_10:
2381 case V_0280A0_COLOR_8_24:
2382 case V_0280A0_COLOR_24_8:
2383 case V_0280A0_COLOR_32_FLOAT:
2384 case V_0280A0_COLOR_16_16_FLOAT:
2385 case V_0280A0_COLOR_16_16:
2386 return ENDIAN_8IN32;
2387
2388 /* 64-bit buffers. */
2389 case V_0280A0_COLOR_16_16_16_16:
2390 case V_0280A0_COLOR_16_16_16_16_FLOAT:
2391 return ENDIAN_8IN16;
2392
2393 case V_0280A0_COLOR_32_32_FLOAT:
2394 case V_0280A0_COLOR_32_32:
2395 case V_0280A0_COLOR_X24_8_32_FLOAT:
2396 return ENDIAN_8IN32;
2397
2398 /* 128-bit buffers. */
2399 case V_0280A0_COLOR_32_32_32_32_FLOAT:
2400 case V_0280A0_COLOR_32_32_32_32:
2401 return ENDIAN_8IN32;
2402 default:
2403 return ENDIAN_NONE; /* Unsupported. */
2404 }
2405 } else {
2406 return ENDIAN_NONE;
2407 }
2408 }
2409
2410 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
2411 {
2412 struct r600_context *rctx = (struct r600_context*)ctx;
2413 struct r600_resource *rbuffer = r600_resource(buf);
2414 unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
2415 struct r600_pipe_sampler_view *view;
2416
2417 /* Reallocate the buffer in the same pipe_resource. */
2418 r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0,
2419 alignment, TRUE);
2420
2421 /* We changed the buffer, now we need to bind it where the old one was bound. */
2422 /* Vertex buffers. */
2423 mask = rctx->vertex_buffer_state.enabled_mask;
2424 while (mask) {
2425 i = u_bit_scan(&mask);
2426 if (rctx->vertex_buffer_state.vb[i].buffer == &rbuffer->b.b) {
2427 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
2428 r600_vertex_buffers_dirty(rctx);
2429 }
2430 }
2431 /* Streamout buffers. */
2432 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
2433 if (rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
2434 if (rctx->b.streamout.begin_emitted) {
2435 r600_emit_streamout_end(&rctx->b);
2436 }
2437 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
2438 r600_streamout_buffers_dirty(&rctx->b);
2439 }
2440 }
2441
2442 /* Constant buffers. */
2443 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2444 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2445 bool found = false;
2446 uint32_t mask = state->enabled_mask;
2447
2448 while (mask) {
2449 unsigned i = u_bit_scan(&mask);
2450 if (state->cb[i].buffer == &rbuffer->b.b) {
2451 found = true;
2452 state->dirty_mask |= 1 << i;
2453 }
2454 }
2455 if (found) {
2456 r600_constant_buffers_dirty(rctx, state);
2457 }
2458 }
2459
2460 /* Texture buffer objects - update the virtual addresses in descriptors. */
2461 LIST_FOR_EACH_ENTRY(view, &rctx->b.texture_buffers, list) {
2462 if (view->base.texture == &rbuffer->b.b) {
2463 unsigned stride = util_format_get_blocksize(view->base.format);
2464 uint64_t offset = (uint64_t)view->base.u.buf.first_element * stride;
2465 uint64_t va = rbuffer->gpu_address + offset;
2466
2467 view->tex_resource_words[0] = va;
2468 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
2469 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
2470 }
2471 }
2472 /* Texture buffer objects - make bindings dirty if needed. */
2473 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
2474 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
2475 bool found = false;
2476 uint32_t mask = state->enabled_mask;
2477
2478 while (mask) {
2479 unsigned i = u_bit_scan(&mask);
2480 if (state->views[i]->base.texture == &rbuffer->b.b) {
2481 found = true;
2482 state->dirty_mask |= 1 << i;
2483 }
2484 }
2485 if (found) {
2486 r600_sampler_views_dirty(rctx, state);
2487 }
2488 }
2489 }
2490
2491 static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
2492 {
2493 struct r600_context *rctx = (struct r600_context*)ctx;
2494
2495 if (rctx->db_misc_state.occlusion_query_enabled != enable) {
2496 rctx->db_misc_state.occlusion_query_enabled = enable;
2497 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2498 }
2499 }
2500
2501 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2502 bool include_draw_vbo)
2503 {
2504 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo);
2505 }
2506
2507 /* keep this at the end of this file, please */
2508 void r600_init_common_state_functions(struct r600_context *rctx)
2509 {
2510 rctx->b.b.create_fs_state = r600_create_ps_state;
2511 rctx->b.b.create_vs_state = r600_create_vs_state;
2512 rctx->b.b.create_gs_state = r600_create_gs_state;
2513 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2514 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2515 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2516 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2517 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2518 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2519 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2520 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2521 rctx->b.b.bind_gs_state = r600_bind_gs_state;
2522 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2523 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2524 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2525 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2526 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2527 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2528 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2529 rctx->b.b.delete_gs_state = r600_delete_gs_state;
2530 rctx->b.b.set_blend_color = r600_set_blend_color;
2531 rctx->b.b.set_clip_state = r600_set_clip_state;
2532 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2533 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2534 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2535 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2536 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2537 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2538 rctx->b.b.set_sampler_views = r600_set_sampler_views;
2539 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2540 rctx->b.b.texture_barrier = r600_texture_barrier;
2541 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2542 rctx->b.b.draw_vbo = r600_draw_vbo;
2543 rctx->b.invalidate_buffer = r600_invalidate_buffer;
2544 rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
2545 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
2546 }
2547
2548 void r600_trace_emit(struct r600_context *rctx)
2549 {
2550 struct r600_screen *rscreen = rctx->screen;
2551 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2552 uint64_t va;
2553 uint32_t reloc;
2554
2555 va = rscreen->b.trace_bo->gpu_address;
2556 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
2557 RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
2558 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2559 radeon_emit(cs, va & 0xFFFFFFFFUL);
2560 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2561 radeon_emit(cs, cs->cdw);
2562 radeon_emit(cs, rscreen->b.cs_count);
2563 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2564 radeon_emit(cs, reloc);
2565 }