2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
37 #include "tgsi/tgsi_scan.h"
38 #include "tgsi/tgsi_ureg.h"
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_add_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
62 void r600_init_atom(struct r600_context
*rctx
,
63 struct r600_atom
*atom
,
65 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
68 atom
->emit
= (void*)emit
;
69 atom
->num_dw
= num_dw
;
70 r600_add_atom(rctx
, atom
, id
);
73 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 r600_emit_command_buffer(rctx
->b
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
78 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
80 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
81 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
82 unsigned alpha_ref
= a
->sx_alpha_ref
;
84 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
88 radeon_set_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
89 a
->sx_alpha_test_control
|
90 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
91 radeon_set_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
94 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
96 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
97 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
98 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
100 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
101 PIPE_BARRIER_SHADER_BUFFER
|
102 PIPE_BARRIER_TEXTURE
|
104 PIPE_BARRIER_STREAMOUT_BUFFER
|
105 PIPE_BARRIER_GLOBAL_BUFFER
)) {
106 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
|
107 R600_CONTEXT_INV_TEX_CACHE
;
110 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
112 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV
;
114 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
117 static void r600_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
119 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
121 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
122 R600_CONTEXT_FLUSH_AND_INV_CB
|
123 R600_CONTEXT_FLUSH_AND_INV
|
124 R600_CONTEXT_WAIT_3D_IDLE
;
125 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
128 static unsigned r600_conv_pipe_prim(unsigned prim
)
130 static const unsigned prim_conv
[] = {
131 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
132 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
133 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
134 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
135 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
136 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
137 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
138 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
139 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
140 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
141 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
142 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
143 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
144 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
145 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
146 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
148 assert(prim
< ARRAY_SIZE(prim_conv
));
149 return prim_conv
[prim
];
152 unsigned r600_conv_prim_to_gs_out(unsigned mode
)
154 static const int prim_conv
[] = {
155 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
156 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
157 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
158 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
159 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
160 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
161 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
162 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
163 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
164 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
165 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
166 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
167 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
168 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
169 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
170 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
172 assert(mode
< ARRAY_SIZE(prim_conv
));
174 return prim_conv
[mode
];
177 /* common state between evergreen and r600 */
179 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
180 struct r600_blend_state
*blend
, bool blend_disable
)
182 unsigned color_control
;
183 bool update_cb
= false;
185 rctx
->alpha_to_one
= blend
->alpha_to_one
;
186 rctx
->dual_src_blend
= blend
->dual_src_blend
;
188 if (!blend_disable
) {
189 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer
);
190 color_control
= blend
->cb_color_control
;
192 /* Blending is disabled. */
193 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
194 color_control
= blend
->cb_color_control_no_blend
;
197 /* Update derived states. */
198 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
199 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
202 if (rctx
->b
.chip_class
<= R700
&&
203 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
204 rctx
->cb_misc_state
.cb_color_control
= color_control
;
207 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
208 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
212 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
214 if (rctx
->framebuffer
.dual_src_blend
!= blend
->dual_src_blend
) {
215 rctx
->framebuffer
.dual_src_blend
= blend
->dual_src_blend
;
216 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
220 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
222 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
223 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
226 r600_set_cso_state_with_cb(rctx
, &rctx
->blend_state
, NULL
, NULL
);
230 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
233 static void r600_set_blend_color(struct pipe_context
*ctx
,
234 const struct pipe_blend_color
*state
)
236 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
238 rctx
->blend_color
.state
= *state
;
239 r600_mark_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
242 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
244 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
245 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
247 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
248 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
249 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
250 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
251 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
254 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
256 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
257 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
259 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
260 radeon_set_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
261 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
262 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
263 if (a
->last_draw_was_indirect
) {
264 a
->last_draw_was_indirect
= false;
265 radeon_set_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
269 static void r600_set_clip_state(struct pipe_context
*ctx
,
270 const struct pipe_clip_state
*state
)
272 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
274 rctx
->clip_state
.state
= *state
;
275 r600_mark_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
276 rctx
->driver_consts
[PIPE_SHADER_VERTEX
].vs_ucp_dirty
= true;
279 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
280 const struct r600_stencil_ref
*state
)
282 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
284 rctx
->stencil_ref
.state
= *state
;
285 r600_mark_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
288 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
290 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
291 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
293 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
294 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
295 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
296 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
297 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
298 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
299 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
300 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
301 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
304 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
305 const struct pipe_stencil_ref
*state
)
307 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
308 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
309 struct r600_stencil_ref ref
;
311 rctx
->stencil_ref
.pipe_state
= *state
;
316 ref
.ref_value
[0] = state
->ref_value
[0];
317 ref
.ref_value
[1] = state
->ref_value
[1];
318 ref
.valuemask
[0] = dsa
->valuemask
[0];
319 ref
.valuemask
[1] = dsa
->valuemask
[1];
320 ref
.writemask
[0] = dsa
->writemask
[0];
321 ref
.writemask
[1] = dsa
->writemask
[1];
323 r600_set_stencil_ref(ctx
, &ref
);
326 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
328 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
329 struct r600_dsa_state
*dsa
= state
;
330 struct r600_stencil_ref ref
;
333 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, NULL
, NULL
);
337 r600_set_cso_state_with_cb(rctx
, &rctx
->dsa_state
, dsa
, &dsa
->buffer
);
339 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
340 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
341 ref
.valuemask
[0] = dsa
->valuemask
[0];
342 ref
.valuemask
[1] = dsa
->valuemask
[1];
343 ref
.writemask
[0] = dsa
->writemask
[0];
344 ref
.writemask
[1] = dsa
->writemask
[1];
345 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
346 rctx
->zwritemask
= dsa
->zwritemask
;
347 if (rctx
->b
.chip_class
>= EVERGREEN
) {
348 /* work around some issue when not writing to zbuffer
349 * we are having lockup on evergreen so do not enable
350 * hyperz when not writing zbuffer
352 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
356 r600_set_stencil_ref(ctx
, &ref
);
358 /* Update alphatest state. */
359 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
360 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
361 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
362 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
363 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
367 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
369 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
370 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
375 rctx
->rasterizer
= rs
;
377 r600_set_cso_state_with_cb(rctx
, &rctx
->rasterizer_state
, rs
, &rs
->buffer
);
379 if (rs
->offset_enable
&&
380 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
381 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
||
382 rs
->offset_units_unscaled
!= rctx
->poly_offset_state
.offset_units_unscaled
)) {
383 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
384 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
385 rctx
->poly_offset_state
.offset_units_unscaled
= rs
->offset_units_unscaled
;
386 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
389 /* Update clip_misc_state. */
390 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
391 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
392 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
393 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
394 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
397 r600_viewport_set_rast_deps(&rctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
399 /* Re-emit PA_SC_LINE_STIPPLE. */
400 rctx
->last_primitive_type
= -1;
403 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
405 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
407 r600_release_command_buffer(&rs
->buffer
);
411 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
412 struct pipe_sampler_view
*state
)
414 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
416 if (view
->tex_resource
->gpu_address
&&
417 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
418 LIST_DELINIT(&view
->list
);
420 pipe_resource_reference(&state
->texture
, NULL
);
424 void r600_sampler_states_dirty(struct r600_context
*rctx
,
425 struct r600_sampler_states
*state
)
427 if (state
->dirty_mask
) {
428 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
429 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
432 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
433 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
434 r600_mark_atom_dirty(rctx
, &state
->atom
);
438 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
439 enum pipe_shader_type shader
,
441 unsigned count
, void **states
)
443 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
444 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
445 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
446 int seamless_cube_map
= -1;
448 /* This sets 1-bit for states with index >= count. */
449 uint32_t disable_mask
= ~((1ull << count
) - 1);
450 /* These are the new states set by this function. */
451 uint32_t new_mask
= 0;
453 assert(start
== 0); /* XXX fix below */
460 for (i
= 0; i
< count
; i
++) {
461 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
463 if (rstate
== dst
->states
.states
[i
]) {
468 if (rstate
->border_color_use
) {
469 dst
->states
.has_bordercolor_mask
|= 1 << i
;
471 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
473 seamless_cube_map
= rstate
->seamless_cube_map
;
477 disable_mask
|= 1 << i
;
481 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
482 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
484 dst
->states
.enabled_mask
&= ~disable_mask
;
485 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
486 dst
->states
.enabled_mask
|= new_mask
;
487 dst
->states
.dirty_mask
|= new_mask
;
488 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
490 r600_sampler_states_dirty(rctx
, &dst
->states
);
492 /* Seamless cubemap state. */
493 if (rctx
->b
.chip_class
<= R700
&&
494 seamless_cube_map
!= -1 &&
495 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
496 /* change in TA_CNTL_AUX need a pipeline flush */
497 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
498 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
499 r600_mark_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
503 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
508 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
510 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
511 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
513 if (rctx
->blend_state
.cso
== state
) {
514 ctx
->bind_blend_state(ctx
, NULL
);
517 r600_release_command_buffer(&blend
->buffer
);
518 r600_release_command_buffer(&blend
->buffer_no_blend
);
522 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
524 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
525 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
527 if (rctx
->dsa_state
.cso
== state
) {
528 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
531 r600_release_command_buffer(&dsa
->buffer
);
535 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
537 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
539 r600_set_cso_state(rctx
, &rctx
->vertex_fetch_shader
, state
);
542 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
544 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
545 r600_resource_reference(&shader
->buffer
, NULL
);
549 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
551 if (rctx
->vertex_buffer_state
.dirty_mask
) {
552 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
553 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
554 r600_mark_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
558 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
559 unsigned start_slot
, unsigned count
,
560 const struct pipe_vertex_buffer
*input
)
562 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
563 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
564 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
566 uint32_t disable_mask
= 0;
567 /* These are the new buffers set by this function. */
568 uint32_t new_buffer_mask
= 0;
570 /* Set vertex buffers. */
572 for (i
= 0; i
< count
; i
++) {
573 if ((input
[i
].buffer
.resource
!= vb
[i
].buffer
.resource
) ||
574 (vb
[i
].stride
!= input
[i
].stride
) ||
575 (vb
[i
].buffer_offset
!= input
[i
].buffer_offset
) ||
576 (vb
[i
].is_user_buffer
!= input
[i
].is_user_buffer
)) {
577 if (input
[i
].buffer
.resource
) {
578 vb
[i
].stride
= input
[i
].stride
;
579 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
580 pipe_resource_reference(&vb
[i
].buffer
.resource
, input
[i
].buffer
.resource
);
581 new_buffer_mask
|= 1 << i
;
582 r600_context_add_resource_size(ctx
, input
[i
].buffer
.resource
);
584 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
585 disable_mask
|= 1 << i
;
590 for (i
= 0; i
< count
; i
++) {
591 pipe_resource_reference(&vb
[i
].buffer
.resource
, NULL
);
593 disable_mask
= ((1ull << count
) - 1);
596 disable_mask
<<= start_slot
;
597 new_buffer_mask
<<= start_slot
;
599 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
600 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
601 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
602 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
604 r600_vertex_buffers_dirty(rctx
);
607 void r600_sampler_views_dirty(struct r600_context
*rctx
,
608 struct r600_samplerview_state
*state
)
610 if (state
->dirty_mask
) {
611 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
612 util_bitcount(state
->dirty_mask
);
613 r600_mark_atom_dirty(rctx
, &state
->atom
);
617 static void r600_set_sampler_views(struct pipe_context
*pipe
,
618 enum pipe_shader_type shader
,
619 unsigned start
, unsigned count
,
620 struct pipe_sampler_view
**views
)
622 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
623 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
624 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
625 uint32_t dirty_sampler_states_mask
= 0;
627 /* This sets 1-bit for textures with index >= count. */
628 uint32_t disable_mask
= ~((1ull << count
) - 1);
629 /* These are the new textures set by this function. */
630 uint32_t new_mask
= 0;
632 /* Set textures with index >= count to NULL. */
633 uint32_t remaining_mask
;
635 assert(start
== 0); /* XXX fix below */
642 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
644 while (remaining_mask
) {
645 i
= u_bit_scan(&remaining_mask
);
646 assert(dst
->views
.views
[i
]);
648 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
651 for (i
= 0; i
< count
; i
++) {
652 if (rviews
[i
] == dst
->views
.views
[i
]) {
657 struct r600_texture
*rtex
=
658 (struct r600_texture
*)rviews
[i
]->base
.texture
;
659 bool is_buffer
= rviews
[i
]->base
.texture
->target
== PIPE_BUFFER
;
661 if (!is_buffer
&& rtex
->db_compatible
) {
662 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
664 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
667 /* Track compressed colorbuffers. */
668 if (!is_buffer
&& rtex
->cmask
.size
) {
669 dst
->views
.compressed_colortex_mask
|= 1 << i
;
671 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
674 /* Changing from array to non-arrays textures and vice versa requires
675 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
676 if (rctx
->b
.chip_class
<= R700
&&
677 (dst
->states
.enabled_mask
& (1 << i
)) &&
678 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
679 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
680 dirty_sampler_states_mask
|= 1 << i
;
683 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
685 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
687 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
688 disable_mask
|= 1 << i
;
692 dst
->views
.enabled_mask
&= ~disable_mask
;
693 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
694 dst
->views
.enabled_mask
|= new_mask
;
695 dst
->views
.dirty_mask
|= new_mask
;
696 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
697 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
698 dst
->views
.dirty_buffer_constants
= TRUE
;
699 r600_sampler_views_dirty(rctx
, &dst
->views
);
701 if (dirty_sampler_states_mask
) {
702 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
703 r600_sampler_states_dirty(rctx
, &dst
->states
);
707 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state
*views
)
709 uint32_t mask
= views
->enabled_mask
;
712 unsigned i
= u_bit_scan(&mask
);
713 struct pipe_resource
*res
= views
->views
[i
]->base
.texture
;
715 if (res
&& res
->target
!= PIPE_BUFFER
) {
716 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
718 if (rtex
->cmask
.size
) {
719 views
->compressed_colortex_mask
|= 1 << i
;
721 views
->compressed_colortex_mask
&= ~(1 << i
);
727 static int r600_get_hw_atomic_count(const struct pipe_context
*ctx
,
728 enum pipe_shader_type shader
)
730 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
733 case PIPE_SHADER_FRAGMENT
:
734 case PIPE_SHADER_COMPUTE
:
737 case PIPE_SHADER_VERTEX
:
738 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
740 case PIPE_SHADER_GEOMETRY
:
741 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
742 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
744 case PIPE_SHADER_TESS_EVAL
:
745 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
746 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
747 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0);
749 case PIPE_SHADER_TESS_CTRL
:
750 value
= rctx
->ps_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
751 rctx
->vs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] +
752 (rctx
->gs_shader
? rctx
->gs_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
] : 0) +
753 rctx
->tes_shader
->info
.file_count
[TGSI_FILE_HW_ATOMIC
];
759 static void r600_update_compressed_colortex_mask_images(struct r600_image_state
*images
)
761 uint32_t mask
= images
->enabled_mask
;
764 unsigned i
= u_bit_scan(&mask
);
765 struct pipe_resource
*res
= images
->views
[i
].base
.resource
;
767 if (res
&& res
->target
!= PIPE_BUFFER
) {
768 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
770 if (rtex
->cmask
.size
) {
771 images
->compressed_colortex_mask
|= 1 << i
;
773 images
->compressed_colortex_mask
&= ~(1 << i
);
779 /* Compute the key for the hw shader variant */
780 static inline void r600_shader_selector_key(const struct pipe_context
*ctx
,
781 const struct r600_pipe_shader_selector
*sel
,
782 union r600_shader_key
*key
)
784 const struct r600_context
*rctx
= (struct r600_context
*)ctx
;
785 memset(key
, 0, sizeof(*key
));
788 case PIPE_SHADER_VERTEX
: {
789 key
->vs
.as_ls
= (rctx
->tes_shader
!= NULL
);
791 key
->vs
.as_es
= (rctx
->gs_shader
!= NULL
);
793 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
794 key
->vs
.as_gs_a
= true;
795 key
->vs
.prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
797 key
->vs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_VERTEX
);
800 case PIPE_SHADER_GEOMETRY
:
801 key
->gs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_GEOMETRY
);
802 key
->gs
.tri_strip_adj_fix
= rctx
->gs_tri_strip_adj_fix
;
804 case PIPE_SHADER_FRAGMENT
: {
805 if (rctx
->ps_shader
->info
.images_declared
)
806 key
->ps
.image_size_const_offset
= util_last_bit(rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.enabled_mask
);
807 key
->ps
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_FRAGMENT
);
808 key
->ps
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
809 key
->ps
.alpha_to_one
= rctx
->alpha_to_one
&&
810 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
811 !rctx
->framebuffer
.cb0_is_integer
;
812 key
->ps
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
813 /* Dual-source blending only makes sense with nr_cbufs == 1. */
814 if (key
->ps
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
815 key
->ps
.nr_cbufs
= 2;
818 case PIPE_SHADER_TESS_EVAL
:
819 key
->tes
.as_es
= (rctx
->gs_shader
!= NULL
);
820 key
->tes
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_EVAL
);
822 case PIPE_SHADER_TESS_CTRL
:
823 key
->tcs
.prim_mode
= rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
824 key
->tcs
.first_atomic_counter
= r600_get_hw_atomic_count(ctx
, PIPE_SHADER_TESS_CTRL
);
826 case PIPE_SHADER_COMPUTE
:
833 /* Select the hw shader variant depending on the current state.
834 * (*dirty) is set to 1 if current variant was changed */
835 int r600_shader_select(struct pipe_context
*ctx
,
836 struct r600_pipe_shader_selector
* sel
,
839 union r600_shader_key key
;
840 struct r600_pipe_shader
* shader
= NULL
;
843 r600_shader_selector_key(ctx
, sel
, &key
);
845 /* Check if we don't need to change anything.
846 * This path is also used for most shaders that don't need multiple
847 * variants, it will cost just a computation of the key and this
849 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
853 /* lookup if we have other variants in the list */
854 if (sel
->num_shaders
> 1) {
855 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
857 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
863 p
->next_variant
= c
->next_variant
;
868 if (unlikely(!shader
)) {
869 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
870 shader
->selector
= sel
;
872 r
= r600_pipe_shader_create(ctx
, shader
, key
);
874 R600_ERR("Failed to build shader variant (type=%u) %d\n",
881 /* We don't know the value of nr_ps_max_color_exports until we built
882 * at least one variant, so we may need to recompute the key after
883 * building first variant. */
884 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
885 sel
->num_shaders
== 0) {
886 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
887 r600_shader_selector_key(ctx
, sel
, &key
);
890 memcpy(&shader
->key
, &key
, sizeof(key
));
897 shader
->next_variant
= sel
->current
;
898 sel
->current
= shader
;
903 struct r600_pipe_shader_selector
*r600_create_shader_state_tokens(struct pipe_context
*ctx
,
904 const struct tgsi_token
*tokens
,
905 unsigned pipe_shader_type
)
907 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
909 sel
->type
= pipe_shader_type
;
910 sel
->tokens
= tgsi_dup_tokens(tokens
);
911 tgsi_scan_shader(tokens
, &sel
->info
);
915 static void *r600_create_shader_state(struct pipe_context
*ctx
,
916 const struct pipe_shader_state
*state
,
917 unsigned pipe_shader_type
)
920 struct r600_pipe_shader_selector
*sel
= r600_create_shader_state_tokens(ctx
, state
->tokens
, pipe_shader_type
);
922 sel
->so
= state
->stream_output
;
924 switch (pipe_shader_type
) {
925 case PIPE_SHADER_GEOMETRY
:
926 sel
->gs_output_prim
=
927 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
928 sel
->gs_max_out_vertices
=
929 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
930 sel
->gs_num_invocations
=
931 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
933 case PIPE_SHADER_VERTEX
:
934 case PIPE_SHADER_TESS_CTRL
:
935 sel
->lds_patch_outputs_written_mask
= 0;
936 sel
->lds_outputs_written_mask
= 0;
938 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
939 unsigned name
= sel
->info
.output_semantic_name
[i
];
940 unsigned index
= sel
->info
.output_semantic_index
[i
];
943 case TGSI_SEMANTIC_TESSINNER
:
944 case TGSI_SEMANTIC_TESSOUTER
:
945 case TGSI_SEMANTIC_PATCH
:
946 sel
->lds_patch_outputs_written_mask
|=
947 1ull << r600_get_lds_unique_index(name
, index
);
950 sel
->lds_outputs_written_mask
|=
951 1ull << r600_get_lds_unique_index(name
, index
);
962 static void *r600_create_ps_state(struct pipe_context
*ctx
,
963 const struct pipe_shader_state
*state
)
965 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
968 static void *r600_create_vs_state(struct pipe_context
*ctx
,
969 const struct pipe_shader_state
*state
)
971 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
974 static void *r600_create_gs_state(struct pipe_context
*ctx
,
975 const struct pipe_shader_state
*state
)
977 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
980 static void *r600_create_tcs_state(struct pipe_context
*ctx
,
981 const struct pipe_shader_state
*state
)
983 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_CTRL
);
986 static void *r600_create_tes_state(struct pipe_context
*ctx
,
987 const struct pipe_shader_state
*state
)
989 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_TESS_EVAL
);
992 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
994 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
997 state
= rctx
->dummy_pixel_shader
;
999 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
1002 static struct tgsi_shader_info
*r600_get_vs_info(struct r600_context
*rctx
)
1004 if (rctx
->gs_shader
)
1005 return &rctx
->gs_shader
->info
;
1006 else if (rctx
->tes_shader
)
1007 return &rctx
->tes_shader
->info
;
1008 else if (rctx
->vs_shader
)
1009 return &rctx
->vs_shader
->info
;
1014 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
1016 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1018 if (!state
|| rctx
->vs_shader
== state
)
1021 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
1022 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1024 if (rctx
->vs_shader
->so
.num_outputs
)
1025 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
1028 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
1030 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1032 if (state
== rctx
->gs_shader
)
1035 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
1036 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1041 if (rctx
->gs_shader
->so
.num_outputs
)
1042 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
1045 static void r600_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
1047 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1049 rctx
->tcs_shader
= (struct r600_pipe_shader_selector
*)state
;
1052 static void r600_bind_tes_state(struct pipe_context
*ctx
, void *state
)
1054 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1056 if (state
== rctx
->tes_shader
)
1059 rctx
->tes_shader
= (struct r600_pipe_shader_selector
*)state
;
1060 r600_update_vs_writes_viewport_index(&rctx
->b
, r600_get_vs_info(rctx
));
1065 if (rctx
->tes_shader
->so
.num_outputs
)
1066 rctx
->b
.streamout
.stride_in_dw
= rctx
->tes_shader
->so
.stride
;
1069 void r600_delete_shader_selector(struct pipe_context
*ctx
,
1070 struct r600_pipe_shader_selector
*sel
)
1072 struct r600_pipe_shader
*p
= sel
->current
, *c
;
1074 c
= p
->next_variant
;
1075 r600_pipe_shader_destroy(ctx
, p
);
1085 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
1087 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1088 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1090 if (rctx
->ps_shader
== sel
) {
1091 rctx
->ps_shader
= NULL
;
1094 r600_delete_shader_selector(ctx
, sel
);
1097 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
1099 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1100 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1102 if (rctx
->vs_shader
== sel
) {
1103 rctx
->vs_shader
= NULL
;
1106 r600_delete_shader_selector(ctx
, sel
);
1110 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
1112 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1113 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1115 if (rctx
->gs_shader
== sel
) {
1116 rctx
->gs_shader
= NULL
;
1119 r600_delete_shader_selector(ctx
, sel
);
1122 static void r600_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
1124 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1125 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1127 if (rctx
->tcs_shader
== sel
) {
1128 rctx
->tcs_shader
= NULL
;
1131 r600_delete_shader_selector(ctx
, sel
);
1134 static void r600_delete_tes_state(struct pipe_context
*ctx
, void *state
)
1136 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1137 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
1139 if (rctx
->tes_shader
== sel
) {
1140 rctx
->tes_shader
= NULL
;
1143 r600_delete_shader_selector(ctx
, sel
);
1146 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
1148 if (state
->dirty_mask
) {
1149 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
1150 : util_bitcount(state
->dirty_mask
)*19;
1151 r600_mark_atom_dirty(rctx
, &state
->atom
);
1155 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
1156 enum pipe_shader_type shader
, uint index
,
1157 const struct pipe_constant_buffer
*input
)
1159 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1160 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
1161 struct pipe_constant_buffer
*cb
;
1164 /* Note that the state tracker can unbind constant buffers by
1165 * passing NULL here.
1167 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
1168 state
->enabled_mask
&= ~(1 << index
);
1169 state
->dirty_mask
&= ~(1 << index
);
1170 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
1174 cb
= &state
->cb
[index
];
1175 cb
->buffer_size
= input
->buffer_size
;
1177 ptr
= input
->user_buffer
;
1180 /* Upload the user buffer. */
1181 if (R600_BIG_ENDIAN
) {
1183 unsigned i
, size
= input
->buffer_size
;
1185 if (!(tmpPtr
= malloc(size
))) {
1186 R600_ERR("Failed to allocate BE swap buffer.\n");
1190 for (i
= 0; i
< size
/ 4; ++i
) {
1191 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
1194 u_upload_data(ctx
->stream_uploader
, 0, size
, 256,
1195 tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
1198 u_upload_data(ctx
->stream_uploader
, 0,
1199 input
->buffer_size
, 256, ptr
,
1200 &cb
->buffer_offset
, &cb
->buffer
);
1202 /* account it in gtt */
1203 rctx
->b
.gtt
+= input
->buffer_size
;
1205 /* Setup the hw buffer. */
1206 cb
->buffer_offset
= input
->buffer_offset
;
1207 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1208 r600_context_add_resource_size(ctx
, input
->buffer
);
1211 state
->enabled_mask
|= 1 << index
;
1212 state
->dirty_mask
|= 1 << index
;
1213 r600_constant_buffers_dirty(rctx
, state
);
1216 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1218 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1220 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1223 rctx
->sample_mask
.sample_mask
= sample_mask
;
1224 r600_mark_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1227 void r600_update_driver_const_buffers(struct r600_context
*rctx
, bool compute_only
)
1231 struct pipe_constant_buffer cb
;
1234 start
= compute_only
? PIPE_SHADER_COMPUTE
: 0;
1235 end
= compute_only
? PIPE_SHADER_TYPES
: PIPE_SHADER_COMPUTE
;
1237 for (sh
= start
; sh
< end
; sh
++) {
1238 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[sh
];
1239 if (!info
->vs_ucp_dirty
&&
1240 !info
->texture_const_dirty
&&
1241 !info
->ps_sample_pos_dirty
&&
1242 !info
->tcs_default_levels_dirty
&&
1243 !info
->cs_block_grid_size_dirty
)
1246 ptr
= info
->constants
;
1247 size
= info
->alloc_size
;
1248 if (info
->vs_ucp_dirty
) {
1249 assert(sh
== PIPE_SHADER_VERTEX
);
1251 ptr
= rctx
->clip_state
.state
.ucp
;
1252 size
= R600_UCP_SIZE
;
1254 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1256 info
->vs_ucp_dirty
= false;
1259 else if (info
->ps_sample_pos_dirty
) {
1260 assert(sh
== PIPE_SHADER_FRAGMENT
);
1262 ptr
= rctx
->sample_positions
;
1263 size
= R600_UCP_SIZE
;
1265 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1267 info
->ps_sample_pos_dirty
= false;
1270 else if (info
->cs_block_grid_size_dirty
) {
1271 assert(sh
== PIPE_SHADER_COMPUTE
);
1273 ptr
= rctx
->cs_block_grid_sizes
;
1274 size
= R600_CS_BLOCK_GRID_SIZE
;
1276 memcpy(ptr
, rctx
->cs_block_grid_sizes
, R600_CS_BLOCK_GRID_SIZE
);
1278 info
->cs_block_grid_size_dirty
= false;
1281 else if (info
->tcs_default_levels_dirty
) {
1283 * We'd only really need this for default tcs shader.
1285 assert(sh
== PIPE_SHADER_TESS_CTRL
);
1287 ptr
= rctx
->tess_state
;
1288 size
= R600_TCS_DEFAULT_LEVELS_SIZE
;
1290 memcpy(ptr
, rctx
->tess_state
, R600_TCS_DEFAULT_LEVELS_SIZE
);
1292 info
->tcs_default_levels_dirty
= false;
1295 if (info
->texture_const_dirty
) {
1298 if (sh
== PIPE_SHADER_VERTEX
)
1299 memcpy(ptr
, rctx
->clip_state
.state
.ucp
, R600_UCP_SIZE
);
1300 if (sh
== PIPE_SHADER_FRAGMENT
)
1301 memcpy(ptr
, rctx
->sample_positions
, R600_UCP_SIZE
);
1302 if (sh
== PIPE_SHADER_COMPUTE
)
1303 memcpy(ptr
, rctx
->cs_block_grid_sizes
, R600_CS_BLOCK_GRID_SIZE
);
1304 if (sh
== PIPE_SHADER_TESS_CTRL
)
1305 memcpy(ptr
, rctx
->tess_state
, R600_TCS_DEFAULT_LEVELS_SIZE
);
1307 info
->texture_const_dirty
= false;
1310 cb
.user_buffer
= ptr
;
1311 cb
.buffer_offset
= 0;
1312 cb
.buffer_size
= size
;
1313 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1314 pipe_resource_reference(&cb
.buffer
, NULL
);
1318 static void *r600_alloc_buf_consts(struct r600_context
*rctx
, int shader_type
,
1319 unsigned array_size
, uint32_t *base_offset
)
1321 struct r600_shader_driver_constants_info
*info
= &rctx
->driver_consts
[shader_type
];
1322 if (array_size
+ R600_UCP_SIZE
> info
->alloc_size
) {
1323 info
->constants
= realloc(info
->constants
, array_size
+ R600_UCP_SIZE
);
1324 info
->alloc_size
= array_size
+ R600_UCP_SIZE
;
1326 memset(info
->constants
+ (R600_UCP_SIZE
/ 4), 0, array_size
);
1327 info
->texture_const_dirty
= true;
1328 *base_offset
= R600_UCP_SIZE
;
1329 return info
->constants
;
1332 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1333 * doesn't require full swizzles it does need masking and setting alpha
1334 * to one, so we setup a set of 5 constants with the masks + alpha value
1335 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1336 * then OR the alpha with the value given here.
1337 * We use a 6th constant to store the txq buffer size in
1338 * we use 7th slot for number of cube layers in a cube map array.
1340 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1342 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1344 uint32_t array_size
;
1346 uint32_t *constants
;
1347 uint32_t base_offset
;
1348 if (!samplers
->views
.dirty_buffer_constants
)
1351 samplers
->views
.dirty_buffer_constants
= FALSE
;
1353 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1354 array_size
= bits
* 8 * sizeof(uint32_t);
1356 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
, &base_offset
);
1358 for (i
= 0; i
< bits
; i
++) {
1359 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1360 int offset
= (base_offset
/ 4) + i
* 8;
1361 const struct util_format_description
*desc
;
1362 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1364 for (j
= 0; j
< 4; j
++)
1365 if (j
< desc
->nr_channels
)
1366 constants
[offset
+j
] = 0xffffffff;
1368 constants
[offset
+j
] = 0x0;
1369 if (desc
->nr_channels
< 4) {
1370 if (desc
->channel
[0].pure_integer
)
1371 constants
[offset
+4] = 1;
1373 constants
[offset
+4] = fui(1.0);
1375 constants
[offset
+ 4] = 0;
1377 constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.u
.buf
.size
/
1378 util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1379 constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1385 /* On evergreen we store one value
1386 * 1. number of cube layers in a cube map array.
1388 void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1390 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1391 struct r600_image_state
*images
= NULL
;
1392 int bits
, sview_bits
, img_bits
;
1393 uint32_t array_size
;
1395 uint32_t *constants
;
1396 uint32_t base_offset
;
1398 if (shader_type
== PIPE_SHADER_FRAGMENT
) {
1399 images
= &rctx
->fragment_images
;
1400 } else if (shader_type
== PIPE_SHADER_COMPUTE
) {
1401 images
= &rctx
->compute_images
;
1404 if (!samplers
->views
.dirty_buffer_constants
&&
1405 !(images
&& images
->dirty_buffer_constants
))
1409 images
->dirty_buffer_constants
= FALSE
;
1410 samplers
->views
.dirty_buffer_constants
= FALSE
;
1412 bits
= sview_bits
= util_last_bit(samplers
->views
.enabled_mask
);
1414 bits
+= util_last_bit(images
->enabled_mask
);
1417 array_size
= bits
* sizeof(uint32_t);
1419 constants
= r600_alloc_buf_consts(rctx
, shader_type
, array_size
,
1422 for (i
= 0; i
< sview_bits
; i
++) {
1423 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1424 uint32_t offset
= (base_offset
/ 4) + i
;
1425 constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1429 for (i
= sview_bits
; i
< img_bits
; i
++) {
1430 int idx
= i
- sview_bits
;
1431 if (images
->enabled_mask
& (1 << idx
)) {
1432 uint32_t offset
= (base_offset
/ 4) + i
;
1433 constants
[offset
] = images
->views
[idx
].base
.resource
->array_size
/ 6;
1439 /* set sample xy locations as array of fragment shader constants */
1440 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1442 struct pipe_context
*ctx
= &rctx
->b
.b
;
1444 assert(rctx
->framebuffer
.nr_samples
< R600_UCP_SIZE
);
1445 assert(rctx
->framebuffer
.nr_samples
<= ARRAY_SIZE(rctx
->sample_positions
)/4);
1447 memset(rctx
->sample_positions
, 0, 4 * 4 * 16);
1448 for (unsigned i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1449 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &rctx
->sample_positions
[4*i
]);
1450 /* Also fill in center-zeroed positions used for interpolateAtSample */
1451 rctx
->sample_positions
[4*i
+ 2] = rctx
->sample_positions
[4*i
+ 0] - 0.5f
;
1452 rctx
->sample_positions
[4*i
+ 3] = rctx
->sample_positions
[4*i
+ 1] - 0.5f
;
1455 rctx
->driver_consts
[PIPE_SHADER_FRAGMENT
].ps_sample_pos_dirty
= true;
1458 static void update_shader_atom(struct pipe_context
*ctx
,
1459 struct r600_shader_state
*state
,
1460 struct r600_pipe_shader
*shader
)
1462 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1464 state
->shader
= shader
;
1466 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1467 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1469 state
->atom
.num_dw
= 0;
1471 r600_mark_atom_dirty(rctx
, &state
->atom
);
1474 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1476 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1477 rctx
->shader_stages
.geom_enable
= enable
;
1478 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1481 if (rctx
->gs_rings
.enable
!= enable
) {
1482 rctx
->gs_rings
.enable
= enable
;
1483 r600_mark_atom_dirty(rctx
, &rctx
->gs_rings
.atom
);
1485 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1486 unsigned size
= 0x1C000;
1487 rctx
->gs_rings
.esgs_ring
.buffer
=
1488 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1489 PIPE_USAGE_DEFAULT
, size
);
1490 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1494 rctx
->gs_rings
.gsvs_ring
.buffer
=
1495 pipe_buffer_create(rctx
->b
.b
.screen
, 0,
1496 PIPE_USAGE_DEFAULT
, size
);
1497 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1501 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1502 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1503 if (rctx
->tes_shader
) {
1504 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1505 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1507 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1508 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1511 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1512 R600_GS_RING_CONST_BUFFER
, NULL
);
1513 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1514 R600_GS_RING_CONST_BUFFER
, NULL
);
1515 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_TESS_EVAL
,
1516 R600_GS_RING_CONST_BUFFER
, NULL
);
1521 static void r600_update_clip_state(struct r600_context
*rctx
,
1522 struct r600_pipe_shader
*current
)
1524 if (current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1525 current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1526 current
->shader
.cull_dist_write
!= rctx
->clip_misc_state
.cull_dist_write
||
1527 current
->shader
.vs_position_window_space
!= rctx
->clip_misc_state
.clip_disable
||
1528 current
->shader
.vs_out_viewport
!= rctx
->clip_misc_state
.vs_out_viewport
) {
1529 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= current
->pa_cl_vs_out_cntl
;
1530 rctx
->clip_misc_state
.clip_dist_write
= current
->shader
.clip_dist_write
;
1531 rctx
->clip_misc_state
.cull_dist_write
= current
->shader
.cull_dist_write
;
1532 rctx
->clip_misc_state
.clip_disable
= current
->shader
.vs_position_window_space
;
1533 rctx
->clip_misc_state
.vs_out_viewport
= current
->shader
.vs_out_viewport
;
1534 r600_mark_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
1538 static void r600_generate_fixed_func_tcs(struct r600_context
*rctx
)
1540 struct ureg_src const0
, const1
;
1541 struct ureg_dst tessouter
, tessinner
;
1542 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1545 return; /* if we get here, we're screwed */
1547 assert(!rctx
->fixed_func_tcs_shader
);
1549 ureg_DECL_constant2D(ureg
, 0, 1, R600_BUFFER_INFO_CONST_BUFFER
);
1550 const0
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 0),
1551 R600_BUFFER_INFO_CONST_BUFFER
);
1552 const1
= ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT
, 1),
1553 R600_BUFFER_INFO_CONST_BUFFER
);
1555 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1556 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1558 ureg_MOV(ureg
, tessouter
, const0
);
1559 ureg_MOV(ureg
, tessinner
, const1
);
1562 rctx
->fixed_func_tcs_shader
=
1563 ureg_create_shader_and_destroy(ureg
, &rctx
->b
.b
);
1566 void r600_update_compressed_resource_state(struct r600_context
*rctx
, bool compute_only
)
1571 counter
= p_atomic_read(&rctx
->screen
->b
.compressed_colortex_counter
);
1572 if (counter
!= rctx
->b
.last_compressed_colortex_counter
) {
1573 rctx
->b
.last_compressed_colortex_counter
= counter
;
1576 r600_update_compressed_colortex_mask(&rctx
->samplers
[PIPE_SHADER_COMPUTE
].views
);
1578 for (i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1579 r600_update_compressed_colortex_mask(&rctx
->samplers
[i
].views
);
1583 r600_update_compressed_colortex_mask_images(&rctx
->fragment_images
);
1584 r600_update_compressed_colortex_mask_images(&rctx
->compute_images
);
1587 /* Decompress textures if needed. */
1588 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1589 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1592 if (i
!= PIPE_SHADER_COMPUTE
)
1594 if (views
->compressed_depthtex_mask
) {
1595 r600_decompress_depth_textures(rctx
, views
);
1597 if (views
->compressed_colortex_mask
) {
1598 r600_decompress_color_textures(rctx
, views
);
1603 struct r600_image_state
*istate
;
1605 if (!compute_only
) {
1606 istate
= &rctx
->fragment_images
;
1607 if (istate
->compressed_depthtex_mask
)
1608 r600_decompress_depth_images(rctx
, istate
);
1609 if (istate
->compressed_colortex_mask
)
1610 r600_decompress_color_images(rctx
, istate
);
1613 istate
= &rctx
->compute_images
;
1614 if (istate
->compressed_depthtex_mask
)
1615 r600_decompress_depth_images(rctx
, istate
);
1616 if (istate
->compressed_colortex_mask
)
1617 r600_decompress_color_images(rctx
, istate
);
1621 /* update MEM_SCRATCH buffers if needed */
1622 void r600_setup_scratch_area_for_shader(struct r600_context
*rctx
,
1623 struct r600_pipe_shader
*shader
, struct r600_scratch_buffer
*scratch
,
1624 unsigned ring_base_reg
, unsigned item_size_reg
, unsigned ring_size_reg
)
1626 unsigned num_ses
= rctx
->screen
->b
.info
.max_se
;
1627 unsigned num_pipes
= rctx
->screen
->b
.info
.r600_max_quad_pipes
;
1628 unsigned nthreads
= 128;
1630 unsigned itemsize
= shader
->scratch_space_needed
* 4;
1631 unsigned size
= align(itemsize
* nthreads
* num_pipes
* num_ses
* 4, 256);
1633 if (scratch
->dirty
||
1634 unlikely(shader
->scratch_space_needed
!= scratch
->item_size
||
1635 size
> scratch
->size
)) {
1636 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
1638 scratch
->dirty
= false;
1640 if (size
> scratch
->size
) {
1641 // Release prior one if any
1642 if (scratch
->buffer
) {
1643 pipe_resource_reference((struct pipe_resource
**)&scratch
->buffer
, NULL
);
1646 scratch
->buffer
= (struct r600_resource
*)pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1647 PIPE_USAGE_DEFAULT
, size
);
1648 if (scratch
->buffer
) {
1649 scratch
->size
= size
;
1653 scratch
->item_size
= shader
->scratch_space_needed
;
1655 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1656 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1657 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1659 // multi-SE chips need programming per SE
1660 for (unsigned se
= 0; se
< num_ses
; se
++) {
1661 struct r600_resource
*rbuffer
= scratch
->buffer
;
1662 unsigned size_per_se
= size
/ num_ses
;
1664 // Direct to particular SE
1666 radeon_set_config_reg(cs
, EG_0802C_GRBM_GFX_INDEX
,
1667 S_0802C_INSTANCE_INDEX(0) |
1668 S_0802C_SE_INDEX(se
) |
1669 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1670 S_0802C_SE_BROADCAST_WRITES(0));
1673 radeon_set_config_reg(cs
, ring_base_reg
, (rbuffer
->gpu_address
+ size_per_se
* se
) >> 8);
1674 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1675 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1676 RADEON_USAGE_READWRITE
,
1677 RADEON_PRIO_SCRATCH_BUFFER
));
1678 radeon_set_context_reg(cs
, item_size_reg
, itemsize
);
1679 radeon_set_config_reg(cs
, ring_size_reg
, size_per_se
>> 8);
1682 // Restore broadcast mode
1684 radeon_set_config_reg(cs
, EG_0802C_GRBM_GFX_INDEX
,
1685 S_0802C_INSTANCE_INDEX(0) |
1686 S_0802C_SE_INDEX(0) |
1687 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1688 S_0802C_SE_BROADCAST_WRITES(1));
1691 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1692 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1693 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1697 void r600_setup_scratch_buffers(struct r600_context
*rctx
) {
1698 static const struct {
1702 } regs
[R600_NUM_HW_STAGES
] = {
1703 [R600_HW_STAGE_PS
] = { R_008C68_SQ_PSTMP_RING_BASE
, R_0288BC_SQ_PSTMP_RING_ITEMSIZE
, R_008C6C_SQ_PSTMP_RING_SIZE
},
1704 [R600_HW_STAGE_VS
] = { R_008C60_SQ_VSTMP_RING_BASE
, R_0288B8_SQ_VSTMP_RING_ITEMSIZE
, R_008C64_SQ_VSTMP_RING_SIZE
},
1705 [R600_HW_STAGE_GS
] = { R_008C58_SQ_GSTMP_RING_BASE
, R_0288B4_SQ_GSTMP_RING_ITEMSIZE
, R_008C5C_SQ_GSTMP_RING_SIZE
},
1706 [R600_HW_STAGE_ES
] = { R_008C50_SQ_ESTMP_RING_BASE
, R_0288B0_SQ_ESTMP_RING_ITEMSIZE
, R_008C54_SQ_ESTMP_RING_SIZE
}
1709 for (unsigned i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
1710 struct r600_pipe_shader
*stage
= rctx
->hw_shader_stages
[i
].shader
;
1712 if (stage
&& unlikely(stage
->scratch_space_needed
)) {
1713 r600_setup_scratch_area_for_shader(rctx
, stage
,
1714 &rctx
->scratch_buffers
[i
], regs
[i
].ring_base
, regs
[i
].item_size
, regs
[i
].ring_size
);
1719 #define SELECT_SHADER_OR_FAIL(x) do { \
1720 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
1721 if (unlikely(!rctx->x##_shader->current)) \
1725 #define UPDATE_SHADER(hw, sw) do { \
1726 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1727 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1730 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1731 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1732 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1733 clip_so_current = rctx->sw##_shader->current; \
1737 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1738 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1739 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1740 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1741 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1745 #define SET_NULL_SHADER(hw) do { \
1746 if (rctx->hw_shader_stages[(hw)].shader) \
1747 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1750 static bool r600_update_derived_state(struct r600_context
*rctx
)
1752 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1753 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1754 bool tcs_dirty
= false, tes_dirty
= false, fixed_func_tcs_dirty
= false;
1756 bool need_buf_const
;
1757 struct r600_pipe_shader
*clip_so_current
= NULL
;
1759 if (!rctx
->blitter
->running
)
1760 r600_update_compressed_resource_state(rctx
, false);
1762 SELECT_SHADER_OR_FAIL(ps
);
1764 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1766 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1768 if (rctx
->gs_shader
)
1769 SELECT_SHADER_OR_FAIL(gs
);
1772 if (rctx
->tcs_shader
) {
1773 SELECT_SHADER_OR_FAIL(tcs
);
1775 UPDATE_SHADER(EG_HW_STAGE_HS
, tcs
);
1776 } else if (rctx
->tes_shader
) {
1777 if (!rctx
->fixed_func_tcs_shader
) {
1778 r600_generate_fixed_func_tcs(rctx
);
1779 if (!rctx
->fixed_func_tcs_shader
)
1783 SELECT_SHADER_OR_FAIL(fixed_func_tcs
);
1785 UPDATE_SHADER(EG_HW_STAGE_HS
, fixed_func_tcs
);
1787 SET_NULL_SHADER(EG_HW_STAGE_HS
);
1789 if (rctx
->tes_shader
) {
1790 SELECT_SHADER_OR_FAIL(tes
);
1793 SELECT_SHADER_OR_FAIL(vs
);
1795 if (rctx
->gs_shader
) {
1796 if (!rctx
->shader_stages
.geom_enable
) {
1797 rctx
->shader_stages
.geom_enable
= true;
1798 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1801 /* gs_shader provides GS and VS (copy shader) */
1802 UPDATE_SHADER_GS(R600_HW_STAGE_GS
, R600_HW_STAGE_VS
, gs
);
1804 /* vs_shader is used as ES */
1806 if (rctx
->tes_shader
) {
1807 /* VS goes to LS, TES goes to ES */
1808 UPDATE_SHADER(R600_HW_STAGE_ES
, tes
);
1809 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1811 /* vs_shader is used as ES */
1812 UPDATE_SHADER(R600_HW_STAGE_ES
, vs
);
1813 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1816 if (unlikely(rctx
->hw_shader_stages
[R600_HW_STAGE_GS
].shader
)) {
1817 SET_NULL_SHADER(R600_HW_STAGE_GS
);
1818 SET_NULL_SHADER(R600_HW_STAGE_ES
);
1819 rctx
->shader_stages
.geom_enable
= false;
1820 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1823 if (rctx
->tes_shader
) {
1824 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1825 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, tes
);
1826 UPDATE_SHADER(EG_HW_STAGE_LS
, vs
);
1828 SET_NULL_SHADER(EG_HW_STAGE_LS
);
1829 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS
, vs
);
1834 * XXX: I believe there's some fatal flaw in the dirty state logic when
1835 * enabling/disabling tes.
1836 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1837 * it will therefore overwrite the VS slots. If it now gets disabled,
1838 * the VS needs to rebind all buffer/resource/sampler slots - not only
1839 * has TES overwritten the corresponding slots, but when the VS was
1840 * operating as LS the things with correpsonding dirty bits got bound
1841 * to LS slots and won't reflect what is dirty as VS stage even if the
1842 * TES didn't overwrite it. The story for re-enabled TES is similar.
1843 * In any case, we're not allowed to submit any TES state when
1844 * TES is disabled (the state tracker may not do this but this looks
1845 * like an optimization to me, not something which can be relied on).
1848 /* Update clip misc state. */
1849 if (clip_so_current
) {
1850 r600_update_clip_state(rctx
, clip_so_current
);
1851 rctx
->b
.streamout
.enabled_stream_buffers_mask
= clip_so_current
->enabled_stream_buffers_mask
;
1854 if (unlikely(ps_dirty
|| rctx
->hw_shader_stages
[R600_HW_STAGE_PS
].shader
!= rctx
->ps_shader
->current
||
1855 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1856 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1858 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
||
1859 rctx
->cb_misc_state
.ps_color_export_mask
!= rctx
->ps_shader
->current
->ps_color_export_mask
) {
1860 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1861 rctx
->cb_misc_state
.ps_color_export_mask
= rctx
->ps_shader
->current
->ps_color_export_mask
;
1862 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1865 if (rctx
->b
.chip_class
<= R700
) {
1866 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1868 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1869 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1870 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1874 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1875 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1876 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1878 if (rctx
->b
.chip_class
>= EVERGREEN
)
1879 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1881 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1884 r600_mark_atom_dirty(rctx
, &rctx
->shader_stages
.atom
);
1886 UPDATE_SHADER(R600_HW_STAGE_PS
, ps
);
1888 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1889 evergreen_update_db_shader_control(rctx
);
1891 r600_update_db_shader_control(rctx
);
1894 /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */
1895 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1896 evergreen_setup_scratch_buffers(rctx
);
1898 r600_setup_scratch_buffers(rctx
);
1901 /* on R600 we stuff masks + txq info into one constant buffer */
1902 /* on evergreen we only need a txq info one */
1903 if (rctx
->ps_shader
) {
1904 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1905 if (need_buf_const
) {
1906 if (rctx
->b
.chip_class
< EVERGREEN
)
1907 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1909 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1913 if (rctx
->vs_shader
) {
1914 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1915 if (need_buf_const
) {
1916 if (rctx
->b
.chip_class
< EVERGREEN
)
1917 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1919 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1923 if (rctx
->gs_shader
) {
1924 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1925 if (need_buf_const
) {
1926 if (rctx
->b
.chip_class
< EVERGREEN
)
1927 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1929 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1933 if (rctx
->tes_shader
) {
1934 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1935 need_buf_const
= rctx
->tes_shader
->current
->shader
.uses_tex_buffers
||
1936 rctx
->tes_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1937 if (need_buf_const
) {
1938 eg_setup_buffer_constants(rctx
, PIPE_SHADER_TESS_EVAL
);
1940 if (rctx
->tcs_shader
) {
1941 need_buf_const
= rctx
->tcs_shader
->current
->shader
.uses_tex_buffers
||
1942 rctx
->tcs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1943 if (need_buf_const
) {
1944 eg_setup_buffer_constants(rctx
, PIPE_SHADER_TESS_CTRL
);
1949 r600_update_driver_const_buffers(rctx
, false);
1951 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1952 if (!r600_adjust_gprs(rctx
)) {
1953 /* discard rendering */
1958 if (rctx
->b
.chip_class
== EVERGREEN
) {
1959 if (!evergreen_adjust_gprs(rctx
)) {
1960 /* discard rendering */
1965 blend_disable
= (rctx
->dual_src_blend
&&
1966 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1968 if (blend_disable
!= rctx
->force_blend_disable
) {
1969 rctx
->force_blend_disable
= blend_disable
;
1970 r600_bind_blend_state_internal(rctx
,
1971 rctx
->blend_state
.cso
,
1978 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1980 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
1981 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1983 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1984 state
->pa_cl_clip_cntl
|
1985 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1986 S_028810_CLIP_DISABLE(state
->clip_disable
));
1987 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1988 state
->pa_cl_vs_out_cntl
|
1989 (state
->clip_plane_enable
& state
->clip_dist_write
) |
1990 (state
->cull_dist_write
<< 8));
1991 /* reuse needs to be set off if we write oViewport */
1992 if (rctx
->b
.chip_class
>= EVERGREEN
)
1993 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
1994 S_028AB4_REUSE_OFF(state
->vs_out_viewport
));
1997 /* rast_prim is the primitive type after GS. */
1998 static inline void r600_emit_rasterizer_prim_state(struct r600_context
*rctx
)
2000 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2001 enum pipe_prim_type rast_prim
= rctx
->current_rast_prim
;
2003 /* Skip this if not rendering lines. */
2004 if (rast_prim
!= PIPE_PRIM_LINES
&&
2005 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
2006 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
2007 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
2008 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
2011 if (rast_prim
== rctx
->last_rast_prim
)
2014 /* For lines, reset the stipple pattern at each primitive. Otherwise,
2015 * reset the stipple pattern at each packet (line strips, line loops).
2017 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
2018 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2) |
2019 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
2020 rctx
->last_rast_prim
= rast_prim
;
2023 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
2025 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2026 struct pipe_resource
*indexbuf
= info
->has_user_indices
? NULL
: info
->index
.resource
;
2027 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2028 bool render_cond_bit
= rctx
->b
.render_cond
&& !rctx
->b
.render_cond_force_off
;
2029 bool has_user_indices
= info
->has_user_indices
;
2031 unsigned num_patches
, dirty_tex_counter
, index_offset
= 0;
2032 unsigned index_size
= info
->index_size
;
2034 struct r600_shader_atomic combined_atomics
[8];
2035 uint8_t atomic_used_mask
;
2037 if (!info
->indirect
&& !info
->count
&& (index_size
|| !info
->count_from_stream_output
)) {
2041 if (unlikely(!rctx
->vs_shader
)) {
2045 if (unlikely(!rctx
->ps_shader
&&
2046 (!rctx
->rasterizer
|| !rctx
->rasterizer
->rasterizer_discard
))) {
2051 /* make sure that the gfx ring is only one active */
2052 if (radeon_emitted(rctx
->b
.dma
.cs
, 0)) {
2053 rctx
->b
.dma
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
2056 if (rctx
->cmd_buf_is_compute
) {
2057 rctx
->b
.gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
2058 rctx
->cmd_buf_is_compute
= false;
2061 /* Re-emit the framebuffer state if needed. */
2062 dirty_tex_counter
= p_atomic_read(&rctx
->b
.screen
->dirty_tex_counter
);
2063 if (unlikely(dirty_tex_counter
!= rctx
->b
.last_dirty_tex_counter
)) {
2064 rctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
2065 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
2066 rctx
->framebuffer
.do_update_surf_dirtiness
= true;
2069 if (rctx
->gs_shader
) {
2070 /* Determine whether the GS triangle strip adjacency fix should
2071 * be applied. Rotate every other triangle if
2072 * - triangle strips with adjacency are fed to the GS and
2073 * - primitive restart is disabled (the rotation doesn't help
2074 * when the restart occurs after an odd number of triangles).
2076 bool gs_tri_strip_adj_fix
=
2077 !rctx
->tes_shader
&&
2078 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
2079 !info
->primitive_restart
;
2080 if (gs_tri_strip_adj_fix
!= rctx
->gs_tri_strip_adj_fix
)
2081 rctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
2083 if (!r600_update_derived_state(rctx
)) {
2084 /* useless to render because current rendering command
2090 rctx
->current_rast_prim
= (rctx
->gs_shader
)? rctx
->gs_shader
->gs_output_prim
2091 : (rctx
->tes_shader
)? rctx
->tes_shader
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
]
2094 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2095 evergreen_emit_atomic_buffer_setup_count(rctx
, NULL
, combined_atomics
, &atomic_used_mask
);
2099 index_offset
+= info
->start
* index_size
;
2101 /* Translate 8-bit indices to 16-bit. */
2102 if (unlikely(index_size
== 1)) {
2103 struct pipe_resource
*out_buffer
= NULL
;
2104 unsigned out_offset
;
2106 unsigned start
, count
;
2108 if (likely(!info
->indirect
)) {
2110 count
= info
->count
;
2113 /* Have to get start/count from indirect buffer, slow path ahead... */
2114 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
->indirect
->buffer
;
2115 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
2116 PIPE_TRANSFER_READ
);
2118 data
+= info
->indirect
->offset
/ sizeof(unsigned);
2119 start
= data
[2] * index_size
;
2128 u_upload_alloc(ctx
->stream_uploader
, start
, count
* 2,
2129 256, &out_offset
, &out_buffer
, &ptr
);
2133 util_shorten_ubyte_elts_to_userptr(
2134 &rctx
->b
.b
, info
, 0, 0, index_offset
, count
, ptr
);
2136 indexbuf
= out_buffer
;
2137 index_offset
= out_offset
;
2139 has_user_indices
= false;
2142 /* Upload the index buffer.
2143 * The upload is skipped for small index counts on little-endian machines
2144 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2145 * Indirect draws never use immediate indices.
2146 * Note: Instanced rendering in combination with immediate indices hangs. */
2147 if (has_user_indices
&& (R600_BIG_ENDIAN
|| info
->indirect
||
2148 info
->instance_count
> 1 ||
2149 info
->count
*index_size
> 20)) {
2151 u_upload_data(ctx
->stream_uploader
, 0,
2152 info
->count
* index_size
, 256,
2153 info
->index
.user
, &index_offset
, &indexbuf
);
2154 has_user_indices
= false;
2156 index_bias
= info
->index_bias
;
2158 index_bias
= info
->start
;
2161 /* Set the index offset and primitive restart. */
2162 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
->primitive_restart
||
2163 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
->restart_index
||
2164 rctx
->vgt_state
.vgt_indx_offset
!= index_bias
||
2165 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
->indirect
)) {
2166 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
->primitive_restart
;
2167 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
->restart_index
;
2168 rctx
->vgt_state
.vgt_indx_offset
= index_bias
;
2169 r600_mark_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
2172 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2173 if (rctx
->b
.chip_class
== R600
) {
2174 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
2175 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
2178 if (rctx
->b
.chip_class
>= EVERGREEN
)
2179 evergreen_setup_tess_constants(rctx
, info
, &num_patches
);
2182 r600_need_cs_space(rctx
, has_user_indices
? 5 : 0, TRUE
, util_bitcount(atomic_used_mask
));
2183 r600_flush_emit(rctx
);
2185 mask
= rctx
->dirty_atoms
;
2187 r600_emit_atom(rctx
, rctx
->atoms
[u_bit_scan64(&mask
)]);
2190 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2191 evergreen_emit_atomic_buffer_setup(rctx
, false, combined_atomics
, atomic_used_mask
);
2194 if (rctx
->b
.chip_class
== CAYMAN
) {
2195 /* Copied from radeonsi. */
2196 unsigned primgroup_size
= 128; /* recommended without a GS */
2197 bool ia_switch_on_eop
= false;
2198 bool partial_vs_wave
= false;
2200 if (rctx
->gs_shader
)
2201 primgroup_size
= 64; /* recommended with a GS */
2203 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
2204 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
2205 ia_switch_on_eop
= true;
2208 if (r600_get_strmout_en(&rctx
->b
))
2209 partial_vs_wave
= true;
2211 radeon_set_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
2212 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
2213 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
2214 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
2217 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2218 uint32_t ls_hs_config
= evergreen_get_ls_hs_config(rctx
, info
,
2221 evergreen_set_ls_hs_config(rctx
, cs
, ls_hs_config
);
2222 evergreen_set_lds_alloc(rctx
, cs
, rctx
->lds_alloc
);
2225 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2226 * even though it should have no effect on those. */
2227 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
2228 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
2229 unsigned prim
= info
->mode
;
2231 if (rctx
->gs_shader
) {
2232 prim
= rctx
->gs_shader
->gs_output_prim
;
2234 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
2236 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
2237 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
2238 info
->mode
== R600_PRIM_RECTANGLE_LIST
) {
2239 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
2241 radeon_set_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
2244 /* Update start instance. */
2245 if (!info
->indirect
&& rctx
->last_start_instance
!= info
->start_instance
) {
2246 radeon_set_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
2247 rctx
->last_start_instance
= info
->start_instance
;
2250 /* Update the primitive type. */
2251 if (rctx
->last_primitive_type
!= info
->mode
) {
2252 r600_emit_rasterizer_prim_state(rctx
);
2253 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
2254 r600_conv_pipe_prim(info
->mode
));
2256 rctx
->last_primitive_type
= info
->mode
;
2260 if (likely(!info
->indirect
)) {
2261 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
2262 radeon_emit(cs
, info
->instance_count
);
2264 uint64_t va
= r600_resource(info
->indirect
->buffer
)->gpu_address
;
2265 assert(rctx
->b
.chip_class
>= EVERGREEN
);
2267 // Invalidate so non-indirect draw calls reset this state
2268 rctx
->vgt_state
.last_draw_was_indirect
= true;
2269 rctx
->last_start_instance
= -1;
2271 radeon_emit(cs
, PKT3(EG_PKT3_SET_BASE
, 2, 0));
2272 radeon_emit(cs
, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
);
2273 radeon_emit(cs
, va
);
2274 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2276 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2277 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2278 (struct r600_resource
*)info
->indirect
->buffer
,
2280 RADEON_PRIO_DRAW_INDIRECT
));
2284 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2285 radeon_emit(cs
, index_size
== 4 ?
2286 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
2287 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0)));
2289 if (has_user_indices
) {
2290 unsigned size_bytes
= info
->count
*index_size
;
2291 unsigned size_dw
= align(size_bytes
, 4) / 4;
2292 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, render_cond_bit
));
2293 radeon_emit(cs
, info
->count
);
2294 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_IMMEDIATE
);
2295 radeon_emit_array(cs
, info
->index
.user
, size_dw
);
2297 uint64_t va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
2299 if (likely(!info
->indirect
)) {
2300 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX
, 3, render_cond_bit
));
2301 radeon_emit(cs
, va
);
2302 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2303 radeon_emit(cs
, info
->count
);
2304 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2305 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2306 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2307 (struct r600_resource
*)indexbuf
,
2309 RADEON_PRIO_INDEX_BUFFER
));
2312 uint32_t max_size
= (indexbuf
->width0
- index_offset
) / index_size
;
2314 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BASE
, 1, 0));
2315 radeon_emit(cs
, va
);
2316 radeon_emit(cs
, (va
>> 32UL) & 0xFF);
2318 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2319 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2320 (struct r600_resource
*)indexbuf
,
2322 RADEON_PRIO_INDEX_BUFFER
));
2324 radeon_emit(cs
, PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2325 radeon_emit(cs
, max_size
);
2327 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, render_cond_bit
));
2328 radeon_emit(cs
, info
->indirect
->offset
);
2329 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
2333 if (unlikely(info
->count_from_stream_output
)) {
2334 struct r600_so_target
*t
= (struct r600_so_target
*)info
->count_from_stream_output
;
2335 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
2337 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
2339 radeon_emit(cs
, PKT3(PKT3_COPY_DW
, 4, 0));
2340 radeon_emit(cs
, COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
);
2341 radeon_emit(cs
, va
& 0xFFFFFFFFUL
); /* src address lo */
2342 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
); /* src address hi */
2343 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2); /* dst register */
2344 radeon_emit(cs
, 0); /* unused */
2346 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2347 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
,
2348 t
->buf_filled_size
, RADEON_USAGE_READ
,
2349 RADEON_PRIO_SO_FILLED_SIZE
));
2352 if (likely(!info
->indirect
)) {
2353 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
2354 radeon_emit(cs
, info
->count
);
2357 radeon_emit(cs
, PKT3(EG_PKT3_DRAW_INDIRECT
, 1, render_cond_bit
));
2358 radeon_emit(cs
, info
->indirect
->offset
);
2360 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
2361 (info
->count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0));
2364 /* SMX returns CONTEXT_DONE too early workaround */
2365 if (rctx
->b
.family
== CHIP_R600
||
2366 rctx
->b
.family
== CHIP_RV610
||
2367 rctx
->b
.family
== CHIP_RV630
||
2368 rctx
->b
.family
== CHIP_RV635
) {
2369 /* if we have gs shader or streamout
2370 we need to do a wait idle after every draw */
2371 if (rctx
->gs_shader
|| r600_get_strmout_en(&rctx
->b
)) {
2372 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2376 /* ES ring rolling over at EOP - workaround */
2377 if (rctx
->b
.chip_class
== R600
) {
2378 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2379 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT
));
2383 if (rctx
->b
.chip_class
>= EVERGREEN
)
2384 evergreen_emit_atomic_buffer_save(rctx
, false, combined_atomics
, &atomic_used_mask
);
2386 if (rctx
->trace_buf
)
2387 eg_trace_emit(rctx
);
2389 if (rctx
->framebuffer
.do_update_surf_dirtiness
) {
2390 /* Set the depth buffer as dirty. */
2391 if (rctx
->framebuffer
.state
.zsbuf
) {
2392 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
2393 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2395 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2397 if (rtex
->surface
.has_stencil
)
2398 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2400 if (rctx
->framebuffer
.compressed_cb_mask
) {
2401 struct pipe_surface
*surf
;
2402 struct r600_texture
*rtex
;
2403 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
2406 unsigned i
= u_bit_scan(&mask
);
2407 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
2408 rtex
= (struct r600_texture
*)surf
->texture
;
2410 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2414 rctx
->framebuffer
.do_update_surf_dirtiness
= false;
2417 if (index_size
&& indexbuf
!= info
->index
.resource
)
2418 pipe_resource_reference(&indexbuf
, NULL
);
2419 rctx
->b
.num_draw_calls
++;
2422 uint32_t r600_translate_stencil_op(int s_op
)
2425 case PIPE_STENCIL_OP_KEEP
:
2426 return V_028800_STENCIL_KEEP
;
2427 case PIPE_STENCIL_OP_ZERO
:
2428 return V_028800_STENCIL_ZERO
;
2429 case PIPE_STENCIL_OP_REPLACE
:
2430 return V_028800_STENCIL_REPLACE
;
2431 case PIPE_STENCIL_OP_INCR
:
2432 return V_028800_STENCIL_INCR
;
2433 case PIPE_STENCIL_OP_DECR
:
2434 return V_028800_STENCIL_DECR
;
2435 case PIPE_STENCIL_OP_INCR_WRAP
:
2436 return V_028800_STENCIL_INCR_WRAP
;
2437 case PIPE_STENCIL_OP_DECR_WRAP
:
2438 return V_028800_STENCIL_DECR_WRAP
;
2439 case PIPE_STENCIL_OP_INVERT
:
2440 return V_028800_STENCIL_INVERT
;
2442 R600_ERR("Unknown stencil op %d", s_op
);
2449 uint32_t r600_translate_fill(uint32_t func
)
2452 case PIPE_POLYGON_MODE_FILL
:
2454 case PIPE_POLYGON_MODE_LINE
:
2456 case PIPE_POLYGON_MODE_POINT
:
2464 unsigned r600_tex_wrap(unsigned wrap
)
2468 case PIPE_TEX_WRAP_REPEAT
:
2469 return V_03C000_SQ_TEX_WRAP
;
2470 case PIPE_TEX_WRAP_CLAMP
:
2471 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
2472 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
2473 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
2474 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
2475 return V_03C000_SQ_TEX_CLAMP_BORDER
;
2476 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
2477 return V_03C000_SQ_TEX_MIRROR
;
2478 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
2479 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
2480 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
2481 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
2482 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
2483 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
2487 unsigned r600_tex_mipfilter(unsigned filter
)
2490 case PIPE_TEX_MIPFILTER_NEAREST
:
2491 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
2492 case PIPE_TEX_MIPFILTER_LINEAR
:
2493 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
2495 case PIPE_TEX_MIPFILTER_NONE
:
2496 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
2500 unsigned r600_tex_compare(unsigned compare
)
2504 case PIPE_FUNC_NEVER
:
2505 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
2506 case PIPE_FUNC_LESS
:
2507 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
2508 case PIPE_FUNC_EQUAL
:
2509 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
2510 case PIPE_FUNC_LEQUAL
:
2511 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
2512 case PIPE_FUNC_GREATER
:
2513 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
2514 case PIPE_FUNC_NOTEQUAL
:
2515 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
2516 case PIPE_FUNC_GEQUAL
:
2517 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
2518 case PIPE_FUNC_ALWAYS
:
2519 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
2523 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2525 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2526 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2528 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2529 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2532 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2534 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2535 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2537 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2538 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2539 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2540 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2541 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2544 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2547 struct radeon_cmdbuf
*cs
= rctx
->b
.gfx
.cs
;
2548 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
2553 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
2554 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2555 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->bo
,
2556 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
));
2559 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
2560 const unsigned char *swizzle_view
,
2564 unsigned char swizzle
[4];
2565 unsigned result
= 0;
2566 const uint32_t tex_swizzle_shift
[4] = {
2569 const uint32_t vtx_swizzle_shift
[4] = {
2572 const uint32_t swizzle_bit
[4] = {
2575 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
2578 swizzle_shift
= vtx_swizzle_shift
;
2581 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
2583 memcpy(swizzle
, swizzle_format
, 4);
2587 for (i
= 0; i
< 4; i
++) {
2588 switch (swizzle
[i
]) {
2589 case PIPE_SWIZZLE_Y
:
2590 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
2592 case PIPE_SWIZZLE_Z
:
2593 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
2595 case PIPE_SWIZZLE_W
:
2596 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
2598 case PIPE_SWIZZLE_0
:
2599 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
2601 case PIPE_SWIZZLE_1
:
2602 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
2604 default: /* PIPE_SWIZZLE_X */
2605 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
2611 /* texture format translate */
2612 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
2613 enum pipe_format format
,
2614 const unsigned char *swizzle_view
,
2615 uint32_t *word4_p
, uint32_t *yuv_format_p
,
2616 bool do_endian_swap
)
2618 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
2619 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
2620 const struct util_format_description
*desc
;
2621 boolean uniform
= TRUE
;
2622 bool is_srgb_valid
= FALSE
;
2623 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2624 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2625 const unsigned char swizzle_xxxy
[4] = {0, 0, 0, 1};
2626 const unsigned char swizzle_zyx1
[4] = {2, 1, 0, 5};
2627 const unsigned char swizzle_zyxw
[4] = {2, 1, 0, 3};
2630 const uint32_t sign_bit
[4] = {
2631 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
2632 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
2633 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
2634 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
2637 /* Need to replace the specified texture formats in case of big-endian.
2638 * These formats are formats that have channels with number of bits
2639 * not divisible by 8.
2640 * Mesa conversion functions don't swap bits for those formats, and because
2641 * we transmit this over a serial bus to the GPU (PCIe), the
2642 * bit-endianess is important!!!
2643 * In case we have an "opposite" format, just use that for the swizzling
2644 * information. If we don't have such an "opposite" format, we need
2645 * to use a fixed swizzle info instead (see below)
2647 if (format
== PIPE_FORMAT_R4A4_UNORM
&& do_endian_swap
)
2648 format
= PIPE_FORMAT_A4R4_UNORM
;
2650 desc
= util_format_description(format
);
2654 /* Depth and stencil swizzling is handled separately. */
2655 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
2656 /* Need to check for specific texture formats that don't have
2657 * an "opposite" format we can use. For those formats, we directly
2658 * specify the swizzling, which is the LE swizzling as defined in
2661 if (do_endian_swap
) {
2662 if (format
== PIPE_FORMAT_L4A4_UNORM
)
2663 word4
|= r600_get_swizzle_combined(swizzle_xxxy
, swizzle_view
, FALSE
);
2664 else if (format
== PIPE_FORMAT_B4G4R4A4_UNORM
)
2665 word4
|= r600_get_swizzle_combined(swizzle_zyxw
, swizzle_view
, FALSE
);
2666 else if (format
== PIPE_FORMAT_B4G4R4X4_UNORM
|| format
== PIPE_FORMAT_B5G6R5_UNORM
)
2667 word4
|= r600_get_swizzle_combined(swizzle_zyx1
, swizzle_view
, FALSE
);
2669 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2671 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
2675 /* Colorspace (return non-RGB formats directly). */
2676 switch (desc
->colorspace
) {
2677 /* Depth stencil formats */
2678 case UTIL_FORMAT_COLORSPACE_ZS
:
2680 /* Depth sampler formats. */
2681 case PIPE_FORMAT_Z16_UNORM
:
2682 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2685 case PIPE_FORMAT_Z24X8_UNORM
:
2686 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2687 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2690 case PIPE_FORMAT_X8Z24_UNORM
:
2691 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2692 if (rscreen
->b
.chip_class
< EVERGREEN
)
2694 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2697 case PIPE_FORMAT_Z32_FLOAT
:
2698 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2699 result
= FMT_32_FLOAT
;
2701 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2702 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2703 result
= FMT_X24_8_32_FLOAT
;
2705 /* Stencil sampler formats. */
2706 case PIPE_FORMAT_S8_UINT
:
2707 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2708 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2711 case PIPE_FORMAT_X24S8_UINT
:
2712 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2713 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2716 case PIPE_FORMAT_S8X24_UINT
:
2717 if (rscreen
->b
.chip_class
< EVERGREEN
)
2719 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2720 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
2723 case PIPE_FORMAT_X32_S8X24_UINT
:
2724 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2725 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
2726 result
= FMT_X24_8_32_FLOAT
;
2732 case UTIL_FORMAT_COLORSPACE_YUV
:
2733 yuv_format
|= (1 << 30);
2735 case PIPE_FORMAT_UYVY
:
2736 case PIPE_FORMAT_YUYV
:
2740 goto out_unknown
; /* XXX */
2742 case UTIL_FORMAT_COLORSPACE_SRGB
:
2743 word4
|= S_038010_FORCE_DEGAMMA(1);
2750 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
2752 case PIPE_FORMAT_RGTC1_SNORM
:
2753 case PIPE_FORMAT_LATC1_SNORM
:
2754 word4
|= sign_bit
[0];
2755 case PIPE_FORMAT_RGTC1_UNORM
:
2756 case PIPE_FORMAT_LATC1_UNORM
:
2759 case PIPE_FORMAT_RGTC2_SNORM
:
2760 case PIPE_FORMAT_LATC2_SNORM
:
2761 word4
|= sign_bit
[0] | sign_bit
[1];
2762 case PIPE_FORMAT_RGTC2_UNORM
:
2763 case PIPE_FORMAT_LATC2_UNORM
:
2771 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2773 case PIPE_FORMAT_DXT1_RGB
:
2774 case PIPE_FORMAT_DXT1_RGBA
:
2775 case PIPE_FORMAT_DXT1_SRGB
:
2776 case PIPE_FORMAT_DXT1_SRGBA
:
2778 is_srgb_valid
= TRUE
;
2780 case PIPE_FORMAT_DXT3_RGBA
:
2781 case PIPE_FORMAT_DXT3_SRGBA
:
2783 is_srgb_valid
= TRUE
;
2785 case PIPE_FORMAT_DXT5_RGBA
:
2786 case PIPE_FORMAT_DXT5_SRGBA
:
2788 is_srgb_valid
= TRUE
;
2795 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2796 if (rscreen
->b
.chip_class
< EVERGREEN
)
2800 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2801 case PIPE_FORMAT_BPTC_SRGBA
:
2803 is_srgb_valid
= TRUE
;
2805 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2806 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2808 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2816 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2818 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2819 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2822 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2823 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2831 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2832 result
= FMT_5_9_9_9_SHAREDEXP
;
2834 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2835 result
= FMT_10_11_11_FLOAT
;
2840 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2841 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2842 word4
|= sign_bit
[i
];
2846 /* R8G8Bx_SNORM - XXX CxV8U8 */
2848 /* See whether the components are of the same size. */
2849 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2850 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2853 /* Non-uniform formats. */
2855 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2856 desc
->channel
[0].pure_integer
)
2857 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2858 switch(desc
->nr_channels
) {
2860 if (desc
->channel
[0].size
== 5 &&
2861 desc
->channel
[1].size
== 6 &&
2862 desc
->channel
[2].size
== 5) {
2868 if (desc
->channel
[0].size
== 5 &&
2869 desc
->channel
[1].size
== 5 &&
2870 desc
->channel
[2].size
== 5 &&
2871 desc
->channel
[3].size
== 1) {
2872 result
= FMT_1_5_5_5
;
2875 if (desc
->channel
[0].size
== 10 &&
2876 desc
->channel
[1].size
== 10 &&
2877 desc
->channel
[2].size
== 10 &&
2878 desc
->channel
[3].size
== 2) {
2879 result
= FMT_2_10_10_10
;
2887 /* Find the first non-VOID channel. */
2888 for (i
= 0; i
< 4; i
++) {
2889 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2897 /* uniform formats */
2898 switch (desc
->channel
[i
].type
) {
2899 case UTIL_FORMAT_TYPE_UNSIGNED
:
2900 case UTIL_FORMAT_TYPE_SIGNED
:
2902 if (!desc
->channel
[i
].normalized
&&
2903 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2907 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2908 desc
->channel
[i
].pure_integer
)
2909 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2911 switch (desc
->channel
[i
].size
) {
2913 switch (desc
->nr_channels
) {
2918 result
= FMT_4_4_4_4
;
2923 switch (desc
->nr_channels
) {
2926 is_srgb_valid
= TRUE
;
2932 result
= FMT_8_8_8_8
;
2933 is_srgb_valid
= TRUE
;
2938 switch (desc
->nr_channels
) {
2946 result
= FMT_16_16_16_16
;
2951 switch (desc
->nr_channels
) {
2959 result
= FMT_32_32_32_32
;
2965 case UTIL_FORMAT_TYPE_FLOAT
:
2966 switch (desc
->channel
[i
].size
) {
2968 switch (desc
->nr_channels
) {
2970 result
= FMT_16_FLOAT
;
2973 result
= FMT_16_16_FLOAT
;
2976 result
= FMT_16_16_16_16_FLOAT
;
2981 switch (desc
->nr_channels
) {
2983 result
= FMT_32_FLOAT
;
2986 result
= FMT_32_32_FLOAT
;
2989 result
= FMT_32_32_32_32_FLOAT
;
2998 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
3003 *yuv_format_p
= yuv_format
;
3006 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
3010 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
3011 bool do_endian_swap
)
3013 const struct util_format_description
*desc
= util_format_description(format
);
3014 int channel
= util_format_get_first_non_void_channel(format
);
3019 #define HAS_SIZE(x,y,z,w) \
3020 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
3021 desc->channel[2].size == (z) && desc->channel[3].size == (w))
3023 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
3024 return V_0280A0_COLOR_10_11_11_FLOAT
;
3026 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
3030 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
3032 switch (desc
->nr_channels
) {
3034 switch (desc
->channel
[0].size
) {
3036 return V_0280A0_COLOR_8
;
3039 return V_0280A0_COLOR_16_FLOAT
;
3041 return V_0280A0_COLOR_16
;
3044 return V_0280A0_COLOR_32_FLOAT
;
3046 return V_0280A0_COLOR_32
;
3050 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
3051 switch (desc
->channel
[0].size
) {
3054 return V_0280A0_COLOR_4_4
;
3056 return ~0U; /* removed on Evergreen */
3058 return V_0280A0_COLOR_8_8
;
3061 return V_0280A0_COLOR_16_16_FLOAT
;
3063 return V_0280A0_COLOR_16_16
;
3066 return V_0280A0_COLOR_32_32_FLOAT
;
3068 return V_0280A0_COLOR_32_32
;
3070 } else if (HAS_SIZE(8,24,0,0)) {
3071 return (do_endian_swap
? V_0280A0_COLOR_8_24
: V_0280A0_COLOR_24_8
);
3072 } else if (HAS_SIZE(24,8,0,0)) {
3073 return V_0280A0_COLOR_8_24
;
3077 if (HAS_SIZE(5,6,5,0)) {
3078 return V_0280A0_COLOR_5_6_5
;
3079 } else if (HAS_SIZE(32,8,24,0)) {
3080 return V_0280A0_COLOR_X24_8_32_FLOAT
;
3084 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
3085 desc
->channel
[0].size
== desc
->channel
[2].size
&&
3086 desc
->channel
[0].size
== desc
->channel
[3].size
) {
3087 switch (desc
->channel
[0].size
) {
3089 return V_0280A0_COLOR_4_4_4_4
;
3091 return V_0280A0_COLOR_8_8_8_8
;
3094 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
3096 return V_0280A0_COLOR_16_16_16_16
;
3099 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
3101 return V_0280A0_COLOR_32_32_32_32
;
3103 } else if (HAS_SIZE(5,5,5,1)) {
3104 return V_0280A0_COLOR_1_5_5_5
;
3105 } else if (HAS_SIZE(10,10,10,2)) {
3106 return V_0280A0_COLOR_2_10_10_10
;
3113 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
)
3115 if (R600_BIG_ENDIAN
) {
3116 switch(colorformat
) {
3117 /* 8-bit buffers. */
3118 case V_0280A0_COLOR_4_4
:
3119 case V_0280A0_COLOR_8
:
3122 /* 16-bit buffers. */
3123 case V_0280A0_COLOR_8_8
:
3125 * No need to do endian swaps on array formats,
3126 * as mesa<-->pipe formats conversion take into account
3131 case V_0280A0_COLOR_5_6_5
:
3132 case V_0280A0_COLOR_1_5_5_5
:
3133 case V_0280A0_COLOR_4_4_4_4
:
3134 case V_0280A0_COLOR_16
:
3135 return (do_endian_swap
? ENDIAN_8IN16
: ENDIAN_NONE
);
3137 /* 32-bit buffers. */
3138 case V_0280A0_COLOR_8_8_8_8
:
3140 * No need to do endian swaps on array formats,
3141 * as mesa<-->pipe formats conversion take into account
3146 case V_0280A0_COLOR_2_10_10_10
:
3147 case V_0280A0_COLOR_8_24
:
3148 case V_0280A0_COLOR_24_8
:
3149 case V_0280A0_COLOR_32_FLOAT
:
3150 return (do_endian_swap
? ENDIAN_8IN32
: ENDIAN_NONE
);
3152 case V_0280A0_COLOR_16_16_FLOAT
:
3153 case V_0280A0_COLOR_16_16
:
3154 return ENDIAN_8IN16
;
3156 /* 64-bit buffers. */
3157 case V_0280A0_COLOR_16_16_16_16
:
3158 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
3159 return ENDIAN_8IN16
;
3161 case V_0280A0_COLOR_32_32_FLOAT
:
3162 case V_0280A0_COLOR_32_32
:
3163 case V_0280A0_COLOR_X24_8_32_FLOAT
:
3164 return ENDIAN_8IN32
;
3166 /* 128-bit buffers. */
3167 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
3168 case V_0280A0_COLOR_32_32_32_32
:
3169 return ENDIAN_8IN32
;
3171 return ENDIAN_NONE
; /* Unsupported. */
3178 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
3180 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3181 struct r600_resource
*rbuffer
= r600_resource(buf
);
3182 unsigned i
, shader
, mask
;
3183 struct r600_pipe_sampler_view
*view
;
3185 /* Reallocate the buffer in the same pipe_resource. */
3186 r600_alloc_resource(&rctx
->screen
->b
, rbuffer
);
3188 /* We changed the buffer, now we need to bind it where the old one was bound. */
3189 /* Vertex buffers. */
3190 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
3192 i
= u_bit_scan(&mask
);
3193 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
.resource
== &rbuffer
->b
.b
) {
3194 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
3195 r600_vertex_buffers_dirty(rctx
);
3198 /* Streamout buffers. */
3199 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
3200 if (rctx
->b
.streamout
.targets
[i
] &&
3201 rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
3202 if (rctx
->b
.streamout
.begin_emitted
) {
3203 r600_emit_streamout_end(&rctx
->b
);
3205 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
3206 r600_streamout_buffers_dirty(&rctx
->b
);
3210 /* Constant buffers. */
3211 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3212 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
3214 uint32_t mask
= state
->enabled_mask
;
3217 unsigned i
= u_bit_scan(&mask
);
3218 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
3220 state
->dirty_mask
|= 1 << i
;
3224 r600_constant_buffers_dirty(rctx
, state
);
3228 /* Texture buffer objects - update the virtual addresses in descriptors. */
3229 LIST_FOR_EACH_ENTRY(view
, &rctx
->texture_buffers
, list
) {
3230 if (view
->base
.texture
== &rbuffer
->b
.b
) {
3231 uint64_t offset
= view
->base
.u
.buf
.offset
;
3232 uint64_t va
= rbuffer
->gpu_address
+ offset
;
3234 view
->tex_resource_words
[0] = va
;
3235 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
3236 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
3239 /* Texture buffer objects - make bindings dirty if needed. */
3240 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
3241 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
3243 uint32_t mask
= state
->enabled_mask
;
3246 unsigned i
= u_bit_scan(&mask
);
3247 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
3249 state
->dirty_mask
|= 1 << i
;
3253 r600_sampler_views_dirty(rctx
, state
);
3258 struct r600_image_state
*istate
= &rctx
->fragment_buffers
;
3260 uint32_t mask
= istate
->enabled_mask
;
3263 unsigned i
= u_bit_scan(&mask
);
3264 if (istate
->views
[i
].base
.resource
== &rbuffer
->b
.b
) {
3266 istate
->dirty_mask
|= 1 << i
;
3270 r600_mark_atom_dirty(rctx
, &istate
->atom
);
3276 static void r600_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
3278 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3280 /* Pipeline stat & streamout queries. */
3282 rctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
3283 rctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
3285 rctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
3286 rctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
3289 /* Occlusion queries. */
3290 if (rctx
->db_misc_state
.occlusion_queries_disabled
!= !enable
) {
3291 rctx
->db_misc_state
.occlusion_queries_disabled
= !enable
;
3292 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
3296 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3297 bool include_draw_vbo
)
3299 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
, 0);
3302 /* keep this at the end of this file, please */
3303 void r600_init_common_state_functions(struct r600_context
*rctx
)
3305 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
3306 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
3307 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
3308 rctx
->b
.b
.create_tcs_state
= r600_create_tcs_state
;
3309 rctx
->b
.b
.create_tes_state
= r600_create_tes_state
;
3310 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
3311 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
3312 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
3313 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
3314 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
3315 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
3316 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
3317 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
3318 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
3319 rctx
->b
.b
.bind_tcs_state
= r600_bind_tcs_state
;
3320 rctx
->b
.b
.bind_tes_state
= r600_bind_tes_state
;
3321 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
3322 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
3323 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
3324 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
3325 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
3326 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
3327 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
3328 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
3329 rctx
->b
.b
.delete_tcs_state
= r600_delete_tcs_state
;
3330 rctx
->b
.b
.delete_tes_state
= r600_delete_tes_state
;
3331 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
3332 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
3333 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
3334 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
3335 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
3336 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
3337 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
3338 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
3339 rctx
->b
.b
.memory_barrier
= r600_memory_barrier
;
3340 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
3341 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
3342 rctx
->b
.b
.set_active_query_state
= r600_set_active_query_state
;
3344 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
3345 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
3346 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;