2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "tgsi/tgsi_parse.h"
38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
40 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
43 cb
->buf
= CALLOC(1, 4 * num_dw
);
44 cb
->max_num_dw
= num_dw
;
47 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
52 void r600_init_atom(struct r600_context
*rctx
,
53 struct r600_atom
*atom
,
55 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
58 assert(id
< R600_NUM_ATOMS
);
59 assert(rctx
->atoms
[id
] == NULL
);
60 rctx
->atoms
[id
] = atom
;
63 atom
->num_dw
= num_dw
;
67 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
69 r600_emit_command_buffer(rctx
->rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
72 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
74 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
75 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
76 unsigned alpha_ref
= a
->sx_alpha_ref
;
78 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
82 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
83 a
->sx_alpha_test_control
|
84 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
85 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
88 static void r600_texture_barrier(struct pipe_context
*ctx
)
90 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
92 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
93 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
94 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
97 static unsigned r600_conv_pipe_prim(unsigned prim
)
99 static const unsigned prim_conv
[] = {
100 V_008958_DI_PT_POINTLIST
,
101 V_008958_DI_PT_LINELIST
,
102 V_008958_DI_PT_LINELOOP
,
103 V_008958_DI_PT_LINESTRIP
,
104 V_008958_DI_PT_TRILIST
,
105 V_008958_DI_PT_TRISTRIP
,
106 V_008958_DI_PT_TRIFAN
,
107 V_008958_DI_PT_QUADLIST
,
108 V_008958_DI_PT_QUADSTRIP
,
109 V_008958_DI_PT_POLYGON
,
110 V_008958_DI_PT_LINELIST_ADJ
,
111 V_008958_DI_PT_LINESTRIP_ADJ
,
112 V_008958_DI_PT_TRILIST_ADJ
,
113 V_008958_DI_PT_TRISTRIP_ADJ
,
114 V_008958_DI_PT_RECTLIST
116 return prim_conv
[prim
];
119 /* common state between evergreen and r600 */
121 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
122 struct r600_blend_state
*blend
, bool blend_disable
)
124 unsigned color_control
;
125 bool update_cb
= false;
127 rctx
->alpha_to_one
= blend
->alpha_to_one
;
128 rctx
->dual_src_blend
= blend
->dual_src_blend
;
130 if (!blend_disable
) {
131 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
132 color_control
= blend
->cb_color_control
;
134 /* Blending is disabled. */
135 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
136 color_control
= blend
->cb_color_control_no_blend
;
139 /* Update derived states. */
140 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
141 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
144 if (rctx
->chip_class
<= R700
&&
145 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
146 rctx
->cb_misc_state
.cb_color_control
= color_control
;
149 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
150 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
154 rctx
->cb_misc_state
.atom
.dirty
= true;
158 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
160 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
161 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
166 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
169 static void r600_set_blend_color(struct pipe_context
*ctx
,
170 const struct pipe_blend_color
*state
)
172 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
174 rctx
->blend_color
.state
= *state
;
175 rctx
->blend_color
.atom
.dirty
= true;
178 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
180 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
181 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
183 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
184 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
185 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
186 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
187 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
190 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
192 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
193 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
195 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
196 r600_write_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
197 r600_write_value(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
198 r600_write_value(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
201 static void r600_set_clip_state(struct pipe_context
*ctx
,
202 const struct pipe_clip_state
*state
)
204 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
205 struct pipe_constant_buffer cb
;
207 rctx
->clip_state
.state
= *state
;
208 rctx
->clip_state
.atom
.dirty
= true;
211 cb
.user_buffer
= state
->ucp
;
212 cb
.buffer_offset
= 0;
213 cb
.buffer_size
= 4*4*8;
214 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
215 pipe_resource_reference(&cb
.buffer
, NULL
);
218 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
219 const struct r600_stencil_ref
*state
)
221 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
223 rctx
->stencil_ref
.state
= *state
;
224 rctx
->stencil_ref
.atom
.dirty
= true;
227 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
229 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
230 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
232 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
233 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
234 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
235 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
236 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
237 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
238 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
239 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
240 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
243 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
244 const struct pipe_stencil_ref
*state
)
246 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
247 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
248 struct r600_stencil_ref ref
;
250 rctx
->stencil_ref
.pipe_state
= *state
;
255 ref
.ref_value
[0] = state
->ref_value
[0];
256 ref
.ref_value
[1] = state
->ref_value
[1];
257 ref
.valuemask
[0] = dsa
->valuemask
[0];
258 ref
.valuemask
[1] = dsa
->valuemask
[1];
259 ref
.writemask
[0] = dsa
->writemask
[0];
260 ref
.writemask
[1] = dsa
->writemask
[1];
262 r600_set_stencil_ref(ctx
, &ref
);
265 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
267 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
268 struct r600_dsa_state
*dsa
= state
;
269 struct r600_stencil_ref ref
;
274 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
276 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
277 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
278 ref
.valuemask
[0] = dsa
->valuemask
[0];
279 ref
.valuemask
[1] = dsa
->valuemask
[1];
280 ref
.writemask
[0] = dsa
->writemask
[0];
281 ref
.writemask
[1] = dsa
->writemask
[1];
282 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
283 rctx
->zwritemask
= dsa
->zwritemask
;
284 if (rctx
->chip_class
>= EVERGREEN
) {
285 /* work around some issue when not writting to zbuffer
286 * we are having lockup on evergreen so do not enable
287 * hyperz when not writting zbuffer
289 rctx
->db_misc_state
.atom
.dirty
= true;
293 r600_set_stencil_ref(ctx
, &ref
);
295 /* Update alphatest state. */
296 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
297 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
298 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
299 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
300 rctx
->alphatest_state
.atom
.dirty
= true;
301 if (rctx
->chip_class
>= EVERGREEN
) {
302 evergreen_update_db_shader_control(rctx
);
304 r600_update_db_shader_control(rctx
);
309 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
311 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
312 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
317 rctx
->rasterizer
= rs
;
319 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
321 if (rs
->offset_enable
&&
322 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
323 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
324 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
325 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
326 rctx
->poly_offset_state
.atom
.dirty
= true;
329 /* Update clip_misc_state. */
330 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
331 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
332 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
333 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
334 rctx
->clip_misc_state
.atom
.dirty
= true;
337 /* Workaround for a missing scissor enable on r600. */
338 if (rctx
->chip_class
== R600
&&
339 rs
->scissor_enable
!= rctx
->scissor
.enable
) {
340 rctx
->scissor
.enable
= rs
->scissor_enable
;
341 rctx
->scissor
.atom
.dirty
= true;
344 /* Re-emit PA_SC_LINE_STIPPLE. */
345 rctx
->last_primitive_type
= -1;
348 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
350 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
352 r600_release_command_buffer(&rs
->buffer
);
356 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
357 struct pipe_sampler_view
*state
)
359 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
361 pipe_resource_reference(&state
->texture
, NULL
);
365 void r600_sampler_states_dirty(struct r600_context
*rctx
,
366 struct r600_sampler_states
*state
)
368 if (state
->dirty_mask
) {
369 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
370 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
373 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
374 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
375 state
->atom
.dirty
= true;
379 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
382 unsigned count
, void **states
)
384 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
385 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
386 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
387 int seamless_cube_map
= -1;
389 /* This sets 1-bit for states with index >= count. */
390 uint32_t disable_mask
= ~((1ull << count
) - 1);
391 /* These are the new states set by this function. */
392 uint32_t new_mask
= 0;
394 assert(start
== 0); /* XXX fix below */
396 for (i
= 0; i
< count
; i
++) {
397 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
399 if (rstate
== dst
->states
.states
[i
]) {
404 if (rstate
->border_color_use
) {
405 dst
->states
.has_bordercolor_mask
|= 1 << i
;
407 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
409 seamless_cube_map
= rstate
->seamless_cube_map
;
413 disable_mask
|= 1 << i
;
417 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
418 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
420 dst
->states
.enabled_mask
&= ~disable_mask
;
421 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
422 dst
->states
.enabled_mask
|= new_mask
;
423 dst
->states
.dirty_mask
|= new_mask
;
424 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
426 r600_sampler_states_dirty(rctx
, &dst
->states
);
428 /* Seamless cubemap state. */
429 if (rctx
->chip_class
<= R700
&&
430 seamless_cube_map
!= -1 &&
431 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
432 /* change in TA_CNTL_AUX need a pipeline flush */
433 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
434 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
435 rctx
->seamless_cube_map
.atom
.dirty
= true;
439 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
441 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
444 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
446 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
449 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
454 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
456 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
458 r600_release_command_buffer(&blend
->buffer
);
459 r600_release_command_buffer(&blend
->buffer_no_blend
);
463 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
465 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
467 r600_release_command_buffer(&dsa
->buffer
);
471 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
473 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
475 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
478 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
480 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
481 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
485 static void r600_set_index_buffer(struct pipe_context
*ctx
,
486 const struct pipe_index_buffer
*ib
)
488 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
491 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
492 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
493 r600_context_add_resource_size(ctx
, ib
->buffer
);
495 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
499 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
501 if (rctx
->vertex_buffer_state
.dirty_mask
) {
502 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
503 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
504 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
505 rctx
->vertex_buffer_state
.atom
.dirty
= true;
509 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
510 unsigned start_slot
, unsigned count
,
511 const struct pipe_vertex_buffer
*input
)
513 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
514 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
515 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
517 uint32_t disable_mask
= 0;
518 /* These are the new buffers set by this function. */
519 uint32_t new_buffer_mask
= 0;
521 /* Set vertex buffers. */
523 for (i
= 0; i
< count
; i
++) {
524 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
525 if (input
[i
].buffer
) {
526 vb
[i
].stride
= input
[i
].stride
;
527 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
528 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
529 new_buffer_mask
|= 1 << i
;
530 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
532 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
533 disable_mask
|= 1 << i
;
538 for (i
= 0; i
< count
; i
++) {
539 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
541 disable_mask
= ((1ull << count
) - 1);
544 disable_mask
<<= start_slot
;
545 new_buffer_mask
<<= start_slot
;
547 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
548 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
549 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
550 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
552 r600_vertex_buffers_dirty(rctx
);
555 void r600_sampler_views_dirty(struct r600_context
*rctx
,
556 struct r600_samplerview_state
*state
)
558 if (state
->dirty_mask
) {
559 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
560 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
561 util_bitcount(state
->dirty_mask
);
562 state
->atom
.dirty
= true;
566 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
567 unsigned start
, unsigned count
,
568 struct pipe_sampler_view
**views
)
570 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
571 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
572 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
573 uint32_t dirty_sampler_states_mask
= 0;
575 /* This sets 1-bit for textures with index >= count. */
576 uint32_t disable_mask
= ~((1ull << count
) - 1);
577 /* These are the new textures set by this function. */
578 uint32_t new_mask
= 0;
580 /* Set textures with index >= count to NULL. */
581 uint32_t remaining_mask
;
583 assert(start
== 0); /* XXX fix below */
585 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
587 while (remaining_mask
) {
588 i
= u_bit_scan(&remaining_mask
);
589 assert(dst
->views
.views
[i
]);
591 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
594 for (i
= 0; i
< count
; i
++) {
595 if (rviews
[i
] == dst
->views
.views
[i
]) {
600 struct r600_texture
*rtex
=
601 (struct r600_texture
*)rviews
[i
]->base
.texture
;
603 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
604 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
605 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
607 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
610 /* Track compressed colorbuffers. */
611 if (rtex
->cmask_size
&& rtex
->fmask_size
) {
612 dst
->views
.compressed_colortex_mask
|= 1 << i
;
614 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
617 /* Changing from array to non-arrays textures and vice versa requires
618 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
619 if (rctx
->chip_class
<= R700
&&
620 (dst
->states
.enabled_mask
& (1 << i
)) &&
621 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
622 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
623 dirty_sampler_states_mask
|= 1 << i
;
626 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
628 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
630 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
631 disable_mask
|= 1 << i
;
635 dst
->views
.enabled_mask
&= ~disable_mask
;
636 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
637 dst
->views
.enabled_mask
|= new_mask
;
638 dst
->views
.dirty_mask
|= new_mask
;
639 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
640 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
641 dst
->views
.dirty_txq_constants
= TRUE
;
642 dst
->views
.dirty_buffer_constants
= TRUE
;
643 r600_sampler_views_dirty(rctx
, &dst
->views
);
645 if (dirty_sampler_states_mask
) {
646 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
647 r600_sampler_states_dirty(rctx
, &dst
->states
);
651 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
652 struct pipe_sampler_view
**views
)
654 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
657 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
658 struct pipe_sampler_view
**views
)
660 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
663 static void r600_set_viewport_state(struct pipe_context
*ctx
,
664 const struct pipe_viewport_state
*state
)
666 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
668 rctx
->viewport
.state
= *state
;
669 rctx
->viewport
.atom
.dirty
= true;
672 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
674 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
675 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
677 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
678 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
679 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
680 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
681 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
682 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
683 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
686 /* Compute the key for the hw shader variant */
687 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
688 struct r600_pipe_shader_selector
* sel
)
690 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
691 struct r600_shader_key key
;
692 memset(&key
, 0, sizeof(key
));
694 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
695 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
696 key
.alpha_to_one
= rctx
->alpha_to_one
&&
697 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
698 !rctx
->framebuffer
.cb0_is_integer
;
699 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
700 /* Dual-source blending only makes sense with nr_cbufs == 1. */
701 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
707 /* Select the hw shader variant depending on the current state.
708 * (*dirty) is set to 1 if current variant was changed */
709 static int r600_shader_select(struct pipe_context
*ctx
,
710 struct r600_pipe_shader_selector
* sel
,
713 struct r600_shader_key key
;
714 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
715 struct r600_pipe_shader
* shader
= NULL
;
718 memset(&key
, 0, sizeof(key
));
719 key
= r600_shader_selector_key(ctx
, sel
);
721 /* Check if we don't need to change anything.
722 * This path is also used for most shaders that don't need multiple
723 * variants, it will cost just a computation of the key and this
725 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
729 /* lookup if we have other variants in the list */
730 if (sel
->num_shaders
> 1) {
731 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
733 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
739 p
->next_variant
= c
->next_variant
;
744 if (unlikely(!shader
)) {
745 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
746 shader
->selector
= sel
;
748 r
= r600_pipe_shader_create(ctx
, shader
, key
);
750 R600_ERR("Failed to build shader variant (type=%u) %d\n",
757 /* We don't know the value of nr_ps_max_color_exports until we built
758 * at least one variant, so we may need to recompute the key after
759 * building first variant. */
760 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
761 sel
->num_shaders
== 0) {
762 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
763 key
= r600_shader_selector_key(ctx
, sel
);
766 memcpy(&shader
->key
, &key
, sizeof(key
));
773 shader
->next_variant
= sel
->current
;
774 sel
->current
= shader
;
776 if (rctx
->ps_shader
&&
777 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
778 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
779 rctx
->cb_misc_state
.atom
.dirty
= true;
784 static void *r600_create_shader_state(struct pipe_context
*ctx
,
785 const struct pipe_shader_state
*state
,
786 unsigned pipe_shader_type
)
788 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
791 sel
->type
= pipe_shader_type
;
792 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
793 sel
->so
= state
->stream_output
;
795 r
= r600_shader_select(ctx
, sel
, NULL
);
802 static void *r600_create_ps_state(struct pipe_context
*ctx
,
803 const struct pipe_shader_state
*state
)
805 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
808 static void *r600_create_vs_state(struct pipe_context
*ctx
,
809 const struct pipe_shader_state
*state
)
811 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
814 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
816 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
819 state
= rctx
->dummy_pixel_shader
;
821 rctx
->pixel_shader
.shader
= rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
822 rctx
->pixel_shader
.atom
.num_dw
= rctx
->ps_shader
->current
->command_buffer
.num_dw
;
823 rctx
->pixel_shader
.atom
.dirty
= true;
825 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)rctx
->ps_shader
->current
->bo
);
827 if (rctx
->chip_class
<= R700
) {
828 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
830 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
831 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
832 rctx
->cb_misc_state
.atom
.dirty
= true;
836 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
837 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
838 rctx
->cb_misc_state
.atom
.dirty
= true;
841 if (rctx
->chip_class
>= EVERGREEN
) {
842 evergreen_update_db_shader_control(rctx
);
844 r600_update_db_shader_control(rctx
);
848 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
850 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
855 rctx
->vertex_shader
.shader
= rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
856 rctx
->vertex_shader
.atom
.dirty
= true;
858 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)rctx
->vs_shader
->current
->bo
);
860 /* Update clip misc state. */
861 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
862 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
863 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
864 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
865 rctx
->clip_misc_state
.atom
.dirty
= true;
869 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
870 struct r600_pipe_shader_selector
*sel
)
872 struct r600_pipe_shader
*p
= sel
->current
, *c
;
875 r600_pipe_shader_destroy(ctx
, p
);
885 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
887 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
888 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
890 if (rctx
->ps_shader
== sel
) {
891 rctx
->ps_shader
= NULL
;
894 r600_delete_shader_selector(ctx
, sel
);
897 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
899 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
900 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
902 if (rctx
->vs_shader
== sel
) {
903 rctx
->vs_shader
= NULL
;
906 r600_delete_shader_selector(ctx
, sel
);
909 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
911 if (state
->dirty_mask
) {
912 rctx
->flags
|= R600_CONTEXT_INVAL_READ_CACHES
;
913 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
914 : util_bitcount(state
->dirty_mask
)*19;
915 state
->atom
.dirty
= true;
919 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
920 struct pipe_constant_buffer
*input
)
922 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
923 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
924 struct pipe_constant_buffer
*cb
;
927 /* Note that the state tracker can unbind constant buffers by
930 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
931 state
->enabled_mask
&= ~(1 << index
);
932 state
->dirty_mask
&= ~(1 << index
);
933 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
937 cb
= &state
->cb
[index
];
938 cb
->buffer_size
= input
->buffer_size
;
940 ptr
= input
->user_buffer
;
943 /* Upload the user buffer. */
944 if (R600_BIG_ENDIAN
) {
946 unsigned i
, size
= input
->buffer_size
;
948 if (!(tmpPtr
= malloc(size
))) {
949 R600_ERR("Failed to allocate BE swap buffer.\n");
953 for (i
= 0; i
< size
/ 4; ++i
) {
954 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
957 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
960 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
962 /* account it in gtt */
963 rctx
->gtt
+= input
->buffer_size
;
965 /* Setup the hw buffer. */
966 cb
->buffer_offset
= input
->buffer_offset
;
967 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
968 r600_context_add_resource_size(ctx
, input
->buffer
);
971 state
->enabled_mask
|= 1 << index
;
972 state
->dirty_mask
|= 1 << index
;
973 r600_constant_buffers_dirty(rctx
, state
);
976 static struct pipe_stream_output_target
*
977 r600_create_so_target(struct pipe_context
*ctx
,
978 struct pipe_resource
*buffer
,
979 unsigned buffer_offset
,
980 unsigned buffer_size
)
982 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
983 struct r600_so_target
*t
;
984 struct r600_resource
*rbuffer
= (struct r600_resource
*)buffer
;
986 t
= CALLOC_STRUCT(r600_so_target
);
991 u_suballocator_alloc(rctx
->allocator_so_filled_size
, 4,
992 &t
->buf_filled_size_offset
,
993 (struct pipe_resource
**)&t
->buf_filled_size
);
994 if (!t
->buf_filled_size
) {
999 t
->b
.reference
.count
= 1;
1001 pipe_resource_reference(&t
->b
.buffer
, buffer
);
1002 t
->b
.buffer_offset
= buffer_offset
;
1003 t
->b
.buffer_size
= buffer_size
;
1005 util_range_add(&rbuffer
->valid_buffer_range
, buffer_offset
,
1006 buffer_offset
+ buffer_size
);
1010 static void r600_so_target_destroy(struct pipe_context
*ctx
,
1011 struct pipe_stream_output_target
*target
)
1013 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
1014 pipe_resource_reference(&t
->b
.buffer
, NULL
);
1015 pipe_resource_reference((struct pipe_resource
**)&t
->buf_filled_size
, NULL
);
1019 void r600_streamout_buffers_dirty(struct r600_context
*rctx
)
1021 rctx
->streamout
.num_dw_for_end
=
1022 12 + /* flush_vgt_streamout */
1023 util_bitcount(rctx
->streamout
.enabled_mask
) * 8 + /* STRMOUT_BUFFER_UPDATE */
1024 3 /* set_streamout_enable(0) */;
1026 rctx
->streamout
.begin_atom
.num_dw
=
1027 12 + /* flush_vgt_streamout */
1028 6 + /* set_streamout_enable */
1029 util_bitcount(rctx
->streamout
.enabled_mask
) * 7 + /* SET_CONTEXT_REG */
1030 (rctx
->family
>= CHIP_RS780
&&
1031 rctx
->family
<= CHIP_RV740
? util_bitcount(rctx
->streamout
.enabled_mask
) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1032 util_bitcount(rctx
->streamout
.enabled_mask
& rctx
->streamout
.append_bitmask
) * 8 + /* STRMOUT_BUFFER_UPDATE */
1033 util_bitcount(rctx
->streamout
.enabled_mask
& ~rctx
->streamout
.append_bitmask
) * 6 + /* STRMOUT_BUFFER_UPDATE */
1034 (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RS780
? 2 : 0) + /* SURFACE_BASE_UPDATE */
1035 rctx
->streamout
.num_dw_for_end
;
1037 rctx
->streamout
.begin_atom
.dirty
= true;
1040 static void r600_set_streamout_targets(struct pipe_context
*ctx
,
1041 unsigned num_targets
,
1042 struct pipe_stream_output_target
**targets
,
1043 unsigned append_bitmask
)
1045 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1048 /* Stop streamout. */
1049 if (rctx
->streamout
.num_targets
&& rctx
->streamout
.begin_emitted
) {
1050 r600_emit_streamout_end(rctx
);
1053 /* Set the new targets. */
1054 for (i
= 0; i
< num_targets
; i
++) {
1055 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->streamout
.targets
[i
], targets
[i
]);
1056 r600_context_add_resource_size(ctx
, targets
[i
]->buffer
);
1058 for (; i
< rctx
->streamout
.num_targets
; i
++) {
1059 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->streamout
.targets
[i
], NULL
);
1062 rctx
->streamout
.enabled_mask
= (num_targets
>= 1 && targets
[0] ? 1 : 0) |
1063 (num_targets
>= 2 && targets
[1] ? 2 : 0) |
1064 (num_targets
>= 3 && targets
[2] ? 4 : 0) |
1065 (num_targets
>= 4 && targets
[3] ? 8 : 0);
1067 rctx
->streamout
.num_targets
= num_targets
;
1068 rctx
->streamout
.append_bitmask
= append_bitmask
;
1071 r600_streamout_buffers_dirty(rctx
);
1075 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1077 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1079 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1082 rctx
->sample_mask
.sample_mask
= sample_mask
;
1083 rctx
->sample_mask
.atom
.dirty
= true;
1087 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1088 * doesn't require full swizzles it does need masking and setting alpha
1089 * to one, so we setup a set of 5 constants with the masks + alpha value
1090 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1091 * then OR the alpha with the value given here.
1092 * We use a 6th constant to store the txq buffer size in
1094 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1096 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1098 uint32_t array_size
;
1099 struct pipe_constant_buffer cb
;
1102 if (!samplers
->views
.dirty_buffer_constants
)
1105 samplers
->views
.dirty_buffer_constants
= FALSE
;
1107 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1108 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1109 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1110 memset(samplers
->buffer_constants
, 0, array_size
);
1111 for (i
= 0; i
< bits
; i
++) {
1112 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1114 const struct util_format_description
*desc
;
1115 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1117 for (j
= 0; j
< 4; j
++)
1118 if (j
< desc
->nr_channels
)
1119 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1121 samplers
->buffer_constants
[offset
+j
] = 0x0;
1122 if (desc
->nr_channels
< 4) {
1123 if (desc
->channel
[0].pure_integer
)
1124 samplers
->buffer_constants
[offset
+4] = 1;
1126 samplers
->buffer_constants
[offset
+4] = 0x3f800000;
1128 samplers
->buffer_constants
[offset
+ 4] = 0;
1130 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1135 cb
.user_buffer
= samplers
->buffer_constants
;
1136 cb
.buffer_offset
= 0;
1137 cb
.buffer_size
= array_size
;
1138 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1139 pipe_resource_reference(&cb
.buffer
, NULL
);
1142 /* On evergreen we only need to store the buffer size for TXQ */
1143 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1145 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1147 uint32_t array_size
;
1148 struct pipe_constant_buffer cb
;
1151 if (!samplers
->views
.dirty_buffer_constants
)
1154 samplers
->views
.dirty_buffer_constants
= FALSE
;
1156 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1157 array_size
= bits
* sizeof(uint32_t) * 4;
1158 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1159 memset(samplers
->buffer_constants
, 0, array_size
);
1160 for (i
= 0; i
< bits
; i
++)
1161 if (samplers
->views
.enabled_mask
& (1 << i
))
1162 samplers
->buffer_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1165 cb
.user_buffer
= samplers
->buffer_constants
;
1166 cb
.buffer_offset
= 0;
1167 cb
.buffer_size
= array_size
;
1168 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1169 pipe_resource_reference(&cb
.buffer
, NULL
);
1172 static void r600_setup_txq_cube_array_constants(struct r600_context
*rctx
, int shader_type
)
1174 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1176 uint32_t array_size
;
1177 struct pipe_constant_buffer cb
;
1180 if (!samplers
->views
.dirty_txq_constants
)
1183 samplers
->views
.dirty_txq_constants
= FALSE
;
1185 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1186 array_size
= bits
* sizeof(uint32_t) * 4;
1187 samplers
->txq_constants
= realloc(samplers
->txq_constants
, array_size
);
1188 memset(samplers
->txq_constants
, 0, array_size
);
1189 for (i
= 0; i
< bits
; i
++)
1190 if (samplers
->views
.enabled_mask
& (1 << i
))
1191 samplers
->txq_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1194 cb
.user_buffer
= samplers
->txq_constants
;
1195 cb
.buffer_offset
= 0;
1196 cb
.buffer_size
= array_size
;
1197 rctx
->context
.set_constant_buffer(&rctx
->context
, shader_type
, R600_TXQ_CONST_BUFFER
, &cb
);
1198 pipe_resource_reference(&cb
.buffer
, NULL
);
1201 static bool r600_update_derived_state(struct r600_context
*rctx
)
1203 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1204 bool ps_dirty
= false;
1207 if (!rctx
->blitter
->running
) {
1210 /* Decompress textures if needed. */
1211 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1212 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1213 if (views
->compressed_depthtex_mask
) {
1214 r600_decompress_depth_textures(rctx
, views
);
1216 if (views
->compressed_colortex_mask
) {
1217 r600_decompress_color_textures(rctx
, views
);
1222 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1224 if (rctx
->ps_shader
&& rctx
->rasterizer
&&
1225 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1226 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1228 if (rctx
->chip_class
>= EVERGREEN
)
1229 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1231 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1237 rctx
->pixel_shader
.atom
.num_dw
= rctx
->ps_shader
->current
->command_buffer
.num_dw
;
1238 rctx
->pixel_shader
.atom
.dirty
= true;
1241 /* on R600 we stuff masks + txq info into one constant buffer */
1242 /* on evergreen we only need a txq info one */
1243 if (rctx
->chip_class
< EVERGREEN
) {
1244 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1245 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1246 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1247 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1249 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1250 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1251 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1252 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1256 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1257 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1258 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1259 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_VERTEX
);
1261 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1262 if (!r600_adjust_gprs(rctx
)) {
1263 /* discard rendering */
1268 blend_disable
= (rctx
->dual_src_blend
&&
1269 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1271 if (blend_disable
!= rctx
->force_blend_disable
) {
1272 rctx
->force_blend_disable
= blend_disable
;
1273 r600_bind_blend_state_internal(rctx
,
1274 rctx
->blend_state
.cso
,
1280 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1282 static const int prim_conv
[] = {
1283 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1284 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1285 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1286 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1287 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1288 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1289 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1290 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1291 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1292 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1293 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1294 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1295 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1296 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1297 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1299 assert(mode
< Elements(prim_conv
));
1301 return prim_conv
[mode
];
1304 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1306 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1307 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1309 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1310 state
->pa_cl_clip_cntl
|
1311 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1312 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1313 state
->pa_cl_vs_out_cntl
|
1314 (state
->clip_plane_enable
& state
->clip_dist_write
));
1317 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1319 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1320 struct pipe_draw_info info
= *dinfo
;
1321 struct pipe_index_buffer ib
= {};
1323 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1325 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1330 if (!rctx
->vs_shader
) {
1335 /* make sure that the gfx ring is only one active */
1336 if (rctx
->rings
.dma
.cs
) {
1337 rctx
->rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
);
1340 if (!r600_update_derived_state(rctx
)) {
1341 /* useless to render because current rendering command
1348 /* Initialize the index buffer struct. */
1349 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1350 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1351 ib
.index_size
= rctx
->index_buffer
.index_size
;
1352 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1354 /* Translate 8-bit indices to 16-bit. */
1355 if (ib
.index_size
== 1) {
1356 struct pipe_resource
*out_buffer
= NULL
;
1357 unsigned out_offset
;
1360 u_upload_alloc(rctx
->uploader
, 0, info
.count
* 2,
1361 &out_offset
, &out_buffer
, &ptr
);
1363 util_shorten_ubyte_elts_to_userptr(
1364 &rctx
->context
, &ib
, 0, ib
.offset
, info
.count
, ptr
);
1366 pipe_resource_reference(&ib
.buffer
, NULL
);
1367 ib
.user_buffer
= NULL
;
1368 ib
.buffer
= out_buffer
;
1369 ib
.offset
= out_offset
;
1373 /* Upload the index buffer.
1374 * The upload is skipped for small index counts on little-endian machines
1375 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1376 * Note: Instanced rendering in combination with immediate indices hangs. */
1377 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.instance_count
> 1 ||
1378 info
.count
*ib
.index_size
> 20)) {
1379 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1380 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1381 ib
.user_buffer
= NULL
;
1384 info
.index_bias
= info
.start
;
1387 /* Set the index offset and primitive restart. */
1388 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1389 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1390 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
) {
1391 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1392 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1393 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1394 rctx
->vgt_state
.atom
.dirty
= true;
1397 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1398 if (rctx
->chip_class
== R600
) {
1399 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1400 rctx
->cb_misc_state
.atom
.dirty
= true;
1404 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1405 r600_flush_emit(rctx
);
1407 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1408 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1411 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1414 /* Update start instance. */
1415 if (rctx
->last_start_instance
!= info
.start_instance
) {
1416 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1417 rctx
->last_start_instance
= info
.start_instance
;
1420 /* Update the primitive type. */
1421 if (rctx
->last_primitive_type
!= info
.mode
) {
1422 unsigned ls_mask
= 0;
1424 if (info
.mode
== PIPE_PRIM_LINES
)
1426 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1427 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1430 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1431 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1432 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1433 r600_write_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
1434 r600_conv_prim_to_gs_out(info
.mode
));
1435 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1436 r600_conv_pipe_prim(info
.mode
));
1438 rctx
->last_primitive_type
= info
.mode
;
1442 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1443 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1445 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1446 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1447 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1448 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1450 if (ib
.user_buffer
) {
1451 unsigned size_bytes
= info
.count
*ib
.index_size
;
1452 unsigned size_dw
= align(size_bytes
, 4) / 4;
1453 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->predicate_drawing
);
1454 cs
->buf
[cs
->cdw
++] = info
.count
;
1455 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1456 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1459 uint64_t va
= r600_resource_va(ctx
->screen
, ib
.buffer
) + ib
.offset
;
1460 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1461 cs
->buf
[cs
->cdw
++] = va
;
1462 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1463 cs
->buf
[cs
->cdw
++] = info
.count
;
1464 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1465 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1466 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1469 if (info
.count_from_stream_output
) {
1470 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1471 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->buf_filled_size
) + t
->buf_filled_size_offset
;
1473 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1475 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1476 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1477 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1478 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1479 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1480 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1482 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1483 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, t
->buf_filled_size
, RADEON_USAGE_READ
);
1486 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1487 cs
->buf
[cs
->cdw
++] = info
.count
;
1488 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1489 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1492 if (rctx
->screen
->trace_bo
) {
1493 r600_trace_emit(rctx
);
1496 /* Set the depth buffer as dirty. */
1497 if (rctx
->framebuffer
.state
.zsbuf
) {
1498 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1499 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1501 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1503 if (rctx
->framebuffer
.compressed_cb_mask
) {
1504 struct pipe_surface
*surf
;
1505 struct r600_texture
*rtex
;
1506 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1509 unsigned i
= u_bit_scan(&mask
);
1510 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1511 rtex
= (struct r600_texture
*)surf
->texture
;
1513 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1518 pipe_resource_reference(&ib
.buffer
, NULL
);
1519 rctx
->num_draw_calls
++;
1522 void r600_draw_rectangle(struct blitter_context
*blitter
,
1523 int x1
, int y1
, int x2
, int y2
, float depth
,
1524 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1526 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1527 struct pipe_viewport_state viewport
;
1528 struct pipe_resource
*buf
= NULL
;
1529 unsigned offset
= 0;
1532 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1533 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1537 /* Some operations (like color resolve on r6xx) don't work
1538 * with the conventional primitive types.
1539 * One that works is PT_RECTLIST, which we use here. */
1541 /* setup viewport */
1542 viewport
.scale
[0] = 1.0f
;
1543 viewport
.scale
[1] = 1.0f
;
1544 viewport
.scale
[2] = 1.0f
;
1545 viewport
.scale
[3] = 1.0f
;
1546 viewport
.translate
[0] = 0.0f
;
1547 viewport
.translate
[1] = 0.0f
;
1548 viewport
.translate
[2] = 0.0f
;
1549 viewport
.translate
[3] = 0.0f
;
1550 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1552 /* Upload vertices. The hw rectangle has only 3 vertices,
1553 * I guess the 4th one is derived from the first 3.
1554 * The vertex specification should match u_blitter's vertex element state. */
1555 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1572 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1573 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1574 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1578 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, rctx
->blitter
->vb_slot
, offset
,
1579 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1580 pipe_resource_reference(&buf
, NULL
);
1583 uint32_t r600_translate_stencil_op(int s_op
)
1586 case PIPE_STENCIL_OP_KEEP
:
1587 return V_028800_STENCIL_KEEP
;
1588 case PIPE_STENCIL_OP_ZERO
:
1589 return V_028800_STENCIL_ZERO
;
1590 case PIPE_STENCIL_OP_REPLACE
:
1591 return V_028800_STENCIL_REPLACE
;
1592 case PIPE_STENCIL_OP_INCR
:
1593 return V_028800_STENCIL_INCR
;
1594 case PIPE_STENCIL_OP_DECR
:
1595 return V_028800_STENCIL_DECR
;
1596 case PIPE_STENCIL_OP_INCR_WRAP
:
1597 return V_028800_STENCIL_INCR_WRAP
;
1598 case PIPE_STENCIL_OP_DECR_WRAP
:
1599 return V_028800_STENCIL_DECR_WRAP
;
1600 case PIPE_STENCIL_OP_INVERT
:
1601 return V_028800_STENCIL_INVERT
;
1603 R600_ERR("Unknown stencil op %d", s_op
);
1610 uint32_t r600_translate_fill(uint32_t func
)
1613 case PIPE_POLYGON_MODE_FILL
:
1615 case PIPE_POLYGON_MODE_LINE
:
1617 case PIPE_POLYGON_MODE_POINT
:
1625 unsigned r600_tex_wrap(unsigned wrap
)
1629 case PIPE_TEX_WRAP_REPEAT
:
1630 return V_03C000_SQ_TEX_WRAP
;
1631 case PIPE_TEX_WRAP_CLAMP
:
1632 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1633 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1634 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1635 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1636 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1637 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1638 return V_03C000_SQ_TEX_MIRROR
;
1639 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1640 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1641 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1642 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1643 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1644 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1648 unsigned r600_tex_filter(unsigned filter
)
1652 case PIPE_TEX_FILTER_NEAREST
:
1653 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1654 case PIPE_TEX_FILTER_LINEAR
:
1655 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1659 unsigned r600_tex_mipfilter(unsigned filter
)
1662 case PIPE_TEX_MIPFILTER_NEAREST
:
1663 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1664 case PIPE_TEX_MIPFILTER_LINEAR
:
1665 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1667 case PIPE_TEX_MIPFILTER_NONE
:
1668 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1672 unsigned r600_tex_compare(unsigned compare
)
1676 case PIPE_FUNC_NEVER
:
1677 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1678 case PIPE_FUNC_LESS
:
1679 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1680 case PIPE_FUNC_EQUAL
:
1681 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1682 case PIPE_FUNC_LEQUAL
:
1683 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1684 case PIPE_FUNC_GREATER
:
1685 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1686 case PIPE_FUNC_NOTEQUAL
:
1687 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1688 case PIPE_FUNC_GEQUAL
:
1689 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1690 case PIPE_FUNC_ALWAYS
:
1691 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1695 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1697 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1698 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1700 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1701 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1704 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1706 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1707 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1709 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1710 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1711 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1712 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1713 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1716 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1718 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1719 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
->current
;
1721 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
1723 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1724 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, shader
->bo
, RADEON_USAGE_READ
));
1727 /* keep this at the end of this file, please */
1728 void r600_init_common_state_functions(struct r600_context
*rctx
)
1730 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1731 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1732 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
1733 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1734 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1735 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1736 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1737 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1738 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1739 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1740 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1741 rctx
->context
.delete_blend_state
= r600_delete_blend_state
;
1742 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
1743 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1744 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1745 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1746 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1747 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1748 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1749 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1750 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1751 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1752 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1753 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1754 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1755 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1756 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1757 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1758 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1759 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1760 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1761 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1762 rctx
->context
.set_stream_output_targets
= r600_set_streamout_targets
;
1763 rctx
->context
.draw_vbo
= r600_draw_vbo
;
1766 void r600_trace_emit(struct r600_context
*rctx
)
1768 struct r600_screen
*rscreen
= rctx
->screen
;
1769 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1773 va
= r600_resource_va(&rscreen
->screen
, (void*)rscreen
->trace_bo
);
1774 reloc
= r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rscreen
->trace_bo
, RADEON_USAGE_READWRITE
);
1775 r600_write_value(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
1776 r600_write_value(cs
, va
& 0xFFFFFFFFUL
);
1777 r600_write_value(cs
, (va
>> 32UL) & 0xFFUL
);
1778 r600_write_value(cs
, cs
->cdw
);
1779 r600_write_value(cs
, rscreen
->cs_count
);
1780 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1781 r600_write_value(cs
, reloc
);