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r600g: emit the border color only when it's needed
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "tgsi/tgsi_parse.h"
35 #include <byteswap.h>
36
37 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
40 {
41 cb->buf = CALLOC(1, 4 * num_dw);
42 cb->max_num_dw = num_dw;
43 }
44
45 void r600_release_command_buffer(struct r600_command_buffer *cb)
46 {
47 FREE(cb->buf);
48 }
49
50 void r600_init_atom(struct r600_context *rctx,
51 struct r600_atom *atom,
52 unsigned id,
53 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
54 unsigned num_dw)
55 {
56 assert(id < R600_NUM_ATOMS);
57 assert(rctx->atoms[id] == NULL);
58 rctx->atoms[id] = atom;
59 atom->id = id;
60 atom->emit = emit;
61 atom->num_dw = num_dw;
62 atom->dirty = false;
63 }
64
65 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
66 {
67 r600_emit_command_buffer(rctx->cs, ((struct r600_cso_state*)atom)->cb);
68 }
69
70 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
71 {
72 struct radeon_winsys_cs *cs = rctx->cs;
73 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
74 unsigned alpha_ref = a->sx_alpha_ref;
75
76 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
77 alpha_ref &= ~0x1FFF;
78 }
79
80 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
81 a->sx_alpha_test_control |
82 S_028410_ALPHA_TEST_BYPASS(a->bypass));
83 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
84 }
85
86 static void r600_texture_barrier(struct pipe_context *ctx)
87 {
88 struct r600_context *rctx = (struct r600_context *)ctx;
89
90 rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
91
92 /* R6xx errata */
93 if (rctx->chip_class == R600) {
94 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
95 }
96 }
97
98 static unsigned r600_conv_pipe_prim(unsigned prim)
99 {
100 static const unsigned prim_conv[] = {
101 V_008958_DI_PT_POINTLIST,
102 V_008958_DI_PT_LINELIST,
103 V_008958_DI_PT_LINELOOP,
104 V_008958_DI_PT_LINESTRIP,
105 V_008958_DI_PT_TRILIST,
106 V_008958_DI_PT_TRISTRIP,
107 V_008958_DI_PT_TRIFAN,
108 V_008958_DI_PT_QUADLIST,
109 V_008958_DI_PT_QUADSTRIP,
110 V_008958_DI_PT_POLYGON,
111 V_008958_DI_PT_LINELIST_ADJ,
112 V_008958_DI_PT_LINESTRIP_ADJ,
113 V_008958_DI_PT_TRILIST_ADJ,
114 V_008958_DI_PT_TRISTRIP_ADJ,
115 V_008958_DI_PT_RECTLIST
116 };
117 return prim_conv[prim];
118 }
119
120 /* common state between evergreen and r600 */
121
122 static void r600_bind_blend_state_internal(struct r600_context *rctx,
123 struct r600_blend_state *blend, bool blend_disable)
124 {
125 unsigned color_control;
126 bool update_cb = false;
127
128 rctx->alpha_to_one = blend->alpha_to_one;
129 rctx->dual_src_blend = blend->dual_src_blend;
130
131 if (!blend_disable) {
132 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
133 color_control = blend->cb_color_control;
134 } else {
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
137 color_control = blend->cb_color_control_no_blend;
138 }
139
140 /* Update derived states. */
141 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
142 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
143 update_cb = true;
144 }
145 if (rctx->chip_class <= R700 &&
146 rctx->cb_misc_state.cb_color_control != color_control) {
147 rctx->cb_misc_state.cb_color_control = color_control;
148 update_cb = true;
149 }
150 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
151 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
152 update_cb = true;
153 }
154 if (update_cb) {
155 rctx->cb_misc_state.atom.dirty = true;
156 }
157 }
158
159 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
160 {
161 struct r600_context *rctx = (struct r600_context *)ctx;
162 struct r600_blend_state *blend = (struct r600_blend_state *)state;
163
164 if (blend == NULL)
165 return;
166
167 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
168 }
169
170 static void r600_set_blend_color(struct pipe_context *ctx,
171 const struct pipe_blend_color *state)
172 {
173 struct r600_context *rctx = (struct r600_context *)ctx;
174
175 rctx->blend_color.state = *state;
176 rctx->blend_color.atom.dirty = true;
177 }
178
179 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
180 {
181 struct radeon_winsys_cs *cs = rctx->cs;
182 struct pipe_blend_color *state = &rctx->blend_color.state;
183
184 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
185 r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
186 r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
187 r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
188 r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
189 }
190
191 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
192 {
193 struct radeon_winsys_cs *cs = rctx->cs;
194 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
195
196 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
197 r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
198 }
199
200 void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
201 {
202 struct radeon_winsys_cs *cs = rctx->cs;
203 struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
204
205 r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
206 }
207
208 static void r600_set_clip_state(struct pipe_context *ctx,
209 const struct pipe_clip_state *state)
210 {
211 struct r600_context *rctx = (struct r600_context *)ctx;
212 struct pipe_constant_buffer cb;
213
214 rctx->clip_state.state = *state;
215 rctx->clip_state.atom.dirty = true;
216
217 cb.buffer = NULL;
218 cb.user_buffer = state->ucp;
219 cb.buffer_offset = 0;
220 cb.buffer_size = 4*4*8;
221 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
222 pipe_resource_reference(&cb.buffer, NULL);
223 }
224
225 static void r600_set_stencil_ref(struct pipe_context *ctx,
226 const struct r600_stencil_ref *state)
227 {
228 struct r600_context *rctx = (struct r600_context *)ctx;
229
230 rctx->stencil_ref.state = *state;
231 rctx->stencil_ref.atom.dirty = true;
232 }
233
234 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
235 {
236 struct radeon_winsys_cs *cs = rctx->cs;
237 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
238
239 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
240 r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
241 S_028430_STENCILREF(a->state.ref_value[0]) |
242 S_028430_STENCILMASK(a->state.valuemask[0]) |
243 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
244 r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
245 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
246 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
247 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
248 }
249
250 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
251 const struct pipe_stencil_ref *state)
252 {
253 struct r600_context *rctx = (struct r600_context *)ctx;
254 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
255 struct r600_stencil_ref ref;
256
257 rctx->stencil_ref.pipe_state = *state;
258
259 if (!dsa)
260 return;
261
262 ref.ref_value[0] = state->ref_value[0];
263 ref.ref_value[1] = state->ref_value[1];
264 ref.valuemask[0] = dsa->valuemask[0];
265 ref.valuemask[1] = dsa->valuemask[1];
266 ref.writemask[0] = dsa->writemask[0];
267 ref.writemask[1] = dsa->writemask[1];
268
269 r600_set_stencil_ref(ctx, &ref);
270 }
271
272 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
273 {
274 struct r600_context *rctx = (struct r600_context *)ctx;
275 struct r600_dsa_state *dsa = state;
276 struct r600_stencil_ref ref;
277
278 if (state == NULL)
279 return;
280
281 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
282
283 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
284 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
285 ref.valuemask[0] = dsa->valuemask[0];
286 ref.valuemask[1] = dsa->valuemask[1];
287 ref.writemask[0] = dsa->writemask[0];
288 ref.writemask[1] = dsa->writemask[1];
289
290 r600_set_stencil_ref(ctx, &ref);
291
292 /* Update alphatest state. */
293 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
294 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
295 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
296 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
297 rctx->alphatest_state.atom.dirty = true;
298 }
299 }
300
301 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
302 {
303 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
304 struct r600_context *rctx = (struct r600_context *)ctx;
305
306 if (state == NULL)
307 return;
308
309 rctx->rasterizer = rs;
310
311 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
312
313 if (rs->offset_enable &&
314 (rs->offset_units != rctx->poly_offset_state.offset_units ||
315 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
316 rctx->poly_offset_state.offset_units = rs->offset_units;
317 rctx->poly_offset_state.offset_scale = rs->offset_scale;
318 rctx->poly_offset_state.atom.dirty = true;
319 }
320
321 /* Update clip_misc_state. */
322 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
323 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
324 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
325 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
326 rctx->clip_misc_state.atom.dirty = true;
327 }
328
329 /* Workaround for a missing scissor enable on r600. */
330 if (rctx->chip_class == R600 &&
331 rs->scissor_enable != rctx->scissor.enable) {
332 rctx->scissor.enable = rs->scissor_enable;
333 rctx->scissor.atom.dirty = true;
334 }
335
336 /* Re-emit PA_SC_LINE_STIPPLE. */
337 rctx->last_primitive_type = -1;
338 }
339
340 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
341 {
342 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
343
344 r600_release_command_buffer(&rs->buffer);
345 FREE(rs);
346 }
347
348 static void r600_sampler_view_destroy(struct pipe_context *ctx,
349 struct pipe_sampler_view *state)
350 {
351 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
352
353 pipe_resource_reference(&state->texture, NULL);
354 FREE(resource);
355 }
356
357 void r600_sampler_states_dirty(struct r600_context *rctx,
358 struct r600_sampler_states *state)
359 {
360 if (state->dirty_mask) {
361 if (state->dirty_mask & state->has_bordercolor_mask) {
362 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
363 }
364 state->atom.num_dw =
365 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
366 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
367 state->atom.dirty = true;
368 }
369 }
370
371 static void r600_bind_sampler_states(struct pipe_context *pipe,
372 unsigned shader,
373 unsigned start,
374 unsigned count, void **states)
375 {
376 struct r600_context *rctx = (struct r600_context *)pipe;
377 struct r600_textures_info *dst = &rctx->samplers[shader];
378 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
379 int seamless_cube_map = -1;
380 unsigned i;
381 /* This sets 1-bit for states with index >= count. */
382 uint32_t disable_mask = ~((1ull << count) - 1);
383 /* These are the new states set by this function. */
384 uint32_t new_mask = 0;
385
386 assert(start == 0); /* XXX fix below */
387
388 for (i = 0; i < count; i++) {
389 struct r600_pipe_sampler_state *rstate = rstates[i];
390
391 if (rstate == dst->states.states[i]) {
392 continue;
393 }
394
395 if (rstate) {
396 if (rstate->border_color_use) {
397 dst->states.has_bordercolor_mask |= 1 << i;
398 } else {
399 dst->states.has_bordercolor_mask &= ~(1 << i);
400 }
401 seamless_cube_map = rstate->seamless_cube_map;
402
403 new_mask |= 1 << i;
404 } else {
405 disable_mask |= 1 << i;
406 }
407 }
408
409 memcpy(dst->states.states, rstates, sizeof(void*) * count);
410 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
411
412 dst->states.enabled_mask &= ~disable_mask;
413 dst->states.dirty_mask &= dst->states.enabled_mask;
414 dst->states.enabled_mask |= new_mask;
415 dst->states.dirty_mask |= new_mask;
416 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
417
418 r600_sampler_states_dirty(rctx, &dst->states);
419
420 /* Seamless cubemap state. */
421 if (rctx->chip_class <= R700 &&
422 seamless_cube_map != -1 &&
423 seamless_cube_map != rctx->seamless_cube_map.enabled) {
424 /* change in TA_CNTL_AUX need a pipeline flush */
425 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
426 rctx->seamless_cube_map.enabled = seamless_cube_map;
427 rctx->seamless_cube_map.atom.dirty = true;
428 }
429 }
430
431 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
432 {
433 r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
434 }
435
436 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
437 {
438 r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
439 }
440
441 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
442 {
443 free(state);
444 }
445
446 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
447 {
448 struct r600_blend_state *blend = (struct r600_blend_state*)state;
449
450 r600_release_command_buffer(&blend->buffer);
451 r600_release_command_buffer(&blend->buffer_no_blend);
452 FREE(blend);
453 }
454
455 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
456 {
457 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
458
459 r600_release_command_buffer(&dsa->buffer);
460 free(dsa);
461 }
462
463 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
464 {
465 struct r600_context *rctx = (struct r600_context *)ctx;
466
467 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
468 }
469
470 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
471 {
472 pipe_resource_reference((struct pipe_resource**)&state, NULL);
473 }
474
475 static void r600_set_index_buffer(struct pipe_context *ctx,
476 const struct pipe_index_buffer *ib)
477 {
478 struct r600_context *rctx = (struct r600_context *)ctx;
479
480 if (ib) {
481 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
482 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
483 } else {
484 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
485 }
486 }
487
488 void r600_vertex_buffers_dirty(struct r600_context *rctx)
489 {
490 if (rctx->vertex_buffer_state.dirty_mask) {
491 rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
492 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
493 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
494 rctx->vertex_buffer_state.atom.dirty = true;
495 }
496 }
497
498 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
499 const struct pipe_vertex_buffer *input)
500 {
501 struct r600_context *rctx = (struct r600_context *)ctx;
502 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
503 struct pipe_vertex_buffer *vb = state->vb;
504 unsigned i;
505 /* This sets 1-bit for buffers with index >= count. */
506 uint32_t disable_mask = ~((1ull << count) - 1);
507 /* These are the new buffers set by this function. */
508 uint32_t new_buffer_mask = 0;
509
510 /* Set buffers with index >= count to NULL. */
511 uint32_t remaining_buffers_mask =
512 rctx->vertex_buffer_state.enabled_mask & disable_mask;
513
514 while (remaining_buffers_mask) {
515 i = u_bit_scan(&remaining_buffers_mask);
516 pipe_resource_reference(&vb[i].buffer, NULL);
517 }
518
519 /* Set vertex buffers. */
520 for (i = 0; i < count; i++) {
521 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
522 if (input[i].buffer) {
523 vb[i].stride = input[i].stride;
524 vb[i].buffer_offset = input[i].buffer_offset;
525 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
526 new_buffer_mask |= 1 << i;
527 } else {
528 pipe_resource_reference(&vb[i].buffer, NULL);
529 disable_mask |= 1 << i;
530 }
531 }
532 }
533
534 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
535 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
536 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
537 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
538
539 r600_vertex_buffers_dirty(rctx);
540 }
541
542 void r600_sampler_views_dirty(struct r600_context *rctx,
543 struct r600_samplerview_state *state)
544 {
545 if (state->dirty_mask) {
546 rctx->flags |= R600_CONTEXT_TEX_FLUSH;
547 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
548 util_bitcount(state->dirty_mask);
549 state->atom.dirty = true;
550 }
551 }
552
553 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
554 unsigned start, unsigned count,
555 struct pipe_sampler_view **views)
556 {
557 struct r600_context *rctx = (struct r600_context *) pipe;
558 struct r600_textures_info *dst = &rctx->samplers[shader];
559 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
560 uint32_t dirty_sampler_states_mask = 0;
561 unsigned i;
562 /* This sets 1-bit for textures with index >= count. */
563 uint32_t disable_mask = ~((1ull << count) - 1);
564 /* These are the new textures set by this function. */
565 uint32_t new_mask = 0;
566
567 /* Set textures with index >= count to NULL. */
568 uint32_t remaining_mask;
569
570 assert(start == 0); /* XXX fix below */
571
572 remaining_mask = dst->views.enabled_mask & disable_mask;
573
574 while (remaining_mask) {
575 i = u_bit_scan(&remaining_mask);
576 assert(dst->views.views[i]);
577
578 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
579 }
580
581 for (i = 0; i < count; i++) {
582 if (rviews[i] == dst->views.views[i]) {
583 continue;
584 }
585
586 if (rviews[i]) {
587 struct r600_texture *rtex =
588 (struct r600_texture*)rviews[i]->base.texture;
589
590 if (rtex->is_depth && !rtex->is_flushing_texture) {
591 dst->views.compressed_depthtex_mask |= 1 << i;
592 } else {
593 dst->views.compressed_depthtex_mask &= ~(1 << i);
594 }
595
596 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
597 if (rctx->chip_class != CAYMAN && rtex->cmask_size && rtex->fmask_size) {
598 dst->views.compressed_colortex_mask |= 1 << i;
599 } else {
600 dst->views.compressed_colortex_mask &= ~(1 << i);
601 }
602
603 /* Changing from array to non-arrays textures and vice versa requires
604 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
605 if (rctx->chip_class <= R700 &&
606 (dst->states.enabled_mask & (1 << i)) &&
607 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
608 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
609 dirty_sampler_states_mask |= 1 << i;
610 }
611
612 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
613 new_mask |= 1 << i;
614 } else {
615 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
616 disable_mask |= 1 << i;
617 }
618 }
619
620 dst->views.enabled_mask &= ~disable_mask;
621 dst->views.dirty_mask &= dst->views.enabled_mask;
622 dst->views.enabled_mask |= new_mask;
623 dst->views.dirty_mask |= new_mask;
624 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
625 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
626
627 r600_sampler_views_dirty(rctx, &dst->views);
628
629 if (dirty_sampler_states_mask) {
630 dst->states.dirty_mask |= dirty_sampler_states_mask;
631 r600_sampler_states_dirty(rctx, &dst->states);
632 }
633 }
634
635 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
636 struct pipe_sampler_view **views)
637 {
638 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
639 }
640
641 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
642 struct pipe_sampler_view **views)
643 {
644 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
645 }
646
647 static void r600_set_viewport_state(struct pipe_context *ctx,
648 const struct pipe_viewport_state *state)
649 {
650 struct r600_context *rctx = (struct r600_context *)ctx;
651
652 rctx->viewport.state = *state;
653 rctx->viewport.atom.dirty = true;
654 }
655
656 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
657 {
658 struct radeon_winsys_cs *cs = rctx->cs;
659 struct pipe_viewport_state *state = &rctx->viewport.state;
660
661 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
662 r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
663 r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
664 r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
665 r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
666 r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
667 r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
668 }
669
670 /* Compute the key for the hw shader variant */
671 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
672 struct r600_pipe_shader_selector * sel)
673 {
674 struct r600_context *rctx = (struct r600_context *)ctx;
675 struct r600_shader_key key;
676 memset(&key, 0, sizeof(key));
677
678 if (sel->type == PIPE_SHADER_FRAGMENT) {
679 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
680 key.alpha_to_one = rctx->alpha_to_one &&
681 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
682 !rctx->framebuffer.cb0_is_integer;
683 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
684 /* Dual-source blending only makes sense with nr_cbufs == 1. */
685 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
686 key.nr_cbufs = 2;
687 }
688 return key;
689 }
690
691 /* Select the hw shader variant depending on the current state.
692 * (*dirty) is set to 1 if current variant was changed */
693 static int r600_shader_select(struct pipe_context *ctx,
694 struct r600_pipe_shader_selector* sel,
695 unsigned *dirty)
696 {
697 struct r600_shader_key key;
698 struct r600_context *rctx = (struct r600_context *)ctx;
699 struct r600_pipe_shader * shader = NULL;
700 int r;
701
702 key = r600_shader_selector_key(ctx, sel);
703
704 /* Check if we don't need to change anything.
705 * This path is also used for most shaders that don't need multiple
706 * variants, it will cost just a computation of the key and this
707 * test. */
708 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
709 return 0;
710 }
711
712 /* lookup if we have other variants in the list */
713 if (sel->num_shaders > 1) {
714 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
715
716 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
717 p = c;
718 c = c->next_variant;
719 }
720
721 if (c) {
722 p->next_variant = c->next_variant;
723 shader = c;
724 }
725 }
726
727 if (unlikely(!shader)) {
728 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
729 shader->selector = sel;
730
731 r = r600_pipe_shader_create(ctx, shader, key);
732 if (unlikely(r)) {
733 R600_ERR("Failed to build shader variant (type=%u) %d\n",
734 sel->type, r);
735 sel->current = NULL;
736 return r;
737 }
738
739 /* We don't know the value of nr_ps_max_color_exports until we built
740 * at least one variant, so we may need to recompute the key after
741 * building first variant. */
742 if (sel->type == PIPE_SHADER_FRAGMENT &&
743 sel->num_shaders == 0) {
744 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
745 key = r600_shader_selector_key(ctx, sel);
746 }
747
748 shader->key = key;
749 sel->num_shaders++;
750 }
751
752 if (dirty)
753 *dirty = 1;
754
755 shader->next_variant = sel->current;
756 sel->current = shader;
757
758 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
759 r600_adjust_gprs(rctx);
760 }
761
762 if (rctx->ps_shader &&
763 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
764 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
765 rctx->cb_misc_state.atom.dirty = true;
766 }
767 return 0;
768 }
769
770 static void *r600_create_shader_state(struct pipe_context *ctx,
771 const struct pipe_shader_state *state,
772 unsigned pipe_shader_type)
773 {
774 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
775 int r;
776
777 sel->type = pipe_shader_type;
778 sel->tokens = tgsi_dup_tokens(state->tokens);
779 sel->so = state->stream_output;
780
781 r = r600_shader_select(ctx, sel, NULL);
782 if (r)
783 return NULL;
784
785 return sel;
786 }
787
788 static void *r600_create_ps_state(struct pipe_context *ctx,
789 const struct pipe_shader_state *state)
790 {
791 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
792 }
793
794 static void *r600_create_vs_state(struct pipe_context *ctx,
795 const struct pipe_shader_state *state)
796 {
797 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
798 }
799
800 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
801 {
802 struct r600_context *rctx = (struct r600_context *)ctx;
803
804 if (!state)
805 state = rctx->dummy_pixel_shader;
806
807 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
808 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
809
810 if (rctx->chip_class <= R700) {
811 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
812
813 if (rctx->cb_misc_state.multiwrite != multiwrite) {
814 rctx->cb_misc_state.multiwrite = multiwrite;
815 rctx->cb_misc_state.atom.dirty = true;
816 }
817
818 if (rctx->vs_shader)
819 r600_adjust_gprs(rctx);
820 }
821
822 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
823 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
824 rctx->cb_misc_state.atom.dirty = true;
825 }
826
827 if (rctx->chip_class >= EVERGREEN) {
828 evergreen_update_db_shader_control(rctx);
829 } else {
830 r600_update_db_shader_control(rctx);
831 }
832 }
833
834 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
835 {
836 struct r600_context *rctx = (struct r600_context *)ctx;
837
838 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
839 if (state) {
840 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
841
842 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
843 r600_adjust_gprs(rctx);
844
845 /* Update clip misc state. */
846 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
847 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
848 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
849 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
850 rctx->clip_misc_state.atom.dirty = true;
851 }
852 }
853 }
854
855 static void r600_delete_shader_selector(struct pipe_context *ctx,
856 struct r600_pipe_shader_selector *sel)
857 {
858 struct r600_pipe_shader *p = sel->current, *c;
859 while (p) {
860 c = p->next_variant;
861 r600_pipe_shader_destroy(ctx, p);
862 free(p);
863 p = c;
864 }
865
866 free(sel->tokens);
867 free(sel);
868 }
869
870
871 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
872 {
873 struct r600_context *rctx = (struct r600_context *)ctx;
874 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
875
876 if (rctx->ps_shader == sel) {
877 rctx->ps_shader = NULL;
878 }
879
880 r600_delete_shader_selector(ctx, sel);
881 }
882
883 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
884 {
885 struct r600_context *rctx = (struct r600_context *)ctx;
886 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
887
888 if (rctx->vs_shader == sel) {
889 rctx->vs_shader = NULL;
890 }
891
892 r600_delete_shader_selector(ctx, sel);
893 }
894
895 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
896 {
897 if (state->dirty_mask) {
898 rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
899 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
900 : util_bitcount(state->dirty_mask)*19;
901 state->atom.dirty = true;
902 }
903 }
904
905 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
906 struct pipe_constant_buffer *input)
907 {
908 struct r600_context *rctx = (struct r600_context *)ctx;
909 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
910 struct pipe_constant_buffer *cb;
911 const uint8_t *ptr;
912
913 /* Note that the state tracker can unbind constant buffers by
914 * passing NULL here.
915 */
916 if (unlikely(!input)) {
917 state->enabled_mask &= ~(1 << index);
918 state->dirty_mask &= ~(1 << index);
919 pipe_resource_reference(&state->cb[index].buffer, NULL);
920 return;
921 }
922
923 cb = &state->cb[index];
924 cb->buffer_size = input->buffer_size;
925
926 ptr = input->user_buffer;
927
928 if (ptr) {
929 /* Upload the user buffer. */
930 if (R600_BIG_ENDIAN) {
931 uint32_t *tmpPtr;
932 unsigned i, size = input->buffer_size;
933
934 if (!(tmpPtr = malloc(size))) {
935 R600_ERR("Failed to allocate BE swap buffer.\n");
936 return;
937 }
938
939 for (i = 0; i < size / 4; ++i) {
940 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
941 }
942
943 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
944 free(tmpPtr);
945 } else {
946 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
947 }
948 } else {
949 /* Setup the hw buffer. */
950 cb->buffer_offset = input->buffer_offset;
951 pipe_resource_reference(&cb->buffer, input->buffer);
952 }
953
954 state->enabled_mask |= 1 << index;
955 state->dirty_mask |= 1 << index;
956 r600_constant_buffers_dirty(rctx, state);
957 }
958
959 static struct pipe_stream_output_target *
960 r600_create_so_target(struct pipe_context *ctx,
961 struct pipe_resource *buffer,
962 unsigned buffer_offset,
963 unsigned buffer_size)
964 {
965 struct r600_context *rctx = (struct r600_context *)ctx;
966 struct r600_so_target *t;
967 void *ptr;
968
969 t = CALLOC_STRUCT(r600_so_target);
970 if (!t) {
971 return NULL;
972 }
973
974 t->b.reference.count = 1;
975 t->b.context = ctx;
976 pipe_resource_reference(&t->b.buffer, buffer);
977 t->b.buffer_offset = buffer_offset;
978 t->b.buffer_size = buffer_size;
979
980 t->filled_size = (struct r600_resource*)
981 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
982 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
983 memset(ptr, 0, t->filled_size->buf->size);
984 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
985
986 return &t->b;
987 }
988
989 static void r600_so_target_destroy(struct pipe_context *ctx,
990 struct pipe_stream_output_target *target)
991 {
992 struct r600_so_target *t = (struct r600_so_target*)target;
993 pipe_resource_reference(&t->b.buffer, NULL);
994 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
995 FREE(t);
996 }
997
998 static void r600_set_so_targets(struct pipe_context *ctx,
999 unsigned num_targets,
1000 struct pipe_stream_output_target **targets,
1001 unsigned append_bitmask)
1002 {
1003 struct r600_context *rctx = (struct r600_context *)ctx;
1004 unsigned i;
1005
1006 /* Stop streamout. */
1007 if (rctx->num_so_targets && !rctx->streamout_start) {
1008 r600_context_streamout_end(rctx);
1009 }
1010
1011 /* Set the new targets. */
1012 for (i = 0; i < num_targets; i++) {
1013 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1014 }
1015 for (; i < rctx->num_so_targets; i++) {
1016 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1017 }
1018
1019 rctx->num_so_targets = num_targets;
1020 rctx->streamout_start = num_targets != 0;
1021 rctx->streamout_append_bitmask = append_bitmask;
1022 }
1023
1024 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1025 {
1026 struct r600_context *rctx = (struct r600_context*)pipe;
1027
1028 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1029 return;
1030
1031 rctx->sample_mask.sample_mask = sample_mask;
1032 rctx->sample_mask.atom.dirty = true;
1033 }
1034
1035 static void r600_update_derived_state(struct r600_context *rctx)
1036 {
1037 struct pipe_context * ctx = (struct pipe_context*)rctx;
1038 unsigned ps_dirty = 0;
1039 bool blend_disable;
1040
1041 if (!rctx->blitter->running) {
1042 unsigned i;
1043
1044 /* Decompress textures if needed. */
1045 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1046 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1047 if (views->compressed_depthtex_mask) {
1048 r600_decompress_depth_textures(rctx, views);
1049 }
1050 if (views->compressed_colortex_mask) {
1051 r600_decompress_color_textures(rctx, views);
1052 }
1053 }
1054 }
1055
1056 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1057
1058 if (rctx->ps_shader && rctx->rasterizer &&
1059 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1060 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1061
1062 if (rctx->chip_class >= EVERGREEN)
1063 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1064 else
1065 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1066
1067 ps_dirty = 1;
1068 }
1069
1070 if (ps_dirty)
1071 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1072
1073 blend_disable = (rctx->dual_src_blend &&
1074 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1075
1076 if (blend_disable != rctx->force_blend_disable) {
1077 rctx->force_blend_disable = blend_disable;
1078 r600_bind_blend_state_internal(rctx,
1079 rctx->blend_state.cso,
1080 blend_disable);
1081 }
1082 }
1083
1084 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1085 {
1086 static const int prim_conv[] = {
1087 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1088 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1089 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1090 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1091 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1092 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1093 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1094 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1095 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1096 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1097 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1098 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1099 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1100 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1101 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1102 };
1103 assert(mode < Elements(prim_conv));
1104
1105 return prim_conv[mode];
1106 }
1107
1108 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1109 {
1110 struct radeon_winsys_cs *cs = rctx->cs;
1111 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1112
1113 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1114 state->pa_cl_clip_cntl |
1115 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1116 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1117 state->pa_cl_vs_out_cntl |
1118 (state->clip_plane_enable & state->clip_dist_write));
1119 }
1120
1121 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1122 {
1123 struct r600_context *rctx = (struct r600_context *)ctx;
1124 struct pipe_draw_info info = *dinfo;
1125 struct pipe_index_buffer ib = {};
1126 unsigned i;
1127 struct r600_block *dirty_block = NULL, *next_block = NULL;
1128 struct radeon_winsys_cs *cs = rctx->cs;
1129
1130 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1131 assert(0);
1132 return;
1133 }
1134
1135 if (!rctx->vs_shader) {
1136 assert(0);
1137 return;
1138 }
1139
1140 r600_update_derived_state(rctx);
1141
1142 if (info.indexed) {
1143 /* Initialize the index buffer struct. */
1144 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1145 ib.user_buffer = rctx->index_buffer.user_buffer;
1146 ib.index_size = rctx->index_buffer.index_size;
1147 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1148
1149 /* Translate 8-bit indices to 16-bit. */
1150 if (ib.index_size == 1) {
1151 struct pipe_resource *out_buffer = NULL;
1152 unsigned out_offset;
1153 void *ptr;
1154
1155 u_upload_alloc(rctx->uploader, 0, info.count * 2,
1156 &out_offset, &out_buffer, &ptr);
1157
1158 util_shorten_ubyte_elts_to_userptr(
1159 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1160
1161 pipe_resource_reference(&ib.buffer, NULL);
1162 ib.user_buffer = NULL;
1163 ib.buffer = out_buffer;
1164 ib.offset = out_offset;
1165 ib.index_size = 2;
1166 }
1167
1168 /* Upload the index buffer.
1169 * The upload is skipped for small index counts on little-endian machines
1170 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1171 * Note: Instanced rendering in combination with immediate indices hangs. */
1172 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1173 info.count*ib.index_size > 20)) {
1174 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1175 ib.user_buffer, &ib.offset, &ib.buffer);
1176 ib.user_buffer = NULL;
1177 }
1178 } else {
1179 info.index_bias = info.start;
1180 }
1181
1182 /* Enable stream out if needed. */
1183 if (rctx->streamout_start) {
1184 r600_context_streamout_begin(rctx);
1185 rctx->streamout_start = FALSE;
1186 }
1187
1188 /* Set the index offset and multi primitive */
1189 if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
1190 rctx->vgt2_state.vgt_indx_offset = info.index_bias;
1191 rctx->vgt2_state.atom.dirty = true;
1192 }
1193 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1194 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
1195 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1196 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1197 rctx->vgt_state.atom.dirty = true;
1198 }
1199
1200 /* Emit states. */
1201 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1202 r600_flush_emit(rctx);
1203
1204 for (i = 0; i < R600_NUM_ATOMS; i++) {
1205 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1206 continue;
1207 }
1208 r600_emit_atom(rctx, rctx->atoms[i]);
1209 }
1210 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1211 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1212 }
1213 rctx->pm4_dirty_cdwords = 0;
1214
1215 /* Update start instance. */
1216 if (rctx->last_start_instance != info.start_instance) {
1217 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1218 rctx->last_start_instance = info.start_instance;
1219 }
1220
1221 /* Update the primitive type. */
1222 if (rctx->last_primitive_type != info.mode) {
1223 unsigned ls_mask = 0;
1224
1225 if (info.mode == PIPE_PRIM_LINES)
1226 ls_mask = 1;
1227 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1228 info.mode == PIPE_PRIM_LINE_LOOP)
1229 ls_mask = 2;
1230
1231 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1232 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1233 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1234 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1235 r600_conv_prim_to_gs_out(info.mode));
1236 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1237 r600_conv_pipe_prim(info.mode));
1238
1239 rctx->last_primitive_type = info.mode;
1240 }
1241
1242 /* Draw packets. */
1243 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1244 cs->buf[cs->cdw++] = info.instance_count;
1245 if (info.indexed) {
1246 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1247 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1248 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1249 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1250
1251 if (ib.user_buffer) {
1252 unsigned size_bytes = info.count*ib.index_size;
1253 unsigned size_dw = align(size_bytes, 4) / 4;
1254 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1255 cs->buf[cs->cdw++] = info.count;
1256 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1257 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1258 cs->cdw += size_dw;
1259 } else {
1260 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1261 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1262 cs->buf[cs->cdw++] = va;
1263 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1264 cs->buf[cs->cdw++] = info.count;
1265 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1266 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1267 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1268 }
1269 } else {
1270 if (info.count_from_stream_output) {
1271 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1272 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
1273
1274 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1275
1276 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1277 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1278 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1279 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1280 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1281 cs->buf[cs->cdw++] = 0; /* unused */
1282
1283 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1284 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
1285 }
1286
1287 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1288 cs->buf[cs->cdw++] = info.count;
1289 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1290 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1291 }
1292
1293 /* Set the depth buffer as dirty. */
1294 if (rctx->framebuffer.state.zsbuf) {
1295 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1296 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1297
1298 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1299 }
1300 if (rctx->framebuffer.compressed_cb_mask) {
1301 struct pipe_surface *surf;
1302 struct r600_texture *rtex;
1303 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1304
1305 do {
1306 unsigned i = u_bit_scan(&mask);
1307 surf = rctx->framebuffer.state.cbufs[i];
1308 rtex = (struct r600_texture*)surf->texture;
1309
1310 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1311
1312 } while (mask);
1313 }
1314
1315 pipe_resource_reference(&ib.buffer, NULL);
1316 }
1317
1318 void r600_draw_rectangle(struct blitter_context *blitter,
1319 int x1, int y1, int x2, int y2, float depth,
1320 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1321 {
1322 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1323 struct pipe_viewport_state viewport;
1324 struct pipe_resource *buf = NULL;
1325 unsigned offset = 0;
1326 float *vb;
1327
1328 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1329 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1330 return;
1331 }
1332
1333 /* Some operations (like color resolve on r6xx) don't work
1334 * with the conventional primitive types.
1335 * One that works is PT_RECTLIST, which we use here. */
1336
1337 /* setup viewport */
1338 viewport.scale[0] = 1.0f;
1339 viewport.scale[1] = 1.0f;
1340 viewport.scale[2] = 1.0f;
1341 viewport.scale[3] = 1.0f;
1342 viewport.translate[0] = 0.0f;
1343 viewport.translate[1] = 0.0f;
1344 viewport.translate[2] = 0.0f;
1345 viewport.translate[3] = 0.0f;
1346 rctx->context.set_viewport_state(&rctx->context, &viewport);
1347
1348 /* Upload vertices. The hw rectangle has only 3 vertices,
1349 * I guess the 4th one is derived from the first 3.
1350 * The vertex specification should match u_blitter's vertex element state. */
1351 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1352 vb[0] = x1;
1353 vb[1] = y1;
1354 vb[2] = depth;
1355 vb[3] = 1;
1356
1357 vb[8] = x1;
1358 vb[9] = y2;
1359 vb[10] = depth;
1360 vb[11] = 1;
1361
1362 vb[16] = x2;
1363 vb[17] = y1;
1364 vb[18] = depth;
1365 vb[19] = 1;
1366
1367 if (attrib) {
1368 memcpy(vb+4, attrib->f, sizeof(float)*4);
1369 memcpy(vb+12, attrib->f, sizeof(float)*4);
1370 memcpy(vb+20, attrib->f, sizeof(float)*4);
1371 }
1372
1373 /* draw */
1374 util_draw_vertex_buffer(&rctx->context, NULL, buf, offset,
1375 R600_PRIM_RECTANGLE_LIST, 3, 2);
1376 pipe_resource_reference(&buf, NULL);
1377 }
1378
1379 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1380 struct r600_pipe_state *state,
1381 uint32_t offset, uint32_t value,
1382 uint32_t range_id, uint32_t block_id,
1383 struct r600_resource *bo,
1384 enum radeon_bo_usage usage)
1385
1386 {
1387 struct r600_range *range;
1388 struct r600_block *block;
1389
1390 if (bo) assert(usage);
1391
1392 range = &ctx->range[range_id];
1393 block = range->blocks[block_id];
1394 state->regs[state->nregs].block = block;
1395 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1396
1397 state->regs[state->nregs].value = value;
1398 state->regs[state->nregs].bo = bo;
1399 state->regs[state->nregs].bo_usage = usage;
1400
1401 state->nregs++;
1402 assert(state->nregs < R600_BLOCK_MAX_REG);
1403 }
1404
1405 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1406 struct r600_pipe_state *state,
1407 uint32_t offset, uint32_t value,
1408 uint32_t range_id, uint32_t block_id)
1409 {
1410 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1411 range_id, block_id, NULL, 0);
1412 }
1413
1414 uint32_t r600_translate_stencil_op(int s_op)
1415 {
1416 switch (s_op) {
1417 case PIPE_STENCIL_OP_KEEP:
1418 return V_028800_STENCIL_KEEP;
1419 case PIPE_STENCIL_OP_ZERO:
1420 return V_028800_STENCIL_ZERO;
1421 case PIPE_STENCIL_OP_REPLACE:
1422 return V_028800_STENCIL_REPLACE;
1423 case PIPE_STENCIL_OP_INCR:
1424 return V_028800_STENCIL_INCR;
1425 case PIPE_STENCIL_OP_DECR:
1426 return V_028800_STENCIL_DECR;
1427 case PIPE_STENCIL_OP_INCR_WRAP:
1428 return V_028800_STENCIL_INCR_WRAP;
1429 case PIPE_STENCIL_OP_DECR_WRAP:
1430 return V_028800_STENCIL_DECR_WRAP;
1431 case PIPE_STENCIL_OP_INVERT:
1432 return V_028800_STENCIL_INVERT;
1433 default:
1434 R600_ERR("Unknown stencil op %d", s_op);
1435 assert(0);
1436 break;
1437 }
1438 return 0;
1439 }
1440
1441 uint32_t r600_translate_fill(uint32_t func)
1442 {
1443 switch(func) {
1444 case PIPE_POLYGON_MODE_FILL:
1445 return 2;
1446 case PIPE_POLYGON_MODE_LINE:
1447 return 1;
1448 case PIPE_POLYGON_MODE_POINT:
1449 return 0;
1450 default:
1451 assert(0);
1452 return 0;
1453 }
1454 }
1455
1456 unsigned r600_tex_wrap(unsigned wrap)
1457 {
1458 switch (wrap) {
1459 default:
1460 case PIPE_TEX_WRAP_REPEAT:
1461 return V_03C000_SQ_TEX_WRAP;
1462 case PIPE_TEX_WRAP_CLAMP:
1463 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1464 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1465 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1466 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1467 return V_03C000_SQ_TEX_CLAMP_BORDER;
1468 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1469 return V_03C000_SQ_TEX_MIRROR;
1470 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1471 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1472 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1473 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1474 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1475 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1476 }
1477 }
1478
1479 unsigned r600_tex_filter(unsigned filter)
1480 {
1481 switch (filter) {
1482 default:
1483 case PIPE_TEX_FILTER_NEAREST:
1484 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1485 case PIPE_TEX_FILTER_LINEAR:
1486 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1487 }
1488 }
1489
1490 unsigned r600_tex_mipfilter(unsigned filter)
1491 {
1492 switch (filter) {
1493 case PIPE_TEX_MIPFILTER_NEAREST:
1494 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1495 case PIPE_TEX_MIPFILTER_LINEAR:
1496 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1497 default:
1498 case PIPE_TEX_MIPFILTER_NONE:
1499 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1500 }
1501 }
1502
1503 unsigned r600_tex_compare(unsigned compare)
1504 {
1505 switch (compare) {
1506 default:
1507 case PIPE_FUNC_NEVER:
1508 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1509 case PIPE_FUNC_LESS:
1510 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1511 case PIPE_FUNC_EQUAL:
1512 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1513 case PIPE_FUNC_LEQUAL:
1514 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1515 case PIPE_FUNC_GREATER:
1516 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1517 case PIPE_FUNC_NOTEQUAL:
1518 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1519 case PIPE_FUNC_GEQUAL:
1520 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1521 case PIPE_FUNC_ALWAYS:
1522 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1523 }
1524 }
1525
1526 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1527 {
1528 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1529 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1530 (linear_filter &&
1531 (wrap == PIPE_TEX_WRAP_CLAMP ||
1532 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1533 }
1534
1535 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1536 {
1537 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1538 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1539
1540 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1541 state->border_color.ui[2] || state->border_color.ui[3]) &&
1542 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1543 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1544 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1545 }
1546
1547 /* keep this at the end of this file, please */
1548 void r600_init_common_state_functions(struct r600_context *rctx)
1549 {
1550 rctx->context.create_fs_state = r600_create_ps_state;
1551 rctx->context.create_vs_state = r600_create_vs_state;
1552 rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1553 rctx->context.bind_blend_state = r600_bind_blend_state;
1554 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1555 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1556 rctx->context.bind_fs_state = r600_bind_ps_state;
1557 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1558 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1559 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1560 rctx->context.bind_vs_state = r600_bind_vs_state;
1561 rctx->context.delete_blend_state = r600_delete_blend_state;
1562 rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1563 rctx->context.delete_fs_state = r600_delete_ps_state;
1564 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1565 rctx->context.delete_sampler_state = r600_delete_sampler_state;
1566 rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1567 rctx->context.delete_vs_state = r600_delete_vs_state;
1568 rctx->context.set_blend_color = r600_set_blend_color;
1569 rctx->context.set_clip_state = r600_set_clip_state;
1570 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1571 rctx->context.set_sample_mask = r600_set_sample_mask;
1572 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1573 rctx->context.set_viewport_state = r600_set_viewport_state;
1574 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1575 rctx->context.set_index_buffer = r600_set_index_buffer;
1576 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1577 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1578 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1579 rctx->context.texture_barrier = r600_texture_barrier;
1580 rctx->context.create_stream_output_target = r600_create_so_target;
1581 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1582 rctx->context.set_stream_output_targets = r600_set_so_targets;
1583 rctx->context.draw_vbo = r600_draw_vbo;
1584 }