2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
39 struct radeon_winsys_cs
*cs
= rctx
->cs
;
40 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
42 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
43 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
44 cs
->cdw
+= cb
->atom
.num_dw
;
47 void r600_init_command_buffer(struct r600_context
*rctx
, struct r600_command_buffer
*cb
, unsigned id
, unsigned num_dw
)
49 r600_init_atom(rctx
, &cb
->atom
, id
, r600_emit_command_buffer
, 0);
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 void r600_init_atom(struct r600_context
*rctx
,
60 struct r600_atom
*atom
,
62 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
65 assert(id
< R600_NUM_ATOMS
);
66 assert(rctx
->atoms
[id
] == NULL
);
67 rctx
->atoms
[id
] = atom
;
70 atom
->num_dw
= num_dw
;
74 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
76 struct radeon_winsys_cs
*cs
= rctx
->cs
;
77 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
78 unsigned alpha_ref
= a
->sx_alpha_ref
;
80 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
84 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
85 a
->sx_alpha_test_control
|
86 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
87 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
90 static void r600_texture_barrier(struct pipe_context
*ctx
)
92 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
94 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_TEX_FLUSH
;
97 if (rctx
->chip_class
== R600
) {
98 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
102 static unsigned r600_conv_pipe_prim(unsigned prim
)
104 static const unsigned prim_conv
[] = {
105 V_008958_DI_PT_POINTLIST
,
106 V_008958_DI_PT_LINELIST
,
107 V_008958_DI_PT_LINELOOP
,
108 V_008958_DI_PT_LINESTRIP
,
109 V_008958_DI_PT_TRILIST
,
110 V_008958_DI_PT_TRISTRIP
,
111 V_008958_DI_PT_TRIFAN
,
112 V_008958_DI_PT_QUADLIST
,
113 V_008958_DI_PT_QUADSTRIP
,
114 V_008958_DI_PT_POLYGON
,
115 V_008958_DI_PT_LINELIST_ADJ
,
116 V_008958_DI_PT_LINESTRIP_ADJ
,
117 V_008958_DI_PT_TRILIST_ADJ
,
118 V_008958_DI_PT_TRISTRIP_ADJ
,
119 V_008958_DI_PT_RECTLIST
121 return prim_conv
[prim
];
124 /* common state between evergreen and r600 */
126 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
127 struct r600_pipe_blend
*blend
)
129 struct r600_pipe_state
*rstate
;
130 bool update_cb
= false;
132 rstate
= &blend
->rstate
;
133 rctx
->states
[rstate
->id
] = rstate
;
134 r600_context_pipe_state_set(rctx
, rstate
);
136 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
137 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
140 if (rctx
->chip_class
<= R700
&&
141 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
142 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
145 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
146 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
150 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
154 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
156 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
157 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
163 rctx
->alpha_to_one
= blend
->alpha_to_one
;
164 rctx
->dual_src_blend
= blend
->dual_src_blend
;
166 if (!rctx
->blend_override
)
167 r600_bind_blend_state_internal(rctx
, blend
);
170 static void r600_set_blend_color(struct pipe_context
*ctx
,
171 const struct pipe_blend_color
*state
)
173 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
175 rctx
->blend_color
.state
= *state
;
176 r600_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
179 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
181 struct radeon_winsys_cs
*cs
= rctx
->cs
;
182 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
184 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
185 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
186 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
187 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
188 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
191 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
193 struct radeon_winsys_cs
*cs
= rctx
->cs
;
194 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
196 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
197 r600_write_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, a
->vgt_multi_prim_ib_reset_indx
);
200 void r600_emit_vgt2_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
202 struct radeon_winsys_cs
*cs
= rctx
->cs
;
203 struct r600_vgt2_state
*a
= (struct r600_vgt2_state
*)atom
;
205 r600_write_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, a
->vgt_indx_offset
);
208 static void r600_set_clip_state(struct pipe_context
*ctx
,
209 const struct pipe_clip_state
*state
)
211 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
212 struct pipe_constant_buffer cb
;
214 rctx
->clip_state
.state
= *state
;
215 r600_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
218 cb
.user_buffer
= state
->ucp
;
219 cb
.buffer_offset
= 0;
220 cb
.buffer_size
= 4*4*8;
221 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
222 pipe_resource_reference(&cb
.buffer
, NULL
);
225 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
226 const struct r600_stencil_ref
*state
)
228 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
230 rctx
->stencil_ref
.state
= *state
;
231 r600_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
234 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
236 struct radeon_winsys_cs
*cs
= rctx
->cs
;
237 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
239 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
240 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
241 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
242 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
243 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
244 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
245 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
246 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
247 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
250 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
251 const struct pipe_stencil_ref
*state
)
253 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
254 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
255 struct r600_stencil_ref ref
;
257 rctx
->stencil_ref
.pipe_state
= *state
;
262 ref
.ref_value
[0] = state
->ref_value
[0];
263 ref
.ref_value
[1] = state
->ref_value
[1];
264 ref
.valuemask
[0] = dsa
->valuemask
[0];
265 ref
.valuemask
[1] = dsa
->valuemask
[1];
266 ref
.writemask
[0] = dsa
->writemask
[0];
267 ref
.writemask
[1] = dsa
->writemask
[1];
269 r600_set_stencil_ref(ctx
, &ref
);
272 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
274 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
275 struct r600_pipe_dsa
*dsa
= state
;
276 struct r600_pipe_state
*rstate
;
277 struct r600_stencil_ref ref
;
281 rstate
= &dsa
->rstate
;
282 rctx
->states
[rstate
->id
] = rstate
;
283 r600_context_pipe_state_set(rctx
, rstate
);
285 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
286 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
287 ref
.valuemask
[0] = dsa
->valuemask
[0];
288 ref
.valuemask
[1] = dsa
->valuemask
[1];
289 ref
.writemask
[0] = dsa
->writemask
[0];
290 ref
.writemask
[1] = dsa
->writemask
[1];
292 r600_set_stencil_ref(ctx
, &ref
);
294 /* Update alphatest state. */
295 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
296 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
297 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
298 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
299 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
303 void r600_set_max_scissor(struct r600_context
*rctx
)
305 /* Set a scissor state such that it doesn't do anything. */
306 struct pipe_scissor_state scissor
;
312 r600_set_scissor_state(rctx
, &scissor
);
315 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
317 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
318 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
323 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
324 rctx
->two_side
= rs
->two_side
;
325 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
326 rctx
->multisample_enable
= rs
->multisample_enable
;
328 rctx
->rasterizer
= rs
;
330 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
331 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
333 if (rctx
->chip_class
>= EVERGREEN
) {
334 evergreen_polygon_offset_update(rctx
);
336 r600_polygon_offset_update(rctx
);
339 /* Update clip_misc_state. */
340 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
341 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
342 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
343 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
344 r600_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
347 /* Workaround for a missing scissor enable on r600. */
348 if (rctx
->chip_class
== R600
) {
349 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
350 rctx
->scissor_enable
= rs
->scissor_enable
;
352 if (rs
->scissor_enable
) {
353 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
355 r600_set_max_scissor(rctx
);
361 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
363 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
364 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
366 if (rctx
->rasterizer
== rs
) {
367 rctx
->rasterizer
= NULL
;
369 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
370 rctx
->states
[rs
->rstate
.id
] = NULL
;
375 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
376 struct pipe_sampler_view
*state
)
378 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
380 pipe_resource_reference(&state
->texture
, NULL
);
384 void r600_sampler_states_dirty(struct r600_context
*rctx
,
385 struct r600_sampler_states
*state
)
387 if (state
->dirty_mask
) {
388 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
389 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
392 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
393 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
394 r600_atom_dirty(rctx
, &state
->atom
);
398 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
401 unsigned count
, void **states
)
403 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
404 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
405 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
406 int seamless_cube_map
= -1;
408 /* This sets 1-bit for states with index >= count. */
409 uint32_t disable_mask
= ~((1ull << count
) - 1);
410 /* These are the new states set by this function. */
411 uint32_t new_mask
= 0;
413 assert(start
== 0); /* XXX fix below */
415 for (i
= 0; i
< count
; i
++) {
416 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
418 if (rstate
== dst
->states
.states
[i
]) {
423 if (rstate
->border_color_use
) {
424 dst
->states
.has_bordercolor_mask
|= 1 << i
;
426 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
428 seamless_cube_map
= rstate
->seamless_cube_map
;
432 disable_mask
|= 1 << i
;
436 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
437 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
439 dst
->states
.enabled_mask
&= ~disable_mask
;
440 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
441 dst
->states
.enabled_mask
|= new_mask
;
442 dst
->states
.dirty_mask
|= new_mask
;
443 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
445 r600_sampler_states_dirty(rctx
, &dst
->states
);
447 /* Seamless cubemap state. */
448 if (rctx
->chip_class
<= R700
&&
449 seamless_cube_map
!= -1 &&
450 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
451 /* change in TA_CNTL_AUX need a pipeline flush */
452 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
453 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
454 r600_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
458 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
460 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
463 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
465 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
468 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
473 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
475 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
476 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
478 if (rctx
->states
[rstate
->id
] == rstate
) {
479 rctx
->states
[rstate
->id
] = NULL
;
481 for (int i
= 0; i
< rstate
->nregs
; i
++) {
482 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
487 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
489 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
490 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
492 rctx
->vertex_elements
= v
;
494 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
495 r600_context_pipe_state_set(rctx
, &v
->rstate
);
499 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
501 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
502 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
504 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
505 rctx
->states
[v
->rstate
.id
] = NULL
;
507 if (rctx
->vertex_elements
== state
)
508 rctx
->vertex_elements
= NULL
;
510 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
514 static void r600_set_index_buffer(struct pipe_context
*ctx
,
515 const struct pipe_index_buffer
*ib
)
517 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
520 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
521 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
523 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
527 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
529 if (rctx
->vertex_buffer_state
.dirty_mask
) {
530 rctx
->flags
|= rctx
->has_vertex_cache
? R600_CONTEXT_VTX_FLUSH
: R600_CONTEXT_TEX_FLUSH
;
531 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
532 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
533 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
537 static void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
538 const struct pipe_vertex_buffer
*input
)
540 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
541 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
542 struct pipe_vertex_buffer
*vb
= state
->vb
;
544 /* This sets 1-bit for buffers with index >= count. */
545 uint32_t disable_mask
= ~((1ull << count
) - 1);
546 /* These are the new buffers set by this function. */
547 uint32_t new_buffer_mask
= 0;
549 /* Set buffers with index >= count to NULL. */
550 uint32_t remaining_buffers_mask
=
551 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
553 while (remaining_buffers_mask
) {
554 i
= u_bit_scan(&remaining_buffers_mask
);
555 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
558 /* Set vertex buffers. */
559 for (i
= 0; i
< count
; i
++) {
560 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
561 if (input
[i
].buffer
) {
562 vb
[i
].stride
= input
[i
].stride
;
563 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
564 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
565 new_buffer_mask
|= 1 << i
;
567 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
568 disable_mask
|= 1 << i
;
573 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
574 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
575 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
576 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
578 r600_vertex_buffers_dirty(rctx
);
581 void r600_sampler_views_dirty(struct r600_context
*rctx
,
582 struct r600_samplerview_state
*state
)
584 if (state
->dirty_mask
) {
585 rctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
586 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
587 util_bitcount(state
->dirty_mask
);
588 r600_atom_dirty(rctx
, &state
->atom
);
592 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
593 unsigned start
, unsigned count
,
594 struct pipe_sampler_view
**views
)
596 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
597 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
598 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
599 uint32_t dirty_sampler_states_mask
= 0;
601 /* This sets 1-bit for textures with index >= count. */
602 uint32_t disable_mask
= ~((1ull << count
) - 1);
603 /* These are the new textures set by this function. */
604 uint32_t new_mask
= 0;
606 /* Set textures with index >= count to NULL. */
607 uint32_t remaining_mask
;
609 assert(start
== 0); /* XXX fix below */
611 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
613 while (remaining_mask
) {
614 i
= u_bit_scan(&remaining_mask
);
615 assert(dst
->views
.views
[i
]);
617 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
620 for (i
= 0; i
< count
; i
++) {
621 if (rviews
[i
] == dst
->views
.views
[i
]) {
626 struct r600_texture
*rtex
=
627 (struct r600_texture
*)rviews
[i
]->base
.texture
;
629 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
630 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
632 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
635 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
636 if (rctx
->chip_class
!= CAYMAN
&& rtex
->cmask_size
&& rtex
->fmask_size
) {
637 dst
->views
.compressed_colortex_mask
|= 1 << i
;
639 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
642 /* Changing from array to non-arrays textures and vice versa requires
643 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
644 if (rctx
->chip_class
<= R700
&&
645 (dst
->states
.enabled_mask
& (1 << i
)) &&
646 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
647 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
648 dirty_sampler_states_mask
|= 1 << i
;
651 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
654 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
655 disable_mask
|= 1 << i
;
659 dst
->views
.enabled_mask
&= ~disable_mask
;
660 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
661 dst
->views
.enabled_mask
|= new_mask
;
662 dst
->views
.dirty_mask
|= new_mask
;
663 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
664 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
666 r600_sampler_views_dirty(rctx
, &dst
->views
);
668 if (dirty_sampler_states_mask
) {
669 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
670 r600_sampler_states_dirty(rctx
, &dst
->states
);
674 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
675 struct pipe_sampler_view
**views
)
677 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
680 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
681 struct pipe_sampler_view
**views
)
683 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
686 static void r600_set_viewport_state(struct pipe_context
*ctx
,
687 const struct pipe_viewport_state
*state
)
689 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
691 rctx
->viewport
.state
= *state
;
692 r600_atom_dirty(rctx
, &rctx
->viewport
.atom
);
695 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
697 struct radeon_winsys_cs
*cs
= rctx
->cs
;
698 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
700 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
701 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
702 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
703 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
704 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
705 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
706 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
709 static void *r600_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
710 const struct pipe_vertex_element
*elements
)
712 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
713 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
720 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
722 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
730 /* Compute the key for the hw shader variant */
731 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
732 struct r600_pipe_shader_selector
* sel
)
734 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
735 struct r600_shader_key key
;
736 memset(&key
, 0, sizeof(key
));
738 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
739 key
.color_two_side
= rctx
->two_side
;
740 key
.alpha_to_one
= rctx
->alpha_to_one
&&
741 rctx
->multisample_enable
&&
742 !rctx
->framebuffer
.cb0_is_integer
;
743 key
.dual_src_blend
= rctx
->dual_src_blend
;
744 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
749 /* Select the hw shader variant depending on the current state.
750 * (*dirty) is set to 1 if current variant was changed */
751 static int r600_shader_select(struct pipe_context
*ctx
,
752 struct r600_pipe_shader_selector
* sel
,
755 struct r600_shader_key key
;
756 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
757 struct r600_pipe_shader
* shader
= NULL
;
760 key
= r600_shader_selector_key(ctx
, sel
);
762 /* Check if we don't need to change anything.
763 * This path is also used for most shaders that don't need multiple
764 * variants, it will cost just a computation of the key and this
766 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
770 /* lookup if we have other variants in the list */
771 if (sel
->num_shaders
> 1) {
772 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
774 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
780 p
->next_variant
= c
->next_variant
;
785 if (unlikely(!shader
)) {
786 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
787 shader
->selector
= sel
;
789 r
= r600_pipe_shader_create(ctx
, shader
, key
);
791 R600_ERR("Failed to build shader variant (type=%u) %d\n",
797 /* We don't know the value of nr_ps_max_color_exports until we built
798 * at least one variant, so we may need to recompute the key after
799 * building first variant. */
800 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
801 sel
->num_shaders
== 0) {
802 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
803 key
= r600_shader_selector_key(ctx
, sel
);
813 shader
->next_variant
= sel
->current
;
814 sel
->current
= shader
;
816 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
817 r600_adjust_gprs(rctx
);
820 if (rctx
->ps_shader
&&
821 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
822 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
823 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
828 static void *r600_create_shader_state(struct pipe_context
*ctx
,
829 const struct pipe_shader_state
*state
,
830 unsigned pipe_shader_type
)
832 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
835 sel
->type
= pipe_shader_type
;
836 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
837 sel
->so
= state
->stream_output
;
839 r
= r600_shader_select(ctx
, sel
, NULL
);
846 static void *r600_create_ps_state(struct pipe_context
*ctx
,
847 const struct pipe_shader_state
*state
)
849 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
852 static void *r600_create_vs_state(struct pipe_context
*ctx
,
853 const struct pipe_shader_state
*state
)
855 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
858 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
860 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
863 state
= rctx
->dummy_pixel_shader
;
865 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
866 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
868 if (rctx
->chip_class
<= R700
) {
869 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
871 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
872 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
873 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
877 r600_adjust_gprs(rctx
);
880 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
881 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
882 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
886 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
888 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
890 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
892 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
894 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
895 r600_adjust_gprs(rctx
);
897 /* Update clip misc state. */
898 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
899 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
900 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
901 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
902 r600_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
907 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
908 struct r600_pipe_shader_selector
*sel
)
910 struct r600_pipe_shader
*p
= sel
->current
, *c
;
913 r600_pipe_shader_destroy(ctx
, p
);
923 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
925 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
926 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
928 if (rctx
->ps_shader
== sel
) {
929 rctx
->ps_shader
= NULL
;
932 r600_delete_shader_selector(ctx
, sel
);
935 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
937 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
938 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
940 if (rctx
->vs_shader
== sel
) {
941 rctx
->vs_shader
= NULL
;
944 r600_delete_shader_selector(ctx
, sel
);
947 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
949 if (state
->dirty_mask
) {
950 rctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
951 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
952 : util_bitcount(state
->dirty_mask
)*19;
953 r600_atom_dirty(rctx
, &state
->atom
);
957 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
958 struct pipe_constant_buffer
*input
)
960 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
961 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
962 struct pipe_constant_buffer
*cb
;
965 /* Note that the state tracker can unbind constant buffers by
968 if (unlikely(!input
)) {
969 state
->enabled_mask
&= ~(1 << index
);
970 state
->dirty_mask
&= ~(1 << index
);
971 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
975 cb
= &state
->cb
[index
];
976 cb
->buffer_size
= input
->buffer_size
;
978 ptr
= input
->user_buffer
;
981 /* Upload the user buffer. */
982 if (R600_BIG_ENDIAN
) {
984 unsigned i
, size
= input
->buffer_size
;
986 if (!(tmpPtr
= malloc(size
))) {
987 R600_ERR("Failed to allocate BE swap buffer.\n");
991 for (i
= 0; i
< size
/ 4; ++i
) {
992 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
995 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
998 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
1001 /* Setup the hw buffer. */
1002 cb
->buffer_offset
= input
->buffer_offset
;
1003 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1006 state
->enabled_mask
|= 1 << index
;
1007 state
->dirty_mask
|= 1 << index
;
1008 r600_constant_buffers_dirty(rctx
, state
);
1011 static struct pipe_stream_output_target
*
1012 r600_create_so_target(struct pipe_context
*ctx
,
1013 struct pipe_resource
*buffer
,
1014 unsigned buffer_offset
,
1015 unsigned buffer_size
)
1017 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1018 struct r600_so_target
*t
;
1021 t
= CALLOC_STRUCT(r600_so_target
);
1026 t
->b
.reference
.count
= 1;
1028 pipe_resource_reference(&t
->b
.buffer
, buffer
);
1029 t
->b
.buffer_offset
= buffer_offset
;
1030 t
->b
.buffer_size
= buffer_size
;
1032 t
->filled_size
= (struct r600_resource
*)
1033 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
1034 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
1035 memset(ptr
, 0, t
->filled_size
->buf
->size
);
1036 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
1041 static void r600_so_target_destroy(struct pipe_context
*ctx
,
1042 struct pipe_stream_output_target
*target
)
1044 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
1045 pipe_resource_reference(&t
->b
.buffer
, NULL
);
1046 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
1050 static void r600_set_so_targets(struct pipe_context
*ctx
,
1051 unsigned num_targets
,
1052 struct pipe_stream_output_target
**targets
,
1053 unsigned append_bitmask
)
1055 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1058 /* Stop streamout. */
1059 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
1060 r600_context_streamout_end(rctx
);
1063 /* Set the new targets. */
1064 for (i
= 0; i
< num_targets
; i
++) {
1065 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
1067 for (; i
< rctx
->num_so_targets
; i
++) {
1068 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
1071 rctx
->num_so_targets
= num_targets
;
1072 rctx
->streamout_start
= num_targets
!= 0;
1073 rctx
->streamout_append_bitmask
= append_bitmask
;
1076 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1078 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1080 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1083 rctx
->sample_mask
.sample_mask
= sample_mask
;
1084 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1087 static void r600_update_derived_state(struct r600_context
*rctx
)
1089 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1090 unsigned ps_dirty
= 0, blend_override
;
1092 if (!rctx
->blitter
->running
) {
1095 /* Decompress textures if needed. */
1096 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1097 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1098 if (views
->compressed_depthtex_mask
) {
1099 r600_decompress_depth_textures(rctx
, views
);
1101 if (views
->compressed_colortex_mask
) {
1102 r600_decompress_color_textures(rctx
, views
);
1107 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1109 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
1110 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
1111 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1113 if (rctx
->chip_class
>= EVERGREEN
)
1114 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1116 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1122 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1124 blend_override
= (rctx
->dual_src_blend
&&
1125 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1127 if (blend_override
!= rctx
->blend_override
) {
1128 rctx
->blend_override
= blend_override
;
1129 r600_bind_blend_state_internal(rctx
,
1130 blend_override
? rctx
->no_blend
: rctx
->blend
);
1133 if (rctx
->chip_class
>= EVERGREEN
) {
1134 evergreen_update_dual_export_state(rctx
);
1136 r600_update_dual_export_state(rctx
);
1140 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1142 static const int prim_conv
[] = {
1143 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1144 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1145 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1146 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1147 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1148 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1149 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1150 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1151 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1152 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1153 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1154 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1155 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1156 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1157 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1159 assert(mode
< Elements(prim_conv
));
1161 return prim_conv
[mode
];
1164 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1166 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1167 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1169 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1170 state
->pa_cl_clip_cntl
|
1171 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1172 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1173 state
->pa_cl_vs_out_cntl
|
1174 (state
->clip_plane_enable
& state
->clip_dist_write
));
1177 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1179 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1180 struct pipe_draw_info info
= *dinfo
;
1181 struct pipe_index_buffer ib
= {};
1183 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1184 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1188 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1193 if (!rctx
->vs_shader
) {
1198 r600_update_derived_state(rctx
);
1201 /* Initialize the index buffer struct. */
1202 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1203 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1204 ib
.index_size
= rctx
->index_buffer
.index_size
;
1205 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1207 /* Translate or upload, if needed. */
1208 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1210 ptr
= (uint8_t*)ib
.user_buffer
;
1211 if (!ib
.buffer
&& ptr
) {
1212 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1213 ptr
, &ib
.offset
, &ib
.buffer
);
1216 info
.index_bias
= info
.start
;
1219 /* Enable stream out if needed. */
1220 if (rctx
->streamout_start
) {
1221 r600_context_streamout_begin(rctx
);
1222 rctx
->streamout_start
= FALSE
;
1225 /* Set the index offset and multi primitive */
1226 if (rctx
->vgt2_state
.vgt_indx_offset
!= info
.index_bias
) {
1227 rctx
->vgt2_state
.vgt_indx_offset
= info
.index_bias
;
1228 r600_atom_dirty(rctx
, &rctx
->vgt2_state
.atom
);
1230 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1231 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
) {
1232 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1233 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1234 r600_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1237 /* Emit states (the function expects that we emit at most 17 dwords here). */
1238 r600_need_cs_space(rctx
, 0, TRUE
);
1239 r600_flush_emit(rctx
);
1241 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1242 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1245 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1247 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1248 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1250 rctx
->pm4_dirty_cdwords
= 0;
1252 /* Update start instance. */
1253 if (rctx
->last_start_instance
!= info
.start_instance
) {
1254 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1255 rctx
->last_start_instance
= info
.start_instance
;
1258 /* Update the primitive type. */
1259 if (rctx
->last_primitive_type
!= info
.mode
) {
1260 unsigned ls_mask
= 0;
1262 if (info
.mode
== PIPE_PRIM_LINES
)
1264 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1265 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1268 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1269 S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
1270 r600_write_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
1271 r600_conv_prim_to_gs_out(info
.mode
));
1272 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1273 r600_conv_pipe_prim(info
.mode
));
1275 rctx
->last_primitive_type
= info
.mode
;
1279 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1280 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1282 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1283 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1284 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1285 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1287 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1289 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1290 cs
->buf
[cs
->cdw
++] = va
;
1291 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1292 cs
->buf
[cs
->cdw
++] = info
.count
;
1293 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1294 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1295 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1297 if (info
.count_from_stream_output
) {
1298 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1299 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1301 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1303 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1304 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1305 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1306 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1307 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1308 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1310 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1311 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1314 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1315 cs
->buf
[cs
->cdw
++] = info
.count
;
1316 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1317 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1320 /* Set the depth buffer as dirty. */
1321 if (rctx
->framebuffer
.state
.zsbuf
) {
1322 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1323 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1325 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1327 if (rctx
->framebuffer
.compressed_cb_mask
) {
1328 struct pipe_surface
*surf
;
1329 struct r600_texture
*rtex
;
1330 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1333 unsigned i
= u_bit_scan(&mask
);
1334 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1335 rtex
= (struct r600_texture
*)surf
->texture
;
1337 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1342 pipe_resource_reference(&ib
.buffer
, NULL
);
1345 void r600_draw_rectangle(struct blitter_context
*blitter
,
1346 int x1
, int y1
, int x2
, int y2
, float depth
,
1347 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1349 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1350 struct pipe_viewport_state viewport
;
1351 struct pipe_resource
*buf
= NULL
;
1352 unsigned offset
= 0;
1355 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1356 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1360 /* Some operations (like color resolve on r6xx) don't work
1361 * with the conventional primitive types.
1362 * One that works is PT_RECTLIST, which we use here. */
1364 /* setup viewport */
1365 viewport
.scale
[0] = 1.0f
;
1366 viewport
.scale
[1] = 1.0f
;
1367 viewport
.scale
[2] = 1.0f
;
1368 viewport
.scale
[3] = 1.0f
;
1369 viewport
.translate
[0] = 0.0f
;
1370 viewport
.translate
[1] = 0.0f
;
1371 viewport
.translate
[2] = 0.0f
;
1372 viewport
.translate
[3] = 0.0f
;
1373 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1375 /* Upload vertices. The hw rectangle has only 3 vertices,
1376 * I guess the 4th one is derived from the first 3.
1377 * The vertex specification should match u_blitter's vertex element state. */
1378 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1395 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1396 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1397 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1401 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, offset
,
1402 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1403 pipe_resource_reference(&buf
, NULL
);
1406 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1407 struct r600_pipe_state
*state
,
1408 uint32_t offset
, uint32_t value
,
1409 uint32_t range_id
, uint32_t block_id
,
1410 struct r600_resource
*bo
,
1411 enum radeon_bo_usage usage
)
1414 struct r600_range
*range
;
1415 struct r600_block
*block
;
1417 if (bo
) assert(usage
);
1419 range
= &ctx
->range
[range_id
];
1420 block
= range
->blocks
[block_id
];
1421 state
->regs
[state
->nregs
].block
= block
;
1422 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1424 state
->regs
[state
->nregs
].value
= value
;
1425 state
->regs
[state
->nregs
].bo
= bo
;
1426 state
->regs
[state
->nregs
].bo_usage
= usage
;
1429 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1432 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1433 struct r600_pipe_state
*state
,
1434 uint32_t offset
, uint32_t value
,
1435 uint32_t range_id
, uint32_t block_id
)
1437 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1438 range_id
, block_id
, NULL
, 0);
1441 uint32_t r600_translate_stencil_op(int s_op
)
1444 case PIPE_STENCIL_OP_KEEP
:
1445 return V_028800_STENCIL_KEEP
;
1446 case PIPE_STENCIL_OP_ZERO
:
1447 return V_028800_STENCIL_ZERO
;
1448 case PIPE_STENCIL_OP_REPLACE
:
1449 return V_028800_STENCIL_REPLACE
;
1450 case PIPE_STENCIL_OP_INCR
:
1451 return V_028800_STENCIL_INCR
;
1452 case PIPE_STENCIL_OP_DECR
:
1453 return V_028800_STENCIL_DECR
;
1454 case PIPE_STENCIL_OP_INCR_WRAP
:
1455 return V_028800_STENCIL_INCR_WRAP
;
1456 case PIPE_STENCIL_OP_DECR_WRAP
:
1457 return V_028800_STENCIL_DECR_WRAP
;
1458 case PIPE_STENCIL_OP_INVERT
:
1459 return V_028800_STENCIL_INVERT
;
1461 R600_ERR("Unknown stencil op %d", s_op
);
1468 uint32_t r600_translate_fill(uint32_t func
)
1471 case PIPE_POLYGON_MODE_FILL
:
1473 case PIPE_POLYGON_MODE_LINE
:
1475 case PIPE_POLYGON_MODE_POINT
:
1483 unsigned r600_tex_wrap(unsigned wrap
)
1487 case PIPE_TEX_WRAP_REPEAT
:
1488 return V_03C000_SQ_TEX_WRAP
;
1489 case PIPE_TEX_WRAP_CLAMP
:
1490 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1491 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1492 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1493 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1494 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1495 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1496 return V_03C000_SQ_TEX_MIRROR
;
1497 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1498 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1499 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1500 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1501 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1502 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1506 unsigned r600_tex_filter(unsigned filter
)
1510 case PIPE_TEX_FILTER_NEAREST
:
1511 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1512 case PIPE_TEX_FILTER_LINEAR
:
1513 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1517 unsigned r600_tex_mipfilter(unsigned filter
)
1520 case PIPE_TEX_MIPFILTER_NEAREST
:
1521 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1522 case PIPE_TEX_MIPFILTER_LINEAR
:
1523 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1525 case PIPE_TEX_MIPFILTER_NONE
:
1526 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1530 unsigned r600_tex_compare(unsigned compare
)
1534 case PIPE_FUNC_NEVER
:
1535 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1536 case PIPE_FUNC_LESS
:
1537 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1538 case PIPE_FUNC_EQUAL
:
1539 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1540 case PIPE_FUNC_LEQUAL
:
1541 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1542 case PIPE_FUNC_GREATER
:
1543 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1544 case PIPE_FUNC_NOTEQUAL
:
1545 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1546 case PIPE_FUNC_GEQUAL
:
1547 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1548 case PIPE_FUNC_ALWAYS
:
1549 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1553 /* keep this at the end of this file, please */
1554 void r600_init_common_state_functions(struct r600_context
*rctx
)
1556 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1557 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1558 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1559 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1560 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1561 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1562 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1563 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1564 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1565 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1566 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1567 rctx
->context
.delete_blend_state
= r600_delete_state
;
1568 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1569 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1570 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1571 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1572 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1573 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1574 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1575 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1576 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1577 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1578 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1579 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1580 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1581 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1582 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1583 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1584 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1585 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1586 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1587 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1588 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1589 rctx
->context
.draw_vbo
= r600_draw_vbo
;