2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
39 struct radeon_winsys_cs
*cs
= rctx
->cs
;
40 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
42 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
43 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
44 cs
->cdw
+= cb
->atom
.num_dw
;
47 void r600_init_command_buffer(struct r600_context
*rctx
, struct r600_command_buffer
*cb
, unsigned id
, unsigned num_dw
)
49 r600_init_atom(rctx
, &cb
->atom
, id
, r600_emit_command_buffer
, 0);
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 void r600_init_atom(struct r600_context
*rctx
,
60 struct r600_atom
*atom
,
62 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
65 assert(id
< R600_NUM_ATOMS
);
66 assert(rctx
->atoms
[id
] == NULL
);
67 rctx
->atoms
[id
] = atom
;
70 atom
->num_dw
= num_dw
;
74 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
76 struct radeon_winsys_cs
*cs
= rctx
->cs
;
77 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
78 unsigned alpha_ref
= a
->sx_alpha_ref
;
80 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
84 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
85 a
->sx_alpha_test_control
|
86 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
87 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
90 static void r600_texture_barrier(struct pipe_context
*ctx
)
92 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
94 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_TEX_FLUSH
;
97 if (rctx
->chip_class
== R600
) {
98 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
102 static unsigned r600_conv_pipe_prim(unsigned prim
)
104 static const unsigned prim_conv
[] = {
105 V_008958_DI_PT_POINTLIST
,
106 V_008958_DI_PT_LINELIST
,
107 V_008958_DI_PT_LINELOOP
,
108 V_008958_DI_PT_LINESTRIP
,
109 V_008958_DI_PT_TRILIST
,
110 V_008958_DI_PT_TRISTRIP
,
111 V_008958_DI_PT_TRIFAN
,
112 V_008958_DI_PT_QUADLIST
,
113 V_008958_DI_PT_QUADSTRIP
,
114 V_008958_DI_PT_POLYGON
,
115 V_008958_DI_PT_LINELIST_ADJ
,
116 V_008958_DI_PT_LINESTRIP_ADJ
,
117 V_008958_DI_PT_TRILIST_ADJ
,
118 V_008958_DI_PT_TRISTRIP_ADJ
,
119 V_008958_DI_PT_RECTLIST
121 return prim_conv
[prim
];
124 /* common state between evergreen and r600 */
126 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
127 struct r600_pipe_blend
*blend
)
129 struct r600_pipe_state
*rstate
;
130 bool update_cb
= false;
132 rstate
= &blend
->rstate
;
133 rctx
->states
[rstate
->id
] = rstate
;
134 r600_context_pipe_state_set(rctx
, rstate
);
136 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
137 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
140 if (rctx
->chip_class
<= R700
&&
141 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
142 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
145 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
146 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
150 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
154 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
156 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
157 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
163 rctx
->alpha_to_one
= blend
->alpha_to_one
;
164 rctx
->dual_src_blend
= blend
->dual_src_blend
;
166 if (!rctx
->blend_override
)
167 r600_bind_blend_state_internal(rctx
, blend
);
170 static void r600_set_blend_color(struct pipe_context
*ctx
,
171 const struct pipe_blend_color
*state
)
173 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
175 rctx
->blend_color
.state
= *state
;
176 r600_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
179 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
181 struct radeon_winsys_cs
*cs
= rctx
->cs
;
182 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
184 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
185 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
186 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
187 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
188 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
191 static void r600_set_clip_state(struct pipe_context
*ctx
,
192 const struct pipe_clip_state
*state
)
194 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
195 struct pipe_constant_buffer cb
;
197 rctx
->clip_state
.state
= *state
;
198 r600_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
201 cb
.user_buffer
= state
->ucp
;
202 cb
.buffer_offset
= 0;
203 cb
.buffer_size
= 4*4*8;
204 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
205 pipe_resource_reference(&cb
.buffer
, NULL
);
208 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
209 const struct r600_stencil_ref
*state
)
211 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
213 rctx
->stencil_ref
.state
= *state
;
214 r600_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
217 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
219 struct radeon_winsys_cs
*cs
= rctx
->cs
;
220 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
222 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
223 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
224 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
225 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
226 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
227 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
228 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
229 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
230 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
233 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
234 const struct pipe_stencil_ref
*state
)
236 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
237 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
238 struct r600_stencil_ref ref
;
240 rctx
->stencil_ref
.pipe_state
= *state
;
245 ref
.ref_value
[0] = state
->ref_value
[0];
246 ref
.ref_value
[1] = state
->ref_value
[1];
247 ref
.valuemask
[0] = dsa
->valuemask
[0];
248 ref
.valuemask
[1] = dsa
->valuemask
[1];
249 ref
.writemask
[0] = dsa
->writemask
[0];
250 ref
.writemask
[1] = dsa
->writemask
[1];
252 r600_set_stencil_ref(ctx
, &ref
);
255 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
257 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
258 struct r600_pipe_dsa
*dsa
= state
;
259 struct r600_pipe_state
*rstate
;
260 struct r600_stencil_ref ref
;
264 rstate
= &dsa
->rstate
;
265 rctx
->states
[rstate
->id
] = rstate
;
266 r600_context_pipe_state_set(rctx
, rstate
);
268 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
269 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
270 ref
.valuemask
[0] = dsa
->valuemask
[0];
271 ref
.valuemask
[1] = dsa
->valuemask
[1];
272 ref
.writemask
[0] = dsa
->writemask
[0];
273 ref
.writemask
[1] = dsa
->writemask
[1];
275 r600_set_stencil_ref(ctx
, &ref
);
277 /* Update alphatest state. */
278 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
279 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
280 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
281 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
282 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
286 void r600_set_max_scissor(struct r600_context
*rctx
)
288 /* Set a scissor state such that it doesn't do anything. */
289 struct pipe_scissor_state scissor
;
295 r600_set_scissor_state(rctx
, &scissor
);
298 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
300 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
301 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
306 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
307 rctx
->two_side
= rs
->two_side
;
308 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
309 rctx
->multisample_enable
= rs
->multisample_enable
;
311 rctx
->rasterizer
= rs
;
313 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
314 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
316 if (rctx
->chip_class
>= EVERGREEN
) {
317 evergreen_polygon_offset_update(rctx
);
319 r600_polygon_offset_update(rctx
);
322 /* Update clip_misc_state. */
323 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
324 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
325 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
326 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
327 r600_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
330 /* Workaround for a missing scissor enable on r600. */
331 if (rctx
->chip_class
== R600
) {
332 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
333 rctx
->scissor_enable
= rs
->scissor_enable
;
335 if (rs
->scissor_enable
) {
336 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
338 r600_set_max_scissor(rctx
);
344 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
346 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
347 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
349 if (rctx
->rasterizer
== rs
) {
350 rctx
->rasterizer
= NULL
;
352 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
353 rctx
->states
[rs
->rstate
.id
] = NULL
;
358 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
359 struct pipe_sampler_view
*state
)
361 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
363 pipe_resource_reference(&state
->texture
, NULL
);
367 void r600_sampler_states_dirty(struct r600_context
*rctx
,
368 struct r600_sampler_states
*state
)
370 if (state
->dirty_mask
) {
371 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
372 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
375 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
376 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
377 r600_atom_dirty(rctx
, &state
->atom
);
381 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
384 unsigned count
, void **states
)
386 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
387 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
388 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
389 int seamless_cube_map
= -1;
391 /* This sets 1-bit for states with index >= count. */
392 uint32_t disable_mask
= ~((1ull << count
) - 1);
393 /* These are the new states set by this function. */
394 uint32_t new_mask
= 0;
396 assert(start
== 0); /* XXX fix below */
398 for (i
= 0; i
< count
; i
++) {
399 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
401 if (rstate
== dst
->states
.states
[i
]) {
406 if (rstate
->border_color_use
) {
407 dst
->states
.has_bordercolor_mask
|= 1 << i
;
409 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
411 seamless_cube_map
= rstate
->seamless_cube_map
;
415 disable_mask
|= 1 << i
;
419 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
420 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
422 dst
->states
.enabled_mask
&= ~disable_mask
;
423 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
424 dst
->states
.enabled_mask
|= new_mask
;
425 dst
->states
.dirty_mask
|= new_mask
;
426 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
428 r600_sampler_states_dirty(rctx
, &dst
->states
);
430 /* Seamless cubemap state. */
431 if (rctx
->chip_class
<= R700
&&
432 seamless_cube_map
!= -1 &&
433 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
434 /* change in TA_CNTL_AUX need a pipeline flush */
435 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
436 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
437 r600_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
441 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
443 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
446 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
448 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
451 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
456 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
458 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
459 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
461 if (rctx
->states
[rstate
->id
] == rstate
) {
462 rctx
->states
[rstate
->id
] = NULL
;
464 for (int i
= 0; i
< rstate
->nregs
; i
++) {
465 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
470 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
472 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
473 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
475 rctx
->vertex_elements
= v
;
477 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
478 r600_context_pipe_state_set(rctx
, &v
->rstate
);
482 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
484 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
485 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
487 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
488 rctx
->states
[v
->rstate
.id
] = NULL
;
490 if (rctx
->vertex_elements
== state
)
491 rctx
->vertex_elements
= NULL
;
493 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
497 static void r600_set_index_buffer(struct pipe_context
*ctx
,
498 const struct pipe_index_buffer
*ib
)
500 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
503 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
504 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
506 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
510 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
512 if (rctx
->vertex_buffer_state
.dirty_mask
) {
513 rctx
->flags
|= rctx
->has_vertex_cache
? R600_CONTEXT_VTX_FLUSH
: R600_CONTEXT_TEX_FLUSH
;
514 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
515 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
516 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
520 static void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
521 const struct pipe_vertex_buffer
*input
)
523 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
524 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
525 struct pipe_vertex_buffer
*vb
= state
->vb
;
527 /* This sets 1-bit for buffers with index >= count. */
528 uint32_t disable_mask
= ~((1ull << count
) - 1);
529 /* These are the new buffers set by this function. */
530 uint32_t new_buffer_mask
= 0;
532 /* Set buffers with index >= count to NULL. */
533 uint32_t remaining_buffers_mask
=
534 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
536 while (remaining_buffers_mask
) {
537 i
= u_bit_scan(&remaining_buffers_mask
);
538 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
541 /* Set vertex buffers. */
542 for (i
= 0; i
< count
; i
++) {
543 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
544 if (input
[i
].buffer
) {
545 vb
[i
].stride
= input
[i
].stride
;
546 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
547 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
548 new_buffer_mask
|= 1 << i
;
550 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
551 disable_mask
|= 1 << i
;
556 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
557 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
558 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
559 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
561 r600_vertex_buffers_dirty(rctx
);
564 void r600_sampler_views_dirty(struct r600_context
*rctx
,
565 struct r600_samplerview_state
*state
)
567 if (state
->dirty_mask
) {
568 rctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
569 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
570 util_bitcount(state
->dirty_mask
);
571 r600_atom_dirty(rctx
, &state
->atom
);
575 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
576 unsigned start
, unsigned count
,
577 struct pipe_sampler_view
**views
)
579 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
580 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
581 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
582 uint32_t dirty_sampler_states_mask
= 0;
584 /* This sets 1-bit for textures with index >= count. */
585 uint32_t disable_mask
= ~((1ull << count
) - 1);
586 /* These are the new textures set by this function. */
587 uint32_t new_mask
= 0;
589 /* Set textures with index >= count to NULL. */
590 uint32_t remaining_mask
;
592 assert(start
== 0); /* XXX fix below */
594 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
596 while (remaining_mask
) {
597 i
= u_bit_scan(&remaining_mask
);
598 assert(dst
->views
.views
[i
]);
600 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
603 for (i
= 0; i
< count
; i
++) {
604 if (rviews
[i
] == dst
->views
.views
[i
]) {
609 struct r600_texture
*rtex
=
610 (struct r600_texture
*)rviews
[i
]->base
.texture
;
612 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
613 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
615 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
618 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
619 if (rctx
->chip_class
!= CAYMAN
&& rtex
->cmask_size
&& rtex
->fmask_size
) {
620 dst
->views
.compressed_colortex_mask
|= 1 << i
;
622 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
625 /* Changing from array to non-arrays textures and vice versa requires
626 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
627 if (rctx
->chip_class
<= R700
&&
628 (dst
->states
.enabled_mask
& (1 << i
)) &&
629 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
630 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
631 dirty_sampler_states_mask
|= 1 << i
;
634 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
637 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
638 disable_mask
|= 1 << i
;
642 dst
->views
.enabled_mask
&= ~disable_mask
;
643 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
644 dst
->views
.enabled_mask
|= new_mask
;
645 dst
->views
.dirty_mask
|= new_mask
;
646 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
647 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
649 r600_sampler_views_dirty(rctx
, &dst
->views
);
651 if (dirty_sampler_states_mask
) {
652 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
653 r600_sampler_states_dirty(rctx
, &dst
->states
);
657 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
658 struct pipe_sampler_view
**views
)
660 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
663 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
664 struct pipe_sampler_view
**views
)
666 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
669 static void r600_set_viewport_state(struct pipe_context
*ctx
,
670 const struct pipe_viewport_state
*state
)
672 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
674 rctx
->viewport
.state
= *state
;
675 r600_atom_dirty(rctx
, &rctx
->viewport
.atom
);
678 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
680 struct radeon_winsys_cs
*cs
= rctx
->cs
;
681 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
683 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
684 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
685 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
686 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
687 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
688 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
689 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
692 static void *r600_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
693 const struct pipe_vertex_element
*elements
)
695 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
696 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
703 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
705 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
713 /* Compute the key for the hw shader variant */
714 static INLINE
unsigned r600_shader_selector_key(struct pipe_context
* ctx
,
715 struct r600_pipe_shader_selector
* sel
)
717 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
720 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
721 key
= rctx
->two_side
|
722 ((rctx
->alpha_to_one
&& rctx
->multisample_enable
&& !rctx
->cb0_is_integer
) << 1) |
723 (MIN2(sel
->nr_ps_max_color_exports
, rctx
->nr_cbufs
+ rctx
->dual_src_blend
) << 2);
730 /* Select the hw shader variant depending on the current state.
731 * (*dirty) is set to 1 if current variant was changed */
732 static int r600_shader_select(struct pipe_context
*ctx
,
733 struct r600_pipe_shader_selector
* sel
,
737 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
738 struct r600_pipe_shader
* shader
= NULL
;
741 key
= r600_shader_selector_key(ctx
, sel
);
743 /* Check if we don't need to change anything.
744 * This path is also used for most shaders that don't need multiple
745 * variants, it will cost just a computation of the key and this
747 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
751 /* lookup if we have other variants in the list */
752 if (sel
->num_shaders
> 1) {
753 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
755 while (c
&& c
->key
!= key
) {
761 p
->next_variant
= c
->next_variant
;
766 if (unlikely(!shader
)) {
767 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
768 shader
->selector
= sel
;
770 r
= r600_pipe_shader_create(ctx
, shader
);
772 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
778 /* We don't know the value of nr_ps_max_color_exports until we built
779 * at least one variant, so we may need to recompute the key after
780 * building first variant. */
781 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
782 sel
->num_shaders
== 0) {
783 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
784 key
= r600_shader_selector_key(ctx
, sel
);
794 shader
->next_variant
= sel
->current
;
795 sel
->current
= shader
;
797 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
798 r600_adjust_gprs(rctx
);
801 if (rctx
->ps_shader
&&
802 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
803 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
804 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
809 static void *r600_create_shader_state(struct pipe_context
*ctx
,
810 const struct pipe_shader_state
*state
,
811 unsigned pipe_shader_type
)
813 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
816 sel
->type
= pipe_shader_type
;
817 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
818 sel
->so
= state
->stream_output
;
820 r
= r600_shader_select(ctx
, sel
, NULL
);
827 static void *r600_create_ps_state(struct pipe_context
*ctx
,
828 const struct pipe_shader_state
*state
)
830 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
833 static void *r600_create_vs_state(struct pipe_context
*ctx
,
834 const struct pipe_shader_state
*state
)
836 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
839 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
841 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
844 state
= rctx
->dummy_pixel_shader
;
846 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
847 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
849 if (rctx
->chip_class
<= R700
) {
850 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
852 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
853 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
854 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
858 r600_adjust_gprs(rctx
);
861 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
862 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
863 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
867 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
869 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
871 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
873 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
875 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
876 r600_adjust_gprs(rctx
);
878 /* Update clip misc state. */
879 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
880 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
881 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
882 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
883 r600_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
888 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
889 struct r600_pipe_shader_selector
*sel
)
891 struct r600_pipe_shader
*p
= sel
->current
, *c
;
894 r600_pipe_shader_destroy(ctx
, p
);
904 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
906 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
907 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
909 if (rctx
->ps_shader
== sel
) {
910 rctx
->ps_shader
= NULL
;
913 r600_delete_shader_selector(ctx
, sel
);
916 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
918 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
919 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
921 if (rctx
->vs_shader
== sel
) {
922 rctx
->vs_shader
= NULL
;
925 r600_delete_shader_selector(ctx
, sel
);
928 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
930 if (state
->dirty_mask
) {
931 rctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
932 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
933 : util_bitcount(state
->dirty_mask
)*19;
934 r600_atom_dirty(rctx
, &state
->atom
);
938 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
939 struct pipe_constant_buffer
*input
)
941 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
942 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
943 struct pipe_constant_buffer
*cb
;
946 /* Note that the state tracker can unbind constant buffers by
949 if (unlikely(!input
)) {
950 state
->enabled_mask
&= ~(1 << index
);
951 state
->dirty_mask
&= ~(1 << index
);
952 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
956 cb
= &state
->cb
[index
];
957 cb
->buffer_size
= input
->buffer_size
;
959 ptr
= input
->user_buffer
;
962 /* Upload the user buffer. */
963 if (R600_BIG_ENDIAN
) {
965 unsigned i
, size
= input
->buffer_size
;
967 if (!(tmpPtr
= malloc(size
))) {
968 R600_ERR("Failed to allocate BE swap buffer.\n");
972 for (i
= 0; i
< size
/ 4; ++i
) {
973 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
976 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
979 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
982 /* Setup the hw buffer. */
983 cb
->buffer_offset
= input
->buffer_offset
;
984 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
987 state
->enabled_mask
|= 1 << index
;
988 state
->dirty_mask
|= 1 << index
;
989 r600_constant_buffers_dirty(rctx
, state
);
992 static struct pipe_stream_output_target
*
993 r600_create_so_target(struct pipe_context
*ctx
,
994 struct pipe_resource
*buffer
,
995 unsigned buffer_offset
,
996 unsigned buffer_size
)
998 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
999 struct r600_so_target
*t
;
1002 t
= CALLOC_STRUCT(r600_so_target
);
1007 t
->b
.reference
.count
= 1;
1009 pipe_resource_reference(&t
->b
.buffer
, buffer
);
1010 t
->b
.buffer_offset
= buffer_offset
;
1011 t
->b
.buffer_size
= buffer_size
;
1013 t
->filled_size
= (struct r600_resource
*)
1014 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
1015 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
1016 memset(ptr
, 0, t
->filled_size
->buf
->size
);
1017 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
1022 static void r600_so_target_destroy(struct pipe_context
*ctx
,
1023 struct pipe_stream_output_target
*target
)
1025 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
1026 pipe_resource_reference(&t
->b
.buffer
, NULL
);
1027 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
1031 static void r600_set_so_targets(struct pipe_context
*ctx
,
1032 unsigned num_targets
,
1033 struct pipe_stream_output_target
**targets
,
1034 unsigned append_bitmask
)
1036 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1039 /* Stop streamout. */
1040 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
1041 r600_context_streamout_end(rctx
);
1044 /* Set the new targets. */
1045 for (i
= 0; i
< num_targets
; i
++) {
1046 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
1048 for (; i
< rctx
->num_so_targets
; i
++) {
1049 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
1052 rctx
->num_so_targets
= num_targets
;
1053 rctx
->streamout_start
= num_targets
!= 0;
1054 rctx
->streamout_append_bitmask
= append_bitmask
;
1057 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1059 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1061 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1064 rctx
->sample_mask
.sample_mask
= sample_mask
;
1065 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1068 static void r600_update_derived_state(struct r600_context
*rctx
)
1070 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1071 unsigned ps_dirty
= 0, blend_override
;
1073 if (!rctx
->blitter
->running
) {
1076 /* Decompress textures if needed. */
1077 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1078 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1079 if (views
->compressed_depthtex_mask
) {
1080 r600_decompress_depth_textures(rctx
, views
);
1082 if (views
->compressed_colortex_mask
) {
1083 r600_decompress_color_textures(rctx
, views
);
1088 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1090 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
1091 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
1092 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1094 if (rctx
->chip_class
>= EVERGREEN
)
1095 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1097 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1103 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1105 blend_override
= (rctx
->dual_src_blend
&&
1106 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1108 if (blend_override
!= rctx
->blend_override
) {
1109 rctx
->blend_override
= blend_override
;
1110 r600_bind_blend_state_internal(rctx
,
1111 blend_override
? rctx
->no_blend
: rctx
->blend
);
1114 if (rctx
->chip_class
>= EVERGREEN
) {
1115 evergreen_update_dual_export_state(rctx
);
1117 r600_update_dual_export_state(rctx
);
1121 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1123 static const int prim_conv
[] = {
1124 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1125 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1126 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1127 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1128 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1129 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1130 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1131 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1132 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1133 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1134 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1135 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1136 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1137 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1138 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1140 assert(mode
< Elements(prim_conv
));
1142 return prim_conv
[mode
];
1145 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1147 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1148 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1150 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1151 state
->pa_cl_clip_cntl
|
1152 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1153 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1154 state
->pa_cl_vs_out_cntl
|
1155 (state
->clip_plane_enable
& state
->clip_dist_write
));
1158 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1160 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1161 struct pipe_draw_info info
= *dinfo
;
1162 struct pipe_index_buffer ib
= {};
1164 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1165 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1169 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1174 if (!rctx
->vs_shader
) {
1179 r600_update_derived_state(rctx
);
1182 /* Initialize the index buffer struct. */
1183 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1184 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1185 ib
.index_size
= rctx
->index_buffer
.index_size
;
1186 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1188 /* Translate or upload, if needed. */
1189 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1191 ptr
= (uint8_t*)ib
.user_buffer
;
1192 if (!ib
.buffer
&& ptr
) {
1193 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1194 ptr
, &ib
.offset
, &ib
.buffer
);
1197 info
.index_bias
= info
.start
;
1200 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
1201 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
1202 rctx
->vgt
.nregs
= 0;
1203 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
);
1204 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
);
1205 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
);
1206 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1209 rctx
->vgt
.nregs
= 0;
1210 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
1211 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
1212 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
1213 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
1214 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
1216 /* Enable stream out if needed. */
1217 if (rctx
->streamout_start
) {
1218 r600_context_streamout_begin(rctx
);
1219 rctx
->streamout_start
= FALSE
;
1222 /* Emit states (the function expects that we emit at most 17 dwords here). */
1223 r600_need_cs_space(rctx
, 0, TRUE
);
1224 r600_flush_emit(rctx
);
1226 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1227 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1230 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1232 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1233 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1235 rctx
->pm4_dirty_cdwords
= 0;
1237 /* Update the primitive type. */
1238 if (rctx
->last_primitive_type
!= info
.mode
) {
1239 unsigned ls_mask
= 0;
1241 if (info
.mode
== PIPE_PRIM_LINES
)
1243 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1244 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1247 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1248 S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
1249 r600_write_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
1250 r600_conv_prim_to_gs_out(info
.mode
));
1251 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1252 r600_conv_pipe_prim(info
.mode
));
1254 rctx
->last_primitive_type
= info
.mode
;
1258 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1259 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1261 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1262 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1263 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1264 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1266 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1268 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1269 cs
->buf
[cs
->cdw
++] = va
;
1270 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1271 cs
->buf
[cs
->cdw
++] = info
.count
;
1272 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1273 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1274 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1276 if (info
.count_from_stream_output
) {
1277 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1278 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1280 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1282 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1283 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1284 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1285 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1286 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1287 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1289 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1290 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1293 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1294 cs
->buf
[cs
->cdw
++] = info
.count
;
1295 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1296 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1299 /* Set the depth buffer as dirty. */
1300 if (rctx
->framebuffer
.zsbuf
) {
1301 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
1302 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1304 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1306 if (rctx
->compressed_cb_mask
) {
1307 struct pipe_surface
*surf
;
1308 struct r600_texture
*rtex
;
1309 unsigned mask
= rctx
->compressed_cb_mask
;
1312 unsigned i
= u_bit_scan(&mask
);
1313 surf
= rctx
->framebuffer
.cbufs
[i
];
1314 rtex
= (struct r600_texture
*)surf
->texture
;
1316 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1321 pipe_resource_reference(&ib
.buffer
, NULL
);
1324 void r600_draw_rectangle(struct blitter_context
*blitter
,
1325 unsigned x1
, unsigned y1
, unsigned x2
, unsigned y2
, float depth
,
1326 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1328 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1329 struct pipe_viewport_state viewport
;
1330 struct pipe_resource
*buf
= NULL
;
1331 unsigned offset
= 0;
1334 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1335 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1339 /* Some operations (like color resolve on r6xx) don't work
1340 * with the conventional primitive types.
1341 * One that works is PT_RECTLIST, which we use here. */
1343 /* setup viewport */
1344 viewport
.scale
[0] = 1.0f
;
1345 viewport
.scale
[1] = 1.0f
;
1346 viewport
.scale
[2] = 1.0f
;
1347 viewport
.scale
[3] = 1.0f
;
1348 viewport
.translate
[0] = 0.0f
;
1349 viewport
.translate
[1] = 0.0f
;
1350 viewport
.translate
[2] = 0.0f
;
1351 viewport
.translate
[3] = 0.0f
;
1352 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1354 /* Upload vertices. The hw rectangle has only 3 vertices,
1355 * I guess the 4th one is derived from the first 3.
1356 * The vertex specification should match u_blitter's vertex element state. */
1357 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1374 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1375 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1376 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1380 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, offset
,
1381 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1382 pipe_resource_reference(&buf
, NULL
);
1385 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1386 struct r600_pipe_state
*state
,
1387 uint32_t offset
, uint32_t value
,
1388 uint32_t range_id
, uint32_t block_id
,
1389 struct r600_resource
*bo
,
1390 enum radeon_bo_usage usage
)
1393 struct r600_range
*range
;
1394 struct r600_block
*block
;
1396 if (bo
) assert(usage
);
1398 range
= &ctx
->range
[range_id
];
1399 block
= range
->blocks
[block_id
];
1400 state
->regs
[state
->nregs
].block
= block
;
1401 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1403 state
->regs
[state
->nregs
].value
= value
;
1404 state
->regs
[state
->nregs
].bo
= bo
;
1405 state
->regs
[state
->nregs
].bo_usage
= usage
;
1408 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1411 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1412 struct r600_pipe_state
*state
,
1413 uint32_t offset
, uint32_t value
,
1414 uint32_t range_id
, uint32_t block_id
)
1416 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1417 range_id
, block_id
, NULL
, 0);
1420 uint32_t r600_translate_stencil_op(int s_op
)
1423 case PIPE_STENCIL_OP_KEEP
:
1424 return V_028800_STENCIL_KEEP
;
1425 case PIPE_STENCIL_OP_ZERO
:
1426 return V_028800_STENCIL_ZERO
;
1427 case PIPE_STENCIL_OP_REPLACE
:
1428 return V_028800_STENCIL_REPLACE
;
1429 case PIPE_STENCIL_OP_INCR
:
1430 return V_028800_STENCIL_INCR
;
1431 case PIPE_STENCIL_OP_DECR
:
1432 return V_028800_STENCIL_DECR
;
1433 case PIPE_STENCIL_OP_INCR_WRAP
:
1434 return V_028800_STENCIL_INCR_WRAP
;
1435 case PIPE_STENCIL_OP_DECR_WRAP
:
1436 return V_028800_STENCIL_DECR_WRAP
;
1437 case PIPE_STENCIL_OP_INVERT
:
1438 return V_028800_STENCIL_INVERT
;
1440 R600_ERR("Unknown stencil op %d", s_op
);
1447 uint32_t r600_translate_fill(uint32_t func
)
1450 case PIPE_POLYGON_MODE_FILL
:
1452 case PIPE_POLYGON_MODE_LINE
:
1454 case PIPE_POLYGON_MODE_POINT
:
1462 unsigned r600_tex_wrap(unsigned wrap
)
1466 case PIPE_TEX_WRAP_REPEAT
:
1467 return V_03C000_SQ_TEX_WRAP
;
1468 case PIPE_TEX_WRAP_CLAMP
:
1469 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1470 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1471 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1472 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1473 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1474 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1475 return V_03C000_SQ_TEX_MIRROR
;
1476 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1477 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1478 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1479 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1480 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1481 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1485 unsigned r600_tex_filter(unsigned filter
)
1489 case PIPE_TEX_FILTER_NEAREST
:
1490 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1491 case PIPE_TEX_FILTER_LINEAR
:
1492 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1496 unsigned r600_tex_mipfilter(unsigned filter
)
1499 case PIPE_TEX_MIPFILTER_NEAREST
:
1500 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1501 case PIPE_TEX_MIPFILTER_LINEAR
:
1502 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1504 case PIPE_TEX_MIPFILTER_NONE
:
1505 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1509 unsigned r600_tex_compare(unsigned compare
)
1513 case PIPE_FUNC_NEVER
:
1514 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1515 case PIPE_FUNC_LESS
:
1516 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1517 case PIPE_FUNC_EQUAL
:
1518 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1519 case PIPE_FUNC_LEQUAL
:
1520 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1521 case PIPE_FUNC_GREATER
:
1522 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1523 case PIPE_FUNC_NOTEQUAL
:
1524 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1525 case PIPE_FUNC_GEQUAL
:
1526 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1527 case PIPE_FUNC_ALWAYS
:
1528 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1532 /* keep this at the end of this file, please */
1533 void r600_init_common_state_functions(struct r600_context
*rctx
)
1535 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1536 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1537 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1538 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1539 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1540 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1541 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1542 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1543 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1544 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1545 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1546 rctx
->context
.delete_blend_state
= r600_delete_state
;
1547 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1548 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1549 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1550 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1551 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1552 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1553 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1554 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1555 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1556 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1557 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1558 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1559 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1560 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1561 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1562 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1563 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1564 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1565 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1566 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1567 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1568 rctx
->context
.draw_vbo
= r600_draw_vbo
;