src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "r600_formats.h"
  28 #include "r600_shader.h"
  29 #include "r600d.h"
  30
  31 #include "util/u_draw_quad.h"
  32 #include "util/u_index_modify.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_upload_mgr.h"
  35 #include "tgsi/tgsi_parse.h"
  36 #include <byteswap.h>
  37
  38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
  39
  40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
  41 {
  42         cb->buf = CALLOC(1, 4 * num_dw);
  43         cb->max_num_dw = num_dw;
  44 }
  45
  46 void r600_release_command_buffer(struct r600_command_buffer *cb)
  47 {
  48         FREE(cb->buf);
  49 }
  50
  51 void r600_init_atom(struct r600_context *rctx,
  52                     struct r600_atom *atom,
  53                     unsigned id,
  54                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  55                     unsigned num_dw)
  56 {
  57         assert(id < R600_NUM_ATOMS);
  58         assert(rctx->atoms[id] == NULL);
  59         rctx->atoms[id] = atom;
  60         atom->id = id;
  61         atom->emit = emit;
  62         atom->num_dw = num_dw;
  63         atom->dirty = false;
  64 }
  65
  66 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
  67 {
  68         r600_emit_command_buffer(rctx->rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
  69 }
  70
  71 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
  72 {
  73         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
  74         struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
  75         unsigned alpha_ref = a->sx_alpha_ref;
  76
  77         if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
  78                 alpha_ref &= ~0x1FFF;
  79         }
  80
  81         r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
  82                                a->sx_alpha_test_control |
  83                                S_028410_ALPHA_TEST_BYPASS(a->bypass));
  84         r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
  85 }
  86
  87 static void r600_texture_barrier(struct pipe_context *ctx)
  88 {
  89         struct r600_context *rctx = (struct r600_context *)ctx;
  90
  91         rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
  92         rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
  93         rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
  94 }
  95
  96 static unsigned r600_conv_pipe_prim(unsigned prim)
  97 {
  98         static const unsigned prim_conv[] = {
  99                 V_008958_DI_PT_POINTLIST,
 100                 V_008958_DI_PT_LINELIST,
 101                 V_008958_DI_PT_LINELOOP,
 102                 V_008958_DI_PT_LINESTRIP,
 103                 V_008958_DI_PT_TRILIST,
 104                 V_008958_DI_PT_TRISTRIP,
 105                 V_008958_DI_PT_TRIFAN,
 106                 V_008958_DI_PT_QUADLIST,
 107                 V_008958_DI_PT_QUADSTRIP,
 108                 V_008958_DI_PT_POLYGON,
 109                 V_008958_DI_PT_LINELIST_ADJ,
 110                 V_008958_DI_PT_LINESTRIP_ADJ,
 111                 V_008958_DI_PT_TRILIST_ADJ,
 112                 V_008958_DI_PT_TRISTRIP_ADJ,
 113                 V_008958_DI_PT_RECTLIST
 114         };
 115         return prim_conv[prim];
 116 }
 117
 118 /* common state between evergreen and r600 */
 119
 120 static void r600_bind_blend_state_internal(struct r600_context *rctx,
 121                 struct r600_blend_state *blend, bool blend_disable)
 122 {
 123         unsigned color_control;
 124         bool update_cb = false;
 125
 126         rctx->alpha_to_one = blend->alpha_to_one;
 127         rctx->dual_src_blend = blend->dual_src_blend;
 128
 129         if (!blend_disable) {
 130                 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
 131                 color_control = blend->cb_color_control;
 132         } else {
 133                 /* Blending is disabled. */
 134                 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
 135                 color_control = blend->cb_color_control_no_blend;
 136         }
 137
 138         /* Update derived states. */
 139         if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
 140                 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
 141                 update_cb = true;
 142         }
 143         if (rctx->chip_class <= R700 &&
 144             rctx->cb_misc_state.cb_color_control != color_control) {
 145                 rctx->cb_misc_state.cb_color_control = color_control;
 146                 update_cb = true;
 147         }
 148         if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
 149                 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
 150                 update_cb = true;
 151         }
 152         if (update_cb) {
 153                 rctx->cb_misc_state.atom.dirty = true;
 154         }
 155 }
 156
 157 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 158 {
 159         struct r600_context *rctx = (struct r600_context *)ctx;
 160         struct r600_blend_state *blend = (struct r600_blend_state *)state;
 161
 162         if (blend == NULL)
 163                 return;
 164
 165         r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
 166 }
 167
 168 static void r600_set_blend_color(struct pipe_context *ctx,
 169                                  const struct pipe_blend_color *state)
 170 {
 171         struct r600_context *rctx = (struct r600_context *)ctx;
 172
 173         rctx->blend_color.state = *state;
 174         rctx->blend_color.atom.dirty = true;
 175 }
 176
 177 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
 178 {
 179         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 180         struct pipe_blend_color *state = &rctx->blend_color.state;
 181
 182         r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
 183         r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
 184         r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
 185         r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
 186         r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
 187 }
 188
 189 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
 190 {
 191         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 192         struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
 193
 194         r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
 195         r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
 196         r600_write_value(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
 197         r600_write_value(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
 198 }
 199
 200 static void r600_set_clip_state(struct pipe_context *ctx,
 201                                 const struct pipe_clip_state *state)
 202 {
 203         struct r600_context *rctx = (struct r600_context *)ctx;
 204         struct pipe_constant_buffer cb;
 205
 206         rctx->clip_state.state = *state;
 207         rctx->clip_state.atom.dirty = true;
 208
 209         cb.buffer = NULL;
 210         cb.user_buffer = state->ucp;
 211         cb.buffer_offset = 0;
 212         cb.buffer_size = 4*4*8;
 213         ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
 214         pipe_resource_reference(&cb.buffer, NULL);
 215 }
 216
 217 static void r600_set_stencil_ref(struct pipe_context *ctx,
 218                                  const struct r600_stencil_ref *state)
 219 {
 220         struct r600_context *rctx = (struct r600_context *)ctx;
 221
 222         rctx->stencil_ref.state = *state;
 223         rctx->stencil_ref.atom.dirty = true;
 224 }
 225
 226 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
 227 {
 228         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 229         struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
 230
 231         r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
 232         r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
 233                          S_028430_STENCILREF(a->state.ref_value[0]) |
 234                          S_028430_STENCILMASK(a->state.valuemask[0]) |
 235                          S_028430_STENCILWRITEMASK(a->state.writemask[0]));
 236         r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
 237                          S_028434_STENCILREF_BF(a->state.ref_value[1]) |
 238                          S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
 239                          S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
 240 }
 241
 242 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 243                                       const struct pipe_stencil_ref *state)
 244 {
 245         struct r600_context *rctx = (struct r600_context *)ctx;
 246         struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
 247         struct r600_stencil_ref ref;
 248
 249         rctx->stencil_ref.pipe_state = *state;
 250
 251         if (!dsa)
 252                 return;
 253
 254         ref.ref_value[0] = state->ref_value[0];
 255         ref.ref_value[1] = state->ref_value[1];
 256         ref.valuemask[0] = dsa->valuemask[0];
 257         ref.valuemask[1] = dsa->valuemask[1];
 258         ref.writemask[0] = dsa->writemask[0];
 259         ref.writemask[1] = dsa->writemask[1];
 260
 261         r600_set_stencil_ref(ctx, &ref);
 262 }
 263
 264 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 265 {
 266         struct r600_context *rctx = (struct r600_context *)ctx;
 267         struct r600_dsa_state *dsa = state;
 268         struct r600_stencil_ref ref;
 269
 270         if (state == NULL)
 271                 return;
 272
 273         r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
 274
 275         ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
 276         ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
 277         ref.valuemask[0] = dsa->valuemask[0];
 278         ref.valuemask[1] = dsa->valuemask[1];
 279         ref.writemask[0] = dsa->writemask[0];
 280         ref.writemask[1] = dsa->writemask[1];
 281         if (rctx->zwritemask != dsa->zwritemask) {
 282                 rctx->zwritemask = dsa->zwritemask;
 283                 if (rctx->chip_class >= EVERGREEN) {
 284                         /* work around some issue when not writting to zbuffer
 285                          * we are having lockup on evergreen so do not enable
 286                          * hyperz when not writting zbuffer
 287                          */
 288                         rctx->db_misc_state.atom.dirty = true;
 289                 }
 290         }
 291
 292         r600_set_stencil_ref(ctx, &ref);
 293
 294         /* Update alphatest state. */
 295         if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
 296             rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
 297                 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
 298                 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
 299                 rctx->alphatest_state.atom.dirty = true;
 300                 if (rctx->chip_class >= EVERGREEN) {
 301                         evergreen_update_db_shader_control(rctx);
 302                 } else {
 303                         r600_update_db_shader_control(rctx);
 304                 }
 305         }
 306 }
 307
 308 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 309 {
 310         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 311         struct r600_context *rctx = (struct r600_context *)ctx;
 312
 313         if (state == NULL)
 314                 return;
 315
 316         rctx->rasterizer = rs;
 317
 318         r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
 319
 320         if (rs->offset_enable &&
 321             (rs->offset_units != rctx->poly_offset_state.offset_units ||
 322              rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
 323                 rctx->poly_offset_state.offset_units = rs->offset_units;
 324                 rctx->poly_offset_state.offset_scale = rs->offset_scale;
 325                 rctx->poly_offset_state.atom.dirty = true;
 326         }
 327
 328         /* Update clip_misc_state. */
 329         if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
 330             rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
 331                 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 332                 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
 333                 rctx->clip_misc_state.atom.dirty = true;
 334         }
 335
 336         /* Workaround for a missing scissor enable on r600. */
 337         if (rctx->chip_class == R600 &&
 338             rs->scissor_enable != rctx->scissor.enable) {
 339                 rctx->scissor.enable = rs->scissor_enable;
 340                 rctx->scissor.atom.dirty = true;
 341         }
 342
 343         /* Re-emit PA_SC_LINE_STIPPLE. */
 344         rctx->last_primitive_type = -1;
 345 }
 346
 347 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 348 {
 349         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 350
 351         r600_release_command_buffer(&rs->buffer);
 352         FREE(rs);
 353 }
 354
 355 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 356                                       struct pipe_sampler_view *state)
 357 {
 358         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 359
 360         pipe_resource_reference(&state->texture, NULL);
 361         FREE(resource);
 362 }
 363
 364 void r600_sampler_states_dirty(struct r600_context *rctx,
 365                                struct r600_sampler_states *state)
 366 {
 367         if (state->dirty_mask) {
 368                 if (state->dirty_mask & state->has_bordercolor_mask) {
 369                         rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
 370                 }
 371                 state->atom.num_dw =
 372                         util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
 373                         util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
 374                 state->atom.dirty = true;
 375         }
 376 }
 377
 378 static void r600_bind_sampler_states(struct pipe_context *pipe,
 379                                unsigned shader,
 380                                unsigned start,
 381                                unsigned count, void **states)
 382 {
 383         struct r600_context *rctx = (struct r600_context *)pipe;
 384         struct r600_textures_info *dst = &rctx->samplers[shader];
 385         struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
 386         int seamless_cube_map = -1;
 387         unsigned i;
 388         /* This sets 1-bit for states with index >= count. */
 389         uint32_t disable_mask = ~((1ull << count) - 1);
 390         /* These are the new states set by this function. */
 391         uint32_t new_mask = 0;
 392
 393         assert(start == 0); /* XXX fix below */
 394
 395         for (i = 0; i < count; i++) {
 396                 struct r600_pipe_sampler_state *rstate = rstates[i];
 397
 398                 if (rstate == dst->states.states[i]) {
 399                         continue;
 400                 }
 401
 402                 if (rstate) {
 403                         if (rstate->border_color_use) {
 404                                 dst->states.has_bordercolor_mask |= 1 << i;
 405                         } else {
 406                                 dst->states.has_bordercolor_mask &= ~(1 << i);
 407                         }
 408                         seamless_cube_map = rstate->seamless_cube_map;
 409
 410                         new_mask |= 1 << i;
 411                 } else {
 412                         disable_mask |= 1 << i;
 413                 }
 414         }
 415
 416         memcpy(dst->states.states, rstates, sizeof(void*) * count);
 417         memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
 418
 419         dst->states.enabled_mask &= ~disable_mask;
 420         dst->states.dirty_mask &= dst->states.enabled_mask;
 421         dst->states.enabled_mask |= new_mask;
 422         dst->states.dirty_mask |= new_mask;
 423         dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
 424
 425         r600_sampler_states_dirty(rctx, &dst->states);
 426
 427         /* Seamless cubemap state. */
 428         if (rctx->chip_class <= R700 &&
 429             seamless_cube_map != -1 &&
 430             seamless_cube_map != rctx->seamless_cube_map.enabled) {
 431                 /* change in TA_CNTL_AUX need a pipeline flush */
 432                 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
 433                 rctx->seamless_cube_map.enabled = seamless_cube_map;
 434                 rctx->seamless_cube_map.atom.dirty = true;
 435         }
 436 }
 437
 438 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
 439 {
 440         r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
 441 }
 442
 443 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
 444 {
 445         r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
 446 }
 447
 448 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
 449 {
 450         free(state);
 451 }
 452
 453 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
 454 {
 455         struct r600_blend_state *blend = (struct r600_blend_state*)state;
 456
 457         r600_release_command_buffer(&blend->buffer);
 458         r600_release_command_buffer(&blend->buffer_no_blend);
 459         FREE(blend);
 460 }
 461
 462 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
 463 {
 464         struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
 465
 466         r600_release_command_buffer(&dsa->buffer);
 467         free(dsa);
 468 }
 469
 470 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 471 {
 472         struct r600_context *rctx = (struct r600_context *)ctx;
 473
 474         r600_set_cso_state(&rctx->vertex_fetch_shader, state);
 475 }
 476
 477 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
 478 {
 479         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
 480         pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
 481         FREE(shader);
 482 }
 483
 484 static void r600_set_index_buffer(struct pipe_context *ctx,
 485                            const struct pipe_index_buffer *ib)
 486 {
 487         struct r600_context *rctx = (struct r600_context *)ctx;
 488
 489         if (ib) {
 490                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 491                 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
 492                 r600_context_add_resource_size(ctx, ib->buffer);
 493         } else {
 494                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 495         }
 496 }
 497
 498 void r600_vertex_buffers_dirty(struct r600_context *rctx)
 499 {
 500         if (rctx->vertex_buffer_state.dirty_mask) {
 501                 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
 502                 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
 503                                                util_bitcount(rctx->vertex_buffer_state.dirty_mask);
 504                 rctx->vertex_buffer_state.atom.dirty = true;
 505         }
 506 }
 507
 508 static void r600_set_vertex_buffers(struct pipe_context *ctx,
 509                                     unsigned start_slot, unsigned count,
 510                                     const struct pipe_vertex_buffer *input)
 511 {
 512         struct r600_context *rctx = (struct r600_context *)ctx;
 513         struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
 514         struct pipe_vertex_buffer *vb = state->vb + start_slot;
 515         unsigned i;
 516         uint32_t disable_mask = 0;
 517         /* These are the new buffers set by this function. */
 518         uint32_t new_buffer_mask = 0;
 519
 520         /* Set vertex buffers. */
 521         if (input) {
 522                 for (i = 0; i < count; i++) {
 523                         if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
 524                                 if (input[i].buffer) {
 525                                         vb[i].stride = input[i].stride;
 526                                         vb[i].buffer_offset = input[i].buffer_offset;
 527                                         pipe_resource_reference(&vb[i].buffer, input[i].buffer);
 528                                         new_buffer_mask |= 1 << i;
 529                                         r600_context_add_resource_size(ctx, input[i].buffer);
 530                                 } else {
 531                                         pipe_resource_reference(&vb[i].buffer, NULL);
 532                                         disable_mask |= 1 << i;
 533                                 }
 534                         }
 535                 }
 536         } else {
 537                 for (i = 0; i < count; i++) {
 538                         pipe_resource_reference(&vb[i].buffer, NULL);
 539                 }
 540                 disable_mask = ((1ull << count) - 1);
 541         }
 542
 543         disable_mask <<= start_slot;
 544         new_buffer_mask <<= start_slot;
 545
 546         rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
 547         rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
 548         rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
 549         rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
 550
 551         r600_vertex_buffers_dirty(rctx);
 552 }
 553
 554 void r600_sampler_views_dirty(struct r600_context *rctx,
 555                               struct r600_samplerview_state *state)
 556 {
 557         if (state->dirty_mask) {
 558                 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
 559                 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
 560                                      util_bitcount(state->dirty_mask);
 561                 state->atom.dirty = true;
 562         }
 563 }
 564
 565 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 566                                    unsigned start, unsigned count,
 567                                    struct pipe_sampler_view **views)
 568 {
 569         struct r600_context *rctx = (struct r600_context *) pipe;
 570         struct r600_textures_info *dst = &rctx->samplers[shader];
 571         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
 572         uint32_t dirty_sampler_states_mask = 0;
 573         unsigned i;
 574         /* This sets 1-bit for textures with index >= count. */
 575         uint32_t disable_mask = ~((1ull << count) - 1);
 576         /* These are the new textures set by this function. */
 577         uint32_t new_mask = 0;
 578
 579         /* Set textures with index >= count to NULL. */
 580         uint32_t remaining_mask;
 581
 582         assert(start == 0); /* XXX fix below */
 583
 584         remaining_mask = dst->views.enabled_mask & disable_mask;
 585
 586         while (remaining_mask) {
 587                 i = u_bit_scan(&remaining_mask);
 588                 assert(dst->views.views[i]);
 589
 590                 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 591         }
 592
 593         for (i = 0; i < count; i++) {
 594                 if (rviews[i] == dst->views.views[i]) {
 595                         continue;
 596                 }
 597
 598                 if (rviews[i]) {
 599                         struct r600_texture *rtex =
 600                                 (struct r600_texture*)rviews[i]->base.texture;
 601
 602                         if (rviews[i]->base.texture->target != PIPE_BUFFER) {
 603                                 if (rtex->is_depth && !rtex->is_flushing_texture) {
 604                                         dst->views.compressed_depthtex_mask |= 1 << i;
 605                                 } else {
 606                                         dst->views.compressed_depthtex_mask &= ~(1 << i);
 607                                 }
 608
 609                                 /* Track compressed colorbuffers. */
 610                                 if (rtex->cmask_size && rtex->fmask_size) {
 611                                         dst->views.compressed_colortex_mask |= 1 << i;
 612                                 } else {
 613                                         dst->views.compressed_colortex_mask &= ~(1 << i);
 614                                 }
 615                         }
 616                         /* Changing from array to non-arrays textures and vice versa requires
 617                          * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
 618                         if (rctx->chip_class <= R700 &&
 619                             (dst->states.enabled_mask & (1 << i)) &&
 620                             (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
 621                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
 622                                 dirty_sampler_states_mask |= 1 << i;
 623                         }
 624
 625                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
 626                         new_mask |= 1 << i;
 627                         r600_context_add_resource_size(pipe, views[i]->texture);
 628                 } else {
 629                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 630                         disable_mask |= 1 << i;
 631                 }
 632         }
 633
 634         dst->views.enabled_mask &= ~disable_mask;
 635         dst->views.dirty_mask &= dst->views.enabled_mask;
 636         dst->views.enabled_mask |= new_mask;
 637         dst->views.dirty_mask |= new_mask;
 638         dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
 639         dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
 640         dst->views.dirty_txq_constants = TRUE;
 641         dst->views.dirty_buffer_constants = TRUE;
 642         r600_sampler_views_dirty(rctx, &dst->views);
 643
 644         if (dirty_sampler_states_mask) {
 645                 dst->states.dirty_mask |= dirty_sampler_states_mask;
 646                 r600_sampler_states_dirty(rctx, &dst->states);
 647         }
 648 }
 649
 650 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
 651                                       struct pipe_sampler_view **views)
 652 {
 653         r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
 654 }
 655
 656 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
 657                                       struct pipe_sampler_view **views)
 658 {
 659         r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
 660 }
 661
 662 static void r600_set_viewport_state(struct pipe_context *ctx,
 663                                     const struct pipe_viewport_state *state)
 664 {
 665         struct r600_context *rctx = (struct r600_context *)ctx;
 666
 667         rctx->viewport.state = *state;
 668         rctx->viewport.atom.dirty = true;
 669 }
 670
 671 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
 672 {
 673         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 674         struct pipe_viewport_state *state = &rctx->viewport.state;
 675
 676         r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
 677         r600_write_value(cs, fui(state->scale[0]));     /* R_02843C_PA_CL_VPORT_XSCALE_0  */
 678         r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
 679         r600_write_value(cs, fui(state->scale[1]));     /* R_028444_PA_CL_VPORT_YSCALE_0  */
 680         r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
 681         r600_write_value(cs, fui(state->scale[2]));     /* R_02844C_PA_CL_VPORT_ZSCALE_0  */
 682         r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
 683 }
 684
 685 /* Compute the key for the hw shader variant */
 686 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
 687                 struct r600_pipe_shader_selector * sel)
 688 {
 689         struct r600_context *rctx = (struct r600_context *)ctx;
 690         struct r600_shader_key key;
 691         memset(&key, 0, sizeof(key));
 692
 693         if (sel->type == PIPE_SHADER_FRAGMENT) {
 694                 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
 695                 key.alpha_to_one = rctx->alpha_to_one &&
 696                                    rctx->rasterizer && rctx->rasterizer->multisample_enable &&
 697                                    !rctx->framebuffer.cb0_is_integer;
 698                 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
 699                 /* Dual-source blending only makes sense with nr_cbufs == 1. */
 700                 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
 701                         key.nr_cbufs = 2;
 702         }
 703         return key;
 704 }
 705
 706 /* Select the hw shader variant depending on the current state.
 707  * (*dirty) is set to 1 if current variant was changed */
 708 static int r600_shader_select(struct pipe_context *ctx,
 709         struct r600_pipe_shader_selector* sel,
 710         unsigned *dirty)
 711 {
 712         struct r600_shader_key key;
 713         struct r600_context *rctx = (struct r600_context *)ctx;
 714         struct r600_pipe_shader * shader = NULL;
 715         int r;
 716
 717         key = r600_shader_selector_key(ctx, sel);
 718
 719         /* Check if we don't need to change anything.
 720          * This path is also used for most shaders that don't need multiple
 721          * variants, it will cost just a computation of the key and this
 722          * test. */
 723         if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
 724                 return 0;
 725         }
 726
 727         /* lookup if we have other variants in the list */
 728         if (sel->num_shaders > 1) {
 729                 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
 730
 731                 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
 732                         p = c;
 733                         c = c->next_variant;
 734                 }
 735
 736                 if (c) {
 737                         p->next_variant = c->next_variant;
 738                         shader = c;
 739                 }
 740         }
 741
 742         if (unlikely(!shader)) {
 743                 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
 744                 shader->selector = sel;
 745
 746                 r = r600_pipe_shader_create(ctx, shader, key);
 747                 if (unlikely(r)) {
 748                         R600_ERR("Failed to build shader variant (type=%u) %d\n",
 749                                  sel->type, r);
 750                         sel->current = NULL;
 751                         FREE(shader);
 752                         return r;
 753                 }
 754
 755                 /* We don't know the value of nr_ps_max_color_exports until we built
 756                  * at least one variant, so we may need to recompute the key after
 757                  * building first variant. */
 758                 if (sel->type == PIPE_SHADER_FRAGMENT &&
 759                                 sel->num_shaders == 0) {
 760                         sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
 761                         key = r600_shader_selector_key(ctx, sel);
 762                 }
 763
 764                 shader->key = key;
 765                 sel->num_shaders++;
 766         }
 767
 768         if (dirty)
 769                 *dirty = 1;
 770
 771         shader->next_variant = sel->current;
 772         sel->current = shader;
 773
 774         if (rctx->ps_shader &&
 775             rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 776                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 777                 rctx->cb_misc_state.atom.dirty = true;
 778         }
 779         return 0;
 780 }
 781
 782 static void *r600_create_shader_state(struct pipe_context *ctx,
 783                                const struct pipe_shader_state *state,
 784                                unsigned pipe_shader_type)
 785 {
 786         struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
 787         int r;
 788
 789         sel->type = pipe_shader_type;
 790         sel->tokens = tgsi_dup_tokens(state->tokens);
 791         sel->so = state->stream_output;
 792
 793         r = r600_shader_select(ctx, sel, NULL);
 794         if (r)
 795             return NULL;
 796
 797         return sel;
 798 }
 799
 800 static void *r600_create_ps_state(struct pipe_context *ctx,
 801                                          const struct pipe_shader_state *state)
 802 {
 803         return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
 804 }
 805
 806 static void *r600_create_vs_state(struct pipe_context *ctx,
 807                                          const struct pipe_shader_state *state)
 808 {
 809         return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
 810 }
 811
 812 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
 813 {
 814         struct r600_context *rctx = (struct r600_context *)ctx;
 815
 816         if (!state)
 817                 state = rctx->dummy_pixel_shader;
 818
 819         rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
 820         r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
 821
 822         r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
 823
 824         if (rctx->chip_class <= R700) {
 825                 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
 826
 827                 if (rctx->cb_misc_state.multiwrite != multiwrite) {
 828                         rctx->cb_misc_state.multiwrite = multiwrite;
 829                         rctx->cb_misc_state.atom.dirty = true;
 830                 }
 831         }
 832
 833         if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 834                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 835                 rctx->cb_misc_state.atom.dirty = true;
 836         }
 837
 838         if (rctx->chip_class >= EVERGREEN) {
 839                 evergreen_update_db_shader_control(rctx);
 840         } else {
 841                 r600_update_db_shader_control(rctx);
 842         }
 843 }
 844
 845 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
 846 {
 847         struct r600_context *rctx = (struct r600_context *)ctx;
 848
 849         rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
 850         if (state) {
 851                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
 852
 853                 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
 854
 855                 /* Update clip misc state. */
 856                 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
 857                     rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
 858                         rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
 859                         rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
 860                         rctx->clip_misc_state.atom.dirty = true;
 861                 }
 862         }
 863 }
 864
 865 static void r600_delete_shader_selector(struct pipe_context *ctx,
 866                 struct r600_pipe_shader_selector *sel)
 867 {
 868         struct r600_pipe_shader *p = sel->current, *c;
 869         while (p) {
 870                 c = p->next_variant;
 871                 r600_pipe_shader_destroy(ctx, p);
 872                 free(p);
 873                 p = c;
 874         }
 875
 876         free(sel->tokens);
 877         free(sel);
 878 }
 879
 880
 881 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
 882 {
 883         struct r600_context *rctx = (struct r600_context *)ctx;
 884         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 885
 886         if (rctx->ps_shader == sel) {
 887                 rctx->ps_shader = NULL;
 888         }
 889
 890         r600_delete_shader_selector(ctx, sel);
 891 }
 892
 893 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
 894 {
 895         struct r600_context *rctx = (struct r600_context *)ctx;
 896         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 897
 898         if (rctx->vs_shader == sel) {
 899                 rctx->vs_shader = NULL;
 900         }
 901
 902         r600_delete_shader_selector(ctx, sel);
 903 }
 904
 905 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 906 {
 907         if (state->dirty_mask) {
 908                 rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
 909                 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 910                                                                    : util_bitcount(state->dirty_mask)*19;
 911                 state->atom.dirty = true;
 912         }
 913 }
 914
 915 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 916                                      struct pipe_constant_buffer *input)
 917 {
 918         struct r600_context *rctx = (struct r600_context *)ctx;
 919         struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
 920         struct pipe_constant_buffer *cb;
 921         const uint8_t *ptr;
 922
 923         /* Note that the state tracker can unbind constant buffers by
 924          * passing NULL here.
 925          */
 926         if (unlikely(!input)) {
 927                 state->enabled_mask &= ~(1 << index);
 928                 state->dirty_mask &= ~(1 << index);
 929                 pipe_resource_reference(&state->cb[index].buffer, NULL);
 930                 return;
 931         }
 932
 933         cb = &state->cb[index];
 934         cb->buffer_size = input->buffer_size;
 935
 936         ptr = input->user_buffer;
 937
 938         if (ptr) {
 939                 /* Upload the user buffer. */
 940                 if (R600_BIG_ENDIAN) {
 941                         uint32_t *tmpPtr;
 942                         unsigned i, size = input->buffer_size;
 943
 944                         if (!(tmpPtr = malloc(size))) {
 945                                 R600_ERR("Failed to allocate BE swap buffer.\n");
 946                                 return;
 947                         }
 948
 949                         for (i = 0; i < size / 4; ++i) {
 950                                 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
 951                         }
 952
 953                         u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
 954                         free(tmpPtr);
 955                 } else {
 956                         u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 957                 }
 958                 /* account it in gtt */
 959                 rctx->gtt += input->buffer_size;
 960         } else {
 961                 /* Setup the hw buffer. */
 962                 cb->buffer_offset = input->buffer_offset;
 963                 pipe_resource_reference(&cb->buffer, input->buffer);
 964                 r600_context_add_resource_size(ctx, input->buffer);
 965         }
 966
 967         state->enabled_mask |= 1 << index;
 968         state->dirty_mask |= 1 << index;
 969         r600_constant_buffers_dirty(rctx, state);
 970 }
 971
 972 static struct pipe_stream_output_target *
 973 r600_create_so_target(struct pipe_context *ctx,
 974                       struct pipe_resource *buffer,
 975                       unsigned buffer_offset,
 976                       unsigned buffer_size)
 977 {
 978         struct r600_context *rctx = (struct r600_context *)ctx;
 979         struct r600_so_target *t;
 980         struct r600_resource *rbuffer = (struct r600_resource*)buffer;
 981
 982         t = CALLOC_STRUCT(r600_so_target);
 983         if (!t) {
 984                 return NULL;
 985         }
 986
 987         u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
 988                              &t->buf_filled_size_offset,
 989                              (struct pipe_resource**)&t->buf_filled_size);
 990         if (!t->buf_filled_size) {
 991                 FREE(t);
 992                 return NULL;
 993         }
 994
 995         t->b.reference.count = 1;
 996         t->b.context = ctx;
 997         pipe_resource_reference(&t->b.buffer, buffer);
 998         t->b.buffer_offset = buffer_offset;
 999         t->b.buffer_size = buffer_size;
1000
1001         util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
1002                        buffer_offset + buffer_size);
1003         return &t->b;
1004 }
1005
1006 static void r600_so_target_destroy(struct pipe_context *ctx,
1007                                    struct pipe_stream_output_target *target)
1008 {
1009         struct r600_so_target *t = (struct r600_so_target*)target;
1010         pipe_resource_reference(&t->b.buffer, NULL);
1011         pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
1012         FREE(t);
1013 }
1014
1015 void r600_streamout_buffers_dirty(struct r600_context *rctx)
1016 {
1017         rctx->streamout.num_dw_for_end =
1018                 12 + /* flush_vgt_streamout */
1019                 util_bitcount(rctx->streamout.enabled_mask) * 8 + /* STRMOUT_BUFFER_UPDATE */
1020                 3 /* set_streamout_enable(0) */;
1021
1022         rctx->streamout.begin_atom.num_dw =
1023                 12 + /* flush_vgt_streamout */
1024                 6 + /* set_streamout_enable */
1025                 util_bitcount(rctx->streamout.enabled_mask) * 7 + /* SET_CONTEXT_REG */
1026                 (rctx->family >= CHIP_RS780 &&
1027                  rctx->family <= CHIP_RV740 ? util_bitcount(rctx->streamout.enabled_mask) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1028                 util_bitcount(rctx->streamout.enabled_mask & rctx->streamout.append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
1029                 util_bitcount(rctx->streamout.enabled_mask & ~rctx->streamout.append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
1030                 (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
1031                 rctx->streamout.num_dw_for_end;
1032
1033         rctx->streamout.begin_atom.dirty = true;
1034 }
1035
1036 static void r600_set_streamout_targets(struct pipe_context *ctx,
1037                                        unsigned num_targets,
1038                                        struct pipe_stream_output_target **targets,
1039                                        unsigned append_bitmask)
1040 {
1041         struct r600_context *rctx = (struct r600_context *)ctx;
1042         unsigned i;
1043
1044         /* Stop streamout. */
1045         if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
1046                 r600_emit_streamout_end(rctx);
1047         }
1048
1049         /* Set the new targets. */
1050         for (i = 0; i < num_targets; i++) {
1051                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
1052                 r600_context_add_resource_size(ctx, targets[i]->buffer);
1053         }
1054         for (; i < rctx->streamout.num_targets; i++) {
1055                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
1056         }
1057
1058         rctx->streamout.enabled_mask = (num_targets >= 1 && targets[0] ? 1 : 0) |
1059                                        (num_targets >= 2 && targets[1] ? 2 : 0) |
1060                                        (num_targets >= 3 && targets[2] ? 4 : 0) |
1061                                        (num_targets >= 4 && targets[3] ? 8 : 0);
1062
1063         rctx->streamout.num_targets = num_targets;
1064         rctx->streamout.append_bitmask = append_bitmask;
1065
1066         if (num_targets) {
1067                 r600_streamout_buffers_dirty(rctx);
1068         }
1069 }
1070
1071 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1072 {
1073         struct r600_context *rctx = (struct r600_context*)pipe;
1074
1075         if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1076                 return;
1077
1078         rctx->sample_mask.sample_mask = sample_mask;
1079         rctx->sample_mask.atom.dirty = true;
1080 }
1081
1082 /*
1083  * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1084  * doesn't require full swizzles it does need masking and setting alpha
1085  * to one, so we setup a set of 5 constants with the masks + alpha value
1086  * then in the shader, we AND the 4 components with 0xffffffff or 0,
1087  * then OR the alpha with the value given here.
1088  * We use a 6th constant to store the txq buffer size in
1089  */
1090 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1091 {
1092         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1093         int bits;
1094         uint32_t array_size;
1095         struct pipe_constant_buffer cb;
1096         int i, j;
1097
1098         if (!samplers->views.dirty_buffer_constants)
1099                 return;
1100
1101         samplers->views.dirty_buffer_constants = FALSE;
1102
1103         bits = util_last_bit(samplers->views.enabled_mask);
1104         array_size = bits * 8 * sizeof(uint32_t) * 4;
1105         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1106         memset(samplers->buffer_constants, 0, array_size);
1107         for (i = 0; i < bits; i++) {
1108                 if (samplers->views.enabled_mask & (1 << i)) {
1109                         int offset = i * 8;
1110                         const struct util_format_description *desc;
1111                         desc = util_format_description(samplers->views.views[i]->base.format);
1112
1113                         for (j = 0; j < 4; j++)
1114                                 if (j < desc->nr_channels)
1115                                         samplers->buffer_constants[offset+j] = 0xffffffff;
1116                                 else
1117                                         samplers->buffer_constants[offset+j] = 0x0;
1118                         if (desc->nr_channels < 4) {
1119                                 if (desc->channel[0].pure_integer)
1120                                         samplers->buffer_constants[offset+4] = 1;
1121                                 else
1122                                         samplers->buffer_constants[offset+4] = 0x3f800000;
1123                         } else
1124                                 samplers->buffer_constants[offset + 4] = 0;
1125
1126                         samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1127                 }
1128         }
1129
1130         cb.buffer = NULL;
1131         cb.user_buffer = samplers->buffer_constants;
1132         cb.buffer_offset = 0;
1133         cb.buffer_size = array_size;
1134         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1135         pipe_resource_reference(&cb.buffer, NULL);
1136 }
1137
1138 /* On evergreen we only need to store the buffer size for TXQ */
1139 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1140 {
1141         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1142         int bits;
1143         uint32_t array_size;
1144         struct pipe_constant_buffer cb;
1145         int i;
1146
1147         if (!samplers->views.dirty_buffer_constants)
1148                 return;
1149
1150         samplers->views.dirty_buffer_constants = FALSE;
1151
1152         bits = util_last_bit(samplers->views.enabled_mask);
1153         array_size = bits * sizeof(uint32_t) * 4;
1154         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1155         memset(samplers->buffer_constants, 0, array_size);
1156         for (i = 0; i < bits; i++)
1157                 if (samplers->views.enabled_mask & (1 << i))
1158                    samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1159
1160         cb.buffer = NULL;
1161         cb.user_buffer = samplers->buffer_constants;
1162         cb.buffer_offset = 0;
1163         cb.buffer_size = array_size;
1164         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1165         pipe_resource_reference(&cb.buffer, NULL);
1166 }
1167
1168 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1169 {
1170         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1171         int bits;
1172         uint32_t array_size;
1173         struct pipe_constant_buffer cb;
1174         int i;
1175
1176         if (!samplers->views.dirty_txq_constants)
1177                 return;
1178
1179         samplers->views.dirty_txq_constants = FALSE;
1180
1181         bits = util_last_bit(samplers->views.enabled_mask);
1182         array_size = bits * sizeof(uint32_t) * 4;
1183         samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1184         memset(samplers->txq_constants, 0, array_size);
1185         for (i = 0; i < bits; i++)
1186                 if (samplers->views.enabled_mask & (1 << i))
1187                         samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1188
1189         cb.buffer = NULL;
1190         cb.user_buffer = samplers->txq_constants;
1191         cb.buffer_offset = 0;
1192         cb.buffer_size = array_size;
1193         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1194         pipe_resource_reference(&cb.buffer, NULL);
1195 }
1196
1197 static bool r600_update_derived_state(struct r600_context *rctx)
1198 {
1199         struct pipe_context * ctx = (struct pipe_context*)rctx;
1200         unsigned ps_dirty = 0;
1201         bool blend_disable;
1202
1203         if (!rctx->blitter->running) {
1204                 unsigned i;
1205
1206                 /* Decompress textures if needed. */
1207                 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1208                         struct r600_samplerview_state *views = &rctx->samplers[i].views;
1209                         if (views->compressed_depthtex_mask) {
1210                                 r600_decompress_depth_textures(rctx, views);
1211                         }
1212                         if (views->compressed_colortex_mask) {
1213                                 r600_decompress_color_textures(rctx, views);
1214                         }
1215                 }
1216         }
1217
1218         r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1219
1220         if (rctx->ps_shader && rctx->rasterizer &&
1221             ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1222              (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1223
1224                 if (rctx->chip_class >= EVERGREEN)
1225                         evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1226                 else
1227                         r600_update_ps_state(ctx, rctx->ps_shader->current);
1228
1229                 ps_dirty = 1;
1230         }
1231
1232         if (ps_dirty)
1233                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1234
1235         /* on R600 we stuff masks + txq info into one constant buffer */
1236         /* on evergreen we only need a txq info one */
1237         if (rctx->chip_class < EVERGREEN) {
1238                 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1239                         r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1240                 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1241                         r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1242         } else {
1243                 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1244                         eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1245                 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1246                         eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1247         }
1248
1249
1250         if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1251                 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1252         if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1253                 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1254
1255         if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1256                 if (!r600_adjust_gprs(rctx)) {
1257                         /* discard rendering */
1258                         return false;
1259                 }
1260         }
1261
1262         blend_disable = (rctx->dual_src_blend &&
1263                         rctx->ps_shader->current->nr_ps_color_outputs < 2);
1264
1265         if (blend_disable != rctx->force_blend_disable) {
1266                 rctx->force_blend_disable = blend_disable;
1267                 r600_bind_blend_state_internal(rctx,
1268                                                rctx->blend_state.cso,
1269                                                blend_disable);
1270         }
1271         return true;
1272 }
1273
1274 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1275 {
1276         static const int prim_conv[] = {
1277                 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1278                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1279                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1280                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1281                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1282                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1283                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1284                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1285                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1286                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1287                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1288                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1289                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1290                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1291                 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1292         };
1293         assert(mode < Elements(prim_conv));
1294
1295         return prim_conv[mode];
1296 }
1297
1298 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1299 {
1300         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1301         struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1302
1303         r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1304                                state->pa_cl_clip_cntl |
1305                                (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1306         r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1307                                state->pa_cl_vs_out_cntl |
1308                                (state->clip_plane_enable & state->clip_dist_write));
1309 }
1310
1311 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1312 {
1313         struct r600_context *rctx = (struct r600_context *)ctx;
1314         struct pipe_draw_info info = *dinfo;
1315         struct pipe_index_buffer ib = {};
1316         unsigned i;
1317         struct r600_block *dirty_block = NULL, *next_block = NULL;
1318         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1319
1320         if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1321                 assert(0);
1322                 return;
1323         }
1324
1325         if (!rctx->vs_shader) {
1326                 assert(0);
1327                 return;
1328         }
1329
1330         /* make sure that the gfx ring is only one active */
1331         if (rctx->rings.dma.cs) {
1332                 rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1333         }
1334
1335         if (!r600_update_derived_state(rctx)) {
1336                 /* useless to render because current rendering command
1337                  * can't be achieved
1338                  */
1339                 return;
1340         }
1341
1342         if (info.indexed) {
1343                 /* Initialize the index buffer struct. */
1344                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1345                 ib.user_buffer = rctx->index_buffer.user_buffer;
1346                 ib.index_size = rctx->index_buffer.index_size;
1347                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1348
1349                 /* Translate 8-bit indices to 16-bit. */
1350                 if (ib.index_size == 1) {
1351                         struct pipe_resource *out_buffer = NULL;
1352                         unsigned out_offset;
1353                         void *ptr;
1354
1355                         u_upload_alloc(rctx->uploader, 0, info.count * 2,
1356                                        &out_offset, &out_buffer, &ptr);
1357
1358                         util_shorten_ubyte_elts_to_userptr(
1359                                                 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1360
1361                         pipe_resource_reference(&ib.buffer, NULL);
1362                         ib.user_buffer = NULL;
1363                         ib.buffer = out_buffer;
1364                         ib.offset = out_offset;
1365                         ib.index_size = 2;
1366                 }
1367
1368                 /* Upload the index buffer.
1369                  * The upload is skipped for small index counts on little-endian machines
1370                  * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1371                  * Note: Instanced rendering in combination with immediate indices hangs. */
1372                 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1373                                        info.count*ib.index_size > 20)) {
1374                         u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1375                                       ib.user_buffer, &ib.offset, &ib.buffer);
1376                         ib.user_buffer = NULL;
1377                 }
1378         } else {
1379                 info.index_bias = info.start;
1380         }
1381
1382         /* Set the index offset and primitive restart. */
1383         if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1384             rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1385             rctx->vgt_state.vgt_indx_offset != info.index_bias) {
1386                 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1387                 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1388                 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1389                 rctx->vgt_state.atom.dirty = true;
1390         }
1391
1392         /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1393         if (rctx->chip_class == R600) {
1394                 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1395                 rctx->cb_misc_state.atom.dirty = true;
1396         }
1397
1398         /* Emit states. */
1399         r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1400         r600_flush_emit(rctx);
1401
1402         for (i = 0; i < R600_NUM_ATOMS; i++) {
1403                 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1404                         continue;
1405                 }
1406                 r600_emit_atom(rctx, rctx->atoms[i]);
1407         }
1408         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1409                 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1410         }
1411         rctx->pm4_dirty_cdwords = 0;
1412
1413         /* Update start instance. */
1414         if (rctx->last_start_instance != info.start_instance) {
1415                 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1416                 rctx->last_start_instance = info.start_instance;
1417         }
1418
1419         /* Update the primitive type. */
1420         if (rctx->last_primitive_type != info.mode) {
1421                 unsigned ls_mask = 0;
1422
1423                 if (info.mode == PIPE_PRIM_LINES)
1424                         ls_mask = 1;
1425                 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1426                          info.mode == PIPE_PRIM_LINE_LOOP)
1427                         ls_mask = 2;
1428
1429                 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1430                                        S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1431                                        (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1432                 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1433                                        r600_conv_prim_to_gs_out(info.mode));
1434                 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1435                                       r600_conv_pipe_prim(info.mode));
1436
1437                 rctx->last_primitive_type = info.mode;
1438         }
1439
1440         /* Draw packets. */
1441         cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1442         cs->buf[cs->cdw++] = info.instance_count;
1443         if (info.indexed) {
1444                 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1445                 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1446                                         (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1447                                         (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1448
1449                 if (ib.user_buffer) {
1450                         unsigned size_bytes = info.count*ib.index_size;
1451                         unsigned size_dw = align(size_bytes, 4) / 4;
1452                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1453                         cs->buf[cs->cdw++] = info.count;
1454                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1455                         memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1456                         cs->cdw += size_dw;
1457                 } else {
1458                         uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1459                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1460                         cs->buf[cs->cdw++] = va;
1461                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1462                         cs->buf[cs->cdw++] = info.count;
1463                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1464                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1465                         cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1466                 }
1467         } else {
1468                 if (info.count_from_stream_output) {
1469                         struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1470                         uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1471
1472                         r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1473
1474                         cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1475                         cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1476                         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;     /* src address lo */
1477                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1478                         cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1479                         cs->buf[cs->cdw++] = 0; /* unused */
1480
1481                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1482                         cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1483                 }
1484
1485                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1486                 cs->buf[cs->cdw++] = info.count;
1487                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1488                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1489         }
1490
1491 #if R600_TRACE_CS
1492         if (rctx->screen->trace_bo) {
1493                 r600_trace_emit(rctx);
1494         }
1495 #endif
1496
1497         /* Set the depth buffer as dirty. */
1498         if (rctx->framebuffer.state.zsbuf) {
1499                 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1500                 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1501
1502                 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1503         }
1504         if (rctx->framebuffer.compressed_cb_mask) {
1505                 struct pipe_surface *surf;
1506                 struct r600_texture *rtex;
1507                 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1508
1509                 do {
1510                         unsigned i = u_bit_scan(&mask);
1511                         surf = rctx->framebuffer.state.cbufs[i];
1512                         rtex = (struct r600_texture*)surf->texture;
1513
1514                         rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1515
1516                 } while (mask);
1517         }
1518
1519         pipe_resource_reference(&ib.buffer, NULL);
1520 }
1521
1522 void r600_draw_rectangle(struct blitter_context *blitter,
1523                          int x1, int y1, int x2, int y2, float depth,
1524                          enum blitter_attrib_type type, const union pipe_color_union *attrib)
1525 {
1526         struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1527         struct pipe_viewport_state viewport;
1528         struct pipe_resource *buf = NULL;
1529         unsigned offset = 0;
1530         float *vb;
1531
1532         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1533                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1534                 return;
1535         }
1536
1537         /* Some operations (like color resolve on r6xx) don't work
1538          * with the conventional primitive types.
1539          * One that works is PT_RECTLIST, which we use here. */
1540
1541         /* setup viewport */
1542         viewport.scale[0] = 1.0f;
1543         viewport.scale[1] = 1.0f;
1544         viewport.scale[2] = 1.0f;
1545         viewport.scale[3] = 1.0f;
1546         viewport.translate[0] = 0.0f;
1547         viewport.translate[1] = 0.0f;
1548         viewport.translate[2] = 0.0f;
1549         viewport.translate[3] = 0.0f;
1550         rctx->context.set_viewport_state(&rctx->context, &viewport);
1551
1552         /* Upload vertices. The hw rectangle has only 3 vertices,
1553          * I guess the 4th one is derived from the first 3.
1554          * The vertex specification should match u_blitter's vertex element state. */
1555         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1556         vb[0] = x1;
1557         vb[1] = y1;
1558         vb[2] = depth;
1559         vb[3] = 1;
1560
1561         vb[8] = x1;
1562         vb[9] = y2;
1563         vb[10] = depth;
1564         vb[11] = 1;
1565
1566         vb[16] = x2;
1567         vb[17] = y1;
1568         vb[18] = depth;
1569         vb[19] = 1;
1570
1571         if (attrib) {
1572                 memcpy(vb+4, attrib->f, sizeof(float)*4);
1573                 memcpy(vb+12, attrib->f, sizeof(float)*4);
1574                 memcpy(vb+20, attrib->f, sizeof(float)*4);
1575         }
1576
1577         /* draw */
1578         util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
1579                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
1580         pipe_resource_reference(&buf, NULL);
1581 }
1582
1583 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1584                                  struct r600_pipe_state *state,
1585                                  uint32_t offset, uint32_t value,
1586                                  uint32_t range_id, uint32_t block_id,
1587                                  struct r600_resource *bo,
1588                                  enum radeon_bo_usage usage)
1589
1590 {
1591         struct r600_range *range;
1592         struct r600_block *block;
1593
1594         if (bo) assert(usage);
1595
1596         range = &ctx->range[range_id];
1597         block = range->blocks[block_id];
1598         state->regs[state->nregs].block = block;
1599         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1600
1601         state->regs[state->nregs].value = value;
1602         state->regs[state->nregs].bo = bo;
1603         state->regs[state->nregs].bo_usage = usage;
1604
1605         state->nregs++;
1606         assert(state->nregs < R600_BLOCK_MAX_REG);
1607 }
1608
1609 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1610                               struct r600_pipe_state *state,
1611                               uint32_t offset, uint32_t value,
1612                               uint32_t range_id, uint32_t block_id)
1613 {
1614         _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1615                                     range_id, block_id, NULL, 0);
1616 }
1617
1618 uint32_t r600_translate_stencil_op(int s_op)
1619 {
1620         switch (s_op) {
1621         case PIPE_STENCIL_OP_KEEP:
1622                 return V_028800_STENCIL_KEEP;
1623         case PIPE_STENCIL_OP_ZERO:
1624                 return V_028800_STENCIL_ZERO;
1625         case PIPE_STENCIL_OP_REPLACE:
1626                 return V_028800_STENCIL_REPLACE;
1627         case PIPE_STENCIL_OP_INCR:
1628                 return V_028800_STENCIL_INCR;
1629         case PIPE_STENCIL_OP_DECR:
1630                 return V_028800_STENCIL_DECR;
1631         case PIPE_STENCIL_OP_INCR_WRAP:
1632                 return V_028800_STENCIL_INCR_WRAP;
1633         case PIPE_STENCIL_OP_DECR_WRAP:
1634                 return V_028800_STENCIL_DECR_WRAP;
1635         case PIPE_STENCIL_OP_INVERT:
1636                 return V_028800_STENCIL_INVERT;
1637         default:
1638                 R600_ERR("Unknown stencil op %d", s_op);
1639                 assert(0);
1640                 break;
1641         }
1642         return 0;
1643 }
1644
1645 uint32_t r600_translate_fill(uint32_t func)
1646 {
1647         switch(func) {
1648         case PIPE_POLYGON_MODE_FILL:
1649                 return 2;
1650         case PIPE_POLYGON_MODE_LINE:
1651                 return 1;
1652         case PIPE_POLYGON_MODE_POINT:
1653                 return 0;
1654         default:
1655                 assert(0);
1656                 return 0;
1657         }
1658 }
1659
1660 unsigned r600_tex_wrap(unsigned wrap)
1661 {
1662         switch (wrap) {
1663         default:
1664         case PIPE_TEX_WRAP_REPEAT:
1665                 return V_03C000_SQ_TEX_WRAP;
1666         case PIPE_TEX_WRAP_CLAMP:
1667                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1668         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1669                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1670         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1671                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1672         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1673                 return V_03C000_SQ_TEX_MIRROR;
1674         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1675                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1676         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1677                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1678         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1679                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1680         }
1681 }
1682
1683 unsigned r600_tex_filter(unsigned filter)
1684 {
1685         switch (filter) {
1686         default:
1687         case PIPE_TEX_FILTER_NEAREST:
1688                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1689         case PIPE_TEX_FILTER_LINEAR:
1690                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1691         }
1692 }
1693
1694 unsigned r600_tex_mipfilter(unsigned filter)
1695 {
1696         switch (filter) {
1697         case PIPE_TEX_MIPFILTER_NEAREST:
1698                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1699         case PIPE_TEX_MIPFILTER_LINEAR:
1700                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1701         default:
1702         case PIPE_TEX_MIPFILTER_NONE:
1703                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1704         }
1705 }
1706
1707 unsigned r600_tex_compare(unsigned compare)
1708 {
1709         switch (compare) {
1710         default:
1711         case PIPE_FUNC_NEVER:
1712                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1713         case PIPE_FUNC_LESS:
1714                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1715         case PIPE_FUNC_EQUAL:
1716                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1717         case PIPE_FUNC_LEQUAL:
1718                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1719         case PIPE_FUNC_GREATER:
1720                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1721         case PIPE_FUNC_NOTEQUAL:
1722                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1723         case PIPE_FUNC_GEQUAL:
1724                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1725         case PIPE_FUNC_ALWAYS:
1726                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1727         }
1728 }
1729
1730 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1731 {
1732         return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1733                wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1734                (linear_filter &&
1735                 (wrap == PIPE_TEX_WRAP_CLAMP ||
1736                  wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1737 }
1738
1739 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1740 {
1741         bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1742                              state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1743
1744         return (state->border_color.ui[0] || state->border_color.ui[1] ||
1745                 state->border_color.ui[2] || state->border_color.ui[3]) &&
1746                (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1747                 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1748                 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1749 }
1750
1751 /* keep this at the end of this file, please */
1752 void r600_init_common_state_functions(struct r600_context *rctx)
1753 {
1754         rctx->context.create_fs_state = r600_create_ps_state;
1755         rctx->context.create_vs_state = r600_create_vs_state;
1756         rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1757         rctx->context.bind_blend_state = r600_bind_blend_state;
1758         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1759         rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1760         rctx->context.bind_fs_state = r600_bind_ps_state;
1761         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1762         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1763         rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1764         rctx->context.bind_vs_state = r600_bind_vs_state;
1765         rctx->context.delete_blend_state = r600_delete_blend_state;
1766         rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1767         rctx->context.delete_fs_state = r600_delete_ps_state;
1768         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1769         rctx->context.delete_sampler_state = r600_delete_sampler_state;
1770         rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1771         rctx->context.delete_vs_state = r600_delete_vs_state;
1772         rctx->context.set_blend_color = r600_set_blend_color;
1773         rctx->context.set_clip_state = r600_set_clip_state;
1774         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1775         rctx->context.set_sample_mask = r600_set_sample_mask;
1776         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1777         rctx->context.set_viewport_state = r600_set_viewport_state;
1778         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1779         rctx->context.set_index_buffer = r600_set_index_buffer;
1780         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1781         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1782         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1783         rctx->context.texture_barrier = r600_texture_barrier;
1784         rctx->context.create_stream_output_target = r600_create_so_target;
1785         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1786         rctx->context.set_stream_output_targets = r600_set_streamout_targets;
1787         rctx->context.draw_vbo = r600_draw_vbo;
1788 }
1789
1790 #if R600_TRACE_CS
1791 void r600_trace_emit(struct r600_context *rctx)
1792 {
1793         struct r600_screen *rscreen = rctx->screen;
1794         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1795         uint64_t va;
1796         uint32_t reloc;
1797
1798         va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo);
1799         reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
1800         r600_write_value(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
1801         r600_write_value(cs, va & 0xFFFFFFFFUL);
1802         r600_write_value(cs, (va >> 32UL) & 0xFFUL);
1803         r600_write_value(cs, cs->cdw);
1804         r600_write_value(cs, rscreen->cs_count);
1805         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1806         r600_write_value(cs, reloc);
1807 }
1808 #endif