src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "r600_formats.h"
  28 #include "r600_shader.h"
  29 #include "r600d.h"
  30
  31 #include "util/u_draw_quad.h"
  32 #include "util/u_index_modify.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_upload_mgr.h"
  35 #include "util/u_math.h"
  36 #include "tgsi/tgsi_parse.h"
  37
  38 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
  39
  40 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
  41 {
  42         assert(!cb->buf);
  43         cb->buf = CALLOC(1, 4 * num_dw);
  44         cb->max_num_dw = num_dw;
  45 }
  46
  47 void r600_release_command_buffer(struct r600_command_buffer *cb)
  48 {
  49         FREE(cb->buf);
  50 }
  51
  52 void r600_init_atom(struct r600_context *rctx,
  53                     struct r600_atom *atom,
  54                     unsigned id,
  55                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  56                     unsigned num_dw)
  57 {
  58         assert(id < R600_NUM_ATOMS);
  59         assert(rctx->atoms[id] == NULL);
  60         rctx->atoms[id] = atom;
  61         atom->id = id;
  62         atom->emit = emit;
  63         atom->num_dw = num_dw;
  64         atom->dirty = false;
  65 }
  66
  67 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
  68 {
  69         r600_emit_command_buffer(rctx->rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
  70 }
  71
  72 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
  73 {
  74         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
  75         struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
  76         unsigned alpha_ref = a->sx_alpha_ref;
  77
  78         if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
  79                 alpha_ref &= ~0x1FFF;
  80         }
  81
  82         r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
  83                                a->sx_alpha_test_control |
  84                                S_028410_ALPHA_TEST_BYPASS(a->bypass));
  85         r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
  86 }
  87
  88 static void r600_texture_barrier(struct pipe_context *ctx)
  89 {
  90         struct r600_context *rctx = (struct r600_context *)ctx;
  91
  92         rctx->flags |= R600_CONTEXT_INV_TEX_CACHE |
  93                        R600_CONTEXT_FLUSH_AND_INV_CB |
  94                        R600_CONTEXT_FLUSH_AND_INV |
  95                        R600_CONTEXT_WAIT_3D_IDLE;
  96 }
  97
  98 static unsigned r600_conv_pipe_prim(unsigned prim)
  99 {
 100         static const unsigned prim_conv[] = {
 101                 V_008958_DI_PT_POINTLIST,
 102                 V_008958_DI_PT_LINELIST,
 103                 V_008958_DI_PT_LINELOOP,
 104                 V_008958_DI_PT_LINESTRIP,
 105                 V_008958_DI_PT_TRILIST,
 106                 V_008958_DI_PT_TRISTRIP,
 107                 V_008958_DI_PT_TRIFAN,
 108                 V_008958_DI_PT_QUADLIST,
 109                 V_008958_DI_PT_QUADSTRIP,
 110                 V_008958_DI_PT_POLYGON,
 111                 V_008958_DI_PT_LINELIST_ADJ,
 112                 V_008958_DI_PT_LINESTRIP_ADJ,
 113                 V_008958_DI_PT_TRILIST_ADJ,
 114                 V_008958_DI_PT_TRISTRIP_ADJ,
 115                 V_008958_DI_PT_RECTLIST
 116         };
 117         return prim_conv[prim];
 118 }
 119
 120 /* common state between evergreen and r600 */
 121
 122 static void r600_bind_blend_state_internal(struct r600_context *rctx,
 123                 struct r600_blend_state *blend, bool blend_disable)
 124 {
 125         unsigned color_control;
 126         bool update_cb = false;
 127
 128         rctx->alpha_to_one = blend->alpha_to_one;
 129         rctx->dual_src_blend = blend->dual_src_blend;
 130
 131         if (!blend_disable) {
 132                 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
 133                 color_control = blend->cb_color_control;
 134         } else {
 135                 /* Blending is disabled. */
 136                 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
 137                 color_control = blend->cb_color_control_no_blend;
 138         }
 139
 140         /* Update derived states. */
 141         if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
 142                 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
 143                 update_cb = true;
 144         }
 145         if (rctx->chip_class <= R700 &&
 146             rctx->cb_misc_state.cb_color_control != color_control) {
 147                 rctx->cb_misc_state.cb_color_control = color_control;
 148                 update_cb = true;
 149         }
 150         if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
 151                 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
 152                 update_cb = true;
 153         }
 154         if (update_cb) {
 155                 rctx->cb_misc_state.atom.dirty = true;
 156         }
 157 }
 158
 159 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 160 {
 161         struct r600_context *rctx = (struct r600_context *)ctx;
 162         struct r600_blend_state *blend = (struct r600_blend_state *)state;
 163
 164         if (blend == NULL)
 165                 return;
 166
 167         r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
 168 }
 169
 170 static void r600_set_blend_color(struct pipe_context *ctx,
 171                                  const struct pipe_blend_color *state)
 172 {
 173         struct r600_context *rctx = (struct r600_context *)ctx;
 174
 175         rctx->blend_color.state = *state;
 176         rctx->blend_color.atom.dirty = true;
 177 }
 178
 179 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
 180 {
 181         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 182         struct pipe_blend_color *state = &rctx->blend_color.state;
 183
 184         r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
 185         r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
 186         r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
 187         r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
 188         r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
 189 }
 190
 191 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
 192 {
 193         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 194         struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
 195
 196         r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
 197         r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
 198         r600_write_value(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
 199         r600_write_value(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
 200 }
 201
 202 static void r600_set_clip_state(struct pipe_context *ctx,
 203                                 const struct pipe_clip_state *state)
 204 {
 205         struct r600_context *rctx = (struct r600_context *)ctx;
 206         struct pipe_constant_buffer cb;
 207
 208         rctx->clip_state.state = *state;
 209         rctx->clip_state.atom.dirty = true;
 210
 211         cb.buffer = NULL;
 212         cb.user_buffer = state->ucp;
 213         cb.buffer_offset = 0;
 214         cb.buffer_size = 4*4*8;
 215         ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
 216         pipe_resource_reference(&cb.buffer, NULL);
 217 }
 218
 219 static void r600_set_stencil_ref(struct pipe_context *ctx,
 220                                  const struct r600_stencil_ref *state)
 221 {
 222         struct r600_context *rctx = (struct r600_context *)ctx;
 223
 224         rctx->stencil_ref.state = *state;
 225         rctx->stencil_ref.atom.dirty = true;
 226 }
 227
 228 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
 229 {
 230         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 231         struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
 232
 233         r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
 234         r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
 235                          S_028430_STENCILREF(a->state.ref_value[0]) |
 236                          S_028430_STENCILMASK(a->state.valuemask[0]) |
 237                          S_028430_STENCILWRITEMASK(a->state.writemask[0]));
 238         r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
 239                          S_028434_STENCILREF_BF(a->state.ref_value[1]) |
 240                          S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
 241                          S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
 242 }
 243
 244 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 245                                       const struct pipe_stencil_ref *state)
 246 {
 247         struct r600_context *rctx = (struct r600_context *)ctx;
 248         struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
 249         struct r600_stencil_ref ref;
 250
 251         rctx->stencil_ref.pipe_state = *state;
 252
 253         if (!dsa)
 254                 return;
 255
 256         ref.ref_value[0] = state->ref_value[0];
 257         ref.ref_value[1] = state->ref_value[1];
 258         ref.valuemask[0] = dsa->valuemask[0];
 259         ref.valuemask[1] = dsa->valuemask[1];
 260         ref.writemask[0] = dsa->writemask[0];
 261         ref.writemask[1] = dsa->writemask[1];
 262
 263         r600_set_stencil_ref(ctx, &ref);
 264 }
 265
 266 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 267 {
 268         struct r600_context *rctx = (struct r600_context *)ctx;
 269         struct r600_dsa_state *dsa = state;
 270         struct r600_stencil_ref ref;
 271
 272         if (state == NULL)
 273                 return;
 274
 275         r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
 276
 277         ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
 278         ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
 279         ref.valuemask[0] = dsa->valuemask[0];
 280         ref.valuemask[1] = dsa->valuemask[1];
 281         ref.writemask[0] = dsa->writemask[0];
 282         ref.writemask[1] = dsa->writemask[1];
 283         if (rctx->zwritemask != dsa->zwritemask) {
 284                 rctx->zwritemask = dsa->zwritemask;
 285                 if (rctx->chip_class >= EVERGREEN) {
 286                         /* work around some issue when not writting to zbuffer
 287                          * we are having lockup on evergreen so do not enable
 288                          * hyperz when not writting zbuffer
 289                          */
 290                         rctx->db_misc_state.atom.dirty = true;
 291                 }
 292         }
 293
 294         r600_set_stencil_ref(ctx, &ref);
 295
 296         /* Update alphatest state. */
 297         if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
 298             rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
 299                 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
 300                 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
 301                 rctx->alphatest_state.atom.dirty = true;
 302                 if (rctx->chip_class >= EVERGREEN) {
 303                         evergreen_update_db_shader_control(rctx);
 304                 } else {
 305                         r600_update_db_shader_control(rctx);
 306                 }
 307         }
 308 }
 309
 310 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 311 {
 312         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 313         struct r600_context *rctx = (struct r600_context *)ctx;
 314
 315         if (state == NULL)
 316                 return;
 317
 318         rctx->rasterizer = rs;
 319
 320         r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
 321
 322         if (rs->offset_enable &&
 323             (rs->offset_units != rctx->poly_offset_state.offset_units ||
 324              rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
 325                 rctx->poly_offset_state.offset_units = rs->offset_units;
 326                 rctx->poly_offset_state.offset_scale = rs->offset_scale;
 327                 rctx->poly_offset_state.atom.dirty = true;
 328         }
 329
 330         /* Update clip_misc_state. */
 331         if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
 332             rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
 333                 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 334                 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
 335                 rctx->clip_misc_state.atom.dirty = true;
 336         }
 337
 338         /* Workaround for a missing scissor enable on r600. */
 339         if (rctx->chip_class == R600 &&
 340             rs->scissor_enable != rctx->scissor.enable) {
 341                 rctx->scissor.enable = rs->scissor_enable;
 342                 rctx->scissor.atom.dirty = true;
 343         }
 344
 345         /* Re-emit PA_SC_LINE_STIPPLE. */
 346         rctx->last_primitive_type = -1;
 347 }
 348
 349 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 350 {
 351         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 352
 353         r600_release_command_buffer(&rs->buffer);
 354         FREE(rs);
 355 }
 356
 357 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 358                                       struct pipe_sampler_view *state)
 359 {
 360         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 361
 362         pipe_resource_reference(&state->texture, NULL);
 363         FREE(resource);
 364 }
 365
 366 void r600_sampler_states_dirty(struct r600_context *rctx,
 367                                struct r600_sampler_states *state)
 368 {
 369         if (state->dirty_mask) {
 370                 if (state->dirty_mask & state->has_bordercolor_mask) {
 371                         rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
 372                 }
 373                 state->atom.num_dw =
 374                         util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
 375                         util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
 376                 state->atom.dirty = true;
 377         }
 378 }
 379
 380 static void r600_bind_sampler_states(struct pipe_context *pipe,
 381                                unsigned shader,
 382                                unsigned start,
 383                                unsigned count, void **states)
 384 {
 385         struct r600_context *rctx = (struct r600_context *)pipe;
 386         struct r600_textures_info *dst = &rctx->samplers[shader];
 387         struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
 388         int seamless_cube_map = -1;
 389         unsigned i;
 390         /* This sets 1-bit for states with index >= count. */
 391         uint32_t disable_mask = ~((1ull << count) - 1);
 392         /* These are the new states set by this function. */
 393         uint32_t new_mask = 0;
 394
 395         assert(start == 0); /* XXX fix below */
 396
 397         for (i = 0; i < count; i++) {
 398                 struct r600_pipe_sampler_state *rstate = rstates[i];
 399
 400                 if (rstate == dst->states.states[i]) {
 401                         continue;
 402                 }
 403
 404                 if (rstate) {
 405                         if (rstate->border_color_use) {
 406                                 dst->states.has_bordercolor_mask |= 1 << i;
 407                         } else {
 408                                 dst->states.has_bordercolor_mask &= ~(1 << i);
 409                         }
 410                         seamless_cube_map = rstate->seamless_cube_map;
 411
 412                         new_mask |= 1 << i;
 413                 } else {
 414                         disable_mask |= 1 << i;
 415                 }
 416         }
 417
 418         memcpy(dst->states.states, rstates, sizeof(void*) * count);
 419         memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
 420
 421         dst->states.enabled_mask &= ~disable_mask;
 422         dst->states.dirty_mask &= dst->states.enabled_mask;
 423         dst->states.enabled_mask |= new_mask;
 424         dst->states.dirty_mask |= new_mask;
 425         dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
 426
 427         r600_sampler_states_dirty(rctx, &dst->states);
 428
 429         /* Seamless cubemap state. */
 430         if (rctx->chip_class <= R700 &&
 431             seamless_cube_map != -1 &&
 432             seamless_cube_map != rctx->seamless_cube_map.enabled) {
 433                 /* change in TA_CNTL_AUX need a pipeline flush */
 434                 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
 435                 rctx->seamless_cube_map.enabled = seamless_cube_map;
 436                 rctx->seamless_cube_map.atom.dirty = true;
 437         }
 438 }
 439
 440 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
 441 {
 442         r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
 443 }
 444
 445 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
 446 {
 447         r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
 448 }
 449
 450 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
 451 {
 452         free(state);
 453 }
 454
 455 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
 456 {
 457         struct r600_blend_state *blend = (struct r600_blend_state*)state;
 458
 459         r600_release_command_buffer(&blend->buffer);
 460         r600_release_command_buffer(&blend->buffer_no_blend);
 461         FREE(blend);
 462 }
 463
 464 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
 465 {
 466         struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
 467
 468         r600_release_command_buffer(&dsa->buffer);
 469         free(dsa);
 470 }
 471
 472 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 473 {
 474         struct r600_context *rctx = (struct r600_context *)ctx;
 475
 476         r600_set_cso_state(&rctx->vertex_fetch_shader, state);
 477 }
 478
 479 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
 480 {
 481         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
 482         pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
 483         FREE(shader);
 484 }
 485
 486 static void r600_set_index_buffer(struct pipe_context *ctx,
 487                            const struct pipe_index_buffer *ib)
 488 {
 489         struct r600_context *rctx = (struct r600_context *)ctx;
 490
 491         if (ib) {
 492                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 493                 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
 494                 r600_context_add_resource_size(ctx, ib->buffer);
 495         } else {
 496                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 497         }
 498 }
 499
 500 void r600_vertex_buffers_dirty(struct r600_context *rctx)
 501 {
 502         if (rctx->vertex_buffer_state.dirty_mask) {
 503                 rctx->flags |= R600_CONTEXT_INV_VERTEX_CACHE;
 504                 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
 505                                                util_bitcount(rctx->vertex_buffer_state.dirty_mask);
 506                 rctx->vertex_buffer_state.atom.dirty = true;
 507         }
 508 }
 509
 510 static void r600_set_vertex_buffers(struct pipe_context *ctx,
 511                                     unsigned start_slot, unsigned count,
 512                                     const struct pipe_vertex_buffer *input)
 513 {
 514         struct r600_context *rctx = (struct r600_context *)ctx;
 515         struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
 516         struct pipe_vertex_buffer *vb = state->vb + start_slot;
 517         unsigned i;
 518         uint32_t disable_mask = 0;
 519         /* These are the new buffers set by this function. */
 520         uint32_t new_buffer_mask = 0;
 521
 522         /* Set vertex buffers. */
 523         if (input) {
 524                 for (i = 0; i < count; i++) {
 525                         if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
 526                                 if (input[i].buffer) {
 527                                         vb[i].stride = input[i].stride;
 528                                         vb[i].buffer_offset = input[i].buffer_offset;
 529                                         pipe_resource_reference(&vb[i].buffer, input[i].buffer);
 530                                         new_buffer_mask |= 1 << i;
 531                                         r600_context_add_resource_size(ctx, input[i].buffer);
 532                                 } else {
 533                                         pipe_resource_reference(&vb[i].buffer, NULL);
 534                                         disable_mask |= 1 << i;
 535                                 }
 536                         }
 537                 }
 538         } else {
 539                 for (i = 0; i < count; i++) {
 540                         pipe_resource_reference(&vb[i].buffer, NULL);
 541                 }
 542                 disable_mask = ((1ull << count) - 1);
 543         }
 544
 545         disable_mask <<= start_slot;
 546         new_buffer_mask <<= start_slot;
 547
 548         rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
 549         rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
 550         rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
 551         rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
 552
 553         r600_vertex_buffers_dirty(rctx);
 554 }
 555
 556 void r600_sampler_views_dirty(struct r600_context *rctx,
 557                               struct r600_samplerview_state *state)
 558 {
 559         if (state->dirty_mask) {
 560                 rctx->flags |= R600_CONTEXT_INV_TEX_CACHE;
 561                 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
 562                                      util_bitcount(state->dirty_mask);
 563                 state->atom.dirty = true;
 564         }
 565 }
 566
 567 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 568                                    unsigned start, unsigned count,
 569                                    struct pipe_sampler_view **views)
 570 {
 571         struct r600_context *rctx = (struct r600_context *) pipe;
 572         struct r600_textures_info *dst = &rctx->samplers[shader];
 573         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
 574         uint32_t dirty_sampler_states_mask = 0;
 575         unsigned i;
 576         /* This sets 1-bit for textures with index >= count. */
 577         uint32_t disable_mask = ~((1ull << count) - 1);
 578         /* These are the new textures set by this function. */
 579         uint32_t new_mask = 0;
 580
 581         /* Set textures with index >= count to NULL. */
 582         uint32_t remaining_mask;
 583
 584         assert(start == 0); /* XXX fix below */
 585
 586         remaining_mask = dst->views.enabled_mask & disable_mask;
 587
 588         while (remaining_mask) {
 589                 i = u_bit_scan(&remaining_mask);
 590                 assert(dst->views.views[i]);
 591
 592                 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 593         }
 594
 595         for (i = 0; i < count; i++) {
 596                 if (rviews[i] == dst->views.views[i]) {
 597                         continue;
 598                 }
 599
 600                 if (rviews[i]) {
 601                         struct r600_texture *rtex =
 602                                 (struct r600_texture*)rviews[i]->base.texture;
 603
 604                         if (rviews[i]->base.texture->target != PIPE_BUFFER) {
 605                                 if (rtex->is_depth && !rtex->is_flushing_texture) {
 606                                         dst->views.compressed_depthtex_mask |= 1 << i;
 607                                 } else {
 608                                         dst->views.compressed_depthtex_mask &= ~(1 << i);
 609                                 }
 610
 611                                 /* Track compressed colorbuffers. */
 612                                 if (rtex->cmask_size && rtex->fmask_size) {
 613                                         dst->views.compressed_colortex_mask |= 1 << i;
 614                                 } else {
 615                                         dst->views.compressed_colortex_mask &= ~(1 << i);
 616                                 }
 617                         }
 618                         /* Changing from array to non-arrays textures and vice versa requires
 619                          * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
 620                         if (rctx->chip_class <= R700 &&
 621                             (dst->states.enabled_mask & (1 << i)) &&
 622                             (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
 623                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
 624                                 dirty_sampler_states_mask |= 1 << i;
 625                         }
 626
 627                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
 628                         new_mask |= 1 << i;
 629                         r600_context_add_resource_size(pipe, views[i]->texture);
 630                 } else {
 631                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 632                         disable_mask |= 1 << i;
 633                 }
 634         }
 635
 636         dst->views.enabled_mask &= ~disable_mask;
 637         dst->views.dirty_mask &= dst->views.enabled_mask;
 638         dst->views.enabled_mask |= new_mask;
 639         dst->views.dirty_mask |= new_mask;
 640         dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
 641         dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
 642         dst->views.dirty_txq_constants = TRUE;
 643         dst->views.dirty_buffer_constants = TRUE;
 644         r600_sampler_views_dirty(rctx, &dst->views);
 645
 646         if (dirty_sampler_states_mask) {
 647                 dst->states.dirty_mask |= dirty_sampler_states_mask;
 648                 r600_sampler_states_dirty(rctx, &dst->states);
 649         }
 650 }
 651
 652 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
 653                                       struct pipe_sampler_view **views)
 654 {
 655         r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
 656 }
 657
 658 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
 659                                       struct pipe_sampler_view **views)
 660 {
 661         r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
 662 }
 663
 664 static void r600_set_viewport_states(struct pipe_context *ctx,
 665                                      unsigned start_slot,
 666                                      unsigned num_viewports,
 667                                      const struct pipe_viewport_state *state)
 668 {
 669         struct r600_context *rctx = (struct r600_context *)ctx;
 670
 671         rctx->viewport.state = *state;
 672         rctx->viewport.atom.dirty = true;
 673 }
 674
 675 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
 676 {
 677         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 678         struct pipe_viewport_state *state = &rctx->viewport.state;
 679
 680         r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
 681         r600_write_value(cs, fui(state->scale[0]));     /* R_02843C_PA_CL_VPORT_XSCALE_0  */
 682         r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
 683         r600_write_value(cs, fui(state->scale[1]));     /* R_028444_PA_CL_VPORT_YSCALE_0  */
 684         r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
 685         r600_write_value(cs, fui(state->scale[2]));     /* R_02844C_PA_CL_VPORT_ZSCALE_0  */
 686         r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
 687 }
 688
 689 /* Compute the key for the hw shader variant */
 690 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
 691                 struct r600_pipe_shader_selector * sel)
 692 {
 693         struct r600_context *rctx = (struct r600_context *)ctx;
 694         struct r600_shader_key key;
 695         memset(&key, 0, sizeof(key));
 696
 697         if (sel->type == PIPE_SHADER_FRAGMENT) {
 698                 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
 699                 key.alpha_to_one = rctx->alpha_to_one &&
 700                                    rctx->rasterizer && rctx->rasterizer->multisample_enable &&
 701                                    !rctx->framebuffer.cb0_is_integer;
 702                 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
 703                 /* Dual-source blending only makes sense with nr_cbufs == 1. */
 704                 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
 705                         key.nr_cbufs = 2;
 706         }
 707         return key;
 708 }
 709
 710 /* Select the hw shader variant depending on the current state.
 711  * (*dirty) is set to 1 if current variant was changed */
 712 static int r600_shader_select(struct pipe_context *ctx,
 713         struct r600_pipe_shader_selector* sel,
 714         bool *dirty)
 715 {
 716         struct r600_shader_key key;
 717         struct r600_context *rctx = (struct r600_context *)ctx;
 718         struct r600_pipe_shader * shader = NULL;
 719         int r;
 720
 721         memset(&key, 0, sizeof(key));
 722         key = r600_shader_selector_key(ctx, sel);
 723
 724         /* Check if we don't need to change anything.
 725          * This path is also used for most shaders that don't need multiple
 726          * variants, it will cost just a computation of the key and this
 727          * test. */
 728         if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
 729                 return 0;
 730         }
 731
 732         /* lookup if we have other variants in the list */
 733         if (sel->num_shaders > 1) {
 734                 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
 735
 736                 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
 737                         p = c;
 738                         c = c->next_variant;
 739                 }
 740
 741                 if (c) {
 742                         p->next_variant = c->next_variant;
 743                         shader = c;
 744                 }
 745         }
 746
 747         if (unlikely(!shader)) {
 748                 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
 749                 shader->selector = sel;
 750
 751                 r = r600_pipe_shader_create(ctx, shader, key);
 752                 if (unlikely(r)) {
 753                         R600_ERR("Failed to build shader variant (type=%u) %d\n",
 754                                  sel->type, r);
 755                         sel->current = NULL;
 756                         FREE(shader);
 757                         return r;
 758                 }
 759
 760                 /* We don't know the value of nr_ps_max_color_exports until we built
 761                  * at least one variant, so we may need to recompute the key after
 762                  * building first variant. */
 763                 if (sel->type == PIPE_SHADER_FRAGMENT &&
 764                                 sel->num_shaders == 0) {
 765                         sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
 766                         key = r600_shader_selector_key(ctx, sel);
 767                 }
 768
 769                 memcpy(&shader->key, &key, sizeof(key));
 770                 sel->num_shaders++;
 771         }
 772
 773         if (dirty)
 774                 *dirty = true;
 775
 776         shader->next_variant = sel->current;
 777         sel->current = shader;
 778
 779         if (rctx->ps_shader &&
 780             rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 781                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 782                 rctx->cb_misc_state.atom.dirty = true;
 783         }
 784         return 0;
 785 }
 786
 787 static void *r600_create_shader_state(struct pipe_context *ctx,
 788                                const struct pipe_shader_state *state,
 789                                unsigned pipe_shader_type)
 790 {
 791         struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
 792         int r;
 793
 794         sel->type = pipe_shader_type;
 795         sel->tokens = tgsi_dup_tokens(state->tokens);
 796         sel->so = state->stream_output;
 797
 798         r = r600_shader_select(ctx, sel, NULL);
 799         if (r)
 800             return NULL;
 801
 802         return sel;
 803 }
 804
 805 static void *r600_create_ps_state(struct pipe_context *ctx,
 806                                          const struct pipe_shader_state *state)
 807 {
 808         return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
 809 }
 810
 811 static void *r600_create_vs_state(struct pipe_context *ctx,
 812                                          const struct pipe_shader_state *state)
 813 {
 814         return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
 815 }
 816
 817 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
 818 {
 819         struct r600_context *rctx = (struct r600_context *)ctx;
 820
 821         if (!state)
 822                 state = rctx->dummy_pixel_shader;
 823
 824         rctx->pixel_shader.shader = rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
 825         rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
 826         rctx->pixel_shader.atom.dirty = true;
 827
 828         r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
 829
 830         if (rctx->chip_class <= R700) {
 831                 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
 832
 833                 if (rctx->cb_misc_state.multiwrite != multiwrite) {
 834                         rctx->cb_misc_state.multiwrite = multiwrite;
 835                         rctx->cb_misc_state.atom.dirty = true;
 836                 }
 837         }
 838
 839         if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 840                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 841                 rctx->cb_misc_state.atom.dirty = true;
 842         }
 843
 844         if (rctx->chip_class >= EVERGREEN) {
 845                 evergreen_update_db_shader_control(rctx);
 846         } else {
 847                 r600_update_db_shader_control(rctx);
 848         }
 849 }
 850
 851 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
 852 {
 853         struct r600_context *rctx = (struct r600_context *)ctx;
 854
 855         if (!state)
 856                 return;
 857
 858         rctx->vertex_shader.shader = rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
 859         rctx->vertex_shader.atom.dirty = true;
 860
 861         r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
 862
 863         /* Update clip misc state. */
 864         if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
 865             rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
 866                 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
 867                 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
 868                 rctx->clip_misc_state.atom.dirty = true;
 869         }
 870 }
 871
 872 static void r600_delete_shader_selector(struct pipe_context *ctx,
 873                 struct r600_pipe_shader_selector *sel)
 874 {
 875         struct r600_pipe_shader *p = sel->current, *c;
 876         while (p) {
 877                 c = p->next_variant;
 878                 r600_pipe_shader_destroy(ctx, p);
 879                 free(p);
 880                 p = c;
 881         }
 882
 883         free(sel->tokens);
 884         free(sel);
 885 }
 886
 887
 888 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
 889 {
 890         struct r600_context *rctx = (struct r600_context *)ctx;
 891         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 892
 893         if (rctx->ps_shader == sel) {
 894                 rctx->ps_shader = NULL;
 895         }
 896
 897         r600_delete_shader_selector(ctx, sel);
 898 }
 899
 900 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
 901 {
 902         struct r600_context *rctx = (struct r600_context *)ctx;
 903         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 904
 905         if (rctx->vs_shader == sel) {
 906                 rctx->vs_shader = NULL;
 907         }
 908
 909         r600_delete_shader_selector(ctx, sel);
 910 }
 911
 912 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 913 {
 914         if (state->dirty_mask) {
 915                 rctx->flags |= R600_CONTEXT_INV_CONST_CACHE;
 916                 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 917                                                                    : util_bitcount(state->dirty_mask)*19;
 918                 state->atom.dirty = true;
 919         }
 920 }
 921
 922 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 923                                      struct pipe_constant_buffer *input)
 924 {
 925         struct r600_context *rctx = (struct r600_context *)ctx;
 926         struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
 927         struct pipe_constant_buffer *cb;
 928         const uint8_t *ptr;
 929
 930         /* Note that the state tracker can unbind constant buffers by
 931          * passing NULL here.
 932          */
 933         if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
 934                 state->enabled_mask &= ~(1 << index);
 935                 state->dirty_mask &= ~(1 << index);
 936                 pipe_resource_reference(&state->cb[index].buffer, NULL);
 937                 return;
 938         }
 939
 940         cb = &state->cb[index];
 941         cb->buffer_size = input->buffer_size;
 942
 943         ptr = input->user_buffer;
 944
 945         if (ptr) {
 946                 /* Upload the user buffer. */
 947                 if (R600_BIG_ENDIAN) {
 948                         uint32_t *tmpPtr;
 949                         unsigned i, size = input->buffer_size;
 950
 951                         if (!(tmpPtr = malloc(size))) {
 952                                 R600_ERR("Failed to allocate BE swap buffer.\n");
 953                                 return;
 954                         }
 955
 956                         for (i = 0; i < size / 4; ++i) {
 957                                 tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
 958                         }
 959
 960                         u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
 961                         free(tmpPtr);
 962                 } else {
 963                         u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 964                 }
 965                 /* account it in gtt */
 966                 rctx->gtt += input->buffer_size;
 967         } else {
 968                 /* Setup the hw buffer. */
 969                 cb->buffer_offset = input->buffer_offset;
 970                 pipe_resource_reference(&cb->buffer, input->buffer);
 971                 r600_context_add_resource_size(ctx, input->buffer);
 972         }
 973
 974         state->enabled_mask |= 1 << index;
 975         state->dirty_mask |= 1 << index;
 976         r600_constant_buffers_dirty(rctx, state);
 977 }
 978
 979 static struct pipe_stream_output_target *
 980 r600_create_so_target(struct pipe_context *ctx,
 981                       struct pipe_resource *buffer,
 982                       unsigned buffer_offset,
 983                       unsigned buffer_size)
 984 {
 985         struct r600_context *rctx = (struct r600_context *)ctx;
 986         struct r600_so_target *t;
 987         struct r600_resource *rbuffer = (struct r600_resource*)buffer;
 988
 989         t = CALLOC_STRUCT(r600_so_target);
 990         if (!t) {
 991                 return NULL;
 992         }
 993
 994         u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
 995                              &t->buf_filled_size_offset,
 996                              (struct pipe_resource**)&t->buf_filled_size);
 997         if (!t->buf_filled_size) {
 998                 FREE(t);
 999                 return NULL;
1000         }
1001
1002         t->b.reference.count = 1;
1003         t->b.context = ctx;
1004         pipe_resource_reference(&t->b.buffer, buffer);
1005         t->b.buffer_offset = buffer_offset;
1006         t->b.buffer_size = buffer_size;
1007
1008         util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
1009                        buffer_offset + buffer_size);
1010         return &t->b;
1011 }
1012
1013 static void r600_so_target_destroy(struct pipe_context *ctx,
1014                                    struct pipe_stream_output_target *target)
1015 {
1016         struct r600_so_target *t = (struct r600_so_target*)target;
1017         pipe_resource_reference(&t->b.buffer, NULL);
1018         pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
1019         FREE(t);
1020 }
1021
1022 void r600_streamout_buffers_dirty(struct r600_context *rctx)
1023 {
1024         rctx->streamout.num_dw_for_end =
1025                 12 + /* flush_vgt_streamout */
1026                 util_bitcount(rctx->streamout.enabled_mask) * 8 + /* STRMOUT_BUFFER_UPDATE */
1027                 3 /* set_streamout_enable(0) */;
1028
1029         rctx->streamout.begin_atom.num_dw =
1030                 12 + /* flush_vgt_streamout */
1031                 6 + /* set_streamout_enable */
1032                 util_bitcount(rctx->streamout.enabled_mask) * 7 + /* SET_CONTEXT_REG */
1033                 (rctx->family >= CHIP_RS780 &&
1034                  rctx->family <= CHIP_RV740 ? util_bitcount(rctx->streamout.enabled_mask) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
1035                 util_bitcount(rctx->streamout.enabled_mask & rctx->streamout.append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
1036                 util_bitcount(rctx->streamout.enabled_mask & ~rctx->streamout.append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
1037                 (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
1038                 rctx->streamout.num_dw_for_end;
1039
1040         rctx->streamout.begin_atom.dirty = true;
1041 }
1042
1043 static void r600_set_streamout_targets(struct pipe_context *ctx,
1044                                        unsigned num_targets,
1045                                        struct pipe_stream_output_target **targets,
1046                                        unsigned append_bitmask)
1047 {
1048         struct r600_context *rctx = (struct r600_context *)ctx;
1049         unsigned i;
1050
1051         /* Stop streamout. */
1052         if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
1053                 r600_emit_streamout_end(rctx);
1054         }
1055
1056         /* Set the new targets. */
1057         for (i = 0; i < num_targets; i++) {
1058                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
1059                 r600_context_add_resource_size(ctx, targets[i]->buffer);
1060         }
1061         for (; i < rctx->streamout.num_targets; i++) {
1062                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
1063         }
1064
1065         rctx->streamout.enabled_mask = (num_targets >= 1 && targets[0] ? 1 : 0) |
1066                                        (num_targets >= 2 && targets[1] ? 2 : 0) |
1067                                        (num_targets >= 3 && targets[2] ? 4 : 0) |
1068                                        (num_targets >= 4 && targets[3] ? 8 : 0);
1069
1070         rctx->streamout.num_targets = num_targets;
1071         rctx->streamout.append_bitmask = append_bitmask;
1072
1073         if (num_targets) {
1074                 r600_streamout_buffers_dirty(rctx);
1075         }
1076 }
1077
1078 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1079 {
1080         struct r600_context *rctx = (struct r600_context*)pipe;
1081
1082         if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1083                 return;
1084
1085         rctx->sample_mask.sample_mask = sample_mask;
1086         rctx->sample_mask.atom.dirty = true;
1087 }
1088
1089 /*
1090  * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1091  * doesn't require full swizzles it does need masking and setting alpha
1092  * to one, so we setup a set of 5 constants with the masks + alpha value
1093  * then in the shader, we AND the 4 components with 0xffffffff or 0,
1094  * then OR the alpha with the value given here.
1095  * We use a 6th constant to store the txq buffer size in
1096  */
1097 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1098 {
1099         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1100         int bits;
1101         uint32_t array_size;
1102         struct pipe_constant_buffer cb;
1103         int i, j;
1104
1105         if (!samplers->views.dirty_buffer_constants)
1106                 return;
1107
1108         samplers->views.dirty_buffer_constants = FALSE;
1109
1110         bits = util_last_bit(samplers->views.enabled_mask);
1111         array_size = bits * 8 * sizeof(uint32_t) * 4;
1112         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1113         memset(samplers->buffer_constants, 0, array_size);
1114         for (i = 0; i < bits; i++) {
1115                 if (samplers->views.enabled_mask & (1 << i)) {
1116                         int offset = i * 8;
1117                         const struct util_format_description *desc;
1118                         desc = util_format_description(samplers->views.views[i]->base.format);
1119
1120                         for (j = 0; j < 4; j++)
1121                                 if (j < desc->nr_channels)
1122                                         samplers->buffer_constants[offset+j] = 0xffffffff;
1123                                 else
1124                                         samplers->buffer_constants[offset+j] = 0x0;
1125                         if (desc->nr_channels < 4) {
1126                                 if (desc->channel[0].pure_integer)
1127                                         samplers->buffer_constants[offset+4] = 1;
1128                                 else
1129                                         samplers->buffer_constants[offset+4] = 0x3f800000;
1130                         } else
1131                                 samplers->buffer_constants[offset + 4] = 0;
1132
1133                         samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1134                 }
1135         }
1136
1137         cb.buffer = NULL;
1138         cb.user_buffer = samplers->buffer_constants;
1139         cb.buffer_offset = 0;
1140         cb.buffer_size = array_size;
1141         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1142         pipe_resource_reference(&cb.buffer, NULL);
1143 }
1144
1145 /* On evergreen we only need to store the buffer size for TXQ */
1146 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1147 {
1148         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1149         int bits;
1150         uint32_t array_size;
1151         struct pipe_constant_buffer cb;
1152         int i;
1153
1154         if (!samplers->views.dirty_buffer_constants)
1155                 return;
1156
1157         samplers->views.dirty_buffer_constants = FALSE;
1158
1159         bits = util_last_bit(samplers->views.enabled_mask);
1160         array_size = bits * sizeof(uint32_t) * 4;
1161         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1162         memset(samplers->buffer_constants, 0, array_size);
1163         for (i = 0; i < bits; i++)
1164                 if (samplers->views.enabled_mask & (1 << i))
1165                    samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1166
1167         cb.buffer = NULL;
1168         cb.user_buffer = samplers->buffer_constants;
1169         cb.buffer_offset = 0;
1170         cb.buffer_size = array_size;
1171         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1172         pipe_resource_reference(&cb.buffer, NULL);
1173 }
1174
1175 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1176 {
1177         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1178         int bits;
1179         uint32_t array_size;
1180         struct pipe_constant_buffer cb;
1181         int i;
1182
1183         if (!samplers->views.dirty_txq_constants)
1184                 return;
1185
1186         samplers->views.dirty_txq_constants = FALSE;
1187
1188         bits = util_last_bit(samplers->views.enabled_mask);
1189         array_size = bits * sizeof(uint32_t) * 4;
1190         samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1191         memset(samplers->txq_constants, 0, array_size);
1192         for (i = 0; i < bits; i++)
1193                 if (samplers->views.enabled_mask & (1 << i))
1194                         samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1195
1196         cb.buffer = NULL;
1197         cb.user_buffer = samplers->txq_constants;
1198         cb.buffer_offset = 0;
1199         cb.buffer_size = array_size;
1200         rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1201         pipe_resource_reference(&cb.buffer, NULL);
1202 }
1203
1204 static bool r600_update_derived_state(struct r600_context *rctx)
1205 {
1206         struct pipe_context * ctx = (struct pipe_context*)rctx;
1207         bool ps_dirty = false;
1208         bool blend_disable;
1209
1210         if (!rctx->blitter->running) {
1211                 unsigned i;
1212
1213                 /* Decompress textures if needed. */
1214                 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1215                         struct r600_samplerview_state *views = &rctx->samplers[i].views;
1216                         if (views->compressed_depthtex_mask) {
1217                                 r600_decompress_depth_textures(rctx, views);
1218                         }
1219                         if (views->compressed_colortex_mask) {
1220                                 r600_decompress_color_textures(rctx, views);
1221                         }
1222                 }
1223         }
1224
1225         r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1226
1227         if (rctx->ps_shader && rctx->rasterizer &&
1228             ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1229              (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1230
1231                 if (rctx->chip_class >= EVERGREEN)
1232                         evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1233                 else
1234                         r600_update_ps_state(ctx, rctx->ps_shader->current);
1235
1236                 ps_dirty = true;
1237         }
1238
1239         if (ps_dirty) {
1240                 rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
1241                 rctx->pixel_shader.atom.dirty = true;
1242         }
1243
1244         /* on R600 we stuff masks + txq info into one constant buffer */
1245         /* on evergreen we only need a txq info one */
1246         if (rctx->chip_class < EVERGREEN) {
1247                 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1248                         r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1249                 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1250                         r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1251         } else {
1252                 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1253                         eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1254                 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1255                         eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1256         }
1257
1258
1259         if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1260                 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1261         if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1262                 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1263
1264         if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1265                 if (!r600_adjust_gprs(rctx)) {
1266                         /* discard rendering */
1267                         return false;
1268                 }
1269         }
1270
1271         blend_disable = (rctx->dual_src_blend &&
1272                         rctx->ps_shader->current->nr_ps_color_outputs < 2);
1273
1274         if (blend_disable != rctx->force_blend_disable) {
1275                 rctx->force_blend_disable = blend_disable;
1276                 r600_bind_blend_state_internal(rctx,
1277                                                rctx->blend_state.cso,
1278                                                blend_disable);
1279         }
1280         return true;
1281 }
1282
1283 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1284 {
1285         static const int prim_conv[] = {
1286                 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1287                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1288                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1289                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1290                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1291                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1292                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1293                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1294                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1295                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1296                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1297                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1298                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1299                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1300                 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1301         };
1302         assert(mode < Elements(prim_conv));
1303
1304         return prim_conv[mode];
1305 }
1306
1307 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1308 {
1309         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1310         struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1311
1312         r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1313                                state->pa_cl_clip_cntl |
1314                                (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1315         r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1316                                state->pa_cl_vs_out_cntl |
1317                                (state->clip_plane_enable & state->clip_dist_write));
1318 }
1319
1320 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1321 {
1322         struct r600_context *rctx = (struct r600_context *)ctx;
1323         struct pipe_draw_info info = *dinfo;
1324         struct pipe_index_buffer ib = {};
1325         unsigned i;
1326         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1327
1328         if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1329                 assert(0);
1330                 return;
1331         }
1332
1333         if (!rctx->vs_shader) {
1334                 assert(0);
1335                 return;
1336         }
1337
1338         /* make sure that the gfx ring is only one active */
1339         if (rctx->rings.dma.cs) {
1340                 rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1341         }
1342
1343         if (!r600_update_derived_state(rctx)) {
1344                 /* useless to render because current rendering command
1345                  * can't be achieved
1346                  */
1347                 return;
1348         }
1349
1350         if (info.indexed) {
1351                 /* Initialize the index buffer struct. */
1352                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1353                 ib.user_buffer = rctx->index_buffer.user_buffer;
1354                 ib.index_size = rctx->index_buffer.index_size;
1355                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1356
1357                 /* Translate 8-bit indices to 16-bit. */
1358                 if (ib.index_size == 1) {
1359                         struct pipe_resource *out_buffer = NULL;
1360                         unsigned out_offset;
1361                         void *ptr;
1362
1363                         u_upload_alloc(rctx->uploader, 0, info.count * 2,
1364                                        &out_offset, &out_buffer, &ptr);
1365
1366                         util_shorten_ubyte_elts_to_userptr(
1367                                                 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1368
1369                         pipe_resource_reference(&ib.buffer, NULL);
1370                         ib.user_buffer = NULL;
1371                         ib.buffer = out_buffer;
1372                         ib.offset = out_offset;
1373                         ib.index_size = 2;
1374                 }
1375
1376                 /* Upload the index buffer.
1377                  * The upload is skipped for small index counts on little-endian machines
1378                  * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1379                  * Note: Instanced rendering in combination with immediate indices hangs. */
1380                 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1381                                        info.count*ib.index_size > 20)) {
1382                         u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1383                                       ib.user_buffer, &ib.offset, &ib.buffer);
1384                         ib.user_buffer = NULL;
1385                 }
1386         } else {
1387                 info.index_bias = info.start;
1388         }
1389
1390         /* Set the index offset and primitive restart. */
1391         if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1392             rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1393             rctx->vgt_state.vgt_indx_offset != info.index_bias) {
1394                 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1395                 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1396                 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1397                 rctx->vgt_state.atom.dirty = true;
1398         }
1399
1400         /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1401         if (rctx->chip_class == R600) {
1402                 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1403                 rctx->cb_misc_state.atom.dirty = true;
1404         }
1405
1406         /* Emit states. */
1407         r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1408         r600_flush_emit(rctx);
1409
1410         for (i = 0; i < R600_NUM_ATOMS; i++) {
1411                 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1412                         continue;
1413                 }
1414                 r600_emit_atom(rctx, rctx->atoms[i]);
1415         }
1416
1417         /* Update start instance. */
1418         if (rctx->last_start_instance != info.start_instance) {
1419                 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1420                 rctx->last_start_instance = info.start_instance;
1421         }
1422
1423         /* Update the primitive type. */
1424         if (rctx->last_primitive_type != info.mode) {
1425                 unsigned ls_mask = 0;
1426
1427                 if (info.mode == PIPE_PRIM_LINES)
1428                         ls_mask = 1;
1429                 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1430                          info.mode == PIPE_PRIM_LINE_LOOP)
1431                         ls_mask = 2;
1432
1433                 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1434                                        S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1435                                        (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1436                 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1437                                        r600_conv_prim_to_gs_out(info.mode));
1438                 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1439                                       r600_conv_pipe_prim(info.mode));
1440
1441                 rctx->last_primitive_type = info.mode;
1442         }
1443
1444         /* Draw packets. */
1445         cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1446         cs->buf[cs->cdw++] = info.instance_count;
1447         if (info.indexed) {
1448                 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1449                 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1450                                         (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1451                                         (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1452
1453                 if (ib.user_buffer) {
1454                         unsigned size_bytes = info.count*ib.index_size;
1455                         unsigned size_dw = align(size_bytes, 4) / 4;
1456                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1457                         cs->buf[cs->cdw++] = info.count;
1458                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1459                         memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1460                         cs->cdw += size_dw;
1461                 } else {
1462                         uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1463                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1464                         cs->buf[cs->cdw++] = va;
1465                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1466                         cs->buf[cs->cdw++] = info.count;
1467                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1468                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1469                         cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1470                 }
1471         } else {
1472                 if (info.count_from_stream_output) {
1473                         struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1474                         uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1475
1476                         r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1477
1478                         cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1479                         cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1480                         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;     /* src address lo */
1481                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1482                         cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1483                         cs->buf[cs->cdw++] = 0; /* unused */
1484
1485                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1486                         cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1487                 }
1488
1489                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1490                 cs->buf[cs->cdw++] = info.count;
1491                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1492                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1493         }
1494
1495         if (rctx->screen->trace_bo) {
1496                 r600_trace_emit(rctx);
1497         }
1498
1499         /* Set the depth buffer as dirty. */
1500         if (rctx->framebuffer.state.zsbuf) {
1501                 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1502                 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1503
1504                 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1505         }
1506         if (rctx->framebuffer.compressed_cb_mask) {
1507                 struct pipe_surface *surf;
1508                 struct r600_texture *rtex;
1509                 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1510
1511                 do {
1512                         unsigned i = u_bit_scan(&mask);
1513                         surf = rctx->framebuffer.state.cbufs[i];
1514                         rtex = (struct r600_texture*)surf->texture;
1515
1516                         rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1517
1518                 } while (mask);
1519         }
1520
1521         pipe_resource_reference(&ib.buffer, NULL);
1522         rctx->num_draw_calls++;
1523 }
1524
1525 void r600_draw_rectangle(struct blitter_context *blitter,
1526                          int x1, int y1, int x2, int y2, float depth,
1527                          enum blitter_attrib_type type, const union pipe_color_union *attrib)
1528 {
1529         struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1530         struct pipe_viewport_state viewport;
1531         struct pipe_resource *buf = NULL;
1532         unsigned offset = 0;
1533         float *vb;
1534
1535         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1536                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1537                 return;
1538         }
1539
1540         /* Some operations (like color resolve on r6xx) don't work
1541          * with the conventional primitive types.
1542          * One that works is PT_RECTLIST, which we use here. */
1543
1544         /* setup viewport */
1545         viewport.scale[0] = 1.0f;
1546         viewport.scale[1] = 1.0f;
1547         viewport.scale[2] = 1.0f;
1548         viewport.scale[3] = 1.0f;
1549         viewport.translate[0] = 0.0f;
1550         viewport.translate[1] = 0.0f;
1551         viewport.translate[2] = 0.0f;
1552         viewport.translate[3] = 0.0f;
1553         rctx->context.set_viewport_states(&rctx->context, 0, 1, &viewport);
1554
1555         /* Upload vertices. The hw rectangle has only 3 vertices,
1556          * I guess the 4th one is derived from the first 3.
1557          * The vertex specification should match u_blitter's vertex element state. */
1558         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1559         vb[0] = x1;
1560         vb[1] = y1;
1561         vb[2] = depth;
1562         vb[3] = 1;
1563
1564         vb[8] = x1;
1565         vb[9] = y2;
1566         vb[10] = depth;
1567         vb[11] = 1;
1568
1569         vb[16] = x2;
1570         vb[17] = y1;
1571         vb[18] = depth;
1572         vb[19] = 1;
1573
1574         if (attrib) {
1575                 memcpy(vb+4, attrib->f, sizeof(float)*4);
1576                 memcpy(vb+12, attrib->f, sizeof(float)*4);
1577                 memcpy(vb+20, attrib->f, sizeof(float)*4);
1578         }
1579
1580         /* draw */
1581         util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
1582                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
1583         pipe_resource_reference(&buf, NULL);
1584 }
1585
1586 uint32_t r600_translate_stencil_op(int s_op)
1587 {
1588         switch (s_op) {
1589         case PIPE_STENCIL_OP_KEEP:
1590                 return V_028800_STENCIL_KEEP;
1591         case PIPE_STENCIL_OP_ZERO:
1592                 return V_028800_STENCIL_ZERO;
1593         case PIPE_STENCIL_OP_REPLACE:
1594                 return V_028800_STENCIL_REPLACE;
1595         case PIPE_STENCIL_OP_INCR:
1596                 return V_028800_STENCIL_INCR;
1597         case PIPE_STENCIL_OP_DECR:
1598                 return V_028800_STENCIL_DECR;
1599         case PIPE_STENCIL_OP_INCR_WRAP:
1600                 return V_028800_STENCIL_INCR_WRAP;
1601         case PIPE_STENCIL_OP_DECR_WRAP:
1602                 return V_028800_STENCIL_DECR_WRAP;
1603         case PIPE_STENCIL_OP_INVERT:
1604                 return V_028800_STENCIL_INVERT;
1605         default:
1606                 R600_ERR("Unknown stencil op %d", s_op);
1607                 assert(0);
1608                 break;
1609         }
1610         return 0;
1611 }
1612
1613 uint32_t r600_translate_fill(uint32_t func)
1614 {
1615         switch(func) {
1616         case PIPE_POLYGON_MODE_FILL:
1617                 return 2;
1618         case PIPE_POLYGON_MODE_LINE:
1619                 return 1;
1620         case PIPE_POLYGON_MODE_POINT:
1621                 return 0;
1622         default:
1623                 assert(0);
1624                 return 0;
1625         }
1626 }
1627
1628 unsigned r600_tex_wrap(unsigned wrap)
1629 {
1630         switch (wrap) {
1631         default:
1632         case PIPE_TEX_WRAP_REPEAT:
1633                 return V_03C000_SQ_TEX_WRAP;
1634         case PIPE_TEX_WRAP_CLAMP:
1635                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1636         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1637                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1638         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1639                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1640         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1641                 return V_03C000_SQ_TEX_MIRROR;
1642         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1643                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1644         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1645                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1646         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1647                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1648         }
1649 }
1650
1651 unsigned r600_tex_filter(unsigned filter)
1652 {
1653         switch (filter) {
1654         default:
1655         case PIPE_TEX_FILTER_NEAREST:
1656                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1657         case PIPE_TEX_FILTER_LINEAR:
1658                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1659         }
1660 }
1661
1662 unsigned r600_tex_mipfilter(unsigned filter)
1663 {
1664         switch (filter) {
1665         case PIPE_TEX_MIPFILTER_NEAREST:
1666                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1667         case PIPE_TEX_MIPFILTER_LINEAR:
1668                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1669         default:
1670         case PIPE_TEX_MIPFILTER_NONE:
1671                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1672         }
1673 }
1674
1675 unsigned r600_tex_compare(unsigned compare)
1676 {
1677         switch (compare) {
1678         default:
1679         case PIPE_FUNC_NEVER:
1680                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1681         case PIPE_FUNC_LESS:
1682                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1683         case PIPE_FUNC_EQUAL:
1684                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1685         case PIPE_FUNC_LEQUAL:
1686                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1687         case PIPE_FUNC_GREATER:
1688                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1689         case PIPE_FUNC_NOTEQUAL:
1690                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1691         case PIPE_FUNC_GEQUAL:
1692                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1693         case PIPE_FUNC_ALWAYS:
1694                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1695         }
1696 }
1697
1698 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1699 {
1700         return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1701                wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1702                (linear_filter &&
1703                 (wrap == PIPE_TEX_WRAP_CLAMP ||
1704                  wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1705 }
1706
1707 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1708 {
1709         bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1710                              state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1711
1712         return (state->border_color.ui[0] || state->border_color.ui[1] ||
1713                 state->border_color.ui[2] || state->border_color.ui[3]) &&
1714                (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1715                 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1716                 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1717 }
1718
1719 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1720 {
1721         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1722         struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader->current;
1723
1724         r600_emit_command_buffer(cs, &shader->command_buffer);
1725
1726         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1727         r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, shader->bo, RADEON_USAGE_READ));
1728 }
1729
1730 /* keep this at the end of this file, please */
1731 void r600_init_common_state_functions(struct r600_context *rctx)
1732 {
1733         rctx->context.create_fs_state = r600_create_ps_state;
1734         rctx->context.create_vs_state = r600_create_vs_state;
1735         rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1736         rctx->context.bind_blend_state = r600_bind_blend_state;
1737         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1738         rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1739         rctx->context.bind_fs_state = r600_bind_ps_state;
1740         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1741         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1742         rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1743         rctx->context.bind_vs_state = r600_bind_vs_state;
1744         rctx->context.delete_blend_state = r600_delete_blend_state;
1745         rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1746         rctx->context.delete_fs_state = r600_delete_ps_state;
1747         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1748         rctx->context.delete_sampler_state = r600_delete_sampler_state;
1749         rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1750         rctx->context.delete_vs_state = r600_delete_vs_state;
1751         rctx->context.set_blend_color = r600_set_blend_color;
1752         rctx->context.set_clip_state = r600_set_clip_state;
1753         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1754         rctx->context.set_sample_mask = r600_set_sample_mask;
1755         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1756         rctx->context.set_viewport_states = r600_set_viewport_states;
1757         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1758         rctx->context.set_index_buffer = r600_set_index_buffer;
1759         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1760         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1761         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1762         rctx->context.texture_barrier = r600_texture_barrier;
1763         rctx->context.create_stream_output_target = r600_create_so_target;
1764         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1765         rctx->context.set_stream_output_targets = r600_set_streamout_targets;
1766         rctx->context.draw_vbo = r600_draw_vbo;
1767 }
1768
1769 void r600_trace_emit(struct r600_context *rctx)
1770 {
1771         struct r600_screen *rscreen = rctx->screen;
1772         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1773         uint64_t va;
1774         uint32_t reloc;
1775
1776         va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo);
1777         reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
1778         r600_write_value(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
1779         r600_write_value(cs, va & 0xFFFFFFFFUL);
1780         r600_write_value(cs, (va >> 32UL) & 0xFFUL);
1781         r600_write_value(cs, cs->cdw);
1782         r600_write_value(cs, rscreen->cs_count);
1783         r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1784         r600_write_value(cs, reloc);
1785 }