2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
39 struct radeon_winsys_cs
*cs
= rctx
->cs
;
40 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
42 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
43 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
44 cs
->cdw
+= cb
->atom
.num_dw
;
47 void r600_init_command_buffer(struct r600_context
*rctx
, struct r600_command_buffer
*cb
, unsigned id
, unsigned num_dw
)
49 r600_init_atom(rctx
, &cb
->atom
, id
, r600_emit_command_buffer
, 0);
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 void r600_init_atom(struct r600_context
*rctx
,
60 struct r600_atom
*atom
,
62 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
65 assert(id
< R600_NUM_ATOMS
);
66 assert(rctx
->atoms
[id
] == NULL
);
67 rctx
->atoms
[id
] = atom
;
70 atom
->num_dw
= num_dw
;
74 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
76 struct radeon_winsys_cs
*cs
= rctx
->cs
;
77 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
78 unsigned alpha_ref
= a
->sx_alpha_ref
;
80 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
84 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
85 a
->sx_alpha_test_control
|
86 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
87 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
90 static void r600_texture_barrier(struct pipe_context
*ctx
)
92 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
94 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_TEX_FLUSH
;
97 if (rctx
->chip_class
== R600
) {
98 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
102 static unsigned r600_conv_pipe_prim(unsigned prim
)
104 static const unsigned prim_conv
[] = {
105 V_008958_DI_PT_POINTLIST
,
106 V_008958_DI_PT_LINELIST
,
107 V_008958_DI_PT_LINELOOP
,
108 V_008958_DI_PT_LINESTRIP
,
109 V_008958_DI_PT_TRILIST
,
110 V_008958_DI_PT_TRISTRIP
,
111 V_008958_DI_PT_TRIFAN
,
112 V_008958_DI_PT_QUADLIST
,
113 V_008958_DI_PT_QUADSTRIP
,
114 V_008958_DI_PT_POLYGON
,
115 V_008958_DI_PT_LINELIST_ADJ
,
116 V_008958_DI_PT_LINESTRIP_ADJ
,
117 V_008958_DI_PT_TRILIST_ADJ
,
118 V_008958_DI_PT_TRISTRIP_ADJ
,
119 V_008958_DI_PT_RECTLIST
121 return prim_conv
[prim
];
124 /* common state between evergreen and r600 */
126 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
127 struct r600_pipe_blend
*blend
)
129 struct r600_pipe_state
*rstate
;
130 bool update_cb
= false;
132 rstate
= &blend
->rstate
;
133 rctx
->states
[rstate
->id
] = rstate
;
134 r600_context_pipe_state_set(rctx
, rstate
);
136 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
137 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
140 if (rctx
->chip_class
<= R700
&&
141 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
142 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
145 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
146 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
150 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
154 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
156 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
157 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
163 rctx
->alpha_to_one
= blend
->alpha_to_one
;
164 rctx
->dual_src_blend
= blend
->dual_src_blend
;
166 if (!rctx
->blend_override
)
167 r600_bind_blend_state_internal(rctx
, blend
);
170 static void r600_set_blend_color(struct pipe_context
*ctx
,
171 const struct pipe_blend_color
*state
)
173 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
175 rctx
->blend_color
.state
= *state
;
176 r600_atom_dirty(rctx
, &rctx
->blend_color
.atom
);
179 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
181 struct radeon_winsys_cs
*cs
= rctx
->cs
;
182 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
184 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
185 r600_write_value(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
186 r600_write_value(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
187 r600_write_value(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
188 r600_write_value(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
191 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
193 struct radeon_winsys_cs
*cs
= rctx
->cs
;
194 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
196 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
197 r600_write_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, a
->vgt_multi_prim_ib_reset_indx
);
200 void r600_emit_vgt2_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
202 struct radeon_winsys_cs
*cs
= rctx
->cs
;
203 struct r600_vgt2_state
*a
= (struct r600_vgt2_state
*)atom
;
205 r600_write_context_reg(cs
, R_028408_VGT_INDX_OFFSET
, a
->vgt_indx_offset
);
208 static void r600_set_clip_state(struct pipe_context
*ctx
,
209 const struct pipe_clip_state
*state
)
211 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
212 struct pipe_constant_buffer cb
;
214 rctx
->clip_state
.state
= *state
;
215 r600_atom_dirty(rctx
, &rctx
->clip_state
.atom
);
218 cb
.user_buffer
= state
->ucp
;
219 cb
.buffer_offset
= 0;
220 cb
.buffer_size
= 4*4*8;
221 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, 1, &cb
);
222 pipe_resource_reference(&cb
.buffer
, NULL
);
225 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
226 const struct r600_stencil_ref
*state
)
228 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
230 rctx
->stencil_ref
.state
= *state
;
231 r600_atom_dirty(rctx
, &rctx
->stencil_ref
.atom
);
234 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
236 struct radeon_winsys_cs
*cs
= rctx
->cs
;
237 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
239 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
240 r600_write_value(cs
, /* R_028430_DB_STENCILREFMASK */
241 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
242 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
243 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
244 r600_write_value(cs
, /* R_028434_DB_STENCILREFMASK_BF */
245 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
246 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
247 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
250 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
251 const struct pipe_stencil_ref
*state
)
253 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
254 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
255 struct r600_stencil_ref ref
;
257 rctx
->stencil_ref
.pipe_state
= *state
;
262 ref
.ref_value
[0] = state
->ref_value
[0];
263 ref
.ref_value
[1] = state
->ref_value
[1];
264 ref
.valuemask
[0] = dsa
->valuemask
[0];
265 ref
.valuemask
[1] = dsa
->valuemask
[1];
266 ref
.writemask
[0] = dsa
->writemask
[0];
267 ref
.writemask
[1] = dsa
->writemask
[1];
269 r600_set_stencil_ref(ctx
, &ref
);
272 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
274 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
275 struct r600_pipe_dsa
*dsa
= state
;
276 struct r600_pipe_state
*rstate
;
277 struct r600_stencil_ref ref
;
281 rstate
= &dsa
->rstate
;
282 rctx
->states
[rstate
->id
] = rstate
;
283 r600_context_pipe_state_set(rctx
, rstate
);
285 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
286 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
287 ref
.valuemask
[0] = dsa
->valuemask
[0];
288 ref
.valuemask
[1] = dsa
->valuemask
[1];
289 ref
.writemask
[0] = dsa
->writemask
[0];
290 ref
.writemask
[1] = dsa
->writemask
[1];
292 r600_set_stencil_ref(ctx
, &ref
);
294 /* Update alphatest state. */
295 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
296 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
297 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
298 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
299 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
303 void r600_set_max_scissor(struct r600_context
*rctx
)
305 /* Set a scissor state such that it doesn't do anything. */
306 struct pipe_scissor_state scissor
;
312 r600_set_scissor_state(rctx
, &scissor
);
315 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
317 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
318 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
323 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
324 rctx
->two_side
= rs
->two_side
;
325 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
326 rctx
->multisample_enable
= rs
->multisample_enable
;
328 rctx
->rasterizer
= rs
;
330 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
331 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
333 if (rctx
->chip_class
>= EVERGREEN
) {
334 evergreen_polygon_offset_update(rctx
);
336 r600_polygon_offset_update(rctx
);
339 /* Update clip_misc_state. */
340 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
341 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
342 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
343 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
344 r600_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
347 /* Workaround for a missing scissor enable on r600. */
348 if (rctx
->chip_class
== R600
) {
349 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
350 rctx
->scissor_enable
= rs
->scissor_enable
;
352 if (rs
->scissor_enable
) {
353 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
355 r600_set_max_scissor(rctx
);
361 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
363 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
364 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
366 if (rctx
->rasterizer
== rs
) {
367 rctx
->rasterizer
= NULL
;
369 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
370 rctx
->states
[rs
->rstate
.id
] = NULL
;
375 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
376 struct pipe_sampler_view
*state
)
378 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
380 pipe_resource_reference(&state
->texture
, NULL
);
384 void r600_sampler_states_dirty(struct r600_context
*rctx
,
385 struct r600_sampler_states
*state
)
387 if (state
->dirty_mask
) {
388 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
389 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
392 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
393 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
394 r600_atom_dirty(rctx
, &state
->atom
);
398 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
401 unsigned count
, void **states
)
403 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
404 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
405 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
406 int seamless_cube_map
= -1;
408 /* This sets 1-bit for states with index >= count. */
409 uint32_t disable_mask
= ~((1ull << count
) - 1);
410 /* These are the new states set by this function. */
411 uint32_t new_mask
= 0;
413 assert(start
== 0); /* XXX fix below */
415 for (i
= 0; i
< count
; i
++) {
416 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
418 if (rstate
== dst
->states
.states
[i
]) {
423 if (rstate
->border_color_use
) {
424 dst
->states
.has_bordercolor_mask
|= 1 << i
;
426 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
428 seamless_cube_map
= rstate
->seamless_cube_map
;
432 disable_mask
|= 1 << i
;
436 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
437 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
439 dst
->states
.enabled_mask
&= ~disable_mask
;
440 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
441 dst
->states
.enabled_mask
|= new_mask
;
442 dst
->states
.dirty_mask
|= new_mask
;
443 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
445 r600_sampler_states_dirty(rctx
, &dst
->states
);
447 /* Seamless cubemap state. */
448 if (rctx
->chip_class
<= R700
&&
449 seamless_cube_map
!= -1 &&
450 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
451 /* change in TA_CNTL_AUX need a pipeline flush */
452 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
453 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
454 r600_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
458 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
460 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
463 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
465 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
468 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
473 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
475 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
476 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
478 if (rctx
->states
[rstate
->id
] == rstate
) {
479 rctx
->states
[rstate
->id
] = NULL
;
481 for (int i
= 0; i
< rstate
->nregs
; i
++) {
482 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
487 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
489 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
490 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
492 rctx
->vertex_elements
= v
;
494 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
495 r600_context_pipe_state_set(rctx
, &v
->rstate
);
499 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
501 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
502 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
504 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
505 rctx
->states
[v
->rstate
.id
] = NULL
;
507 if (rctx
->vertex_elements
== state
)
508 rctx
->vertex_elements
= NULL
;
510 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
514 static void r600_set_index_buffer(struct pipe_context
*ctx
,
515 const struct pipe_index_buffer
*ib
)
517 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
520 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
521 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
523 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
527 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
529 if (rctx
->vertex_buffer_state
.dirty_mask
) {
530 rctx
->flags
|= rctx
->has_vertex_cache
? R600_CONTEXT_VTX_FLUSH
: R600_CONTEXT_TEX_FLUSH
;
531 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
532 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
533 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
537 static void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
538 const struct pipe_vertex_buffer
*input
)
540 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
541 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
542 struct pipe_vertex_buffer
*vb
= state
->vb
;
544 /* This sets 1-bit for buffers with index >= count. */
545 uint32_t disable_mask
= ~((1ull << count
) - 1);
546 /* These are the new buffers set by this function. */
547 uint32_t new_buffer_mask
= 0;
549 /* Set buffers with index >= count to NULL. */
550 uint32_t remaining_buffers_mask
=
551 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
553 while (remaining_buffers_mask
) {
554 i
= u_bit_scan(&remaining_buffers_mask
);
555 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
558 /* Set vertex buffers. */
559 for (i
= 0; i
< count
; i
++) {
560 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
561 if (input
[i
].buffer
) {
562 vb
[i
].stride
= input
[i
].stride
;
563 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
564 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
565 new_buffer_mask
|= 1 << i
;
567 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
568 disable_mask
|= 1 << i
;
573 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
574 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
575 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
576 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
578 r600_vertex_buffers_dirty(rctx
);
581 void r600_sampler_views_dirty(struct r600_context
*rctx
,
582 struct r600_samplerview_state
*state
)
584 if (state
->dirty_mask
) {
585 rctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
586 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
587 util_bitcount(state
->dirty_mask
);
588 r600_atom_dirty(rctx
, &state
->atom
);
592 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
593 unsigned start
, unsigned count
,
594 struct pipe_sampler_view
**views
)
596 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
597 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
598 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
599 uint32_t dirty_sampler_states_mask
= 0;
601 /* This sets 1-bit for textures with index >= count. */
602 uint32_t disable_mask
= ~((1ull << count
) - 1);
603 /* These are the new textures set by this function. */
604 uint32_t new_mask
= 0;
606 /* Set textures with index >= count to NULL. */
607 uint32_t remaining_mask
;
609 assert(start
== 0); /* XXX fix below */
611 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
613 while (remaining_mask
) {
614 i
= u_bit_scan(&remaining_mask
);
615 assert(dst
->views
.views
[i
]);
617 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
620 for (i
= 0; i
< count
; i
++) {
621 if (rviews
[i
] == dst
->views
.views
[i
]) {
626 struct r600_texture
*rtex
=
627 (struct r600_texture
*)rviews
[i
]->base
.texture
;
629 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
630 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
632 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
635 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
636 if (rctx
->chip_class
!= CAYMAN
&& rtex
->cmask_size
&& rtex
->fmask_size
) {
637 dst
->views
.compressed_colortex_mask
|= 1 << i
;
639 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
642 /* Changing from array to non-arrays textures and vice versa requires
643 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
644 if (rctx
->chip_class
<= R700
&&
645 (dst
->states
.enabled_mask
& (1 << i
)) &&
646 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
647 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
648 dirty_sampler_states_mask
|= 1 << i
;
651 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
654 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
655 disable_mask
|= 1 << i
;
659 dst
->views
.enabled_mask
&= ~disable_mask
;
660 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
661 dst
->views
.enabled_mask
|= new_mask
;
662 dst
->views
.dirty_mask
|= new_mask
;
663 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
664 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
666 r600_sampler_views_dirty(rctx
, &dst
->views
);
668 if (dirty_sampler_states_mask
) {
669 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
670 r600_sampler_states_dirty(rctx
, &dst
->states
);
674 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
675 struct pipe_sampler_view
**views
)
677 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
680 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
681 struct pipe_sampler_view
**views
)
683 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
686 static void r600_set_viewport_state(struct pipe_context
*ctx
,
687 const struct pipe_viewport_state
*state
)
689 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
691 rctx
->viewport
.state
= *state
;
692 r600_atom_dirty(rctx
, &rctx
->viewport
.atom
);
695 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
697 struct radeon_winsys_cs
*cs
= rctx
->cs
;
698 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
700 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
701 r600_write_value(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
702 r600_write_value(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
703 r600_write_value(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
704 r600_write_value(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
705 r600_write_value(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
706 r600_write_value(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
709 static void *r600_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
710 const struct pipe_vertex_element
*elements
)
712 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
713 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
720 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
722 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
730 /* Compute the key for the hw shader variant */
731 static INLINE
unsigned r600_shader_selector_key(struct pipe_context
* ctx
,
732 struct r600_pipe_shader_selector
* sel
)
734 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
737 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
738 key
= rctx
->two_side
|
739 ((rctx
->alpha_to_one
&& rctx
->multisample_enable
&& !rctx
->cb0_is_integer
) << 1) |
740 (MIN2(sel
->nr_ps_max_color_exports
, rctx
->nr_cbufs
+ rctx
->dual_src_blend
) << 2);
747 /* Select the hw shader variant depending on the current state.
748 * (*dirty) is set to 1 if current variant was changed */
749 static int r600_shader_select(struct pipe_context
*ctx
,
750 struct r600_pipe_shader_selector
* sel
,
754 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
755 struct r600_pipe_shader
* shader
= NULL
;
758 key
= r600_shader_selector_key(ctx
, sel
);
760 /* Check if we don't need to change anything.
761 * This path is also used for most shaders that don't need multiple
762 * variants, it will cost just a computation of the key and this
764 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
768 /* lookup if we have other variants in the list */
769 if (sel
->num_shaders
> 1) {
770 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
772 while (c
&& c
->key
!= key
) {
778 p
->next_variant
= c
->next_variant
;
783 if (unlikely(!shader
)) {
784 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
785 shader
->selector
= sel
;
787 r
= r600_pipe_shader_create(ctx
, shader
);
789 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
795 /* We don't know the value of nr_ps_max_color_exports until we built
796 * at least one variant, so we may need to recompute the key after
797 * building first variant. */
798 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
799 sel
->num_shaders
== 0) {
800 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
801 key
= r600_shader_selector_key(ctx
, sel
);
811 shader
->next_variant
= sel
->current
;
812 sel
->current
= shader
;
814 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
815 r600_adjust_gprs(rctx
);
818 if (rctx
->ps_shader
&&
819 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
820 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
821 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
826 static void *r600_create_shader_state(struct pipe_context
*ctx
,
827 const struct pipe_shader_state
*state
,
828 unsigned pipe_shader_type
)
830 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
833 sel
->type
= pipe_shader_type
;
834 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
835 sel
->so
= state
->stream_output
;
837 r
= r600_shader_select(ctx
, sel
, NULL
);
844 static void *r600_create_ps_state(struct pipe_context
*ctx
,
845 const struct pipe_shader_state
*state
)
847 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
850 static void *r600_create_vs_state(struct pipe_context
*ctx
,
851 const struct pipe_shader_state
*state
)
853 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
856 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
858 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
861 state
= rctx
->dummy_pixel_shader
;
863 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
864 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
866 if (rctx
->chip_class
<= R700
) {
867 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
869 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
870 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
871 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
875 r600_adjust_gprs(rctx
);
878 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
879 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
880 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
884 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
886 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
888 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
890 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
892 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
893 r600_adjust_gprs(rctx
);
895 /* Update clip misc state. */
896 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
897 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
898 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
899 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
900 r600_atom_dirty(rctx
, &rctx
->clip_misc_state
.atom
);
905 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
906 struct r600_pipe_shader_selector
*sel
)
908 struct r600_pipe_shader
*p
= sel
->current
, *c
;
911 r600_pipe_shader_destroy(ctx
, p
);
921 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
923 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
924 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
926 if (rctx
->ps_shader
== sel
) {
927 rctx
->ps_shader
= NULL
;
930 r600_delete_shader_selector(ctx
, sel
);
933 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
935 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
936 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
938 if (rctx
->vs_shader
== sel
) {
939 rctx
->vs_shader
= NULL
;
942 r600_delete_shader_selector(ctx
, sel
);
945 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
947 if (state
->dirty_mask
) {
948 rctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
949 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
950 : util_bitcount(state
->dirty_mask
)*19;
951 r600_atom_dirty(rctx
, &state
->atom
);
955 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
956 struct pipe_constant_buffer
*input
)
958 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
959 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
960 struct pipe_constant_buffer
*cb
;
963 /* Note that the state tracker can unbind constant buffers by
966 if (unlikely(!input
)) {
967 state
->enabled_mask
&= ~(1 << index
);
968 state
->dirty_mask
&= ~(1 << index
);
969 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
973 cb
= &state
->cb
[index
];
974 cb
->buffer_size
= input
->buffer_size
;
976 ptr
= input
->user_buffer
;
979 /* Upload the user buffer. */
980 if (R600_BIG_ENDIAN
) {
982 unsigned i
, size
= input
->buffer_size
;
984 if (!(tmpPtr
= malloc(size
))) {
985 R600_ERR("Failed to allocate BE swap buffer.\n");
989 for (i
= 0; i
< size
/ 4; ++i
) {
990 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
993 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
996 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
999 /* Setup the hw buffer. */
1000 cb
->buffer_offset
= input
->buffer_offset
;
1001 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
1004 state
->enabled_mask
|= 1 << index
;
1005 state
->dirty_mask
|= 1 << index
;
1006 r600_constant_buffers_dirty(rctx
, state
);
1009 static struct pipe_stream_output_target
*
1010 r600_create_so_target(struct pipe_context
*ctx
,
1011 struct pipe_resource
*buffer
,
1012 unsigned buffer_offset
,
1013 unsigned buffer_size
)
1015 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1016 struct r600_so_target
*t
;
1019 t
= CALLOC_STRUCT(r600_so_target
);
1024 t
->b
.reference
.count
= 1;
1026 pipe_resource_reference(&t
->b
.buffer
, buffer
);
1027 t
->b
.buffer_offset
= buffer_offset
;
1028 t
->b
.buffer_size
= buffer_size
;
1030 t
->filled_size
= (struct r600_resource
*)
1031 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
1032 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
1033 memset(ptr
, 0, t
->filled_size
->buf
->size
);
1034 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
1039 static void r600_so_target_destroy(struct pipe_context
*ctx
,
1040 struct pipe_stream_output_target
*target
)
1042 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
1043 pipe_resource_reference(&t
->b
.buffer
, NULL
);
1044 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
1048 static void r600_set_so_targets(struct pipe_context
*ctx
,
1049 unsigned num_targets
,
1050 struct pipe_stream_output_target
**targets
,
1051 unsigned append_bitmask
)
1053 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1056 /* Stop streamout. */
1057 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
1058 r600_context_streamout_end(rctx
);
1061 /* Set the new targets. */
1062 for (i
= 0; i
< num_targets
; i
++) {
1063 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
1065 for (; i
< rctx
->num_so_targets
; i
++) {
1066 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
1069 rctx
->num_so_targets
= num_targets
;
1070 rctx
->streamout_start
= num_targets
!= 0;
1071 rctx
->streamout_append_bitmask
= append_bitmask
;
1074 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1076 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1078 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1081 rctx
->sample_mask
.sample_mask
= sample_mask
;
1082 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1085 static void r600_update_derived_state(struct r600_context
*rctx
)
1087 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1088 unsigned ps_dirty
= 0, blend_override
;
1090 if (!rctx
->blitter
->running
) {
1093 /* Decompress textures if needed. */
1094 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1095 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1096 if (views
->compressed_depthtex_mask
) {
1097 r600_decompress_depth_textures(rctx
, views
);
1099 if (views
->compressed_colortex_mask
) {
1100 r600_decompress_color_textures(rctx
, views
);
1105 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1107 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
1108 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
1109 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1111 if (rctx
->chip_class
>= EVERGREEN
)
1112 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1114 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1120 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1122 blend_override
= (rctx
->dual_src_blend
&&
1123 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1125 if (blend_override
!= rctx
->blend_override
) {
1126 rctx
->blend_override
= blend_override
;
1127 r600_bind_blend_state_internal(rctx
,
1128 blend_override
? rctx
->no_blend
: rctx
->blend
);
1131 if (rctx
->chip_class
>= EVERGREEN
) {
1132 evergreen_update_dual_export_state(rctx
);
1134 r600_update_dual_export_state(rctx
);
1138 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1140 static const int prim_conv
[] = {
1141 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1142 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1143 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1144 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1145 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1146 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1147 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1148 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1149 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1150 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1151 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1152 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1153 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1154 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1155 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1157 assert(mode
< Elements(prim_conv
));
1159 return prim_conv
[mode
];
1162 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1164 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1165 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1167 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1168 state
->pa_cl_clip_cntl
|
1169 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1170 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1171 state
->pa_cl_vs_out_cntl
|
1172 (state
->clip_plane_enable
& state
->clip_dist_write
));
1175 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1177 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1178 struct pipe_draw_info info
= *dinfo
;
1179 struct pipe_index_buffer ib
= {};
1181 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1182 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1186 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1191 if (!rctx
->vs_shader
) {
1196 r600_update_derived_state(rctx
);
1199 /* Initialize the index buffer struct. */
1200 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1201 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1202 ib
.index_size
= rctx
->index_buffer
.index_size
;
1203 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1205 /* Translate or upload, if needed. */
1206 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1208 ptr
= (uint8_t*)ib
.user_buffer
;
1209 if (!ib
.buffer
&& ptr
) {
1210 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1211 ptr
, &ib
.offset
, &ib
.buffer
);
1214 info
.index_bias
= info
.start
;
1217 /* Enable stream out if needed. */
1218 if (rctx
->streamout_start
) {
1219 r600_context_streamout_begin(rctx
);
1220 rctx
->streamout_start
= FALSE
;
1223 /* Set the index offset and multi primitive */
1224 if (rctx
->vgt2_state
.vgt_indx_offset
!= info
.index_bias
) {
1225 rctx
->vgt2_state
.vgt_indx_offset
= info
.index_bias
;
1226 r600_atom_dirty(rctx
, &rctx
->vgt2_state
.atom
);
1228 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1229 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
) {
1230 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1231 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1232 r600_atom_dirty(rctx
, &rctx
->vgt_state
.atom
);
1235 /* Emit states (the function expects that we emit at most 17 dwords here). */
1236 r600_need_cs_space(rctx
, 0, TRUE
);
1237 r600_flush_emit(rctx
);
1239 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1240 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1243 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1245 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1246 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1248 rctx
->pm4_dirty_cdwords
= 0;
1250 /* Update start instance. */
1251 if (rctx
->last_start_instance
!= info
.start_instance
) {
1252 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1253 rctx
->last_start_instance
= info
.start_instance
;
1256 /* Update the primitive type. */
1257 if (rctx
->last_primitive_type
!= info
.mode
) {
1258 unsigned ls_mask
= 0;
1260 if (info
.mode
== PIPE_PRIM_LINES
)
1262 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1263 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1266 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1267 S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
1268 r600_write_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
1269 r600_conv_prim_to_gs_out(info
.mode
));
1270 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1271 r600_conv_pipe_prim(info
.mode
));
1273 rctx
->last_primitive_type
= info
.mode
;
1277 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1278 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1280 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1281 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1282 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1283 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1285 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1287 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1288 cs
->buf
[cs
->cdw
++] = va
;
1289 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1290 cs
->buf
[cs
->cdw
++] = info
.count
;
1291 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1292 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1293 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1295 if (info
.count_from_stream_output
) {
1296 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1297 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1299 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1301 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1302 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1303 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1304 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1305 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1306 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1308 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1309 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1312 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1313 cs
->buf
[cs
->cdw
++] = info
.count
;
1314 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1315 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1318 /* Set the depth buffer as dirty. */
1319 if (rctx
->framebuffer
.zsbuf
) {
1320 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
1321 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1323 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1325 if (rctx
->compressed_cb_mask
) {
1326 struct pipe_surface
*surf
;
1327 struct r600_texture
*rtex
;
1328 unsigned mask
= rctx
->compressed_cb_mask
;
1331 unsigned i
= u_bit_scan(&mask
);
1332 surf
= rctx
->framebuffer
.cbufs
[i
];
1333 rtex
= (struct r600_texture
*)surf
->texture
;
1335 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1340 pipe_resource_reference(&ib
.buffer
, NULL
);
1343 void r600_draw_rectangle(struct blitter_context
*blitter
,
1344 unsigned x1
, unsigned y1
, unsigned x2
, unsigned y2
, float depth
,
1345 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1347 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1348 struct pipe_viewport_state viewport
;
1349 struct pipe_resource
*buf
= NULL
;
1350 unsigned offset
= 0;
1353 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1354 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1358 /* Some operations (like color resolve on r6xx) don't work
1359 * with the conventional primitive types.
1360 * One that works is PT_RECTLIST, which we use here. */
1362 /* setup viewport */
1363 viewport
.scale
[0] = 1.0f
;
1364 viewport
.scale
[1] = 1.0f
;
1365 viewport
.scale
[2] = 1.0f
;
1366 viewport
.scale
[3] = 1.0f
;
1367 viewport
.translate
[0] = 0.0f
;
1368 viewport
.translate
[1] = 0.0f
;
1369 viewport
.translate
[2] = 0.0f
;
1370 viewport
.translate
[3] = 0.0f
;
1371 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1373 /* Upload vertices. The hw rectangle has only 3 vertices,
1374 * I guess the 4th one is derived from the first 3.
1375 * The vertex specification should match u_blitter's vertex element state. */
1376 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1393 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1394 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1395 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1399 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, offset
,
1400 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1401 pipe_resource_reference(&buf
, NULL
);
1404 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1405 struct r600_pipe_state
*state
,
1406 uint32_t offset
, uint32_t value
,
1407 uint32_t range_id
, uint32_t block_id
,
1408 struct r600_resource
*bo
,
1409 enum radeon_bo_usage usage
)
1412 struct r600_range
*range
;
1413 struct r600_block
*block
;
1415 if (bo
) assert(usage
);
1417 range
= &ctx
->range
[range_id
];
1418 block
= range
->blocks
[block_id
];
1419 state
->regs
[state
->nregs
].block
= block
;
1420 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1422 state
->regs
[state
->nregs
].value
= value
;
1423 state
->regs
[state
->nregs
].bo
= bo
;
1424 state
->regs
[state
->nregs
].bo_usage
= usage
;
1427 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1430 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1431 struct r600_pipe_state
*state
,
1432 uint32_t offset
, uint32_t value
,
1433 uint32_t range_id
, uint32_t block_id
)
1435 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1436 range_id
, block_id
, NULL
, 0);
1439 uint32_t r600_translate_stencil_op(int s_op
)
1442 case PIPE_STENCIL_OP_KEEP
:
1443 return V_028800_STENCIL_KEEP
;
1444 case PIPE_STENCIL_OP_ZERO
:
1445 return V_028800_STENCIL_ZERO
;
1446 case PIPE_STENCIL_OP_REPLACE
:
1447 return V_028800_STENCIL_REPLACE
;
1448 case PIPE_STENCIL_OP_INCR
:
1449 return V_028800_STENCIL_INCR
;
1450 case PIPE_STENCIL_OP_DECR
:
1451 return V_028800_STENCIL_DECR
;
1452 case PIPE_STENCIL_OP_INCR_WRAP
:
1453 return V_028800_STENCIL_INCR_WRAP
;
1454 case PIPE_STENCIL_OP_DECR_WRAP
:
1455 return V_028800_STENCIL_DECR_WRAP
;
1456 case PIPE_STENCIL_OP_INVERT
:
1457 return V_028800_STENCIL_INVERT
;
1459 R600_ERR("Unknown stencil op %d", s_op
);
1466 uint32_t r600_translate_fill(uint32_t func
)
1469 case PIPE_POLYGON_MODE_FILL
:
1471 case PIPE_POLYGON_MODE_LINE
:
1473 case PIPE_POLYGON_MODE_POINT
:
1481 unsigned r600_tex_wrap(unsigned wrap
)
1485 case PIPE_TEX_WRAP_REPEAT
:
1486 return V_03C000_SQ_TEX_WRAP
;
1487 case PIPE_TEX_WRAP_CLAMP
:
1488 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1489 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1490 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1491 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1492 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1493 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1494 return V_03C000_SQ_TEX_MIRROR
;
1495 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1496 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1497 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1498 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1499 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1500 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1504 unsigned r600_tex_filter(unsigned filter
)
1508 case PIPE_TEX_FILTER_NEAREST
:
1509 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1510 case PIPE_TEX_FILTER_LINEAR
:
1511 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1515 unsigned r600_tex_mipfilter(unsigned filter
)
1518 case PIPE_TEX_MIPFILTER_NEAREST
:
1519 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1520 case PIPE_TEX_MIPFILTER_LINEAR
:
1521 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1523 case PIPE_TEX_MIPFILTER_NONE
:
1524 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1528 unsigned r600_tex_compare(unsigned compare
)
1532 case PIPE_FUNC_NEVER
:
1533 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1534 case PIPE_FUNC_LESS
:
1535 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1536 case PIPE_FUNC_EQUAL
:
1537 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1538 case PIPE_FUNC_LEQUAL
:
1539 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1540 case PIPE_FUNC_GREATER
:
1541 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1542 case PIPE_FUNC_NOTEQUAL
:
1543 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1544 case PIPE_FUNC_GEQUAL
:
1545 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1546 case PIPE_FUNC_ALWAYS
:
1547 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1551 /* keep this at the end of this file, please */
1552 void r600_init_common_state_functions(struct r600_context
*rctx
)
1554 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1555 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1556 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1557 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1558 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1559 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1560 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1561 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1562 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1563 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1564 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1565 rctx
->context
.delete_blend_state
= r600_delete_state
;
1566 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1567 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1568 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1569 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1570 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1571 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1572 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1573 rctx
->context
.set_clip_state
= r600_set_clip_state
;
1574 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1575 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1576 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1577 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1578 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1579 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1580 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1581 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1582 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1583 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1584 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1585 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1586 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1587 rctx
->context
.draw_vbo
= r600_draw_vbo
;