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radeon: don't use old bind_vertex/fragment_sampler_states() hooks
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/u_draw_quad.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
38
39 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
40
41 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
42 {
43 assert(!cb->buf);
44 cb->buf = CALLOC(1, 4 * num_dw);
45 cb->max_num_dw = num_dw;
46 }
47
48 void r600_release_command_buffer(struct r600_command_buffer *cb)
49 {
50 FREE(cb->buf);
51 }
52
53 void r600_init_atom(struct r600_context *rctx,
54 struct r600_atom *atom,
55 unsigned id,
56 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
57 unsigned num_dw)
58 {
59 assert(id < R600_NUM_ATOMS);
60 assert(rctx->atoms[id] == NULL);
61 rctx->atoms[id] = atom;
62 atom->emit = (void*)emit;
63 atom->num_dw = num_dw;
64 atom->dirty = false;
65 }
66
67 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
68 {
69 r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
70 }
71
72 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
73 {
74 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
75 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
76 unsigned alpha_ref = a->sx_alpha_ref;
77
78 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
79 alpha_ref &= ~0x1FFF;
80 }
81
82 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
83 a->sx_alpha_test_control |
84 S_028410_ALPHA_TEST_BYPASS(a->bypass));
85 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
86 }
87
88 static void r600_texture_barrier(struct pipe_context *ctx)
89 {
90 struct r600_context *rctx = (struct r600_context *)ctx;
91
92 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
93 R600_CONTEXT_FLUSH_AND_INV_CB |
94 R600_CONTEXT_FLUSH_AND_INV |
95 R600_CONTEXT_WAIT_3D_IDLE;
96 }
97
98 static unsigned r600_conv_pipe_prim(unsigned prim)
99 {
100 static const unsigned prim_conv[] = {
101 V_008958_DI_PT_POINTLIST,
102 V_008958_DI_PT_LINELIST,
103 V_008958_DI_PT_LINELOOP,
104 V_008958_DI_PT_LINESTRIP,
105 V_008958_DI_PT_TRILIST,
106 V_008958_DI_PT_TRISTRIP,
107 V_008958_DI_PT_TRIFAN,
108 V_008958_DI_PT_QUADLIST,
109 V_008958_DI_PT_QUADSTRIP,
110 V_008958_DI_PT_POLYGON,
111 V_008958_DI_PT_LINELIST_ADJ,
112 V_008958_DI_PT_LINESTRIP_ADJ,
113 V_008958_DI_PT_TRILIST_ADJ,
114 V_008958_DI_PT_TRISTRIP_ADJ,
115 V_008958_DI_PT_RECTLIST
116 };
117 return prim_conv[prim];
118 }
119
120 /* common state between evergreen and r600 */
121
122 static void r600_bind_blend_state_internal(struct r600_context *rctx,
123 struct r600_blend_state *blend, bool blend_disable)
124 {
125 unsigned color_control;
126 bool update_cb = false;
127
128 rctx->alpha_to_one = blend->alpha_to_one;
129 rctx->dual_src_blend = blend->dual_src_blend;
130
131 if (!blend_disable) {
132 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
133 color_control = blend->cb_color_control;
134 } else {
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
137 color_control = blend->cb_color_control_no_blend;
138 }
139
140 /* Update derived states. */
141 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
142 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
143 update_cb = true;
144 }
145 if (rctx->b.chip_class <= R700 &&
146 rctx->cb_misc_state.cb_color_control != color_control) {
147 rctx->cb_misc_state.cb_color_control = color_control;
148 update_cb = true;
149 }
150 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
151 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
152 update_cb = true;
153 }
154 if (update_cb) {
155 rctx->cb_misc_state.atom.dirty = true;
156 }
157 }
158
159 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
160 {
161 struct r600_context *rctx = (struct r600_context *)ctx;
162 struct r600_blend_state *blend = (struct r600_blend_state *)state;
163
164 if (blend == NULL)
165 return;
166
167 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
168 }
169
170 static void r600_set_blend_color(struct pipe_context *ctx,
171 const struct pipe_blend_color *state)
172 {
173 struct r600_context *rctx = (struct r600_context *)ctx;
174
175 rctx->blend_color.state = *state;
176 rctx->blend_color.atom.dirty = true;
177 }
178
179 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
180 {
181 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
182 struct pipe_blend_color *state = &rctx->blend_color.state;
183
184 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
185 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
186 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
187 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
188 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
189 }
190
191 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
192 {
193 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
194 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
195
196 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
197 r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
198 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
199 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
200 }
201
202 static void r600_set_clip_state(struct pipe_context *ctx,
203 const struct pipe_clip_state *state)
204 {
205 struct r600_context *rctx = (struct r600_context *)ctx;
206 struct pipe_constant_buffer cb;
207
208 rctx->clip_state.state = *state;
209 rctx->clip_state.atom.dirty = true;
210
211 cb.buffer = NULL;
212 cb.user_buffer = state->ucp;
213 cb.buffer_offset = 0;
214 cb.buffer_size = 4*4*8;
215 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
216 pipe_resource_reference(&cb.buffer, NULL);
217 }
218
219 static void r600_set_stencil_ref(struct pipe_context *ctx,
220 const struct r600_stencil_ref *state)
221 {
222 struct r600_context *rctx = (struct r600_context *)ctx;
223
224 rctx->stencil_ref.state = *state;
225 rctx->stencil_ref.atom.dirty = true;
226 }
227
228 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
229 {
230 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
231 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
232
233 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
234 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
235 S_028430_STENCILREF(a->state.ref_value[0]) |
236 S_028430_STENCILMASK(a->state.valuemask[0]) |
237 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
238 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
239 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
240 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
241 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
242 }
243
244 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
245 const struct pipe_stencil_ref *state)
246 {
247 struct r600_context *rctx = (struct r600_context *)ctx;
248 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
249 struct r600_stencil_ref ref;
250
251 rctx->stencil_ref.pipe_state = *state;
252
253 if (!dsa)
254 return;
255
256 ref.ref_value[0] = state->ref_value[0];
257 ref.ref_value[1] = state->ref_value[1];
258 ref.valuemask[0] = dsa->valuemask[0];
259 ref.valuemask[1] = dsa->valuemask[1];
260 ref.writemask[0] = dsa->writemask[0];
261 ref.writemask[1] = dsa->writemask[1];
262
263 r600_set_stencil_ref(ctx, &ref);
264 }
265
266 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
267 {
268 struct r600_context *rctx = (struct r600_context *)ctx;
269 struct r600_dsa_state *dsa = state;
270 struct r600_stencil_ref ref;
271
272 if (state == NULL)
273 return;
274
275 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
276
277 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
278 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
279 ref.valuemask[0] = dsa->valuemask[0];
280 ref.valuemask[1] = dsa->valuemask[1];
281 ref.writemask[0] = dsa->writemask[0];
282 ref.writemask[1] = dsa->writemask[1];
283 if (rctx->zwritemask != dsa->zwritemask) {
284 rctx->zwritemask = dsa->zwritemask;
285 if (rctx->b.chip_class >= EVERGREEN) {
286 /* work around some issue when not writting to zbuffer
287 * we are having lockup on evergreen so do not enable
288 * hyperz when not writting zbuffer
289 */
290 rctx->db_misc_state.atom.dirty = true;
291 }
292 }
293
294 r600_set_stencil_ref(ctx, &ref);
295
296 /* Update alphatest state. */
297 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
298 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
299 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
300 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
301 rctx->alphatest_state.atom.dirty = true;
302 if (rctx->b.chip_class >= EVERGREEN) {
303 evergreen_update_db_shader_control(rctx);
304 } else {
305 r600_update_db_shader_control(rctx);
306 }
307 }
308 }
309
310 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
311 {
312 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
313 struct r600_context *rctx = (struct r600_context *)ctx;
314
315 if (state == NULL)
316 return;
317
318 rctx->rasterizer = rs;
319
320 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
321
322 if (rs->offset_enable &&
323 (rs->offset_units != rctx->poly_offset_state.offset_units ||
324 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
325 rctx->poly_offset_state.offset_units = rs->offset_units;
326 rctx->poly_offset_state.offset_scale = rs->offset_scale;
327 rctx->poly_offset_state.atom.dirty = true;
328 }
329
330 /* Update clip_misc_state. */
331 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
332 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
333 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
334 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
335 rctx->clip_misc_state.atom.dirty = true;
336 }
337
338 /* Workaround for a missing scissor enable on r600. */
339 if (rctx->b.chip_class == R600 &&
340 rs->scissor_enable != rctx->scissor.enable) {
341 rctx->scissor.enable = rs->scissor_enable;
342 rctx->scissor.atom.dirty = true;
343 }
344
345 /* Re-emit PA_SC_LINE_STIPPLE. */
346 rctx->last_primitive_type = -1;
347 }
348
349 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
350 {
351 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
352
353 r600_release_command_buffer(&rs->buffer);
354 FREE(rs);
355 }
356
357 static void r600_sampler_view_destroy(struct pipe_context *ctx,
358 struct pipe_sampler_view *state)
359 {
360 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
361
362 pipe_resource_reference(&state->texture, NULL);
363 FREE(resource);
364 }
365
366 void r600_sampler_states_dirty(struct r600_context *rctx,
367 struct r600_sampler_states *state)
368 {
369 if (state->dirty_mask) {
370 if (state->dirty_mask & state->has_bordercolor_mask) {
371 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
372 }
373 state->atom.num_dw =
374 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
375 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
376 state->atom.dirty = true;
377 }
378 }
379
380 static void r600_bind_sampler_states(struct pipe_context *pipe,
381 unsigned shader,
382 unsigned start,
383 unsigned count, void **states)
384 {
385 struct r600_context *rctx = (struct r600_context *)pipe;
386 struct r600_textures_info *dst = &rctx->samplers[shader];
387 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
388 int seamless_cube_map = -1;
389 unsigned i;
390 /* This sets 1-bit for states with index >= count. */
391 uint32_t disable_mask = ~((1ull << count) - 1);
392 /* These are the new states set by this function. */
393 uint32_t new_mask = 0;
394
395 assert(start == 0); /* XXX fix below */
396
397 if (shader != PIPE_SHADER_VERTEX &&
398 shader != PIPE_SHADER_FRAGMENT) {
399 assert(!"Only vertex/fragment sampler are implemented.");
400 return;
401 }
402
403 for (i = 0; i < count; i++) {
404 struct r600_pipe_sampler_state *rstate = rstates[i];
405
406 if (rstate == dst->states.states[i]) {
407 continue;
408 }
409
410 if (rstate) {
411 if (rstate->border_color_use) {
412 dst->states.has_bordercolor_mask |= 1 << i;
413 } else {
414 dst->states.has_bordercolor_mask &= ~(1 << i);
415 }
416 seamless_cube_map = rstate->seamless_cube_map;
417
418 new_mask |= 1 << i;
419 } else {
420 disable_mask |= 1 << i;
421 }
422 }
423
424 memcpy(dst->states.states, rstates, sizeof(void*) * count);
425 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
426
427 dst->states.enabled_mask &= ~disable_mask;
428 dst->states.dirty_mask &= dst->states.enabled_mask;
429 dst->states.enabled_mask |= new_mask;
430 dst->states.dirty_mask |= new_mask;
431 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
432
433 r600_sampler_states_dirty(rctx, &dst->states);
434
435 /* Seamless cubemap state. */
436 if (rctx->b.chip_class <= R700 &&
437 seamless_cube_map != -1 &&
438 seamless_cube_map != rctx->seamless_cube_map.enabled) {
439 /* change in TA_CNTL_AUX need a pipeline flush */
440 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
441 rctx->seamless_cube_map.enabled = seamless_cube_map;
442 rctx->seamless_cube_map.atom.dirty = true;
443 }
444 }
445
446 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
447 {
448 free(state);
449 }
450
451 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
452 {
453 struct r600_blend_state *blend = (struct r600_blend_state*)state;
454
455 r600_release_command_buffer(&blend->buffer);
456 r600_release_command_buffer(&blend->buffer_no_blend);
457 FREE(blend);
458 }
459
460 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
461 {
462 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
463
464 r600_release_command_buffer(&dsa->buffer);
465 free(dsa);
466 }
467
468 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
469 {
470 struct r600_context *rctx = (struct r600_context *)ctx;
471
472 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
473 }
474
475 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
476 {
477 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
478 pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
479 FREE(shader);
480 }
481
482 static void r600_set_index_buffer(struct pipe_context *ctx,
483 const struct pipe_index_buffer *ib)
484 {
485 struct r600_context *rctx = (struct r600_context *)ctx;
486
487 if (ib) {
488 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
489 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
490 r600_context_add_resource_size(ctx, ib->buffer);
491 } else {
492 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
493 }
494 }
495
496 void r600_vertex_buffers_dirty(struct r600_context *rctx)
497 {
498 if (rctx->vertex_buffer_state.dirty_mask) {
499 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
500 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
501 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
502 rctx->vertex_buffer_state.atom.dirty = true;
503 }
504 }
505
506 static void r600_set_vertex_buffers(struct pipe_context *ctx,
507 unsigned start_slot, unsigned count,
508 const struct pipe_vertex_buffer *input)
509 {
510 struct r600_context *rctx = (struct r600_context *)ctx;
511 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
512 struct pipe_vertex_buffer *vb = state->vb + start_slot;
513 unsigned i;
514 uint32_t disable_mask = 0;
515 /* These are the new buffers set by this function. */
516 uint32_t new_buffer_mask = 0;
517
518 /* Set vertex buffers. */
519 if (input) {
520 for (i = 0; i < count; i++) {
521 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
522 if (input[i].buffer) {
523 vb[i].stride = input[i].stride;
524 vb[i].buffer_offset = input[i].buffer_offset;
525 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
526 new_buffer_mask |= 1 << i;
527 r600_context_add_resource_size(ctx, input[i].buffer);
528 } else {
529 pipe_resource_reference(&vb[i].buffer, NULL);
530 disable_mask |= 1 << i;
531 }
532 }
533 }
534 } else {
535 for (i = 0; i < count; i++) {
536 pipe_resource_reference(&vb[i].buffer, NULL);
537 }
538 disable_mask = ((1ull << count) - 1);
539 }
540
541 disable_mask <<= start_slot;
542 new_buffer_mask <<= start_slot;
543
544 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
545 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
546 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
547 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
548
549 r600_vertex_buffers_dirty(rctx);
550 }
551
552 void r600_sampler_views_dirty(struct r600_context *rctx,
553 struct r600_samplerview_state *state)
554 {
555 if (state->dirty_mask) {
556 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
557 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
558 util_bitcount(state->dirty_mask);
559 state->atom.dirty = true;
560 }
561 }
562
563 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
564 unsigned start, unsigned count,
565 struct pipe_sampler_view **views)
566 {
567 struct r600_context *rctx = (struct r600_context *) pipe;
568 struct r600_textures_info *dst = &rctx->samplers[shader];
569 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
570 uint32_t dirty_sampler_states_mask = 0;
571 unsigned i;
572 /* This sets 1-bit for textures with index >= count. */
573 uint32_t disable_mask = ~((1ull << count) - 1);
574 /* These are the new textures set by this function. */
575 uint32_t new_mask = 0;
576
577 /* Set textures with index >= count to NULL. */
578 uint32_t remaining_mask;
579
580 assert(start == 0); /* XXX fix below */
581
582 remaining_mask = dst->views.enabled_mask & disable_mask;
583
584 while (remaining_mask) {
585 i = u_bit_scan(&remaining_mask);
586 assert(dst->views.views[i]);
587
588 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
589 }
590
591 for (i = 0; i < count; i++) {
592 if (rviews[i] == dst->views.views[i]) {
593 continue;
594 }
595
596 if (rviews[i]) {
597 struct r600_texture *rtex =
598 (struct r600_texture*)rviews[i]->base.texture;
599
600 if (rviews[i]->base.texture->target != PIPE_BUFFER) {
601 if (rtex->is_depth && !rtex->is_flushing_texture) {
602 dst->views.compressed_depthtex_mask |= 1 << i;
603 } else {
604 dst->views.compressed_depthtex_mask &= ~(1 << i);
605 }
606
607 /* Track compressed colorbuffers. */
608 if (rtex->cmask.size) {
609 dst->views.compressed_colortex_mask |= 1 << i;
610 } else {
611 dst->views.compressed_colortex_mask &= ~(1 << i);
612 }
613 }
614 /* Changing from array to non-arrays textures and vice versa requires
615 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
616 if (rctx->b.chip_class <= R700 &&
617 (dst->states.enabled_mask & (1 << i)) &&
618 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
619 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
620 dirty_sampler_states_mask |= 1 << i;
621 }
622
623 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
624 new_mask |= 1 << i;
625 r600_context_add_resource_size(pipe, views[i]->texture);
626 } else {
627 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
628 disable_mask |= 1 << i;
629 }
630 }
631
632 dst->views.enabled_mask &= ~disable_mask;
633 dst->views.dirty_mask &= dst->views.enabled_mask;
634 dst->views.enabled_mask |= new_mask;
635 dst->views.dirty_mask |= new_mask;
636 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
637 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
638 dst->views.dirty_txq_constants = TRUE;
639 dst->views.dirty_buffer_constants = TRUE;
640 r600_sampler_views_dirty(rctx, &dst->views);
641
642 if (dirty_sampler_states_mask) {
643 dst->states.dirty_mask |= dirty_sampler_states_mask;
644 r600_sampler_states_dirty(rctx, &dst->states);
645 }
646 }
647
648 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
649 struct pipe_sampler_view **views)
650 {
651 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
652 }
653
654 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
655 struct pipe_sampler_view **views)
656 {
657 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
658 }
659
660 static void r600_set_viewport_states(struct pipe_context *ctx,
661 unsigned start_slot,
662 unsigned num_viewports,
663 const struct pipe_viewport_state *state)
664 {
665 struct r600_context *rctx = (struct r600_context *)ctx;
666
667 rctx->viewport.state = *state;
668 rctx->viewport.atom.dirty = true;
669 }
670
671 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
672 {
673 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
674 struct pipe_viewport_state *state = &rctx->viewport.state;
675
676 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
677 radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
678 radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
679 radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
680 radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
681 radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
682 radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
683 }
684
685 /* Compute the key for the hw shader variant */
686 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
687 struct r600_pipe_shader_selector * sel)
688 {
689 struct r600_context *rctx = (struct r600_context *)ctx;
690 struct r600_shader_key key;
691 memset(&key, 0, sizeof(key));
692
693 if (sel->type == PIPE_SHADER_FRAGMENT) {
694 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
695 key.alpha_to_one = rctx->alpha_to_one &&
696 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
697 !rctx->framebuffer.cb0_is_integer;
698 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
699 /* Dual-source blending only makes sense with nr_cbufs == 1. */
700 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
701 key.nr_cbufs = 2;
702 }
703 return key;
704 }
705
706 /* Select the hw shader variant depending on the current state.
707 * (*dirty) is set to 1 if current variant was changed */
708 static int r600_shader_select(struct pipe_context *ctx,
709 struct r600_pipe_shader_selector* sel,
710 bool *dirty)
711 {
712 struct r600_shader_key key;
713 struct r600_context *rctx = (struct r600_context *)ctx;
714 struct r600_pipe_shader * shader = NULL;
715 int r;
716
717 memset(&key, 0, sizeof(key));
718 key = r600_shader_selector_key(ctx, sel);
719
720 /* Check if we don't need to change anything.
721 * This path is also used for most shaders that don't need multiple
722 * variants, it will cost just a computation of the key and this
723 * test. */
724 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
725 return 0;
726 }
727
728 /* lookup if we have other variants in the list */
729 if (sel->num_shaders > 1) {
730 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
731
732 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
733 p = c;
734 c = c->next_variant;
735 }
736
737 if (c) {
738 p->next_variant = c->next_variant;
739 shader = c;
740 }
741 }
742
743 if (unlikely(!shader)) {
744 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
745 shader->selector = sel;
746
747 r = r600_pipe_shader_create(ctx, shader, key);
748 if (unlikely(r)) {
749 R600_ERR("Failed to build shader variant (type=%u) %d\n",
750 sel->type, r);
751 sel->current = NULL;
752 FREE(shader);
753 return r;
754 }
755
756 /* We don't know the value of nr_ps_max_color_exports until we built
757 * at least one variant, so we may need to recompute the key after
758 * building first variant. */
759 if (sel->type == PIPE_SHADER_FRAGMENT &&
760 sel->num_shaders == 0) {
761 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
762 key = r600_shader_selector_key(ctx, sel);
763 }
764
765 memcpy(&shader->key, &key, sizeof(key));
766 sel->num_shaders++;
767 }
768
769 if (dirty)
770 *dirty = true;
771
772 shader->next_variant = sel->current;
773 sel->current = shader;
774
775 if (rctx->ps_shader &&
776 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
777 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
778 rctx->cb_misc_state.atom.dirty = true;
779 }
780 return 0;
781 }
782
783 static void *r600_create_shader_state(struct pipe_context *ctx,
784 const struct pipe_shader_state *state,
785 unsigned pipe_shader_type)
786 {
787 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
788 int r;
789
790 sel->type = pipe_shader_type;
791 sel->tokens = tgsi_dup_tokens(state->tokens);
792 sel->so = state->stream_output;
793
794 r = r600_shader_select(ctx, sel, NULL);
795 if (r)
796 return NULL;
797
798 return sel;
799 }
800
801 static void *r600_create_ps_state(struct pipe_context *ctx,
802 const struct pipe_shader_state *state)
803 {
804 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
805 }
806
807 static void *r600_create_vs_state(struct pipe_context *ctx,
808 const struct pipe_shader_state *state)
809 {
810 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
811 }
812
813 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
814 {
815 struct r600_context *rctx = (struct r600_context *)ctx;
816
817 if (!state)
818 state = rctx->dummy_pixel_shader;
819
820 rctx->pixel_shader.shader = rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
821 rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
822 rctx->pixel_shader.atom.dirty = true;
823
824 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
825
826 if (rctx->b.chip_class <= R700) {
827 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
828
829 if (rctx->cb_misc_state.multiwrite != multiwrite) {
830 rctx->cb_misc_state.multiwrite = multiwrite;
831 rctx->cb_misc_state.atom.dirty = true;
832 }
833 }
834
835 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
836 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
837 rctx->cb_misc_state.atom.dirty = true;
838 }
839
840 if (rctx->b.chip_class >= EVERGREEN) {
841 evergreen_update_db_shader_control(rctx);
842 } else {
843 r600_update_db_shader_control(rctx);
844 }
845 }
846
847 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
848 {
849 struct r600_context *rctx = (struct r600_context *)ctx;
850
851 if (!state)
852 return;
853
854 rctx->vertex_shader.shader = rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
855 rctx->vertex_shader.atom.dirty = true;
856 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
857
858 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
859
860 /* Update clip misc state. */
861 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
862 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
863 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
864 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
865 rctx->clip_misc_state.atom.dirty = true;
866 }
867 }
868
869 static void r600_delete_shader_selector(struct pipe_context *ctx,
870 struct r600_pipe_shader_selector *sel)
871 {
872 struct r600_pipe_shader *p = sel->current, *c;
873 while (p) {
874 c = p->next_variant;
875 r600_pipe_shader_destroy(ctx, p);
876 free(p);
877 p = c;
878 }
879
880 free(sel->tokens);
881 free(sel);
882 }
883
884
885 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
886 {
887 struct r600_context *rctx = (struct r600_context *)ctx;
888 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
889
890 if (rctx->ps_shader == sel) {
891 rctx->ps_shader = NULL;
892 }
893
894 r600_delete_shader_selector(ctx, sel);
895 }
896
897 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
898 {
899 struct r600_context *rctx = (struct r600_context *)ctx;
900 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
901
902 if (rctx->vs_shader == sel) {
903 rctx->vs_shader = NULL;
904 }
905
906 r600_delete_shader_selector(ctx, sel);
907 }
908
909 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
910 {
911 if (state->dirty_mask) {
912 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
913 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
914 : util_bitcount(state->dirty_mask)*19;
915 state->atom.dirty = true;
916 }
917 }
918
919 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
920 struct pipe_constant_buffer *input)
921 {
922 struct r600_context *rctx = (struct r600_context *)ctx;
923 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
924 struct pipe_constant_buffer *cb;
925 const uint8_t *ptr;
926
927 /* Note that the state tracker can unbind constant buffers by
928 * passing NULL here.
929 */
930 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
931 state->enabled_mask &= ~(1 << index);
932 state->dirty_mask &= ~(1 << index);
933 pipe_resource_reference(&state->cb[index].buffer, NULL);
934 return;
935 }
936
937 cb = &state->cb[index];
938 cb->buffer_size = input->buffer_size;
939
940 ptr = input->user_buffer;
941
942 if (ptr) {
943 /* Upload the user buffer. */
944 if (R600_BIG_ENDIAN) {
945 uint32_t *tmpPtr;
946 unsigned i, size = input->buffer_size;
947
948 if (!(tmpPtr = malloc(size))) {
949 R600_ERR("Failed to allocate BE swap buffer.\n");
950 return;
951 }
952
953 for (i = 0; i < size / 4; ++i) {
954 tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
955 }
956
957 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
958 free(tmpPtr);
959 } else {
960 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
961 }
962 /* account it in gtt */
963 rctx->b.gtt += input->buffer_size;
964 } else {
965 /* Setup the hw buffer. */
966 cb->buffer_offset = input->buffer_offset;
967 pipe_resource_reference(&cb->buffer, input->buffer);
968 r600_context_add_resource_size(ctx, input->buffer);
969 }
970
971 state->enabled_mask |= 1 << index;
972 state->dirty_mask |= 1 << index;
973 r600_constant_buffers_dirty(rctx, state);
974 }
975
976 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
977 {
978 struct r600_context *rctx = (struct r600_context*)pipe;
979
980 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
981 return;
982
983 rctx->sample_mask.sample_mask = sample_mask;
984 rctx->sample_mask.atom.dirty = true;
985 }
986
987 /*
988 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
989 * doesn't require full swizzles it does need masking and setting alpha
990 * to one, so we setup a set of 5 constants with the masks + alpha value
991 * then in the shader, we AND the 4 components with 0xffffffff or 0,
992 * then OR the alpha with the value given here.
993 * We use a 6th constant to store the txq buffer size in
994 */
995 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
996 {
997 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
998 int bits;
999 uint32_t array_size;
1000 struct pipe_constant_buffer cb;
1001 int i, j;
1002
1003 if (!samplers->views.dirty_buffer_constants)
1004 return;
1005
1006 samplers->views.dirty_buffer_constants = FALSE;
1007
1008 bits = util_last_bit(samplers->views.enabled_mask);
1009 array_size = bits * 8 * sizeof(uint32_t) * 4;
1010 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1011 memset(samplers->buffer_constants, 0, array_size);
1012 for (i = 0; i < bits; i++) {
1013 if (samplers->views.enabled_mask & (1 << i)) {
1014 int offset = i * 8;
1015 const struct util_format_description *desc;
1016 desc = util_format_description(samplers->views.views[i]->base.format);
1017
1018 for (j = 0; j < 4; j++)
1019 if (j < desc->nr_channels)
1020 samplers->buffer_constants[offset+j] = 0xffffffff;
1021 else
1022 samplers->buffer_constants[offset+j] = 0x0;
1023 if (desc->nr_channels < 4) {
1024 if (desc->channel[0].pure_integer)
1025 samplers->buffer_constants[offset+4] = 1;
1026 else
1027 samplers->buffer_constants[offset+4] = 0x3f800000;
1028 } else
1029 samplers->buffer_constants[offset + 4] = 0;
1030
1031 samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1032 }
1033 }
1034
1035 cb.buffer = NULL;
1036 cb.user_buffer = samplers->buffer_constants;
1037 cb.buffer_offset = 0;
1038 cb.buffer_size = array_size;
1039 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1040 pipe_resource_reference(&cb.buffer, NULL);
1041 }
1042
1043 /* On evergreen we only need to store the buffer size for TXQ */
1044 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1045 {
1046 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1047 int bits;
1048 uint32_t array_size;
1049 struct pipe_constant_buffer cb;
1050 int i;
1051
1052 if (!samplers->views.dirty_buffer_constants)
1053 return;
1054
1055 samplers->views.dirty_buffer_constants = FALSE;
1056
1057 bits = util_last_bit(samplers->views.enabled_mask);
1058 array_size = bits * sizeof(uint32_t) * 4;
1059 samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1060 memset(samplers->buffer_constants, 0, array_size);
1061 for (i = 0; i < bits; i++)
1062 if (samplers->views.enabled_mask & (1 << i))
1063 samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1064
1065 cb.buffer = NULL;
1066 cb.user_buffer = samplers->buffer_constants;
1067 cb.buffer_offset = 0;
1068 cb.buffer_size = array_size;
1069 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1070 pipe_resource_reference(&cb.buffer, NULL);
1071 }
1072
1073 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1074 {
1075 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1076 int bits;
1077 uint32_t array_size;
1078 struct pipe_constant_buffer cb;
1079 int i;
1080
1081 if (!samplers->views.dirty_txq_constants)
1082 return;
1083
1084 samplers->views.dirty_txq_constants = FALSE;
1085
1086 bits = util_last_bit(samplers->views.enabled_mask);
1087 array_size = bits * sizeof(uint32_t) * 4;
1088 samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1089 memset(samplers->txq_constants, 0, array_size);
1090 for (i = 0; i < bits; i++)
1091 if (samplers->views.enabled_mask & (1 << i))
1092 samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1093
1094 cb.buffer = NULL;
1095 cb.user_buffer = samplers->txq_constants;
1096 cb.buffer_offset = 0;
1097 cb.buffer_size = array_size;
1098 rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1099 pipe_resource_reference(&cb.buffer, NULL);
1100 }
1101
1102 static bool r600_update_derived_state(struct r600_context *rctx)
1103 {
1104 struct pipe_context * ctx = (struct pipe_context*)rctx;
1105 bool ps_dirty = false;
1106 bool blend_disable;
1107
1108 if (!rctx->blitter->running) {
1109 unsigned i;
1110
1111 /* Decompress textures if needed. */
1112 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1113 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1114 if (views->compressed_depthtex_mask) {
1115 r600_decompress_depth_textures(rctx, views);
1116 }
1117 if (views->compressed_colortex_mask) {
1118 r600_decompress_color_textures(rctx, views);
1119 }
1120 }
1121 }
1122
1123 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1124
1125 if (rctx->ps_shader && rctx->rasterizer &&
1126 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1127 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1128
1129 if (rctx->b.chip_class >= EVERGREEN)
1130 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1131 else
1132 r600_update_ps_state(ctx, rctx->ps_shader->current);
1133
1134 ps_dirty = true;
1135 }
1136
1137 if (ps_dirty) {
1138 rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
1139 rctx->pixel_shader.atom.dirty = true;
1140 }
1141
1142 /* on R600 we stuff masks + txq info into one constant buffer */
1143 /* on evergreen we only need a txq info one */
1144 if (rctx->b.chip_class < EVERGREEN) {
1145 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1146 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1147 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1148 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1149 } else {
1150 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1151 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1152 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1153 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1154 }
1155
1156
1157 if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1158 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1159 if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1160 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1161
1162 if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1163 if (!r600_adjust_gprs(rctx)) {
1164 /* discard rendering */
1165 return false;
1166 }
1167 }
1168
1169 blend_disable = (rctx->dual_src_blend &&
1170 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1171
1172 if (blend_disable != rctx->force_blend_disable) {
1173 rctx->force_blend_disable = blend_disable;
1174 r600_bind_blend_state_internal(rctx,
1175 rctx->blend_state.cso,
1176 blend_disable);
1177 }
1178 return true;
1179 }
1180
1181 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1182 {
1183 static const int prim_conv[] = {
1184 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1185 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1186 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1187 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1188 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1189 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1190 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1191 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1192 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1193 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1194 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1195 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1196 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1197 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1198 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1199 };
1200 assert(mode < Elements(prim_conv));
1201
1202 return prim_conv[mode];
1203 }
1204
1205 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1206 {
1207 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1208 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1209
1210 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1211 state->pa_cl_clip_cntl |
1212 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1213 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1214 state->pa_cl_vs_out_cntl |
1215 (state->clip_plane_enable & state->clip_dist_write));
1216 }
1217
1218 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1219 {
1220 struct r600_context *rctx = (struct r600_context *)ctx;
1221 struct pipe_draw_info info = *dinfo;
1222 struct pipe_index_buffer ib = {};
1223 unsigned i;
1224 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1225
1226 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1227 assert(0);
1228 return;
1229 }
1230
1231 if (!rctx->vs_shader) {
1232 assert(0);
1233 return;
1234 }
1235
1236 /* make sure that the gfx ring is only one active */
1237 if (rctx->b.rings.dma.cs) {
1238 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1239 }
1240
1241 if (!r600_update_derived_state(rctx)) {
1242 /* useless to render because current rendering command
1243 * can't be achieved
1244 */
1245 return;
1246 }
1247
1248 if (info.indexed) {
1249 /* Initialize the index buffer struct. */
1250 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1251 ib.user_buffer = rctx->index_buffer.user_buffer;
1252 ib.index_size = rctx->index_buffer.index_size;
1253 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1254
1255 /* Translate 8-bit indices to 16-bit. */
1256 if (ib.index_size == 1) {
1257 struct pipe_resource *out_buffer = NULL;
1258 unsigned out_offset;
1259 void *ptr;
1260
1261 u_upload_alloc(rctx->uploader, 0, info.count * 2,
1262 &out_offset, &out_buffer, &ptr);
1263
1264 util_shorten_ubyte_elts_to_userptr(
1265 &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
1266
1267 pipe_resource_reference(&ib.buffer, NULL);
1268 ib.user_buffer = NULL;
1269 ib.buffer = out_buffer;
1270 ib.offset = out_offset;
1271 ib.index_size = 2;
1272 }
1273
1274 /* Upload the index buffer.
1275 * The upload is skipped for small index counts on little-endian machines
1276 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1277 * Note: Instanced rendering in combination with immediate indices hangs. */
1278 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1279 info.count*ib.index_size > 20)) {
1280 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1281 ib.user_buffer, &ib.offset, &ib.buffer);
1282 ib.user_buffer = NULL;
1283 }
1284 } else {
1285 info.index_bias = info.start;
1286 }
1287
1288 /* Set the index offset and primitive restart. */
1289 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1290 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1291 rctx->vgt_state.vgt_indx_offset != info.index_bias) {
1292 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1293 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1294 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1295 rctx->vgt_state.atom.dirty = true;
1296 }
1297
1298 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1299 if (rctx->b.chip_class == R600) {
1300 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1301 rctx->cb_misc_state.atom.dirty = true;
1302 }
1303
1304 /* Emit states. */
1305 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1306 r600_flush_emit(rctx);
1307
1308 for (i = 0; i < R600_NUM_ATOMS; i++) {
1309 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1310 continue;
1311 }
1312 r600_emit_atom(rctx, rctx->atoms[i]);
1313 }
1314
1315 /* Update start instance. */
1316 if (rctx->last_start_instance != info.start_instance) {
1317 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1318 rctx->last_start_instance = info.start_instance;
1319 }
1320
1321 /* Update the primitive type. */
1322 if (rctx->last_primitive_type != info.mode) {
1323 unsigned ls_mask = 0;
1324
1325 if (info.mode == PIPE_PRIM_LINES)
1326 ls_mask = 1;
1327 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1328 info.mode == PIPE_PRIM_LINE_LOOP)
1329 ls_mask = 2;
1330
1331 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1332 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1333 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1334 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1335 r600_conv_prim_to_gs_out(info.mode));
1336 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1337 r600_conv_pipe_prim(info.mode));
1338
1339 rctx->last_primitive_type = info.mode;
1340 }
1341
1342 /* Draw packets. */
1343 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1344 cs->buf[cs->cdw++] = info.instance_count;
1345 if (info.indexed) {
1346 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1347 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1348 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1349 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1350
1351 if (ib.user_buffer) {
1352 unsigned size_bytes = info.count*ib.index_size;
1353 unsigned size_dw = align(size_bytes, 4) / 4;
1354 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1355 cs->buf[cs->cdw++] = info.count;
1356 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1357 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1358 cs->cdw += size_dw;
1359 } else {
1360 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1361 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1362 cs->buf[cs->cdw++] = va;
1363 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1364 cs->buf[cs->cdw++] = info.count;
1365 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1366 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1367 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1368 }
1369 } else {
1370 if (info.count_from_stream_output) {
1371 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1372 uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1373
1374 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1375
1376 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1377 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1378 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1379 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1380 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1381 cs->buf[cs->cdw++] = 0; /* unused */
1382
1383 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1384 cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1385 }
1386
1387 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1388 cs->buf[cs->cdw++] = info.count;
1389 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1390 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1391 }
1392
1393 if (rctx->screen->trace_bo) {
1394 r600_trace_emit(rctx);
1395 }
1396
1397 /* Set the depth buffer as dirty. */
1398 if (rctx->framebuffer.state.zsbuf) {
1399 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1400 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1401
1402 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1403 }
1404 if (rctx->framebuffer.compressed_cb_mask) {
1405 struct pipe_surface *surf;
1406 struct r600_texture *rtex;
1407 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1408
1409 do {
1410 unsigned i = u_bit_scan(&mask);
1411 surf = rctx->framebuffer.state.cbufs[i];
1412 rtex = (struct r600_texture*)surf->texture;
1413
1414 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1415
1416 } while (mask);
1417 }
1418
1419 pipe_resource_reference(&ib.buffer, NULL);
1420 rctx->num_draw_calls++;
1421 }
1422
1423 void r600_draw_rectangle(struct blitter_context *blitter,
1424 int x1, int y1, int x2, int y2, float depth,
1425 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1426 {
1427 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1428 struct pipe_viewport_state viewport;
1429 struct pipe_resource *buf = NULL;
1430 unsigned offset = 0;
1431 float *vb;
1432
1433 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1434 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1435 return;
1436 }
1437
1438 /* Some operations (like color resolve on r6xx) don't work
1439 * with the conventional primitive types.
1440 * One that works is PT_RECTLIST, which we use here. */
1441
1442 /* setup viewport */
1443 viewport.scale[0] = 1.0f;
1444 viewport.scale[1] = 1.0f;
1445 viewport.scale[2] = 1.0f;
1446 viewport.scale[3] = 1.0f;
1447 viewport.translate[0] = 0.0f;
1448 viewport.translate[1] = 0.0f;
1449 viewport.translate[2] = 0.0f;
1450 viewport.translate[3] = 0.0f;
1451 rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
1452
1453 /* Upload vertices. The hw rectangle has only 3 vertices,
1454 * I guess the 4th one is derived from the first 3.
1455 * The vertex specification should match u_blitter's vertex element state. */
1456 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1457 vb[0] = x1;
1458 vb[1] = y1;
1459 vb[2] = depth;
1460 vb[3] = 1;
1461
1462 vb[8] = x1;
1463 vb[9] = y2;
1464 vb[10] = depth;
1465 vb[11] = 1;
1466
1467 vb[16] = x2;
1468 vb[17] = y1;
1469 vb[18] = depth;
1470 vb[19] = 1;
1471
1472 if (attrib) {
1473 memcpy(vb+4, attrib->f, sizeof(float)*4);
1474 memcpy(vb+12, attrib->f, sizeof(float)*4);
1475 memcpy(vb+20, attrib->f, sizeof(float)*4);
1476 }
1477
1478 /* draw */
1479 util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
1480 R600_PRIM_RECTANGLE_LIST, 3, 2);
1481 pipe_resource_reference(&buf, NULL);
1482 }
1483
1484 uint32_t r600_translate_stencil_op(int s_op)
1485 {
1486 switch (s_op) {
1487 case PIPE_STENCIL_OP_KEEP:
1488 return V_028800_STENCIL_KEEP;
1489 case PIPE_STENCIL_OP_ZERO:
1490 return V_028800_STENCIL_ZERO;
1491 case PIPE_STENCIL_OP_REPLACE:
1492 return V_028800_STENCIL_REPLACE;
1493 case PIPE_STENCIL_OP_INCR:
1494 return V_028800_STENCIL_INCR;
1495 case PIPE_STENCIL_OP_DECR:
1496 return V_028800_STENCIL_DECR;
1497 case PIPE_STENCIL_OP_INCR_WRAP:
1498 return V_028800_STENCIL_INCR_WRAP;
1499 case PIPE_STENCIL_OP_DECR_WRAP:
1500 return V_028800_STENCIL_DECR_WRAP;
1501 case PIPE_STENCIL_OP_INVERT:
1502 return V_028800_STENCIL_INVERT;
1503 default:
1504 R600_ERR("Unknown stencil op %d", s_op);
1505 assert(0);
1506 break;
1507 }
1508 return 0;
1509 }
1510
1511 uint32_t r600_translate_fill(uint32_t func)
1512 {
1513 switch(func) {
1514 case PIPE_POLYGON_MODE_FILL:
1515 return 2;
1516 case PIPE_POLYGON_MODE_LINE:
1517 return 1;
1518 case PIPE_POLYGON_MODE_POINT:
1519 return 0;
1520 default:
1521 assert(0);
1522 return 0;
1523 }
1524 }
1525
1526 unsigned r600_tex_wrap(unsigned wrap)
1527 {
1528 switch (wrap) {
1529 default:
1530 case PIPE_TEX_WRAP_REPEAT:
1531 return V_03C000_SQ_TEX_WRAP;
1532 case PIPE_TEX_WRAP_CLAMP:
1533 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1534 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1535 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1536 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1537 return V_03C000_SQ_TEX_CLAMP_BORDER;
1538 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1539 return V_03C000_SQ_TEX_MIRROR;
1540 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1541 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1542 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1543 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1544 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1545 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1546 }
1547 }
1548
1549 unsigned r600_tex_filter(unsigned filter)
1550 {
1551 switch (filter) {
1552 default:
1553 case PIPE_TEX_FILTER_NEAREST:
1554 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1555 case PIPE_TEX_FILTER_LINEAR:
1556 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1557 }
1558 }
1559
1560 unsigned r600_tex_mipfilter(unsigned filter)
1561 {
1562 switch (filter) {
1563 case PIPE_TEX_MIPFILTER_NEAREST:
1564 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1565 case PIPE_TEX_MIPFILTER_LINEAR:
1566 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1567 default:
1568 case PIPE_TEX_MIPFILTER_NONE:
1569 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1570 }
1571 }
1572
1573 unsigned r600_tex_compare(unsigned compare)
1574 {
1575 switch (compare) {
1576 default:
1577 case PIPE_FUNC_NEVER:
1578 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1579 case PIPE_FUNC_LESS:
1580 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1581 case PIPE_FUNC_EQUAL:
1582 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1583 case PIPE_FUNC_LEQUAL:
1584 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1585 case PIPE_FUNC_GREATER:
1586 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1587 case PIPE_FUNC_NOTEQUAL:
1588 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1589 case PIPE_FUNC_GEQUAL:
1590 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1591 case PIPE_FUNC_ALWAYS:
1592 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1593 }
1594 }
1595
1596 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1597 {
1598 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1599 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1600 (linear_filter &&
1601 (wrap == PIPE_TEX_WRAP_CLAMP ||
1602 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1603 }
1604
1605 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1606 {
1607 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1608 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1609
1610 return (state->border_color.ui[0] || state->border_color.ui[1] ||
1611 state->border_color.ui[2] || state->border_color.ui[3]) &&
1612 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1613 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1614 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1615 }
1616
1617 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1618 {
1619 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1620 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader->current;
1621
1622 r600_emit_command_buffer(cs, &shader->command_buffer);
1623
1624 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1625 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
1626 }
1627
1628 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1629 struct pipe_resource *texture,
1630 const struct pipe_surface *templ,
1631 unsigned width, unsigned height)
1632 {
1633 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1634
1635 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1636 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1637 assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
1638 if (surface == NULL)
1639 return NULL;
1640 pipe_reference_init(&surface->base.reference, 1);
1641 pipe_resource_reference(&surface->base.texture, texture);
1642 surface->base.context = pipe;
1643 surface->base.format = templ->format;
1644 surface->base.width = width;
1645 surface->base.height = height;
1646 surface->base.u = templ->u;
1647 return &surface->base;
1648 }
1649
1650 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1651 struct pipe_resource *tex,
1652 const struct pipe_surface *templ)
1653 {
1654 unsigned level = templ->u.tex.level;
1655
1656 return r600_create_surface_custom(pipe, tex, templ,
1657 u_minify(tex->width0, level),
1658 u_minify(tex->height0, level));
1659 }
1660
1661 static void r600_surface_destroy(struct pipe_context *pipe,
1662 struct pipe_surface *surface)
1663 {
1664 struct r600_surface *surf = (struct r600_surface*)surface;
1665 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1666 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1667 pipe_resource_reference(&surface->texture, NULL);
1668 FREE(surface);
1669 }
1670
1671 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1672 const unsigned char *swizzle_view,
1673 boolean vtx)
1674 {
1675 unsigned i;
1676 unsigned char swizzle[4];
1677 unsigned result = 0;
1678 const uint32_t tex_swizzle_shift[4] = {
1679 16, 19, 22, 25,
1680 };
1681 const uint32_t vtx_swizzle_shift[4] = {
1682 3, 6, 9, 12,
1683 };
1684 const uint32_t swizzle_bit[4] = {
1685 0, 1, 2, 3,
1686 };
1687 const uint32_t *swizzle_shift = tex_swizzle_shift;
1688
1689 if (vtx)
1690 swizzle_shift = vtx_swizzle_shift;
1691
1692 if (swizzle_view) {
1693 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1694 } else {
1695 memcpy(swizzle, swizzle_format, 4);
1696 }
1697
1698 /* Get swizzle. */
1699 for (i = 0; i < 4; i++) {
1700 switch (swizzle[i]) {
1701 case UTIL_FORMAT_SWIZZLE_Y:
1702 result |= swizzle_bit[1] << swizzle_shift[i];
1703 break;
1704 case UTIL_FORMAT_SWIZZLE_Z:
1705 result |= swizzle_bit[2] << swizzle_shift[i];
1706 break;
1707 case UTIL_FORMAT_SWIZZLE_W:
1708 result |= swizzle_bit[3] << swizzle_shift[i];
1709 break;
1710 case UTIL_FORMAT_SWIZZLE_0:
1711 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1712 break;
1713 case UTIL_FORMAT_SWIZZLE_1:
1714 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1715 break;
1716 default: /* UTIL_FORMAT_SWIZZLE_X */
1717 result |= swizzle_bit[0] << swizzle_shift[i];
1718 }
1719 }
1720 return result;
1721 }
1722
1723 /* texture format translate */
1724 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1725 enum pipe_format format,
1726 const unsigned char *swizzle_view,
1727 uint32_t *word4_p, uint32_t *yuv_format_p)
1728 {
1729 struct r600_screen *rscreen = (struct r600_screen *)screen;
1730 uint32_t result = 0, word4 = 0, yuv_format = 0;
1731 const struct util_format_description *desc;
1732 boolean uniform = TRUE;
1733 bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1734 bool is_srgb_valid = FALSE;
1735 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1736 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1737
1738 int i;
1739 const uint32_t sign_bit[4] = {
1740 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1741 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1742 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1743 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1744 };
1745 desc = util_format_description(format);
1746
1747 /* Depth and stencil swizzling is handled separately. */
1748 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1749 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1750 }
1751
1752 /* Colorspace (return non-RGB formats directly). */
1753 switch (desc->colorspace) {
1754 /* Depth stencil formats */
1755 case UTIL_FORMAT_COLORSPACE_ZS:
1756 switch (format) {
1757 /* Depth sampler formats. */
1758 case PIPE_FORMAT_Z16_UNORM:
1759 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1760 result = FMT_16;
1761 goto out_word4;
1762 case PIPE_FORMAT_Z24X8_UNORM:
1763 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1764 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1765 result = FMT_8_24;
1766 goto out_word4;
1767 case PIPE_FORMAT_X8Z24_UNORM:
1768 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1769 if (rscreen->b.chip_class < EVERGREEN)
1770 goto out_unknown;
1771 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1772 result = FMT_24_8;
1773 goto out_word4;
1774 case PIPE_FORMAT_Z32_FLOAT:
1775 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1776 result = FMT_32_FLOAT;
1777 goto out_word4;
1778 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1779 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1780 result = FMT_X24_8_32_FLOAT;
1781 goto out_word4;
1782 /* Stencil sampler formats. */
1783 case PIPE_FORMAT_S8_UINT:
1784 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1785 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1786 result = FMT_8;
1787 goto out_word4;
1788 case PIPE_FORMAT_X24S8_UINT:
1789 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1790 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1791 result = FMT_8_24;
1792 goto out_word4;
1793 case PIPE_FORMAT_S8X24_UINT:
1794 if (rscreen->b.chip_class < EVERGREEN)
1795 goto out_unknown;
1796 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1797 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1798 result = FMT_24_8;
1799 goto out_word4;
1800 case PIPE_FORMAT_X32_S8X24_UINT:
1801 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1802 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1803 result = FMT_X24_8_32_FLOAT;
1804 goto out_word4;
1805 default:
1806 goto out_unknown;
1807 }
1808
1809 case UTIL_FORMAT_COLORSPACE_YUV:
1810 yuv_format |= (1 << 30);
1811 switch (format) {
1812 case PIPE_FORMAT_UYVY:
1813 case PIPE_FORMAT_YUYV:
1814 default:
1815 break;
1816 }
1817 goto out_unknown; /* XXX */
1818
1819 case UTIL_FORMAT_COLORSPACE_SRGB:
1820 word4 |= S_038010_FORCE_DEGAMMA(1);
1821 break;
1822
1823 default:
1824 break;
1825 }
1826
1827 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1828 if (!enable_s3tc)
1829 goto out_unknown;
1830
1831 switch (format) {
1832 case PIPE_FORMAT_RGTC1_SNORM:
1833 case PIPE_FORMAT_LATC1_SNORM:
1834 word4 |= sign_bit[0];
1835 case PIPE_FORMAT_RGTC1_UNORM:
1836 case PIPE_FORMAT_LATC1_UNORM:
1837 result = FMT_BC4;
1838 goto out_word4;
1839 case PIPE_FORMAT_RGTC2_SNORM:
1840 case PIPE_FORMAT_LATC2_SNORM:
1841 word4 |= sign_bit[0] | sign_bit[1];
1842 case PIPE_FORMAT_RGTC2_UNORM:
1843 case PIPE_FORMAT_LATC2_UNORM:
1844 result = FMT_BC5;
1845 goto out_word4;
1846 default:
1847 goto out_unknown;
1848 }
1849 }
1850
1851 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1852
1853 if (!enable_s3tc)
1854 goto out_unknown;
1855
1856 if (!util_format_s3tc_enabled) {
1857 goto out_unknown;
1858 }
1859
1860 switch (format) {
1861 case PIPE_FORMAT_DXT1_RGB:
1862 case PIPE_FORMAT_DXT1_RGBA:
1863 case PIPE_FORMAT_DXT1_SRGB:
1864 case PIPE_FORMAT_DXT1_SRGBA:
1865 result = FMT_BC1;
1866 is_srgb_valid = TRUE;
1867 goto out_word4;
1868 case PIPE_FORMAT_DXT3_RGBA:
1869 case PIPE_FORMAT_DXT3_SRGBA:
1870 result = FMT_BC2;
1871 is_srgb_valid = TRUE;
1872 goto out_word4;
1873 case PIPE_FORMAT_DXT5_RGBA:
1874 case PIPE_FORMAT_DXT5_SRGBA:
1875 result = FMT_BC3;
1876 is_srgb_valid = TRUE;
1877 goto out_word4;
1878 default:
1879 goto out_unknown;
1880 }
1881 }
1882
1883 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1884 switch (format) {
1885 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1886 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1887 result = FMT_GB_GR;
1888 goto out_word4;
1889 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1890 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1891 result = FMT_BG_RG;
1892 goto out_word4;
1893 default:
1894 goto out_unknown;
1895 }
1896 }
1897
1898 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1899 result = FMT_5_9_9_9_SHAREDEXP;
1900 goto out_word4;
1901 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1902 result = FMT_10_11_11_FLOAT;
1903 goto out_word4;
1904 }
1905
1906
1907 for (i = 0; i < desc->nr_channels; i++) {
1908 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1909 word4 |= sign_bit[i];
1910 }
1911 }
1912
1913 /* R8G8Bx_SNORM - XXX CxV8U8 */
1914
1915 /* See whether the components are of the same size. */
1916 for (i = 1; i < desc->nr_channels; i++) {
1917 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1918 }
1919
1920 /* Non-uniform formats. */
1921 if (!uniform) {
1922 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1923 desc->channel[0].pure_integer)
1924 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1925 switch(desc->nr_channels) {
1926 case 3:
1927 if (desc->channel[0].size == 5 &&
1928 desc->channel[1].size == 6 &&
1929 desc->channel[2].size == 5) {
1930 result = FMT_5_6_5;
1931 goto out_word4;
1932 }
1933 goto out_unknown;
1934 case 4:
1935 if (desc->channel[0].size == 5 &&
1936 desc->channel[1].size == 5 &&
1937 desc->channel[2].size == 5 &&
1938 desc->channel[3].size == 1) {
1939 result = FMT_1_5_5_5;
1940 goto out_word4;
1941 }
1942 if (desc->channel[0].size == 10 &&
1943 desc->channel[1].size == 10 &&
1944 desc->channel[2].size == 10 &&
1945 desc->channel[3].size == 2) {
1946 result = FMT_2_10_10_10;
1947 goto out_word4;
1948 }
1949 goto out_unknown;
1950 }
1951 goto out_unknown;
1952 }
1953
1954 /* Find the first non-VOID channel. */
1955 for (i = 0; i < 4; i++) {
1956 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1957 break;
1958 }
1959 }
1960
1961 if (i == 4)
1962 goto out_unknown;
1963
1964 /* uniform formats */
1965 switch (desc->channel[i].type) {
1966 case UTIL_FORMAT_TYPE_UNSIGNED:
1967 case UTIL_FORMAT_TYPE_SIGNED:
1968 #if 0
1969 if (!desc->channel[i].normalized &&
1970 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1971 goto out_unknown;
1972 }
1973 #endif
1974 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1975 desc->channel[i].pure_integer)
1976 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1977
1978 switch (desc->channel[i].size) {
1979 case 4:
1980 switch (desc->nr_channels) {
1981 case 2:
1982 result = FMT_4_4;
1983 goto out_word4;
1984 case 4:
1985 result = FMT_4_4_4_4;
1986 goto out_word4;
1987 }
1988 goto out_unknown;
1989 case 8:
1990 switch (desc->nr_channels) {
1991 case 1:
1992 result = FMT_8;
1993 goto out_word4;
1994 case 2:
1995 result = FMT_8_8;
1996 goto out_word4;
1997 case 4:
1998 result = FMT_8_8_8_8;
1999 is_srgb_valid = TRUE;
2000 goto out_word4;
2001 }
2002 goto out_unknown;
2003 case 16:
2004 switch (desc->nr_channels) {
2005 case 1:
2006 result = FMT_16;
2007 goto out_word4;
2008 case 2:
2009 result = FMT_16_16;
2010 goto out_word4;
2011 case 4:
2012 result = FMT_16_16_16_16;
2013 goto out_word4;
2014 }
2015 goto out_unknown;
2016 case 32:
2017 switch (desc->nr_channels) {
2018 case 1:
2019 result = FMT_32;
2020 goto out_word4;
2021 case 2:
2022 result = FMT_32_32;
2023 goto out_word4;
2024 case 4:
2025 result = FMT_32_32_32_32;
2026 goto out_word4;
2027 }
2028 }
2029 goto out_unknown;
2030
2031 case UTIL_FORMAT_TYPE_FLOAT:
2032 switch (desc->channel[i].size) {
2033 case 16:
2034 switch (desc->nr_channels) {
2035 case 1:
2036 result = FMT_16_FLOAT;
2037 goto out_word4;
2038 case 2:
2039 result = FMT_16_16_FLOAT;
2040 goto out_word4;
2041 case 4:
2042 result = FMT_16_16_16_16_FLOAT;
2043 goto out_word4;
2044 }
2045 goto out_unknown;
2046 case 32:
2047 switch (desc->nr_channels) {
2048 case 1:
2049 result = FMT_32_FLOAT;
2050 goto out_word4;
2051 case 2:
2052 result = FMT_32_32_FLOAT;
2053 goto out_word4;
2054 case 4:
2055 result = FMT_32_32_32_32_FLOAT;
2056 goto out_word4;
2057 }
2058 }
2059 goto out_unknown;
2060 }
2061
2062 out_word4:
2063
2064 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2065 return ~0;
2066 if (word4_p)
2067 *word4_p = word4;
2068 if (yuv_format_p)
2069 *yuv_format_p = yuv_format;
2070 return result;
2071 out_unknown:
2072 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2073 return ~0;
2074 }
2075
2076 /* keep this at the end of this file, please */
2077 void r600_init_common_state_functions(struct r600_context *rctx)
2078 {
2079 rctx->b.b.create_fs_state = r600_create_ps_state;
2080 rctx->b.b.create_vs_state = r600_create_vs_state;
2081 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2082 rctx->b.b.bind_blend_state = r600_bind_blend_state;
2083 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2084 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2085 rctx->b.b.bind_fs_state = r600_bind_ps_state;
2086 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2087 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2088 rctx->b.b.bind_vs_state = r600_bind_vs_state;
2089 rctx->b.b.delete_blend_state = r600_delete_blend_state;
2090 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2091 rctx->b.b.delete_fs_state = r600_delete_ps_state;
2092 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2093 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2094 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2095 rctx->b.b.delete_vs_state = r600_delete_vs_state;
2096 rctx->b.b.set_blend_color = r600_set_blend_color;
2097 rctx->b.b.set_clip_state = r600_set_clip_state;
2098 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2099 rctx->b.b.set_sample_mask = r600_set_sample_mask;
2100 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2101 rctx->b.b.set_viewport_states = r600_set_viewport_states;
2102 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2103 rctx->b.b.set_index_buffer = r600_set_index_buffer;
2104 rctx->b.b.set_fragment_sampler_views = r600_set_ps_sampler_views;
2105 rctx->b.b.set_vertex_sampler_views = r600_set_vs_sampler_views;
2106 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2107 rctx->b.b.texture_barrier = r600_texture_barrier;
2108 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2109 rctx->b.b.create_surface = r600_create_surface;
2110 rctx->b.b.surface_destroy = r600_surface_destroy;
2111 rctx->b.b.draw_vbo = r600_draw_vbo;
2112 }
2113
2114 void r600_trace_emit(struct r600_context *rctx)
2115 {
2116 struct r600_screen *rscreen = rctx->screen;
2117 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2118 uint64_t va;
2119 uint32_t reloc;
2120
2121 va = r600_resource_va(&rscreen->b.b, (void*)rscreen->trace_bo);
2122 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
2123 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2124 radeon_emit(cs, va & 0xFFFFFFFFUL);
2125 radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2126 radeon_emit(cs, cs->cdw);
2127 radeon_emit(cs, rscreen->cs_count);
2128 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2129 radeon_emit(cs, reloc);
2130 }