2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
37 struct radeon_winsys_cs
*cs
= rctx
->cs
;
38 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
40 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
41 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
42 cs
->cdw
+= cb
->atom
.num_dw
;
45 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
)
47 cb
->atom
.emit
= r600_emit_command_buffer
;
49 cb
->atom
.flags
= flags
;
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 static void r600_emit_surface_sync(struct r600_context
*rctx
, struct r600_atom
*atom
)
61 struct radeon_winsys_cs
*cs
= rctx
->cs
;
62 struct r600_surface_sync_cmd
*a
= (struct r600_surface_sync_cmd
*)atom
;
64 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SURFACE_SYNC
, 3, 0);
65 cs
->buf
[cs
->cdw
++] = a
->flush_flags
; /* CP_COHER_CNTL */
66 cs
->buf
[cs
->cdw
++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs
->buf
[cs
->cdw
++] = 0; /* CP_COHER_BASE */
68 cs
->buf
[cs
->cdw
++] = 0x0000000A; /* POLL_INTERVAL */
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context
*rctx
, struct r600_atom
*atom
)
75 struct radeon_winsys_cs
*cs
= rctx
->cs
;
76 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
77 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0);
80 void r600_init_atom(struct r600_atom
*atom
,
81 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
82 unsigned num_dw
, enum r600_atom_flags flags
)
85 atom
->num_dw
= num_dw
;
89 static void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
91 struct radeon_winsys_cs
*cs
= rctx
->cs
;
92 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
93 unsigned alpha_ref
= a
->sx_alpha_ref
;
95 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
99 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
100 a
->sx_alpha_test_control
|
101 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
102 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
105 void r600_init_common_atoms(struct r600_context
*rctx
)
107 r600_init_atom(&rctx
->surface_sync_cmd
.atom
, r600_emit_surface_sync
, 5, EMIT_EARLY
);
108 r600_init_atom(&rctx
->r6xx_flush_and_inv_cmd
, r600_emit_r6xx_flush_and_inv
, 2, EMIT_EARLY
);
109 r600_init_atom(&rctx
->alphatest_state
.atom
, r600_emit_alphatest_state
, 3, 0);
110 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
113 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
)
117 if (rctx
->framebuffer
.nr_cbufs
) {
118 flags
|= S_0085F0_CB_ACTION_ENA(1) |
119 (((1 << rctx
->framebuffer
.nr_cbufs
) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT
);
122 /* Workaround for broken flushing on some R6xx chipsets. */
123 if (rctx
->family
== CHIP_RV670
||
124 rctx
->family
== CHIP_RS780
||
125 rctx
->family
== CHIP_RS880
) {
126 flags
|= S_0085F0_CB1_DEST_BASE_ENA(1) |
127 S_0085F0_DEST_BASE_0_ENA(1);
132 void r600_texture_barrier(struct pipe_context
*ctx
)
134 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
136 rctx
->surface_sync_cmd
.flush_flags
|= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx
);
137 r600_atom_dirty(rctx
, &rctx
->surface_sync_cmd
.atom
);
140 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
142 static const int prim_conv
[] = {
143 V_008958_DI_PT_POINTLIST
,
144 V_008958_DI_PT_LINELIST
,
145 V_008958_DI_PT_LINELOOP
,
146 V_008958_DI_PT_LINESTRIP
,
147 V_008958_DI_PT_TRILIST
,
148 V_008958_DI_PT_TRISTRIP
,
149 V_008958_DI_PT_TRIFAN
,
150 V_008958_DI_PT_QUADLIST
,
151 V_008958_DI_PT_QUADSTRIP
,
152 V_008958_DI_PT_POLYGON
,
159 *prim
= prim_conv
[pprim
];
161 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
167 /* common state between evergreen and r600 */
168 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
170 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
171 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
172 struct r600_pipe_state
*rstate
;
173 bool update_cb
= false;
177 rstate
= &blend
->rstate
;
178 rctx
->states
[rstate
->id
] = rstate
;
179 rctx
->dual_src_blend
= blend
->dual_src_blend
;
180 r600_context_pipe_state_set(rctx
, rstate
);
182 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
183 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
186 if (rctx
->chip_class
<= R700
&&
187 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
188 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
191 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
192 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
196 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
200 void r600_set_blend_color(struct pipe_context
*ctx
,
201 const struct pipe_blend_color
*state
)
203 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
204 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
209 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
210 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
211 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
212 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
213 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
215 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
216 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
217 r600_context_pipe_state_set(rctx
, rstate
);
220 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
221 const struct r600_stencil_ref
*state
)
223 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
224 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
229 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
230 r600_pipe_state_add_reg(rstate
,
231 R_028430_DB_STENCILREFMASK
,
232 S_028430_STENCILREF(state
->ref_value
[0]) |
233 S_028430_STENCILMASK(state
->valuemask
[0]) |
234 S_028430_STENCILWRITEMASK(state
->writemask
[0]));
235 r600_pipe_state_add_reg(rstate
,
236 R_028434_DB_STENCILREFMASK_BF
,
237 S_028434_STENCILREF_BF(state
->ref_value
[1]) |
238 S_028434_STENCILMASK_BF(state
->valuemask
[1]) |
239 S_028434_STENCILWRITEMASK_BF(state
->writemask
[1]));
241 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
242 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
243 r600_context_pipe_state_set(rctx
, rstate
);
246 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
247 const struct pipe_stencil_ref
*state
)
249 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
250 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
251 struct r600_stencil_ref ref
;
253 rctx
->stencil_ref
= *state
;
258 ref
.ref_value
[0] = state
->ref_value
[0];
259 ref
.ref_value
[1] = state
->ref_value
[1];
260 ref
.valuemask
[0] = dsa
->valuemask
[0];
261 ref
.valuemask
[1] = dsa
->valuemask
[1];
262 ref
.writemask
[0] = dsa
->writemask
[0];
263 ref
.writemask
[1] = dsa
->writemask
[1];
265 r600_set_stencil_ref(ctx
, &ref
);
268 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
270 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
271 struct r600_pipe_dsa
*dsa
= state
;
272 struct r600_pipe_state
*rstate
;
273 struct r600_stencil_ref ref
;
277 rstate
= &dsa
->rstate
;
278 rctx
->states
[rstate
->id
] = rstate
;
279 r600_context_pipe_state_set(rctx
, rstate
);
281 ref
.ref_value
[0] = rctx
->stencil_ref
.ref_value
[0];
282 ref
.ref_value
[1] = rctx
->stencil_ref
.ref_value
[1];
283 ref
.valuemask
[0] = dsa
->valuemask
[0];
284 ref
.valuemask
[1] = dsa
->valuemask
[1];
285 ref
.writemask
[0] = dsa
->writemask
[0];
286 ref
.writemask
[1] = dsa
->writemask
[1];
288 r600_set_stencil_ref(ctx
, &ref
);
290 /* Update alphatest state. */
291 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
292 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
293 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
294 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
295 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
299 void r600_set_max_scissor(struct r600_context
*rctx
)
301 /* Set a scissor state such that it doesn't do anything. */
302 struct pipe_scissor_state scissor
;
308 r600_set_scissor_state(rctx
, &scissor
);
311 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
313 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
314 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
319 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
320 rctx
->two_side
= rs
->two_side
;
321 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
322 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
324 rctx
->rasterizer
= rs
;
326 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
327 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
329 if (rctx
->chip_class
>= EVERGREEN
) {
330 evergreen_polygon_offset_update(rctx
);
332 r600_polygon_offset_update(rctx
);
335 /* Workaround for a missing scissor enable on r600. */
336 if (rctx
->chip_class
== R600
) {
337 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
338 rctx
->scissor_enable
= rs
->scissor_enable
;
340 if (rs
->scissor_enable
) {
341 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
343 r600_set_max_scissor(rctx
);
349 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
351 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
352 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
354 if (rctx
->rasterizer
== rs
) {
355 rctx
->rasterizer
= NULL
;
357 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
358 rctx
->states
[rs
->rstate
.id
] = NULL
;
363 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
364 struct pipe_sampler_view
*state
)
366 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
368 pipe_resource_reference(&state
->texture
, NULL
);
372 static void r600_bind_samplers(struct r600_context
*rctx
,
373 struct r600_textures_info
*dst
,
374 unsigned count
, void **states
)
376 int seamless_cube_map
= -1;
379 memcpy(dst
->samplers
, states
, sizeof(void*) * count
);
380 dst
->n_samplers
= count
;
381 dst
->atom_sampler
.num_dw
= 0;
383 for (i
= 0; i
< count
; i
++) {
384 struct r600_pipe_sampler_state
*sampler
= states
[i
];
386 if (sampler
== NULL
) {
389 if (sampler
->border_color_use
) {
390 dst
->atom_sampler
.num_dw
+= 11;
391 rctx
->flags
|= R600_PARTIAL_FLUSH
;
393 dst
->atom_sampler
.num_dw
+= 5;
395 seamless_cube_map
= sampler
->seamless_cube_map
;
397 if (rctx
->chip_class
<= R700
&& seamless_cube_map
!= -1 && seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
398 /* change in TA_CNTL_AUX need a pipeline flush */
399 rctx
->flags
|= R600_PARTIAL_FLUSH
;
400 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
401 r600_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
403 if (dst
->atom_sampler
.num_dw
) {
404 r600_atom_dirty(rctx
, &dst
->atom_sampler
);
408 void r600_bind_vs_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
)
410 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
411 r600_bind_samplers(rctx
, &rctx
->vs_samplers
, count
, states
);
414 void r600_bind_ps_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
)
416 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
417 r600_bind_samplers(rctx
, &rctx
->ps_samplers
, count
, states
);
420 void r600_delete_sampler(struct pipe_context
*ctx
, void *state
)
425 void r600_delete_state(struct pipe_context
*ctx
, void *state
)
427 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
428 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
430 if (rctx
->states
[rstate
->id
] == rstate
) {
431 rctx
->states
[rstate
->id
] = NULL
;
433 for (int i
= 0; i
< rstate
->nregs
; i
++) {
434 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
439 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
441 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
442 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
444 rctx
->vertex_elements
= v
;
446 r600_inval_shader_cache(rctx
);
448 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
449 r600_context_pipe_state_set(rctx
, &v
->rstate
);
453 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
455 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
456 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
458 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
459 rctx
->states
[v
->rstate
.id
] = NULL
;
461 if (rctx
->vertex_elements
== state
)
462 rctx
->vertex_elements
= NULL
;
464 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
468 void r600_set_index_buffer(struct pipe_context
*ctx
,
469 const struct pipe_index_buffer
*ib
)
471 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
474 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
475 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
477 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
481 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
483 if (rctx
->vertex_buffer_state
.dirty_mask
) {
484 r600_inval_vertex_cache(rctx
);
485 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
486 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
487 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
491 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
492 const struct pipe_vertex_buffer
*input
)
494 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
495 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
496 struct pipe_vertex_buffer
*vb
= state
->vb
;
498 /* This sets 1-bit for buffers with index >= count. */
499 uint32_t disable_mask
= ~((1ull << count
) - 1);
500 /* These are the new buffers set by this function. */
501 uint32_t new_buffer_mask
= 0;
503 /* Set buffers with index >= count to NULL. */
504 uint32_t remaining_buffers_mask
=
505 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
507 while (remaining_buffers_mask
) {
508 i
= u_bit_scan(&remaining_buffers_mask
);
509 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
512 /* Set vertex buffers. */
513 for (i
= 0; i
< count
; i
++) {
514 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
515 if (input
[i
].buffer
) {
516 vb
[i
].stride
= input
[i
].stride
;
517 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
518 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
519 new_buffer_mask
|= 1 << i
;
521 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
522 disable_mask
|= 1 << i
;
527 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
528 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
529 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
530 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
532 r600_vertex_buffers_dirty(rctx
);
535 void r600_sampler_views_dirty(struct r600_context
*rctx
,
536 struct r600_samplerview_state
*state
)
538 if (state
->dirty_mask
) {
539 r600_inval_texture_cache(rctx
);
540 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
541 util_bitcount(state
->dirty_mask
);
542 r600_atom_dirty(rctx
, &state
->atom
);
546 void r600_set_sampler_views(struct r600_context
*rctx
,
547 struct r600_textures_info
*dst
,
549 struct pipe_sampler_view
**views
)
551 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
553 /* This sets 1-bit for textures with index >= count. */
554 uint32_t disable_mask
= ~((1ull << count
) - 1);
555 /* These are the new textures set by this function. */
556 uint32_t new_mask
= 0;
558 /* Set textures with index >= count to NULL. */
559 uint32_t remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
561 while (remaining_mask
) {
562 i
= u_bit_scan(&remaining_mask
);
563 assert(dst
->views
.views
[i
]);
565 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
568 for (i
= 0; i
< count
; i
++) {
569 if (rviews
[i
] == dst
->views
.views
[i
]) {
574 struct r600_resource_texture
*rtex
=
575 (struct r600_resource_texture
*)rviews
[i
]->base
.texture
;
577 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
578 dst
->views
.depth_texture_mask
|= 1 << i
;
580 dst
->views
.depth_texture_mask
&= ~(1 << i
);
583 /* Changing from array to non-arrays textures and vice
584 * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */
585 if (rctx
->chip_class
<= R700
&&
586 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
587 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
588 r600_atom_dirty(rctx
, &dst
->atom_sampler
);
591 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
594 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
595 disable_mask
|= 1 << i
;
599 dst
->views
.enabled_mask
&= ~disable_mask
;
600 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
601 dst
->views
.enabled_mask
|= new_mask
;
602 dst
->views
.dirty_mask
|= new_mask
;
603 dst
->views
.depth_texture_mask
&= dst
->views
.enabled_mask
;
605 r600_sampler_views_dirty(rctx
, &dst
->views
);
608 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
610 const struct pipe_vertex_element
*elements
)
612 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
613 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
620 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
622 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
630 /* Compute the key for the hw shader variant */
631 static INLINE
unsigned r600_shader_selector_key(struct pipe_context
* ctx
,
632 struct r600_pipe_shader_selector
* sel
)
634 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
637 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
638 key
= rctx
->two_side
|
639 MIN2(sel
->nr_ps_max_color_exports
, rctx
->nr_cbufs
+ rctx
->dual_src_blend
) << 1;
646 /* Select the hw shader variant depending on the current state.
647 * (*dirty) is set to 1 if current variant was changed */
648 static int r600_shader_select(struct pipe_context
*ctx
,
649 struct r600_pipe_shader_selector
* sel
,
653 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
654 struct r600_pipe_shader
* shader
= NULL
;
657 key
= r600_shader_selector_key(ctx
, sel
);
659 /* Check if we don't need to change anything.
660 * This path is also used for most shaders that don't need multiple
661 * variants, it will cost just a computation of the key and this
663 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
667 /* lookup if we have other variants in the list */
668 if (sel
->num_shaders
> 1) {
669 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
671 while (c
&& c
->key
!= key
) {
677 p
->next_variant
= c
->next_variant
;
682 if (unlikely(!shader
)) {
683 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
684 shader
->selector
= sel
;
686 r
= r600_pipe_shader_create(ctx
, shader
);
688 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
694 /* We don't know the value of nr_ps_max_color_exports until we built
695 * at least one variant, so we may need to recompute the key after
696 * building first variant. */
697 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
698 sel
->num_shaders
== 0) {
699 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
700 key
= r600_shader_selector_key(ctx
, sel
);
710 shader
->next_variant
= sel
->current
;
711 sel
->current
= shader
;
713 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
714 r600_adjust_gprs(rctx
);
717 if (rctx
->ps_shader
&&
718 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
719 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
720 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
725 static void *r600_create_shader_state(struct pipe_context
*ctx
,
726 const struct pipe_shader_state
*state
,
727 unsigned pipe_shader_type
)
729 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
732 sel
->type
= pipe_shader_type
;
733 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
734 sel
->so
= state
->stream_output
;
736 r
= r600_shader_select(ctx
, sel
, NULL
);
743 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
744 const struct pipe_shader_state
*state
)
746 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
749 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
750 const struct pipe_shader_state
*state
)
752 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
755 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
757 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
760 state
= rctx
->dummy_pixel_shader
;
762 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
763 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
765 if (rctx
->chip_class
<= R700
) {
766 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
768 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
769 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
770 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
774 r600_adjust_gprs(rctx
);
777 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
778 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
779 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
783 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
785 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
787 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
789 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
791 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
792 r600_adjust_gprs(rctx
);
796 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
797 struct r600_pipe_shader_selector
*sel
)
799 struct r600_pipe_shader
*p
= sel
->current
, *c
;
802 r600_pipe_shader_destroy(ctx
, p
);
812 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
814 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
815 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
817 if (rctx
->ps_shader
== sel
) {
818 rctx
->ps_shader
= NULL
;
821 r600_delete_shader_selector(ctx
, sel
);
824 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
826 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
827 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
829 if (rctx
->vs_shader
== sel
) {
830 rctx
->vs_shader
= NULL
;
833 r600_delete_shader_selector(ctx
, sel
);
836 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
838 if (state
->dirty_mask
) {
839 r600_inval_shader_cache(rctx
);
840 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
841 : util_bitcount(state
->dirty_mask
)*19;
842 r600_atom_dirty(rctx
, &state
->atom
);
846 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
847 struct pipe_constant_buffer
*input
)
849 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
850 struct r600_constbuf_state
*state
;
851 struct pipe_constant_buffer
*cb
;
855 case PIPE_SHADER_VERTEX
:
856 state
= &rctx
->vs_constbuf_state
;
858 case PIPE_SHADER_FRAGMENT
:
859 state
= &rctx
->ps_constbuf_state
;
865 /* Note that the state tracker can unbind constant buffers by
868 if (unlikely(!input
)) {
869 state
->enabled_mask
&= ~(1 << index
);
870 state
->dirty_mask
&= ~(1 << index
);
871 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
875 cb
= &state
->cb
[index
];
876 cb
->buffer_size
= input
->buffer_size
;
878 ptr
= input
->user_buffer
;
881 /* Upload the user buffer. */
882 if (R600_BIG_ENDIAN
) {
884 unsigned i
, size
= input
->buffer_size
;
886 if (!(tmpPtr
= malloc(size
))) {
887 R600_ERR("Failed to allocate BE swap buffer.\n");
891 for (i
= 0; i
< size
/ 4; ++i
) {
892 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
895 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
898 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
901 /* Setup the hw buffer. */
902 cb
->buffer_offset
= input
->buffer_offset
;
903 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
906 state
->enabled_mask
|= 1 << index
;
907 state
->dirty_mask
|= 1 << index
;
908 r600_constant_buffers_dirty(rctx
, state
);
911 struct pipe_stream_output_target
*
912 r600_create_so_target(struct pipe_context
*ctx
,
913 struct pipe_resource
*buffer
,
914 unsigned buffer_offset
,
915 unsigned buffer_size
)
917 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
918 struct r600_so_target
*t
;
921 t
= CALLOC_STRUCT(r600_so_target
);
926 t
->b
.reference
.count
= 1;
928 pipe_resource_reference(&t
->b
.buffer
, buffer
);
929 t
->b
.buffer_offset
= buffer_offset
;
930 t
->b
.buffer_size
= buffer_size
;
932 t
->filled_size
= (struct r600_resource
*)
933 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
934 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
935 memset(ptr
, 0, t
->filled_size
->buf
->size
);
936 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
941 void r600_so_target_destroy(struct pipe_context
*ctx
,
942 struct pipe_stream_output_target
*target
)
944 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
945 pipe_resource_reference(&t
->b
.buffer
, NULL
);
946 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
950 void r600_set_so_targets(struct pipe_context
*ctx
,
951 unsigned num_targets
,
952 struct pipe_stream_output_target
**targets
,
953 unsigned append_bitmask
)
955 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
958 /* Stop streamout. */
959 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
960 r600_context_streamout_end(rctx
);
963 /* Set the new targets. */
964 for (i
= 0; i
< num_targets
; i
++) {
965 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
967 for (; i
< rctx
->num_so_targets
; i
++) {
968 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
971 rctx
->num_so_targets
= num_targets
;
972 rctx
->streamout_start
= num_targets
!= 0;
973 rctx
->streamout_append_bitmask
= append_bitmask
;
976 static void r600_update_derived_state(struct r600_context
*rctx
)
978 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
979 unsigned ps_dirty
= 0;
981 if (!rctx
->blitter
->running
) {
982 /* Flush depth textures which need to be flushed. */
983 if (rctx
->vs_samplers
.views
.depth_texture_mask
) {
984 r600_flush_depth_textures(rctx
, &rctx
->vs_samplers
.views
);
986 if (rctx
->ps_samplers
.views
.depth_texture_mask
) {
987 r600_flush_depth_textures(rctx
, &rctx
->ps_samplers
.views
);
991 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
993 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
994 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
995 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
997 if (rctx
->chip_class
>= EVERGREEN
)
998 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1000 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1006 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1008 if (rctx
->chip_class
>= EVERGREEN
) {
1009 evergreen_update_dual_export_state(rctx
);
1011 r600_update_dual_export_state(rctx
);
1015 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1017 static const int prim_conv
[] = {
1018 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1019 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1020 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1021 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1022 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1023 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1024 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1025 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1026 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1027 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1028 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1029 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1030 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1031 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1033 assert(mode
< Elements(prim_conv
));
1035 return prim_conv
[mode
];
1038 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1040 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1041 struct pipe_draw_info info
= *dinfo
;
1042 struct pipe_index_buffer ib
= {};
1043 unsigned prim
, ls_mask
= 0;
1044 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1045 struct r600_atom
*state
= NULL
, *next_state
= NULL
;
1046 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1050 if ((!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) ||
1051 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
1056 if (!rctx
->vs_shader
) {
1061 r600_update_derived_state(rctx
);
1063 /* partial flush triggered by border color change */
1064 if (rctx
->flags
& R600_PARTIAL_FLUSH
) {
1065 rctx
->flags
&= ~R600_PARTIAL_FLUSH
;
1066 r600_write_value(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1067 r600_write_value(cs
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1071 /* Initialize the index buffer struct. */
1072 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1073 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1074 ib
.index_size
= rctx
->index_buffer
.index_size
;
1075 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1077 /* Translate or upload, if needed. */
1078 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1080 ptr
= (uint8_t*)ib
.user_buffer
;
1081 if (!ib
.buffer
&& ptr
) {
1082 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1083 ptr
, &ib
.offset
, &ib
.buffer
);
1086 info
.index_bias
= info
.start
;
1089 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
1090 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
1091 rctx
->vgt
.nregs
= 0;
1092 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
1093 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0);
1094 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
);
1095 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
);
1096 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
);
1097 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1098 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A0C_PA_SC_LINE_STIPPLE
, 0);
1099 r600_pipe_state_add_reg(&rctx
->vgt
, R_02881C_PA_CL_VS_OUT_CNTL
, 0);
1100 r600_pipe_state_add_reg(&rctx
->vgt
, R_028810_PA_CL_CLIP_CNTL
, 0);
1103 rctx
->vgt
.nregs
= 0;
1104 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
1105 r600_pipe_state_mod_reg(&rctx
->vgt
, r600_conv_prim_to_gs_out(info
.mode
));
1106 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
1107 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
1108 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
1109 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
1111 if (prim
== V_008958_DI_PT_LINELIST
)
1113 else if (prim
== V_008958_DI_PT_LINESTRIP
||
1114 prim
== V_008958_DI_PT_LINELOOP
)
1116 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
1117 r600_pipe_state_mod_reg(&rctx
->vgt
,
1118 rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
|
1119 (rctx
->rasterizer
->clip_plane_enable
& rctx
->vs_shader
->current
->shader
.clip_dist_write
));
1120 r600_pipe_state_mod_reg(&rctx
->vgt
,
1121 rctx
->pa_cl_clip_cntl
|
1122 (rctx
->vs_shader
->current
->shader
.clip_dist_write
||
1123 rctx
->vs_shader
->current
->shader
.vs_prohibit_ucps
?
1124 0 : rctx
->rasterizer
->clip_plane_enable
& 0x3F));
1126 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
1128 /* Enable stream out if needed. */
1129 if (rctx
->streamout_start
) {
1130 r600_context_streamout_begin(rctx
);
1131 rctx
->streamout_start
= FALSE
;
1134 /* Emit states (the function expects that we emit at most 17 dwords here). */
1135 r600_need_cs_space(rctx
, 0, TRUE
);
1137 LIST_FOR_EACH_ENTRY_SAFE(state
, next_state
, &rctx
->dirty_states
, head
) {
1138 r600_emit_atom(rctx
, state
);
1140 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1141 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1143 rctx
->pm4_dirty_cdwords
= 0;
1146 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1147 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1149 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1150 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1151 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1152 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1154 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1156 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1157 cs
->buf
[cs
->cdw
++] = va
;
1158 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1159 cs
->buf
[cs
->cdw
++] = info
.count
;
1160 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1161 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1162 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1164 if (info
.count_from_stream_output
) {
1165 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1166 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1168 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1170 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1171 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1172 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1173 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1174 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1175 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1177 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1178 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1181 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1182 cs
->buf
[cs
->cdw
++] = info
.count
;
1183 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1184 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1187 rctx
->flags
|= R600_CONTEXT_DST_CACHES_DIRTY
| R600_CONTEXT_DRAW_PENDING
;
1189 /* Set the depth buffer as dirty. */
1190 if (rctx
->framebuffer
.zsbuf
) {
1191 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
1192 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)surf
->texture
;
1194 rtex
->dirty_db_mask
|= 1 << surf
->u
.tex
.level
;
1197 pipe_resource_reference(&ib
.buffer
, NULL
);
1200 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1201 struct r600_pipe_state
*state
,
1202 uint32_t offset
, uint32_t value
,
1203 uint32_t range_id
, uint32_t block_id
,
1204 struct r600_resource
*bo
,
1205 enum radeon_bo_usage usage
)
1208 struct r600_range
*range
;
1209 struct r600_block
*block
;
1211 if (bo
) assert(usage
);
1213 range
= &ctx
->range
[range_id
];
1214 block
= range
->blocks
[block_id
];
1215 state
->regs
[state
->nregs
].block
= block
;
1216 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1218 state
->regs
[state
->nregs
].value
= value
;
1219 state
->regs
[state
->nregs
].bo
= bo
;
1220 state
->regs
[state
->nregs
].bo_usage
= usage
;
1223 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1226 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1227 struct r600_pipe_state
*state
,
1228 uint32_t offset
, uint32_t value
,
1229 uint32_t range_id
, uint32_t block_id
)
1231 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1232 range_id
, block_id
, NULL
, 0);
1235 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state
*state
,
1236 uint32_t offset
, uint32_t value
,
1237 struct r600_resource
*bo
,
1238 enum radeon_bo_usage usage
)
1240 if (bo
) assert(usage
);
1242 state
->regs
[state
->nregs
].id
= offset
;
1243 state
->regs
[state
->nregs
].block
= NULL
;
1244 state
->regs
[state
->nregs
].value
= value
;
1245 state
->regs
[state
->nregs
].bo
= bo
;
1246 state
->regs
[state
->nregs
].bo_usage
= usage
;
1249 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1252 uint32_t r600_translate_stencil_op(int s_op
)
1255 case PIPE_STENCIL_OP_KEEP
:
1256 return V_028800_STENCIL_KEEP
;
1257 case PIPE_STENCIL_OP_ZERO
:
1258 return V_028800_STENCIL_ZERO
;
1259 case PIPE_STENCIL_OP_REPLACE
:
1260 return V_028800_STENCIL_REPLACE
;
1261 case PIPE_STENCIL_OP_INCR
:
1262 return V_028800_STENCIL_INCR
;
1263 case PIPE_STENCIL_OP_DECR
:
1264 return V_028800_STENCIL_DECR
;
1265 case PIPE_STENCIL_OP_INCR_WRAP
:
1266 return V_028800_STENCIL_INCR_WRAP
;
1267 case PIPE_STENCIL_OP_DECR_WRAP
:
1268 return V_028800_STENCIL_DECR_WRAP
;
1269 case PIPE_STENCIL_OP_INVERT
:
1270 return V_028800_STENCIL_INVERT
;
1272 R600_ERR("Unknown stencil op %d", s_op
);
1279 uint32_t r600_translate_fill(uint32_t func
)
1282 case PIPE_POLYGON_MODE_FILL
:
1284 case PIPE_POLYGON_MODE_LINE
:
1286 case PIPE_POLYGON_MODE_POINT
:
1294 unsigned r600_tex_wrap(unsigned wrap
)
1298 case PIPE_TEX_WRAP_REPEAT
:
1299 return V_03C000_SQ_TEX_WRAP
;
1300 case PIPE_TEX_WRAP_CLAMP
:
1301 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1302 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1303 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1304 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1305 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1306 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1307 return V_03C000_SQ_TEX_MIRROR
;
1308 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1309 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1310 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1311 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1312 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1313 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1317 unsigned r600_tex_filter(unsigned filter
)
1321 case PIPE_TEX_FILTER_NEAREST
:
1322 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1323 case PIPE_TEX_FILTER_LINEAR
:
1324 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1328 unsigned r600_tex_mipfilter(unsigned filter
)
1331 case PIPE_TEX_MIPFILTER_NEAREST
:
1332 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1333 case PIPE_TEX_MIPFILTER_LINEAR
:
1334 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1336 case PIPE_TEX_MIPFILTER_NONE
:
1337 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1341 unsigned r600_tex_compare(unsigned compare
)
1345 case PIPE_FUNC_NEVER
:
1346 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1347 case PIPE_FUNC_LESS
:
1348 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1349 case PIPE_FUNC_EQUAL
:
1350 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1351 case PIPE_FUNC_LEQUAL
:
1352 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1353 case PIPE_FUNC_GREATER
:
1354 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1355 case PIPE_FUNC_NOTEQUAL
:
1356 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1357 case PIPE_FUNC_GEQUAL
:
1358 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1359 case PIPE_FUNC_ALWAYS
:
1360 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;