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u_vbuf: override set_index_buffer
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_blitter.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
33 #include <byteswap.h>
34
35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
36 {
37 struct radeon_winsys_cs *cs = rctx->cs;
38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
39
40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
42 cs->cdw += cb->atom.num_dw;
43 }
44
45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
46 {
47 cb->atom.emit = r600_emit_command_buffer;
48 cb->atom.num_dw = 0;
49 cb->atom.flags = flags;
50 cb->buf = CALLOC(1, 4 * num_dw);
51 cb->max_num_dw = num_dw;
52 }
53
54 void r600_release_command_buffer(struct r600_command_buffer *cb)
55 {
56 FREE(cb->buf);
57 }
58
59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
60 {
61 struct radeon_winsys_cs *cs = rctx->cs;
62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
63
64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
69
70 a->flush_flags = 0;
71 }
72
73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
74 {
75 struct radeon_winsys_cs *cs = rctx->cs;
76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
78 }
79
80 void r600_init_atom(struct r600_atom *atom,
81 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
82 unsigned num_dw, enum r600_atom_flags flags)
83 {
84 atom->emit = emit;
85 atom->num_dw = num_dw;
86 atom->flags = flags;
87 }
88
89 void r600_init_common_atoms(struct r600_context *rctx)
90 {
91 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
92 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
93 }
94
95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
96 {
97 unsigned flags = 0;
98
99 if (rctx->framebuffer.nr_cbufs) {
100 flags |= S_0085F0_CB_ACTION_ENA(1) |
101 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
102 }
103
104 /* Workaround for broken flushing on some R6xx chipsets. */
105 if (rctx->family == CHIP_RV670 ||
106 rctx->family == CHIP_RS780 ||
107 rctx->family == CHIP_RS880) {
108 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
109 S_0085F0_DEST_BASE_0_ENA(1);
110 }
111 return flags;
112 }
113
114 void r600_texture_barrier(struct pipe_context *ctx)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117
118 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
119 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
120 }
121
122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
123 {
124 static const int prim_conv[] = {
125 V_008958_DI_PT_POINTLIST,
126 V_008958_DI_PT_LINELIST,
127 V_008958_DI_PT_LINELOOP,
128 V_008958_DI_PT_LINESTRIP,
129 V_008958_DI_PT_TRILIST,
130 V_008958_DI_PT_TRISTRIP,
131 V_008958_DI_PT_TRIFAN,
132 V_008958_DI_PT_QUADLIST,
133 V_008958_DI_PT_QUADSTRIP,
134 V_008958_DI_PT_POLYGON,
135 -1,
136 -1,
137 -1,
138 -1
139 };
140
141 *prim = prim_conv[pprim];
142 if (*prim == -1) {
143 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
144 return false;
145 }
146 return true;
147 }
148
149 /* common state between evergreen and r600 */
150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
151 {
152 struct r600_context *rctx = (struct r600_context *)ctx;
153 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
154 struct r600_pipe_state *rstate;
155
156 if (state == NULL)
157 return;
158 rstate = &blend->rstate;
159 rctx->states[rstate->id] = rstate;
160 rctx->cb_target_mask = blend->cb_target_mask;
161 /* Replace every bit except MULTIWRITE_ENABLE. */
162 rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
163 rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
164 rctx->dual_src_blend = blend->dual_src_blend;
165 r600_context_pipe_state_set(rctx, rstate);
166 }
167
168 void r600_set_blend_color(struct pipe_context *ctx,
169 const struct pipe_blend_color *state)
170 {
171 struct r600_context *rctx = (struct r600_context *)ctx;
172 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
173
174 if (rstate == NULL)
175 return;
176
177 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
178 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
179 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
180 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
181 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
182
183 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
184 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
185 r600_context_pipe_state_set(rctx, rstate);
186 }
187
188 static void r600_set_stencil_ref(struct pipe_context *ctx,
189 const struct r600_stencil_ref *state)
190 {
191 struct r600_context *rctx = (struct r600_context *)ctx;
192 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
193
194 if (rstate == NULL)
195 return;
196
197 rstate->id = R600_PIPE_STATE_STENCIL_REF;
198 r600_pipe_state_add_reg(rstate,
199 R_028430_DB_STENCILREFMASK,
200 S_028430_STENCILREF(state->ref_value[0]) |
201 S_028430_STENCILMASK(state->valuemask[0]) |
202 S_028430_STENCILWRITEMASK(state->writemask[0]));
203 r600_pipe_state_add_reg(rstate,
204 R_028434_DB_STENCILREFMASK_BF,
205 S_028434_STENCILREF_BF(state->ref_value[1]) |
206 S_028434_STENCILMASK_BF(state->valuemask[1]) |
207 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
208
209 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
210 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
211 r600_context_pipe_state_set(rctx, rstate);
212 }
213
214 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
215 const struct pipe_stencil_ref *state)
216 {
217 struct r600_context *rctx = (struct r600_context *)ctx;
218 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
219 struct r600_stencil_ref ref;
220
221 rctx->stencil_ref = *state;
222
223 if (!dsa)
224 return;
225
226 ref.ref_value[0] = state->ref_value[0];
227 ref.ref_value[1] = state->ref_value[1];
228 ref.valuemask[0] = dsa->valuemask[0];
229 ref.valuemask[1] = dsa->valuemask[1];
230 ref.writemask[0] = dsa->writemask[0];
231 ref.writemask[1] = dsa->writemask[1];
232
233 r600_set_stencil_ref(ctx, &ref);
234 }
235
236 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
237 {
238 struct r600_context *rctx = (struct r600_context *)ctx;
239 struct r600_pipe_dsa *dsa = state;
240 struct r600_pipe_state *rstate;
241 struct r600_stencil_ref ref;
242
243 if (state == NULL)
244 return;
245 rstate = &dsa->rstate;
246 rctx->states[rstate->id] = rstate;
247 rctx->alpha_ref = dsa->alpha_ref;
248 rctx->alpha_ref_dirty = true;
249 r600_context_pipe_state_set(rctx, rstate);
250
251 ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
252 ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
253 ref.valuemask[0] = dsa->valuemask[0];
254 ref.valuemask[1] = dsa->valuemask[1];
255 ref.writemask[0] = dsa->writemask[0];
256 ref.writemask[1] = dsa->writemask[1];
257
258 r600_set_stencil_ref(ctx, &ref);
259
260 if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
261 rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
262 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
263 }
264 }
265
266 void r600_set_max_scissor(struct r600_context *rctx)
267 {
268 /* Set a scissor state such that it doesn't do anything. */
269 struct pipe_scissor_state scissor;
270 scissor.minx = 0;
271 scissor.miny = 0;
272 scissor.maxx = 8192;
273 scissor.maxy = 8192;
274
275 r600_set_scissor_state(rctx, &scissor);
276 }
277
278 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
279 {
280 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
281 struct r600_context *rctx = (struct r600_context *)ctx;
282
283 if (state == NULL)
284 return;
285
286 rctx->sprite_coord_enable = rs->sprite_coord_enable;
287 rctx->two_side = rs->two_side;
288 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
289 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
290
291 rctx->rasterizer = rs;
292
293 rctx->states[rs->rstate.id] = &rs->rstate;
294 r600_context_pipe_state_set(rctx, &rs->rstate);
295
296 if (rctx->chip_class >= EVERGREEN) {
297 evergreen_polygon_offset_update(rctx);
298 } else {
299 r600_polygon_offset_update(rctx);
300 }
301
302 /* Workaround for a missing scissor enable on r600. */
303 if (rctx->chip_class == R600) {
304 if (rs->scissor_enable != rctx->scissor_enable) {
305 rctx->scissor_enable = rs->scissor_enable;
306
307 if (rs->scissor_enable) {
308 r600_set_scissor_state(rctx, &rctx->scissor_state);
309 } else {
310 r600_set_max_scissor(rctx);
311 }
312 }
313 }
314 }
315
316 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
317 {
318 struct r600_context *rctx = (struct r600_context *)ctx;
319 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
320
321 if (rctx->rasterizer == rs) {
322 rctx->rasterizer = NULL;
323 }
324 if (rctx->states[rs->rstate.id] == &rs->rstate) {
325 rctx->states[rs->rstate.id] = NULL;
326 }
327 free(rs);
328 }
329
330 void r600_sampler_view_destroy(struct pipe_context *ctx,
331 struct pipe_sampler_view *state)
332 {
333 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
334
335 pipe_resource_reference(&state->texture, NULL);
336 FREE(resource);
337 }
338
339 void r600_delete_state(struct pipe_context *ctx, void *state)
340 {
341 struct r600_context *rctx = (struct r600_context *)ctx;
342 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
343
344 if (rctx->states[rstate->id] == rstate) {
345 rctx->states[rstate->id] = NULL;
346 }
347 for (int i = 0; i < rstate->nregs; i++) {
348 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
349 }
350 free(rstate);
351 }
352
353 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
354 {
355 struct r600_context *rctx = (struct r600_context *)ctx;
356 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
357
358 rctx->vertex_elements = v;
359 if (v) {
360 r600_inval_shader_cache(rctx);
361 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
362 v->vmgr_elements);
363
364 rctx->states[v->rstate.id] = &v->rstate;
365 r600_context_pipe_state_set(rctx, &v->rstate);
366 }
367 }
368
369 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
370 {
371 struct r600_context *rctx = (struct r600_context *)ctx;
372 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
373
374 if (rctx->states[v->rstate.id] == &v->rstate) {
375 rctx->states[v->rstate.id] = NULL;
376 }
377 if (rctx->vertex_elements == state)
378 rctx->vertex_elements = NULL;
379
380 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
381 u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
382 FREE(state);
383 }
384
385 void r600_set_index_buffer(struct pipe_context *ctx,
386 const struct pipe_index_buffer *ib)
387 {
388 struct r600_context *rctx = (struct r600_context *)ctx;
389
390 if (ib) {
391 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
392 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
393 } else {
394 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
395 }
396 }
397
398 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
399 const struct pipe_vertex_buffer *buffers)
400 {
401 struct r600_context *rctx = (struct r600_context *)ctx;
402
403 u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
404 rctx->vertex_buffers_dirty = true;
405 }
406
407 void *r600_create_vertex_elements(struct pipe_context *ctx,
408 unsigned count,
409 const struct pipe_vertex_element *elements)
410 {
411 struct r600_context *rctx = (struct r600_context *)ctx;
412 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
413
414 assert(count < 32);
415 if (!v)
416 return NULL;
417
418 v->count = count;
419 v->vmgr_elements =
420 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
421 elements, v->elements);
422
423 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
424 FREE(v);
425 return NULL;
426 }
427
428 return v;
429 }
430
431 void *r600_create_shader_state(struct pipe_context *ctx,
432 const struct pipe_shader_state *state)
433 {
434 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
435 int r;
436
437 shader->tokens = tgsi_dup_tokens(state->tokens);
438 shader->so = state->stream_output;
439
440 r = r600_pipe_shader_create(ctx, shader);
441 if (r) {
442 return NULL;
443 }
444 return shader;
445 }
446
447 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
448 {
449 struct r600_context *rctx = (struct r600_context *)ctx;
450
451 if (!state) {
452 state = rctx->dummy_pixel_shader;
453 }
454
455 rctx->ps_shader = (struct r600_pipe_shader *)state;
456
457 r600_inval_shader_cache(rctx);
458 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
459
460 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
461 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
462
463 if (rctx->ps_shader && rctx->vs_shader) {
464 r600_adjust_gprs(rctx);
465 }
466 }
467
468 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
469 {
470 struct r600_context *rctx = (struct r600_context *)ctx;
471
472 rctx->vs_shader = (struct r600_pipe_shader *)state;
473 if (state) {
474 r600_inval_shader_cache(rctx);
475 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
476 }
477 if (rctx->ps_shader && rctx->vs_shader) {
478 r600_adjust_gprs(rctx);
479 }
480 }
481
482 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
483 {
484 struct r600_context *rctx = (struct r600_context *)ctx;
485 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
486
487 if (rctx->ps_shader == shader) {
488 rctx->ps_shader = NULL;
489 }
490
491 free(shader->tokens);
492 r600_pipe_shader_destroy(ctx, shader);
493 free(shader);
494 }
495
496 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
497 {
498 struct r600_context *rctx = (struct r600_context *)ctx;
499 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
500
501 if (rctx->vs_shader == shader) {
502 rctx->vs_shader = NULL;
503 }
504
505 free(shader->tokens);
506 r600_pipe_shader_destroy(ctx, shader);
507 free(shader);
508 }
509
510 static void r600_update_alpha_ref(struct r600_context *rctx)
511 {
512 unsigned alpha_ref;
513 struct r600_pipe_state rstate;
514
515 alpha_ref = rctx->alpha_ref;
516 rstate.nregs = 0;
517 if (rctx->export_16bpc)
518 alpha_ref &= ~0x1FFF;
519 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
520
521 r600_context_pipe_state_set(rctx, &rstate);
522 rctx->alpha_ref_dirty = false;
523 }
524
525 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
526 {
527 r600_inval_shader_cache(rctx);
528 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
529 : util_bitcount(state->dirty_mask)*19;
530 r600_atom_dirty(rctx, &state->atom);
531 }
532
533 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
534 struct pipe_resource *buffer)
535 {
536 struct r600_context *rctx = (struct r600_context *)ctx;
537 struct r600_constbuf_state *state;
538 struct r600_constant_buffer *cb;
539 uint8_t *ptr;
540
541 switch (shader) {
542 case PIPE_SHADER_VERTEX:
543 state = &rctx->vs_constbuf_state;
544 break;
545 case PIPE_SHADER_FRAGMENT:
546 state = &rctx->ps_constbuf_state;
547 break;
548 default:
549 return;
550 }
551
552 /* Note that the state tracker can unbind constant buffers by
553 * passing NULL here.
554 */
555 if (unlikely(!buffer)) {
556 state->enabled_mask &= ~(1 << index);
557 state->dirty_mask &= ~(1 << index);
558 pipe_resource_reference(&state->cb[index].buffer, NULL);
559 return;
560 }
561
562 cb = &state->cb[index];
563 cb->buffer_size = buffer->width0;
564
565 ptr = u_vbuf_resource(buffer)->user_ptr;
566
567 if (ptr) {
568 /* Upload the user buffer. */
569 if (R600_BIG_ENDIAN) {
570 uint32_t *tmpPtr;
571 unsigned i, size = buffer->width0;
572
573 if (!(tmpPtr = malloc(size))) {
574 R600_ERR("Failed to allocate BE swap buffer.\n");
575 return;
576 }
577
578 for (i = 0; i < size / 4; ++i) {
579 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
580 }
581
582 u_upload_data(rctx->vbuf_mgr->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
583 free(tmpPtr);
584 } else {
585 u_upload_data(rctx->vbuf_mgr->uploader, 0, buffer->width0, ptr, &cb->buffer_offset, &cb->buffer);
586 }
587 } else {
588 /* Setup the hw buffer. */
589 cb->buffer_offset = 0;
590 pipe_resource_reference(&cb->buffer, buffer);
591 }
592
593 state->enabled_mask |= 1 << index;
594 state->dirty_mask |= 1 << index;
595 r600_constant_buffers_dirty(rctx, state);
596 }
597
598 struct pipe_stream_output_target *
599 r600_create_so_target(struct pipe_context *ctx,
600 struct pipe_resource *buffer,
601 unsigned buffer_offset,
602 unsigned buffer_size)
603 {
604 struct r600_context *rctx = (struct r600_context *)ctx;
605 struct r600_so_target *t;
606 void *ptr;
607
608 t = CALLOC_STRUCT(r600_so_target);
609 if (!t) {
610 return NULL;
611 }
612
613 t->b.reference.count = 1;
614 t->b.context = ctx;
615 pipe_resource_reference(&t->b.buffer, buffer);
616 t->b.buffer_offset = buffer_offset;
617 t->b.buffer_size = buffer_size;
618
619 t->filled_size = (struct r600_resource*)
620 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
621 ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
622 memset(ptr, 0, t->filled_size->buf->size);
623 rctx->ws->buffer_unmap(t->filled_size->buf);
624
625 return &t->b;
626 }
627
628 void r600_so_target_destroy(struct pipe_context *ctx,
629 struct pipe_stream_output_target *target)
630 {
631 struct r600_so_target *t = (struct r600_so_target*)target;
632 pipe_resource_reference(&t->b.buffer, NULL);
633 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
634 FREE(t);
635 }
636
637 void r600_set_so_targets(struct pipe_context *ctx,
638 unsigned num_targets,
639 struct pipe_stream_output_target **targets,
640 unsigned append_bitmask)
641 {
642 struct r600_context *rctx = (struct r600_context *)ctx;
643 unsigned i;
644
645 /* Stop streamout. */
646 if (rctx->num_so_targets) {
647 r600_context_streamout_end(rctx);
648 }
649
650 /* Set the new targets. */
651 for (i = 0; i < num_targets; i++) {
652 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
653 }
654 for (; i < rctx->num_so_targets; i++) {
655 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
656 }
657
658 rctx->num_so_targets = num_targets;
659 rctx->streamout_start = num_targets != 0;
660 rctx->streamout_append_bitmask = append_bitmask;
661 }
662
663 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
664 {
665 struct r600_context *rctx = (struct r600_context *)ctx;
666 int r;
667
668 r600_pipe_shader_destroy(ctx, shader);
669 r = r600_pipe_shader_create(ctx, shader);
670 if (r) {
671 return r;
672 }
673 r600_context_pipe_state_set(rctx, &shader->rstate);
674
675 return 0;
676 }
677
678 static void r600_update_derived_state(struct r600_context *rctx)
679 {
680 struct pipe_context * ctx = (struct pipe_context*)rctx;
681
682 if (!rctx->blitter->running) {
683 if (rctx->have_depth_fb || rctx->have_depth_texture)
684 r600_flush_depth_textures(rctx);
685 }
686
687 if (rctx->chip_class < EVERGREEN) {
688 r600_update_sampler_states(rctx);
689 }
690
691 if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
692 ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
693 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
694 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
695 }
696
697 if (rctx->alpha_ref_dirty) {
698 r600_update_alpha_ref(rctx);
699 }
700
701 if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
702 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
703 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
704
705 if (rctx->chip_class >= EVERGREEN)
706 evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
707 else
708 r600_pipe_shader_ps(ctx, rctx->ps_shader);
709
710 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
711 }
712
713 if (rctx->dual_src_blend)
714 rctx->cb_shader_mask = rctx->ps_shader->ps_cb_shader_mask | rctx->fb_cb_shader_mask;
715 else
716 rctx->cb_shader_mask = rctx->fb_cb_shader_mask;
717 }
718
719 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
720 {
721 static const int prim_conv[] = {
722 V_028A6C_OUTPRIM_TYPE_POINTLIST,
723 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
724 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
725 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
726 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
727 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
728 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
729 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
730 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
731 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
732 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
733 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
734 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
735 V_028A6C_OUTPRIM_TYPE_TRISTRIP
736 };
737 assert(mode < Elements(prim_conv));
738
739 return prim_conv[mode];
740 }
741
742 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
743 {
744 struct r600_context *rctx = (struct r600_context *)ctx;
745 struct pipe_draw_info info = *dinfo;
746 struct pipe_index_buffer ib = {};
747 unsigned prim, mask, ls_mask = 0;
748 struct r600_block *dirty_block = NULL, *next_block = NULL;
749 struct r600_atom *state = NULL, *next_state = NULL;
750 struct radeon_winsys_cs *cs = rctx->cs;
751 uint64_t va;
752 uint8_t *ptr;
753
754 if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
755 (info.indexed && !rctx->index_buffer.buffer) ||
756 !r600_conv_pipe_prim(info.mode, &prim)) {
757 assert(0);
758 return;
759 }
760
761 if (!rctx->vs_shader) {
762 assert(0);
763 return;
764 }
765
766 r600_update_derived_state(rctx);
767
768 /* Update vertex buffers. */
769 if ((u_vbuf_draw_begin(rctx->vbuf_mgr, &info) & U_VBUF_BUFFERS_UPDATED) ||
770 rctx->vertex_buffers_dirty) {
771 r600_inval_vertex_cache(rctx);
772 rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
773 rctx->vbuf_mgr->nr_real_vertex_buffers;
774 r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
775 rctx->vertex_buffers_dirty = FALSE;
776 }
777
778 if (info.indexed) {
779 /* Initialize the index buffer struct. */
780 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
781 ib.index_size = rctx->index_buffer.index_size;
782 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
783
784 /* Translate or upload, if needed. */
785 r600_translate_index_buffer(rctx, &ib, info.count);
786
787 ptr = u_vbuf_resource(ib.buffer)->user_ptr;
788 if (ptr) {
789 u_upload_data(rctx->vbuf_mgr->uploader, 0, info.count * ib.index_size,
790 ptr, &ib.offset, &ib.buffer);
791 }
792 } else {
793 info.index_bias = info.start;
794 if (info.count_from_stream_output) {
795 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
796 }
797 }
798
799 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
800
801 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
802 rctx->vgt.id = R600_PIPE_STATE_VGT;
803 rctx->vgt.nregs = 0;
804 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
805 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
806 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask);
807 r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0);
808 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
809 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
810 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
811 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
812 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
813 if (rctx->chip_class <= R700)
814 r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
815 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
816 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
817
818 if (rctx->chip_class <= R700)
819 r600_pipe_state_add_reg(&rctx->vgt, R_0280A4_CB_COLOR1_INFO, 0);
820 else
821 r600_pipe_state_add_reg(&rctx->vgt, 0x28CAC, 0);
822 }
823
824 rctx->vgt.nregs = 0;
825 r600_pipe_state_mod_reg(&rctx->vgt, prim);
826 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
827 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
828 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
829 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
830 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
831 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
832 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
833
834 if (prim == V_008958_DI_PT_LINELIST)
835 ls_mask = 1;
836 else if (prim == V_008958_DI_PT_LINESTRIP)
837 ls_mask = 2;
838 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
839 if (rctx->chip_class <= R700)
840 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
841 r600_pipe_state_mod_reg(&rctx->vgt,
842 rctx->vs_shader->pa_cl_vs_out_cntl |
843 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
844 r600_pipe_state_mod_reg(&rctx->vgt,
845 rctx->pa_cl_clip_cntl |
846 (rctx->vs_shader->shader.clip_dist_write ||
847 rctx->vs_shader->shader.vs_prohibit_ucps ?
848 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
849
850 if (rctx->dual_src_blend) {
851 r600_pipe_state_mod_reg(&rctx->vgt,
852 rctx->color0_format);
853 }
854
855 r600_context_pipe_state_set(rctx, &rctx->vgt);
856
857 /* Emit states (the function expects that we emit at most 17 dwords here). */
858 r600_need_cs_space(rctx, 0, TRUE);
859
860 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
861 r600_emit_atom(rctx, state);
862 }
863 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
864 r600_context_block_emit_dirty(rctx, dirty_block);
865 }
866 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
867 r600_context_block_resource_emit_dirty(rctx, dirty_block);
868 }
869 rctx->pm4_dirty_cdwords = 0;
870
871 /* Enable stream out if needed. */
872 if (rctx->streamout_start) {
873 r600_context_streamout_begin(rctx);
874 rctx->streamout_start = FALSE;
875 }
876
877 /* draw packet */
878 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
879 cs->buf[cs->cdw++] = ib.index_size == 4 ?
880 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
881 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
882 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
883 cs->buf[cs->cdw++] = info.instance_count;
884 if (info.indexed) {
885 va = r600_resource_va(ctx->screen, ib.buffer);
886 va += ib.offset;
887 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
888 cs->buf[cs->cdw++] = va;
889 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
890 cs->buf[cs->cdw++] = info.count;
891 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
892 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
893 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
894 } else {
895 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
896 cs->buf[cs->cdw++] = info.count;
897 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
898 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
899 }
900
901 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
902
903 if (rctx->framebuffer.zsbuf)
904 {
905 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
906 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
907 }
908
909 pipe_resource_reference(&ib.buffer, NULL);
910 u_vbuf_draw_end(rctx->vbuf_mgr);
911 }
912
913 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
914 struct r600_pipe_state *state,
915 uint32_t offset, uint32_t value,
916 uint32_t range_id, uint32_t block_id,
917 struct r600_resource *bo,
918 enum radeon_bo_usage usage)
919
920 {
921 struct r600_range *range;
922 struct r600_block *block;
923
924 if (bo) assert(usage);
925
926 range = &ctx->range[range_id];
927 block = range->blocks[block_id];
928 state->regs[state->nregs].block = block;
929 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
930
931 state->regs[state->nregs].value = value;
932 state->regs[state->nregs].bo = bo;
933 state->regs[state->nregs].bo_usage = usage;
934
935 state->nregs++;
936 assert(state->nregs < R600_BLOCK_MAX_REG);
937 }
938
939 void _r600_pipe_state_add_reg(struct r600_context *ctx,
940 struct r600_pipe_state *state,
941 uint32_t offset, uint32_t value,
942 uint32_t range_id, uint32_t block_id)
943 {
944 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
945 range_id, block_id, NULL, 0);
946 }
947
948 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
949 uint32_t offset, uint32_t value,
950 struct r600_resource *bo,
951 enum radeon_bo_usage usage)
952 {
953 if (bo) assert(usage);
954
955 state->regs[state->nregs].id = offset;
956 state->regs[state->nregs].block = NULL;
957 state->regs[state->nregs].value = value;
958 state->regs[state->nregs].bo = bo;
959 state->regs[state->nregs].bo_usage = usage;
960
961 state->nregs++;
962 assert(state->nregs < R600_BLOCK_MAX_REG);
963 }
964
965 uint32_t r600_translate_stencil_op(int s_op)
966 {
967 switch (s_op) {
968 case PIPE_STENCIL_OP_KEEP:
969 return V_028800_STENCIL_KEEP;
970 case PIPE_STENCIL_OP_ZERO:
971 return V_028800_STENCIL_ZERO;
972 case PIPE_STENCIL_OP_REPLACE:
973 return V_028800_STENCIL_REPLACE;
974 case PIPE_STENCIL_OP_INCR:
975 return V_028800_STENCIL_INCR;
976 case PIPE_STENCIL_OP_DECR:
977 return V_028800_STENCIL_DECR;
978 case PIPE_STENCIL_OP_INCR_WRAP:
979 return V_028800_STENCIL_INCR_WRAP;
980 case PIPE_STENCIL_OP_DECR_WRAP:
981 return V_028800_STENCIL_DECR_WRAP;
982 case PIPE_STENCIL_OP_INVERT:
983 return V_028800_STENCIL_INVERT;
984 default:
985 R600_ERR("Unknown stencil op %d", s_op);
986 assert(0);
987 break;
988 }
989 return 0;
990 }
991
992 uint32_t r600_translate_fill(uint32_t func)
993 {
994 switch(func) {
995 case PIPE_POLYGON_MODE_FILL:
996 return 2;
997 case PIPE_POLYGON_MODE_LINE:
998 return 1;
999 case PIPE_POLYGON_MODE_POINT:
1000 return 0;
1001 default:
1002 assert(0);
1003 return 0;
1004 }
1005 }
1006
1007 unsigned r600_tex_wrap(unsigned wrap)
1008 {
1009 switch (wrap) {
1010 default:
1011 case PIPE_TEX_WRAP_REPEAT:
1012 return V_03C000_SQ_TEX_WRAP;
1013 case PIPE_TEX_WRAP_CLAMP:
1014 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1015 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1016 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1017 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1018 return V_03C000_SQ_TEX_CLAMP_BORDER;
1019 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1020 return V_03C000_SQ_TEX_MIRROR;
1021 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1022 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1023 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1024 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1025 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1026 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1027 }
1028 }
1029
1030 unsigned r600_tex_filter(unsigned filter)
1031 {
1032 switch (filter) {
1033 default:
1034 case PIPE_TEX_FILTER_NEAREST:
1035 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1036 case PIPE_TEX_FILTER_LINEAR:
1037 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1038 }
1039 }
1040
1041 unsigned r600_tex_mipfilter(unsigned filter)
1042 {
1043 switch (filter) {
1044 case PIPE_TEX_MIPFILTER_NEAREST:
1045 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1046 case PIPE_TEX_MIPFILTER_LINEAR:
1047 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1048 default:
1049 case PIPE_TEX_MIPFILTER_NONE:
1050 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1051 }
1052 }
1053
1054 unsigned r600_tex_compare(unsigned compare)
1055 {
1056 switch (compare) {
1057 default:
1058 case PIPE_FUNC_NEVER:
1059 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1060 case PIPE_FUNC_LESS:
1061 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1062 case PIPE_FUNC_EQUAL:
1063 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1064 case PIPE_FUNC_LEQUAL:
1065 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1066 case PIPE_FUNC_GREATER:
1067 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1068 case PIPE_FUNC_NOTEQUAL:
1069 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1070 case PIPE_FUNC_GEQUAL:
1071 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1072 case PIPE_FUNC_ALWAYS:
1073 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1074 }
1075 }