src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "r600_formats.h"
  28 #include "r600d.h"
  29
  30 #include "util/u_blitter.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include <byteswap.h>
  34
  35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
  36 {
  37         struct radeon_winsys_cs *cs = rctx->cs;
  38         struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
  39
  40         assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
  41         memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
  42         cs->cdw += cb->atom.num_dw;
  43 }
  44
  45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
  46 {
  47         cb->atom.emit = r600_emit_command_buffer;
  48         cb->atom.num_dw = 0;
  49         cb->atom.flags = flags;
  50         cb->buf = CALLOC(1, 4 * num_dw);
  51         cb->max_num_dw = num_dw;
  52 }
  53
  54 void r600_release_command_buffer(struct r600_command_buffer *cb)
  55 {
  56         FREE(cb->buf);
  57 }
  58
  59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  60 {
  61         struct radeon_winsys_cs *cs = rctx->cs;
  62         struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
  63
  64         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  65         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  66         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  67         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  68         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  69
  70         a->flush_flags = 0;
  71 }
  72
  73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  74 {
  75         struct radeon_winsys_cs *cs = rctx->cs;
  76         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  77         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  78 }
  79
  80 void r600_init_atom(struct r600_atom *atom,
  81                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  82                     unsigned num_dw, enum r600_atom_flags flags)
  83 {
  84         atom->emit = emit;
  85         atom->num_dw = num_dw;
  86         atom->flags = flags;
  87 }
  88
  89 void r600_init_common_atoms(struct r600_context *rctx)
  90 {
  91         r600_init_atom(&rctx->surface_sync_cmd.atom,    r600_emit_surface_sync,         5, EMIT_EARLY);
  92         r600_init_atom(&rctx->r6xx_flush_and_inv_cmd,   r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  93 }
  94
  95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  96 {
  97         unsigned flags = 0;
  98
  99         if (rctx->framebuffer.nr_cbufs) {
 100                 flags |= S_0085F0_CB_ACTION_ENA(1) |
 101                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
 102         }
 103
 104         /* Workaround for broken flushing on some R6xx chipsets. */
 105         if (rctx->family == CHIP_RV670 ||
 106             rctx->family == CHIP_RS780 ||
 107             rctx->family == CHIP_RS880) {
 108                 flags |=  S_0085F0_CB1_DEST_BASE_ENA(1) |
 109                           S_0085F0_DEST_BASE_0_ENA(1);
 110         }
 111         return flags;
 112 }
 113
 114 void r600_texture_barrier(struct pipe_context *ctx)
 115 {
 116         struct r600_context *rctx = (struct r600_context *)ctx;
 117
 118         rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
 119         r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
 120 }
 121
 122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 123 {
 124         static const int prim_conv[] = {
 125                 V_008958_DI_PT_POINTLIST,
 126                 V_008958_DI_PT_LINELIST,
 127                 V_008958_DI_PT_LINELOOP,
 128                 V_008958_DI_PT_LINESTRIP,
 129                 V_008958_DI_PT_TRILIST,
 130                 V_008958_DI_PT_TRISTRIP,
 131                 V_008958_DI_PT_TRIFAN,
 132                 V_008958_DI_PT_QUADLIST,
 133                 V_008958_DI_PT_QUADSTRIP,
 134                 V_008958_DI_PT_POLYGON,
 135                 -1,
 136                 -1,
 137                 -1,
 138                 -1
 139         };
 140
 141         *prim = prim_conv[pprim];
 142         if (*prim == -1) {
 143                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 144                 return false;
 145         }
 146         return true;
 147 }
 148
 149 /* common state between evergreen and r600 */
 150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 151 {
 152         struct r600_context *rctx = (struct r600_context *)ctx;
 153         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 154         struct r600_pipe_state *rstate;
 155
 156         if (state == NULL)
 157                 return;
 158         rstate = &blend->rstate;
 159         rctx->states[rstate->id] = rstate;
 160         rctx->cb_target_mask = blend->cb_target_mask;
 161
 162         /* Replace every bit except MULTIWRITE_ENABLE. */
 163         rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
 164         rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
 165
 166         r600_context_pipe_state_set(rctx, rstate);
 167 }
 168
 169 void r600_set_blend_color(struct pipe_context *ctx,
 170                           const struct pipe_blend_color *state)
 171 {
 172         struct r600_context *rctx = (struct r600_context *)ctx;
 173         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 174
 175         if (rstate == NULL)
 176                 return;
 177
 178         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 179         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
 180         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
 181         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
 182         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
 183
 184         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 185         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 186         r600_context_pipe_state_set(rctx, rstate);
 187 }
 188
 189 static void r600_set_stencil_ref(struct pipe_context *ctx,
 190                                  const struct r600_stencil_ref *state)
 191 {
 192         struct r600_context *rctx = (struct r600_context *)ctx;
 193         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 194
 195         if (rstate == NULL)
 196                 return;
 197
 198         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 199         r600_pipe_state_add_reg(rstate,
 200                                 R_028430_DB_STENCILREFMASK,
 201                                 S_028430_STENCILREF(state->ref_value[0]) |
 202                                 S_028430_STENCILMASK(state->valuemask[0]) |
 203                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
 204                                 NULL, 0);
 205         r600_pipe_state_add_reg(rstate,
 206                                 R_028434_DB_STENCILREFMASK_BF,
 207                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 208                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 209                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 210                                 NULL, 0);
 211
 212         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 213         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 214         r600_context_pipe_state_set(rctx, rstate);
 215 }
 216
 217 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 218                                const struct pipe_stencil_ref *state)
 219 {
 220         struct r600_context *rctx = (struct r600_context *)ctx;
 221         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 222         struct r600_stencil_ref ref;
 223
 224         rctx->stencil_ref = *state;
 225
 226         if (!dsa)
 227                 return;
 228
 229         ref.ref_value[0] = state->ref_value[0];
 230         ref.ref_value[1] = state->ref_value[1];
 231         ref.valuemask[0] = dsa->valuemask[0];
 232         ref.valuemask[1] = dsa->valuemask[1];
 233         ref.writemask[0] = dsa->writemask[0];
 234         ref.writemask[1] = dsa->writemask[1];
 235
 236         r600_set_stencil_ref(ctx, &ref);
 237 }
 238
 239 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 240 {
 241         struct r600_context *rctx = (struct r600_context *)ctx;
 242         struct r600_pipe_dsa *dsa = state;
 243         struct r600_pipe_state *rstate;
 244         struct r600_stencil_ref ref;
 245
 246         if (state == NULL)
 247                 return;
 248         rstate = &dsa->rstate;
 249         rctx->states[rstate->id] = rstate;
 250         rctx->alpha_ref = dsa->alpha_ref;
 251         rctx->alpha_ref_dirty = true;
 252         r600_context_pipe_state_set(rctx, rstate);
 253
 254         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 255         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 256         ref.valuemask[0] = dsa->valuemask[0];
 257         ref.valuemask[1] = dsa->valuemask[1];
 258         ref.writemask[0] = dsa->writemask[0];
 259         ref.writemask[1] = dsa->writemask[1];
 260
 261         r600_set_stencil_ref(ctx, &ref);
 262
 263         if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
 264                 rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
 265                 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
 266         }
 267 }
 268
 269 void r600_set_max_scissor(struct r600_context *rctx)
 270 {
 271         /* Set a scissor state such that it doesn't do anything. */
 272         struct pipe_scissor_state scissor;
 273         scissor.minx = 0;
 274         scissor.miny = 0;
 275         scissor.maxx = 8192;
 276         scissor.maxy = 8192;
 277
 278         r600_set_scissor_state(rctx, &scissor);
 279 }
 280
 281 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 282 {
 283         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 284         struct r600_context *rctx = (struct r600_context *)ctx;
 285
 286         if (state == NULL)
 287                 return;
 288
 289         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 290         rctx->two_side = rs->two_side;
 291         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 292         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 293
 294         rctx->rasterizer = rs;
 295
 296         rctx->states[rs->rstate.id] = &rs->rstate;
 297         r600_context_pipe_state_set(rctx, &rs->rstate);
 298
 299         if (rctx->chip_class >= EVERGREEN) {
 300                 evergreen_polygon_offset_update(rctx);
 301         } else {
 302                 r600_polygon_offset_update(rctx);
 303         }
 304
 305         /* Workaround for a missing scissor enable on r600. */
 306         if (rctx->chip_class == R600) {
 307                 if (rs->scissor_enable != rctx->scissor_enable) {
 308                         rctx->scissor_enable = rs->scissor_enable;
 309
 310                         if (rs->scissor_enable) {
 311                                 r600_set_scissor_state(rctx, &rctx->scissor_state);
 312                         } else {
 313                                 r600_set_max_scissor(rctx);
 314                         }
 315                 }
 316         }
 317 }
 318
 319 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 320 {
 321         struct r600_context *rctx = (struct r600_context *)ctx;
 322         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 323
 324         if (rctx->rasterizer == rs) {
 325                 rctx->rasterizer = NULL;
 326         }
 327         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 328                 rctx->states[rs->rstate.id] = NULL;
 329         }
 330         free(rs);
 331 }
 332
 333 void r600_sampler_view_destroy(struct pipe_context *ctx,
 334                                struct pipe_sampler_view *state)
 335 {
 336         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 337
 338         pipe_resource_reference(&state->texture, NULL);
 339         FREE(resource);
 340 }
 341
 342 void r600_delete_state(struct pipe_context *ctx, void *state)
 343 {
 344         struct r600_context *rctx = (struct r600_context *)ctx;
 345         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 346
 347         if (rctx->states[rstate->id] == rstate) {
 348                 rctx->states[rstate->id] = NULL;
 349         }
 350         for (int i = 0; i < rstate->nregs; i++) {
 351                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 352         }
 353         free(rstate);
 354 }
 355
 356 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 357 {
 358         struct r600_context *rctx = (struct r600_context *)ctx;
 359         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 360
 361         rctx->vertex_elements = v;
 362         if (v) {
 363                 r600_inval_shader_cache(rctx);
 364                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 365                                                 v->vmgr_elements);
 366
 367                 rctx->states[v->rstate.id] = &v->rstate;
 368                 r600_context_pipe_state_set(rctx, &v->rstate);
 369         }
 370 }
 371
 372 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 373 {
 374         struct r600_context *rctx = (struct r600_context *)ctx;
 375         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 376
 377         if (rctx->states[v->rstate.id] == &v->rstate) {
 378                 rctx->states[v->rstate.id] = NULL;
 379         }
 380         if (rctx->vertex_elements == state)
 381                 rctx->vertex_elements = NULL;
 382
 383         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 384         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 385         FREE(state);
 386 }
 387
 388
 389 void r600_set_index_buffer(struct pipe_context *ctx,
 390                            const struct pipe_index_buffer *ib)
 391 {
 392         struct r600_context *rctx = (struct r600_context *)ctx;
 393
 394         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 395 }
 396
 397 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 398                              const struct pipe_vertex_buffer *buffers)
 399 {
 400         struct r600_context *rctx = (struct r600_context *)ctx;
 401
 402         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 403         rctx->vertex_buffers_dirty = true;
 404 }
 405
 406 void *r600_create_vertex_elements(struct pipe_context *ctx,
 407                                   unsigned count,
 408                                   const struct pipe_vertex_element *elements)
 409 {
 410         struct r600_context *rctx = (struct r600_context *)ctx;
 411         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 412
 413         assert(count < 32);
 414         if (!v)
 415                 return NULL;
 416
 417         v->count = count;
 418         v->vmgr_elements =
 419                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 420                                                   elements, v->elements);
 421
 422         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 423                 FREE(v);
 424                 return NULL;
 425         }
 426
 427         return v;
 428 }
 429
 430 void *r600_create_shader_state(struct pipe_context *ctx,
 431                                const struct pipe_shader_state *state)
 432 {
 433         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 434         int r;
 435
 436         shader->tokens = tgsi_dup_tokens(state->tokens);
 437         shader->so = state->stream_output;
 438
 439         r =  r600_pipe_shader_create(ctx, shader);
 440         if (r) {
 441                 return NULL;
 442         }
 443         return shader;
 444 }
 445
 446 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 447 {
 448         struct r600_context *rctx = (struct r600_context *)ctx;
 449
 450         if (!state) {
 451                 state = rctx->dummy_pixel_shader;
 452         }
 453
 454         rctx->ps_shader = (struct r600_pipe_shader *)state;
 455
 456         r600_inval_shader_cache(rctx);
 457         r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 458
 459         rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
 460         rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
 461
 462         if (rctx->ps_shader && rctx->vs_shader) {
 463                 r600_adjust_gprs(rctx);
 464         }
 465 }
 466
 467 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 468 {
 469         struct r600_context *rctx = (struct r600_context *)ctx;
 470
 471         rctx->vs_shader = (struct r600_pipe_shader *)state;
 472         if (state) {
 473                 r600_inval_shader_cache(rctx);
 474                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 475         }
 476         if (rctx->ps_shader && rctx->vs_shader) {
 477                 r600_adjust_gprs(rctx);
 478         }
 479 }
 480
 481 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 482 {
 483         struct r600_context *rctx = (struct r600_context *)ctx;
 484         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 485
 486         if (rctx->ps_shader == shader) {
 487                 rctx->ps_shader = NULL;
 488         }
 489
 490         free(shader->tokens);
 491         r600_pipe_shader_destroy(ctx, shader);
 492         free(shader);
 493 }
 494
 495 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 496 {
 497         struct r600_context *rctx = (struct r600_context *)ctx;
 498         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 499
 500         if (rctx->vs_shader == shader) {
 501                 rctx->vs_shader = NULL;
 502         }
 503
 504         free(shader->tokens);
 505         r600_pipe_shader_destroy(ctx, shader);
 506         free(shader);
 507 }
 508
 509 static void r600_update_alpha_ref(struct r600_context *rctx)
 510 {
 511         unsigned alpha_ref;
 512         struct r600_pipe_state rstate;
 513
 514         alpha_ref = rctx->alpha_ref;
 515         rstate.nregs = 0;
 516         if (rctx->export_16bpc)
 517                 alpha_ref &= ~0x1FFF;
 518         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
 519
 520         r600_context_pipe_state_set(rctx, &rstate);
 521         rctx->alpha_ref_dirty = false;
 522 }
 523
 524 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 525 {
 526         r600_inval_shader_cache(rctx);
 527         state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 528                                                            : util_bitcount(state->dirty_mask)*19;
 529         r600_atom_dirty(rctx, &state->atom);
 530 }
 531
 532 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 533                               struct pipe_resource *buffer)
 534 {
 535         struct r600_context *rctx = (struct r600_context *)ctx;
 536         struct r600_constbuf_state *state;
 537         struct r600_constant_buffer *cb;
 538         uint8_t *ptr;
 539
 540         switch (shader) {
 541         case PIPE_SHADER_VERTEX:
 542                 state = &rctx->vs_constbuf_state;
 543                 break;
 544         case PIPE_SHADER_FRAGMENT:
 545                 state = &rctx->ps_constbuf_state;
 546                 break;
 547         default:
 548                 return;
 549         }
 550
 551         /* Note that the state tracker can unbind constant buffers by
 552          * passing NULL here.
 553          */
 554         if (unlikely(!buffer)) {
 555                 state->enabled_mask &= ~(1 << index);
 556                 state->dirty_mask &= ~(1 << index);
 557                 pipe_resource_reference(&state->cb[index].buffer, NULL);
 558                 return;
 559         }
 560
 561         cb = &state->cb[index];
 562         cb->buffer_size = buffer->width0;
 563
 564         ptr = u_vbuf_resource(buffer)->user_ptr;
 565
 566         if (ptr) {
 567                 /* Upload the user buffer. */
 568                 if (R600_BIG_ENDIAN) {
 569                         uint32_t *tmpPtr;
 570                         unsigned i, size = buffer->width0;
 571
 572                         if (!(tmpPtr = malloc(size))) {
 573                                 R600_ERR("Failed to allocate BE swap buffer.\n");
 574                                 return;
 575                         }
 576
 577                         for (i = 0; i < size / 4; ++i) {
 578                                 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
 579                         }
 580
 581                         u_upload_data(rctx->vbuf_mgr->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
 582                         free(tmpPtr);
 583                 } else {
 584                         u_upload_data(rctx->vbuf_mgr->uploader, 0, buffer->width0, ptr, &cb->buffer_offset, &cb->buffer);
 585                 }
 586         } else {
 587                 /* Setup the hw buffer. */
 588                 cb->buffer_offset = 0;
 589                 pipe_resource_reference(&cb->buffer, buffer);
 590         }
 591
 592         state->enabled_mask |= 1 << index;
 593         state->dirty_mask |= 1 << index;
 594         r600_constant_buffers_dirty(rctx, state);
 595 }
 596
 597 struct pipe_stream_output_target *
 598 r600_create_so_target(struct pipe_context *ctx,
 599                       struct pipe_resource *buffer,
 600                       unsigned buffer_offset,
 601                       unsigned buffer_size)
 602 {
 603         struct r600_context *rctx = (struct r600_context *)ctx;
 604         struct r600_so_target *t;
 605         void *ptr;
 606
 607         t = CALLOC_STRUCT(r600_so_target);
 608         if (!t) {
 609                 return NULL;
 610         }
 611
 612         t->b.reference.count = 1;
 613         t->b.context = ctx;
 614         pipe_resource_reference(&t->b.buffer, buffer);
 615         t->b.buffer_offset = buffer_offset;
 616         t->b.buffer_size = buffer_size;
 617
 618         t->filled_size = (struct r600_resource*)
 619                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 620         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
 621         memset(ptr, 0, t->filled_size->buf->size);
 622         rctx->ws->buffer_unmap(t->filled_size->buf);
 623
 624         return &t->b;
 625 }
 626
 627 void r600_so_target_destroy(struct pipe_context *ctx,
 628                             struct pipe_stream_output_target *target)
 629 {
 630         struct r600_so_target *t = (struct r600_so_target*)target;
 631         pipe_resource_reference(&t->b.buffer, NULL);
 632         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 633         FREE(t);
 634 }
 635
 636 void r600_set_so_targets(struct pipe_context *ctx,
 637                          unsigned num_targets,
 638                          struct pipe_stream_output_target **targets,
 639                          unsigned append_bitmask)
 640 {
 641         struct r600_context *rctx = (struct r600_context *)ctx;
 642         unsigned i;
 643
 644         /* Stop streamout. */
 645         if (rctx->num_so_targets) {
 646                 r600_context_streamout_end(rctx);
 647         }
 648
 649         /* Set the new targets. */
 650         for (i = 0; i < num_targets; i++) {
 651                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 652         }
 653         for (; i < rctx->num_so_targets; i++) {
 654                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 655         }
 656
 657         rctx->num_so_targets = num_targets;
 658         rctx->streamout_start = num_targets != 0;
 659         rctx->streamout_append_bitmask = append_bitmask;
 660 }
 661
 662 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 663 {
 664         struct r600_context *rctx = (struct r600_context *)ctx;
 665         int r;
 666
 667         r600_pipe_shader_destroy(ctx, shader);
 668         r = r600_pipe_shader_create(ctx, shader);
 669         if (r) {
 670                 return r;
 671         }
 672         r600_context_pipe_state_set(rctx, &shader->rstate);
 673
 674         return 0;
 675 }
 676
 677 static void r600_update_derived_state(struct r600_context *rctx)
 678 {
 679         struct pipe_context * ctx = (struct pipe_context*)rctx;
 680
 681         if (!rctx->blitter->running) {
 682                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 683                         r600_flush_depth_textures(rctx);
 684         }
 685
 686         if (rctx->chip_class < EVERGREEN) {
 687                 r600_update_sampler_states(rctx);
 688         }
 689
 690         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 691             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 692              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 693                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 694         }
 695
 696         if (rctx->alpha_ref_dirty) {
 697                 r600_update_alpha_ref(rctx);
 698         }
 699
 700         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 701                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 702                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
 703
 704                 if (rctx->chip_class >= EVERGREEN)
 705                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 706                 else
 707                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 708
 709                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 710         }
 711
 712 }
 713
 714 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
 715 {
 716         static const int prim_conv[] = {
 717                 V_028A6C_OUTPRIM_TYPE_POINTLIST,
 718                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 719                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 720                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 721                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 722                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 723                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 724                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 725                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 726                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 727                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 728                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 729                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 730                 V_028A6C_OUTPRIM_TYPE_TRISTRIP
 731         };
 732         assert(mode < Elements(prim_conv));
 733
 734         return prim_conv[mode];
 735 }
 736
 737 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 738 {
 739         struct r600_context *rctx = (struct r600_context *)ctx;
 740         struct pipe_draw_info info = *dinfo;
 741         struct pipe_index_buffer ib = {};
 742         unsigned prim, mask, ls_mask = 0;
 743         struct r600_block *dirty_block = NULL, *next_block = NULL;
 744         struct r600_atom *state = NULL, *next_state = NULL;
 745         struct radeon_winsys_cs *cs = rctx->cs;
 746         uint64_t va;
 747         uint8_t *ptr;
 748
 749         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 750             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 751             !r600_conv_pipe_prim(info.mode, &prim)) {
 752                 assert(0);
 753                 return;
 754         }
 755
 756         if (!rctx->vs_shader) {
 757                 assert(0);
 758                 return;
 759         }
 760
 761         r600_update_derived_state(rctx);
 762
 763         /* Update vertex buffers. */
 764         if ((u_vbuf_draw_begin(rctx->vbuf_mgr, &info) & U_VBUF_BUFFERS_UPDATED) ||
 765             rctx->vertex_buffers_dirty) {
 766                 r600_inval_vertex_cache(rctx);
 767                 rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
 768                                                    rctx->vbuf_mgr->nr_real_vertex_buffers;
 769                 r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
 770                 rctx->vertex_buffers_dirty = FALSE;
 771         }
 772
 773         if (info.indexed) {
 774                 /* Initialize the index buffer struct. */
 775                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 776                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 777                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 778
 779                 /* Translate or upload, if needed. */
 780                 r600_translate_index_buffer(rctx, &ib, info.count);
 781
 782                 ptr = u_vbuf_resource(ib.buffer)->user_ptr;
 783                 if (ptr) {
 784                         u_upload_data(rctx->vbuf_mgr->uploader, 0, info.count * ib.index_size,
 785                                       ptr, &ib.offset, &ib.buffer);
 786                 }
 787         } else {
 788                 info.index_bias = info.start;
 789                 if (info.count_from_stream_output) {
 790                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 791                 }
 792         }
 793
 794         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 795
 796         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 797                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 798                 rctx->vgt.nregs = 0;
 799                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
 800                 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, NULL, 0);
 801                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
 802                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
 803                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
 804                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
 805                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
 806                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
 807                 if (rctx->chip_class <= R700)
 808                         r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
 809                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
 810                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
 811         }
 812
 813         rctx->vgt.nregs = 0;
 814         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 815         r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
 816         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 817         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 818         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 819         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 820         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 821
 822         if (prim == V_008958_DI_PT_LINELIST)
 823                 ls_mask = 1;
 824         else if (prim == V_008958_DI_PT_LINESTRIP)
 825                 ls_mask = 2;
 826         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 827         if (rctx->chip_class <= R700)
 828                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 829         r600_pipe_state_mod_reg(&rctx->vgt,
 830                                 rctx->vs_shader->pa_cl_vs_out_cntl |
 831                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
 832         r600_pipe_state_mod_reg(&rctx->vgt,
 833                                 rctx->pa_cl_clip_cntl |
 834                                 (rctx->vs_shader->shader.clip_dist_write ||
 835                                  rctx->vs_shader->shader.vs_prohibit_ucps ?
 836                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F));
 837
 838         r600_context_pipe_state_set(rctx, &rctx->vgt);
 839
 840         /* Emit states (the function expects that we emit at most 17 dwords here). */
 841         r600_need_cs_space(rctx, 0, TRUE);
 842
 843         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 844                 r600_emit_atom(rctx, state);
 845         }
 846         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 847                 r600_context_block_emit_dirty(rctx, dirty_block);
 848         }
 849         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
 850                 r600_context_block_resource_emit_dirty(rctx, dirty_block);
 851         }
 852         rctx->pm4_dirty_cdwords = 0;
 853
 854         /* Enable stream out if needed. */
 855         if (rctx->streamout_start) {
 856                 r600_context_streamout_begin(rctx);
 857                 rctx->streamout_start = FALSE;
 858         }
 859
 860         /* draw packet */
 861         cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
 862         cs->buf[cs->cdw++] = ib.index_size == 4 ?
 863                                 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
 864                                 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
 865         cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
 866         cs->buf[cs->cdw++] = info.instance_count;
 867         if (info.indexed) {
 868                 va = r600_resource_va(ctx->screen, ib.buffer);
 869                 va += ib.offset;
 870                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
 871                 cs->buf[cs->cdw++] = va;
 872                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
 873                 cs->buf[cs->cdw++] = info.count;
 874                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
 875                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
 876                 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
 877         } else {
 878                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
 879                 cs->buf[cs->cdw++] = info.count;
 880                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
 881                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
 882         }
 883
 884         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 885
 886         if (rctx->framebuffer.zsbuf)
 887         {
 888                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 889                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 890         }
 891
 892         pipe_resource_reference(&ib.buffer, NULL);
 893         u_vbuf_draw_end(rctx->vbuf_mgr);
 894 }
 895
 896 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 897                               struct r600_pipe_state *state,
 898                               uint32_t offset, uint32_t value,
 899                               uint32_t range_id, uint32_t block_id,
 900                               struct r600_resource *bo,
 901                               enum radeon_bo_usage usage)
 902 {
 903         struct r600_range *range;
 904         struct r600_block *block;
 905
 906         if (bo) assert(usage);
 907
 908         range = &ctx->range[range_id];
 909         block = range->blocks[block_id];
 910         state->regs[state->nregs].block = block;
 911         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 912
 913         state->regs[state->nregs].value = value;
 914         state->regs[state->nregs].bo = bo;
 915         state->regs[state->nregs].bo_usage = usage;
 916
 917         state->nregs++;
 918         assert(state->nregs < R600_BLOCK_MAX_REG);
 919 }
 920
 921 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 922                                      uint32_t offset, uint32_t value,
 923                                      struct r600_resource *bo,
 924                                      enum radeon_bo_usage usage)
 925 {
 926         if (bo) assert(usage);
 927
 928         state->regs[state->nregs].id = offset;
 929         state->regs[state->nregs].block = NULL;
 930         state->regs[state->nregs].value = value;
 931         state->regs[state->nregs].bo = bo;
 932         state->regs[state->nregs].bo_usage = usage;
 933
 934         state->nregs++;
 935         assert(state->nregs < R600_BLOCK_MAX_REG);
 936 }
 937
 938 uint32_t r600_translate_stencil_op(int s_op)
 939 {
 940         switch (s_op) {
 941         case PIPE_STENCIL_OP_KEEP:
 942                 return V_028800_STENCIL_KEEP;
 943         case PIPE_STENCIL_OP_ZERO:
 944                 return V_028800_STENCIL_ZERO;
 945         case PIPE_STENCIL_OP_REPLACE:
 946                 return V_028800_STENCIL_REPLACE;
 947         case PIPE_STENCIL_OP_INCR:
 948                 return V_028800_STENCIL_INCR;
 949         case PIPE_STENCIL_OP_DECR:
 950                 return V_028800_STENCIL_DECR;
 951         case PIPE_STENCIL_OP_INCR_WRAP:
 952                 return V_028800_STENCIL_INCR_WRAP;
 953         case PIPE_STENCIL_OP_DECR_WRAP:
 954                 return V_028800_STENCIL_DECR_WRAP;
 955         case PIPE_STENCIL_OP_INVERT:
 956                 return V_028800_STENCIL_INVERT;
 957         default:
 958                 R600_ERR("Unknown stencil op %d", s_op);
 959                 assert(0);
 960                 break;
 961         }
 962         return 0;
 963 }
 964
 965 uint32_t r600_translate_fill(uint32_t func)
 966 {
 967         switch(func) {
 968         case PIPE_POLYGON_MODE_FILL:
 969                 return 2;
 970         case PIPE_POLYGON_MODE_LINE:
 971                 return 1;
 972         case PIPE_POLYGON_MODE_POINT:
 973                 return 0;
 974         default:
 975                 assert(0);
 976                 return 0;
 977         }
 978 }
 979
 980 unsigned r600_tex_wrap(unsigned wrap)
 981 {
 982         switch (wrap) {
 983         default:
 984         case PIPE_TEX_WRAP_REPEAT:
 985                 return V_03C000_SQ_TEX_WRAP;
 986         case PIPE_TEX_WRAP_CLAMP:
 987                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 988         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 989                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 990         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 991                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 992         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 993                 return V_03C000_SQ_TEX_MIRROR;
 994         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 995                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 996         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 997                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 998         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 999                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1000         }
1001 }
1002
1003 unsigned r600_tex_filter(unsigned filter)
1004 {
1005         switch (filter) {
1006         default:
1007         case PIPE_TEX_FILTER_NEAREST:
1008                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1009         case PIPE_TEX_FILTER_LINEAR:
1010                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1011         }
1012 }
1013
1014 unsigned r600_tex_mipfilter(unsigned filter)
1015 {
1016         switch (filter) {
1017         case PIPE_TEX_MIPFILTER_NEAREST:
1018                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1019         case PIPE_TEX_MIPFILTER_LINEAR:
1020                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1021         default:
1022         case PIPE_TEX_MIPFILTER_NONE:
1023                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1024         }
1025 }
1026
1027 unsigned r600_tex_compare(unsigned compare)
1028 {
1029         switch (compare) {
1030         default:
1031         case PIPE_FUNC_NEVER:
1032                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1033         case PIPE_FUNC_LESS:
1034                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1035         case PIPE_FUNC_EQUAL:
1036                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1037         case PIPE_FUNC_LEQUAL:
1038                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1039         case PIPE_FUNC_GREATER:
1040                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1041         case PIPE_FUNC_NOTEQUAL:
1042                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1043         case PIPE_FUNC_GEQUAL:
1044                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1045         case PIPE_FUNC_ALWAYS:
1046                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1047         }
1048 }