src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
  38 {
  39         static const int prim_conv[] = {
  40                 V_008958_DI_PT_POINTLIST,
  41                 V_008958_DI_PT_LINELIST,
  42                 V_008958_DI_PT_LINELOOP,
  43                 V_008958_DI_PT_LINESTRIP,
  44                 V_008958_DI_PT_TRILIST,
  45                 V_008958_DI_PT_TRISTRIP,
  46                 V_008958_DI_PT_TRIFAN,
  47                 V_008958_DI_PT_QUADLIST,
  48                 V_008958_DI_PT_QUADSTRIP,
  49                 V_008958_DI_PT_POLYGON,
  50                 -1,
  51                 -1,
  52                 -1,
  53                 -1
  54         };
  55
  56         *prim = prim_conv[pprim];
  57         if (*prim == -1) {
  58                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
  59                 return false;
  60         }
  61         return true;
  62 }
  63
  64 /* common state between evergreen and r600 */
  65 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
  66 {
  67         struct r600_context *rctx = (struct r600_context *)ctx;
  68         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
  69         struct r600_pipe_state *rstate;
  70
  71         if (state == NULL)
  72                 return;
  73         rstate = &blend->rstate;
  74         rctx->states[rstate->id] = rstate;
  75         rctx->cb_target_mask = blend->cb_target_mask;
  76
  77         /* Replace every bit except MULTIWRITE_ENABLE. */
  78         rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
  79         rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
  80
  81         r600_context_pipe_state_set(rctx, rstate);
  82 }
  83
  84 static void r600_set_stencil_ref(struct pipe_context *ctx,
  85                                  const struct r600_stencil_ref *state)
  86 {
  87         struct r600_context *rctx = (struct r600_context *)ctx;
  88         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
  89
  90         if (rstate == NULL)
  91                 return;
  92
  93         rstate->id = R600_PIPE_STATE_STENCIL_REF;
  94         r600_pipe_state_add_reg(rstate,
  95                                 R_028430_DB_STENCILREFMASK,
  96                                 S_028430_STENCILREF(state->ref_value[0]) |
  97                                 S_028430_STENCILMASK(state->valuemask[0]) |
  98                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
  99                                 NULL, 0);
 100         r600_pipe_state_add_reg(rstate,
 101                                 R_028434_DB_STENCILREFMASK_BF,
 102                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 103                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 104                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 105                                 NULL, 0);
 106
 107         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 108         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 109         r600_context_pipe_state_set(rctx, rstate);
 110 }
 111
 112 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 113                                const struct pipe_stencil_ref *state)
 114 {
 115         struct r600_context *rctx = (struct r600_context *)ctx;
 116         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 117         struct r600_stencil_ref ref;
 118
 119         rctx->stencil_ref = *state;
 120
 121         if (!dsa)
 122                 return;
 123
 124         ref.ref_value[0] = state->ref_value[0];
 125         ref.ref_value[1] = state->ref_value[1];
 126         ref.valuemask[0] = dsa->valuemask[0];
 127         ref.valuemask[1] = dsa->valuemask[1];
 128         ref.writemask[0] = dsa->writemask[0];
 129         ref.writemask[1] = dsa->writemask[1];
 130
 131         r600_set_stencil_ref(ctx, &ref);
 132 }
 133
 134 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 135 {
 136         struct r600_context *rctx = (struct r600_context *)ctx;
 137         struct r600_pipe_dsa *dsa = state;
 138         struct r600_pipe_state *rstate;
 139         struct r600_stencil_ref ref;
 140
 141         if (state == NULL)
 142                 return;
 143         rstate = &dsa->rstate;
 144         rctx->states[rstate->id] = rstate;
 145         rctx->alpha_ref = dsa->alpha_ref;
 146         rctx->alpha_ref_dirty = true;
 147         r600_context_pipe_state_set(rctx, rstate);
 148
 149         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 150         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 151         ref.valuemask[0] = dsa->valuemask[0];
 152         ref.valuemask[1] = dsa->valuemask[1];
 153         ref.writemask[0] = dsa->writemask[0];
 154         ref.writemask[1] = dsa->writemask[1];
 155
 156         r600_set_stencil_ref(ctx, &ref);
 157 }
 158
 159 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 160 {
 161         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 162         struct r600_context *rctx = (struct r600_context *)ctx;
 163
 164         if (state == NULL)
 165                 return;
 166
 167         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 168         rctx->two_side = rs->two_side;
 169         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 170         rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
 171         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 172
 173         rctx->rasterizer = rs;
 174
 175         rctx->states[rs->rstate.id] = &rs->rstate;
 176         r600_context_pipe_state_set(rctx, &rs->rstate);
 177
 178         if (rctx->chip_class >= EVERGREEN) {
 179                 evergreen_polygon_offset_update(rctx);
 180         } else {
 181                 r600_polygon_offset_update(rctx);
 182         }
 183 }
 184
 185 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 186 {
 187         struct r600_context *rctx = (struct r600_context *)ctx;
 188         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 189
 190         if (rctx->rasterizer == rs) {
 191                 rctx->rasterizer = NULL;
 192         }
 193         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 194                 rctx->states[rs->rstate.id] = NULL;
 195         }
 196         free(rs);
 197 }
 198
 199 void r600_sampler_view_destroy(struct pipe_context *ctx,
 200                                struct pipe_sampler_view *state)
 201 {
 202         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 203
 204         pipe_resource_reference(&state->texture, NULL);
 205         FREE(resource);
 206 }
 207
 208 void r600_delete_state(struct pipe_context *ctx, void *state)
 209 {
 210         struct r600_context *rctx = (struct r600_context *)ctx;
 211         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 212
 213         if (rctx->states[rstate->id] == rstate) {
 214                 rctx->states[rstate->id] = NULL;
 215         }
 216         for (int i = 0; i < rstate->nregs; i++) {
 217                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 218         }
 219         free(rstate);
 220 }
 221
 222 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 223 {
 224         struct r600_context *rctx = (struct r600_context *)ctx;
 225         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 226
 227         rctx->vertex_elements = v;
 228         if (v) {
 229                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 230                                                 v->vmgr_elements);
 231
 232                 rctx->states[v->rstate.id] = &v->rstate;
 233                 r600_context_pipe_state_set(rctx, &v->rstate);
 234         }
 235 }
 236
 237 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 238 {
 239         struct r600_context *rctx = (struct r600_context *)ctx;
 240         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 241
 242         if (rctx->states[v->rstate.id] == &v->rstate) {
 243                 rctx->states[v->rstate.id] = NULL;
 244         }
 245         if (rctx->vertex_elements == state)
 246                 rctx->vertex_elements = NULL;
 247
 248         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 249         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 250         FREE(state);
 251 }
 252
 253
 254 void r600_set_index_buffer(struct pipe_context *ctx,
 255                            const struct pipe_index_buffer *ib)
 256 {
 257         struct r600_context *rctx = (struct r600_context *)ctx;
 258
 259         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 260 }
 261
 262 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 263                              const struct pipe_vertex_buffer *buffers)
 264 {
 265         struct r600_context *rctx = (struct r600_context *)ctx;
 266         int i;
 267
 268         /* Zero states. */
 269         for (i = 0; i < count; i++) {
 270                 if (!buffers[i].buffer) {
 271                         if (rctx->chip_class >= EVERGREEN) {
 272                                 evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 273                         } else {
 274                                 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 275                         }
 276                 }
 277         }
 278         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 279                 if (rctx->chip_class >= EVERGREEN) {
 280                         evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 281                 } else {
 282                         r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 283                 }
 284         }
 285
 286         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 287 }
 288
 289 void *r600_create_vertex_elements(struct pipe_context *ctx,
 290                                   unsigned count,
 291                                   const struct pipe_vertex_element *elements)
 292 {
 293         struct r600_context *rctx = (struct r600_context *)ctx;
 294         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 295
 296         assert(count < 32);
 297         if (!v)
 298                 return NULL;
 299
 300         v->count = count;
 301         v->vmgr_elements =
 302                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 303                                                   elements, v->elements);
 304
 305         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 306                 FREE(v);
 307                 return NULL;
 308         }
 309
 310         return v;
 311 }
 312
 313 void *r600_create_shader_state(struct pipe_context *ctx,
 314                                const struct pipe_shader_state *state)
 315 {
 316         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 317         int r;
 318
 319         shader->tokens = tgsi_dup_tokens(state->tokens);
 320         shader->so = state->stream_output;
 321
 322         r =  r600_pipe_shader_create(ctx, shader);
 323         if (r) {
 324                 return NULL;
 325         }
 326         return shader;
 327 }
 328
 329 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 330 {
 331         struct r600_context *rctx = (struct r600_context *)ctx;
 332
 333         /* TODO delete old shader */
 334         rctx->ps_shader = (struct r600_pipe_shader *)state;
 335         if (state) {
 336                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 337
 338                 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
 339                 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
 340         }
 341         if (rctx->ps_shader && rctx->vs_shader) {
 342                 r600_adjust_gprs(rctx);
 343         }
 344 }
 345
 346 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 347 {
 348         struct r600_context *rctx = (struct r600_context *)ctx;
 349
 350         /* TODO delete old shader */
 351         rctx->vs_shader = (struct r600_pipe_shader *)state;
 352         if (state) {
 353                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 354         }
 355         if (rctx->ps_shader && rctx->vs_shader) {
 356                 r600_adjust_gprs(rctx);
 357         }
 358 }
 359
 360 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 361 {
 362         struct r600_context *rctx = (struct r600_context *)ctx;
 363         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 364
 365         if (rctx->ps_shader == shader) {
 366                 rctx->ps_shader = NULL;
 367         }
 368
 369         free(shader->tokens);
 370         r600_pipe_shader_destroy(ctx, shader);
 371         free(shader);
 372 }
 373
 374 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 375 {
 376         struct r600_context *rctx = (struct r600_context *)ctx;
 377         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 378
 379         if (rctx->vs_shader == shader) {
 380                 rctx->vs_shader = NULL;
 381         }
 382
 383         free(shader->tokens);
 384         r600_pipe_shader_destroy(ctx, shader);
 385         free(shader);
 386 }
 387
 388 static void r600_update_alpha_ref(struct r600_context *rctx)
 389 {
 390         unsigned alpha_ref;
 391         struct r600_pipe_state rstate;
 392
 393         alpha_ref = rctx->alpha_ref;
 394         rstate.nregs = 0;
 395         if (rctx->export_16bpc)
 396                 alpha_ref &= ~0x1FFF;
 397         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
 398
 399         r600_context_pipe_state_set(rctx, &rstate);
 400         rctx->alpha_ref_dirty = false;
 401 }
 402
 403 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 404                               struct pipe_resource *buffer)
 405 {
 406         struct r600_context *rctx = (struct r600_context *)ctx;
 407         struct r600_resource *rbuffer = r600_resource(buffer);
 408         struct r600_pipe_resource_state *rstate;
 409         uint64_t va_offset;
 410         uint32_t offset;
 411
 412         /* Note that the state tracker can unbind constant buffers by
 413          * passing NULL here.
 414          */
 415         if (buffer == NULL) {
 416                 return;
 417         }
 418
 419         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 420         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 421         va_offset += offset;
 422         va_offset >>= 8;
 423
 424         switch (shader) {
 425         case PIPE_SHADER_VERTEX:
 426                 rctx->vs_const_buffer.nregs = 0;
 427                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 428                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
 429                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 430                                         NULL, 0);
 431                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 432                                         R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
 433                                         va_offset, rbuffer, RADEON_USAGE_READ);
 434                 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
 435
 436                 rstate = &rctx->vs_const_buffer_resource[index];
 437                 if (!rstate->id) {
 438                         if (rctx->chip_class >= EVERGREEN) {
 439                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 440                         } else {
 441                                 r600_pipe_init_buffer_resource(rctx, rstate);
 442                         }
 443                 }
 444
 445                 if (rctx->chip_class >= EVERGREEN) {
 446                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 447                         evergreen_context_pipe_state_set_vs_resource(rctx, rstate, index);
 448                 } else {
 449                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 450                         r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
 451                 }
 452                 break;
 453         case PIPE_SHADER_FRAGMENT:
 454                 rctx->ps_const_buffer.nregs = 0;
 455                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 456                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 457                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 458                                         NULL, 0);
 459                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 460                                         R_028940_ALU_CONST_CACHE_PS_0,
 461                                         va_offset, rbuffer, RADEON_USAGE_READ);
 462                 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
 463
 464                 rstate = &rctx->ps_const_buffer_resource[index];
 465                 if (!rstate->id) {
 466                         if (rctx->chip_class >= EVERGREEN) {
 467                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 468                         } else {
 469                                 r600_pipe_init_buffer_resource(rctx, rstate);
 470                         }
 471                 }
 472                 if (rctx->chip_class >= EVERGREEN) {
 473                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 474                         evergreen_context_pipe_state_set_ps_resource(rctx, rstate, index);
 475                 } else {
 476                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 477                         r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
 478                 }
 479                 break;
 480         default:
 481                 R600_ERR("unsupported %d\n", shader);
 482                 return;
 483         }
 484
 485         if (buffer != &rbuffer->b.b.b)
 486                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 487 }
 488
 489 struct pipe_stream_output_target *
 490 r600_create_so_target(struct pipe_context *ctx,
 491                       struct pipe_resource *buffer,
 492                       unsigned buffer_offset,
 493                       unsigned buffer_size)
 494 {
 495         struct r600_context *rctx = (struct r600_context *)ctx;
 496         struct r600_so_target *t;
 497         void *ptr;
 498
 499         t = CALLOC_STRUCT(r600_so_target);
 500         if (!t) {
 501                 return NULL;
 502         }
 503
 504         t->b.reference.count = 1;
 505         t->b.context = ctx;
 506         pipe_resource_reference(&t->b.buffer, buffer);
 507         t->b.buffer_offset = buffer_offset;
 508         t->b.buffer_size = buffer_size;
 509
 510         t->filled_size = (struct r600_resource*)
 511                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 512         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
 513         memset(ptr, 0, t->filled_size->buf->size);
 514         rctx->ws->buffer_unmap(t->filled_size->buf);
 515
 516         return &t->b;
 517 }
 518
 519 void r600_so_target_destroy(struct pipe_context *ctx,
 520                             struct pipe_stream_output_target *target)
 521 {
 522         struct r600_so_target *t = (struct r600_so_target*)target;
 523         pipe_resource_reference(&t->b.buffer, NULL);
 524         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 525         FREE(t);
 526 }
 527
 528 void r600_set_so_targets(struct pipe_context *ctx,
 529                          unsigned num_targets,
 530                          struct pipe_stream_output_target **targets,
 531                          unsigned append_bitmask)
 532 {
 533         struct r600_context *rctx = (struct r600_context *)ctx;
 534         unsigned i;
 535
 536         /* Stop streamout. */
 537         if (rctx->num_so_targets) {
 538                 r600_context_streamout_end(rctx);
 539         }
 540
 541         /* Set the new targets. */
 542         for (i = 0; i < num_targets; i++) {
 543                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 544         }
 545         for (; i < rctx->num_so_targets; i++) {
 546                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 547         }
 548
 549         rctx->num_so_targets = num_targets;
 550         rctx->streamout_start = num_targets != 0;
 551         rctx->streamout_append_bitmask = append_bitmask;
 552 }
 553
 554 static void r600_vertex_buffer_update(struct r600_context *rctx)
 555 {
 556         struct r600_pipe_resource_state *rstate;
 557         struct r600_resource *rbuffer;
 558         struct pipe_vertex_buffer *vertex_buffer;
 559         unsigned i, count, offset;
 560
 561         if (rctx->vertex_elements->vbuffer_need_offset) {
 562                 /* one resource per vertex elements */
 563                 count = rctx->vertex_elements->count;
 564         } else {
 565                 /* bind vertex buffer once */
 566                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 567         }
 568
 569         for (i = 0 ; i < count; i++) {
 570                 rstate = &rctx->fs_resource[i];
 571
 572                 if (rctx->vertex_elements->vbuffer_need_offset) {
 573                         /* one resource per vertex elements */
 574                         unsigned vbuffer_index;
 575                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 576                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 577                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 578                         offset = rctx->vertex_elements->vbuffer_offset[i];
 579                 } else {
 580                         /* bind vertex buffer once */
 581                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 582                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 583                         offset = 0;
 584                 }
 585                 if (vertex_buffer == NULL || rbuffer == NULL)
 586                         continue;
 587                 offset += vertex_buffer->buffer_offset;
 588
 589                 if (!rstate->id) {
 590                         if (rctx->chip_class >= EVERGREEN) {
 591                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 592                         } else {
 593                                 r600_pipe_init_buffer_resource(rctx, rstate);
 594                         }
 595                 }
 596
 597                 if (rctx->chip_class >= EVERGREEN) {
 598                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 599                         evergreen_context_pipe_state_set_fs_resource(rctx, rstate, i);
 600                 } else {
 601                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 602                         r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
 603                 }
 604         }
 605 }
 606
 607 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 608 {
 609         struct r600_context *rctx = (struct r600_context *)ctx;
 610         int r;
 611
 612         r600_pipe_shader_destroy(ctx, shader);
 613         r = r600_pipe_shader_create(ctx, shader);
 614         if (r) {
 615                 return r;
 616         }
 617         r600_context_pipe_state_set(rctx, &shader->rstate);
 618
 619         return 0;
 620 }
 621
 622 static void r600_update_derived_state(struct r600_context *rctx)
 623 {
 624         struct pipe_context * ctx = (struct pipe_context*)rctx;
 625         struct r600_pipe_state rstate;
 626
 627         rstate.nregs = 0;
 628
 629         if (rstate.nregs)
 630                 r600_context_pipe_state_set(rctx, &rstate);
 631
 632         if (!rctx->blitter->running) {
 633                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 634                         r600_flush_depth_textures(rctx);
 635         }
 636
 637         if (rctx->chip_class < EVERGREEN) {
 638                 r600_update_sampler_states(rctx);
 639         }
 640
 641         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 642             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 643              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 644                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 645         }
 646
 647         if (rctx->alpha_ref_dirty) {
 648                 r600_update_alpha_ref(rctx);
 649         }
 650
 651         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 652                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 653                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
 654
 655                 if (rctx->chip_class >= EVERGREEN)
 656                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 657                 else
 658                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 659
 660                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 661         }
 662
 663 }
 664
 665 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 666 {
 667         struct r600_context *rctx = (struct r600_context *)ctx;
 668         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 669         struct pipe_draw_info info = *dinfo;
 670         struct r600_draw rdraw = {};
 671         struct pipe_index_buffer ib = {};
 672         unsigned prim, mask, ls_mask = 0;
 673         struct r600_block *dirty_block = NULL, *next_block = NULL;
 674
 675         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 676             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 677             !r600_conv_pipe_prim(info.mode, &prim)) {
 678                 return;
 679         }
 680
 681         if (!rctx->ps_shader || !rctx->vs_shader)
 682                 return;
 683
 684         r600_update_derived_state(rctx);
 685
 686         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 687         r600_vertex_buffer_update(rctx);
 688
 689         rdraw.vgt_num_indices = info.count;
 690         rdraw.vgt_num_instances = info.instance_count;
 691
 692         if (info.indexed) {
 693                 /* Initialize the index buffer struct. */
 694                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 695                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 696                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 697
 698                 /* Translate or upload, if needed. */
 699                 r600_translate_index_buffer(rctx, &ib, info.count);
 700
 701                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 702                         r600_upload_index_buffer(rctx, &ib, info.count);
 703                 }
 704
 705                 /* Initialize the r600_draw struct with index buffer info. */
 706                 if (ib.index_size == 4) {
 707                         rdraw.vgt_index_type = VGT_INDEX_32 |
 708                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 709                 } else {
 710                         rdraw.vgt_index_type = VGT_INDEX_16 |
 711                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 712                 }
 713                 rdraw.indices = (struct r600_resource*)ib.buffer;
 714                 rdraw.indices_bo_offset = ib.offset;
 715                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 716         } else {
 717                 info.index_bias = info.start;
 718                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 719                 if (info.count_from_stream_output) {
 720                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 721
 722                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 723                 }
 724         }
 725
 726         rctx->vs_so_stride_in_dw = rctx->vs_shader->so.stride;
 727
 728         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 729
 730         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 731                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 732                 rctx->vgt.nregs = 0;
 733                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
 734                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
 735                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
 736                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
 737                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
 738                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
 739                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
 740                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
 741                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
 742                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
 743                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0);
 744                 if (rctx->chip_class <= R700)
 745                         r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
 746                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
 747                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
 748         }
 749
 750         rctx->vgt.nregs = 0;
 751         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 752         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 753         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 754         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 755         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 756         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 757         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 758         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 759         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 760
 761         if (prim == V_008958_DI_PT_LINELIST)
 762                 ls_mask = 1;
 763         else if (prim == V_008958_DI_PT_LINESTRIP)
 764                 ls_mask = 2;
 765         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 766
 767         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 768                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
 769         } else {
 770                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
 771         }
 772         if (rctx->chip_class <= R700)
 773                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 774         r600_pipe_state_mod_reg(&rctx->vgt,
 775                                 rctx->vs_shader->pa_cl_vs_out_cntl |
 776                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
 777         r600_pipe_state_mod_reg(&rctx->vgt,
 778                                 rctx->pa_cl_clip_cntl |
 779                                 (rctx->vs_shader->shader.clip_dist_write ||
 780                                  rctx->vs_shader->shader.vs_prohibit_ucps ?
 781                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F));
 782
 783         r600_context_pipe_state_set(rctx, &rctx->vgt);
 784
 785         rdraw.db_render_override = dsa->db_render_override;
 786         rdraw.db_render_control = dsa->db_render_control;
 787
 788         /* Emit states. */
 789         r600_need_cs_space(rctx, 0, TRUE);
 790
 791         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 792                 r600_context_block_emit_dirty(rctx, dirty_block);
 793         }
 794         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
 795                 r600_context_block_resource_emit_dirty(rctx, dirty_block);
 796         }
 797         rctx->pm4_dirty_cdwords = 0;
 798
 799         /* Enable stream out if needed. */
 800         if (rctx->streamout_start) {
 801                 r600_context_streamout_begin(rctx);
 802                 rctx->streamout_start = FALSE;
 803         }
 804
 805         if (rctx->chip_class >= EVERGREEN) {
 806                 evergreen_context_draw(rctx, &rdraw);
 807         } else {
 808                 r600_context_draw(rctx, &rdraw);
 809         }
 810
 811         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 812
 813         if (rctx->framebuffer.zsbuf)
 814         {
 815                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 816                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 817         }
 818
 819         pipe_resource_reference(&ib.buffer, NULL);
 820         u_vbuf_draw_end(rctx->vbuf_mgr);
 821 }
 822
 823 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 824                               struct r600_pipe_state *state,
 825                               uint32_t offset, uint32_t value,
 826                               uint32_t range_id, uint32_t block_id,
 827                               struct r600_resource *bo,
 828                               enum radeon_bo_usage usage)
 829 {
 830         struct r600_range *range;
 831         struct r600_block *block;
 832
 833         if (bo) assert(usage);
 834
 835         range = &ctx->range[range_id];
 836         block = range->blocks[block_id];
 837         state->regs[state->nregs].block = block;
 838         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 839
 840         state->regs[state->nregs].value = value;
 841         state->regs[state->nregs].bo = bo;
 842         state->regs[state->nregs].bo_usage = usage;
 843
 844         state->nregs++;
 845         assert(state->nregs < R600_BLOCK_MAX_REG);
 846 }
 847
 848 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 849                                      uint32_t offset, uint32_t value,
 850                                      struct r600_resource *bo,
 851                                      enum radeon_bo_usage usage)
 852 {
 853         if (bo) assert(usage);
 854
 855         state->regs[state->nregs].id = offset;
 856         state->regs[state->nregs].block = NULL;
 857         state->regs[state->nregs].value = value;
 858         state->regs[state->nregs].bo = bo;
 859         state->regs[state->nregs].bo_usage = usage;
 860
 861         state->nregs++;
 862         assert(state->nregs < R600_BLOCK_MAX_REG);
 863 }