2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
30 #include "util/u_draw_quad.h"
31 #include "util/u_upload_mgr.h"
32 #include "tgsi/tgsi_parse.h"
35 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
39 struct radeon_winsys_cs
*cs
= rctx
->cs
;
40 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
42 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
43 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
44 cs
->cdw
+= cb
->atom
.num_dw
;
47 void r600_init_command_buffer(struct r600_context
*rctx
, struct r600_command_buffer
*cb
, unsigned id
, unsigned num_dw
)
49 r600_init_atom(rctx
, &cb
->atom
, id
, r600_emit_command_buffer
, 0);
50 cb
->buf
= CALLOC(1, 4 * num_dw
);
51 cb
->max_num_dw
= num_dw
;
54 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
59 void r600_init_atom(struct r600_context
*rctx
,
60 struct r600_atom
*atom
,
62 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
65 assert(id
< R600_MAX_ATOM
);
66 assert(rctx
->atoms
[id
] == NULL
);
67 rctx
->atoms
[id
] = atom
;
70 atom
->num_dw
= num_dw
;
74 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
76 struct radeon_winsys_cs
*cs
= rctx
->cs
;
77 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
78 unsigned alpha_ref
= a
->sx_alpha_ref
;
80 if (rctx
->chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
84 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
85 a
->sx_alpha_test_control
|
86 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
87 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
90 static void r600_texture_barrier(struct pipe_context
*ctx
)
92 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
94 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
| R600_CONTEXT_TEX_FLUSH
;
97 if (rctx
->chip_class
== R600
) {
98 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
102 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
104 static const int prim_conv
[] = {
105 V_008958_DI_PT_POINTLIST
,
106 V_008958_DI_PT_LINELIST
,
107 V_008958_DI_PT_LINELOOP
,
108 V_008958_DI_PT_LINESTRIP
,
109 V_008958_DI_PT_TRILIST
,
110 V_008958_DI_PT_TRISTRIP
,
111 V_008958_DI_PT_TRIFAN
,
112 V_008958_DI_PT_QUADLIST
,
113 V_008958_DI_PT_QUADSTRIP
,
114 V_008958_DI_PT_POLYGON
,
119 V_008958_DI_PT_RECTLIST
122 *prim
= prim_conv
[pprim
];
124 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
130 /* common state between evergreen and r600 */
132 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
133 struct r600_pipe_blend
*blend
)
135 struct r600_pipe_state
*rstate
;
136 bool update_cb
= false;
138 rstate
= &blend
->rstate
;
139 rctx
->states
[rstate
->id
] = rstate
;
140 r600_context_pipe_state_set(rctx
, rstate
);
142 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
143 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
146 if (rctx
->chip_class
<= R700
&&
147 rctx
->cb_misc_state
.cb_color_control
!= blend
->cb_color_control
) {
148 rctx
->cb_misc_state
.cb_color_control
= blend
->cb_color_control
;
151 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
152 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
156 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
160 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
169 rctx
->alpha_to_one
= blend
->alpha_to_one
;
170 rctx
->dual_src_blend
= blend
->dual_src_blend
;
172 if (!rctx
->blend_override
)
173 r600_bind_blend_state_internal(rctx
, blend
);
176 static void r600_set_blend_color(struct pipe_context
*ctx
,
177 const struct pipe_blend_color
*state
)
179 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
180 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
185 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
186 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
187 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
188 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
189 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
191 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
192 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
193 r600_context_pipe_state_set(rctx
, rstate
);
196 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
197 const struct r600_stencil_ref
*state
)
199 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
200 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
205 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
206 r600_pipe_state_add_reg(rstate
,
207 R_028430_DB_STENCILREFMASK
,
208 S_028430_STENCILREF(state
->ref_value
[0]) |
209 S_028430_STENCILMASK(state
->valuemask
[0]) |
210 S_028430_STENCILWRITEMASK(state
->writemask
[0]));
211 r600_pipe_state_add_reg(rstate
,
212 R_028434_DB_STENCILREFMASK_BF
,
213 S_028434_STENCILREF_BF(state
->ref_value
[1]) |
214 S_028434_STENCILMASK_BF(state
->valuemask
[1]) |
215 S_028434_STENCILWRITEMASK_BF(state
->writemask
[1]));
217 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
218 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
219 r600_context_pipe_state_set(rctx
, rstate
);
222 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
223 const struct pipe_stencil_ref
*state
)
225 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
226 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
227 struct r600_stencil_ref ref
;
229 rctx
->stencil_ref
= *state
;
234 ref
.ref_value
[0] = state
->ref_value
[0];
235 ref
.ref_value
[1] = state
->ref_value
[1];
236 ref
.valuemask
[0] = dsa
->valuemask
[0];
237 ref
.valuemask
[1] = dsa
->valuemask
[1];
238 ref
.writemask
[0] = dsa
->writemask
[0];
239 ref
.writemask
[1] = dsa
->writemask
[1];
241 r600_set_stencil_ref(ctx
, &ref
);
244 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
246 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
247 struct r600_pipe_dsa
*dsa
= state
;
248 struct r600_pipe_state
*rstate
;
249 struct r600_stencil_ref ref
;
253 rstate
= &dsa
->rstate
;
254 rctx
->states
[rstate
->id
] = rstate
;
255 r600_context_pipe_state_set(rctx
, rstate
);
257 ref
.ref_value
[0] = rctx
->stencil_ref
.ref_value
[0];
258 ref
.ref_value
[1] = rctx
->stencil_ref
.ref_value
[1];
259 ref
.valuemask
[0] = dsa
->valuemask
[0];
260 ref
.valuemask
[1] = dsa
->valuemask
[1];
261 ref
.writemask
[0] = dsa
->writemask
[0];
262 ref
.writemask
[1] = dsa
->writemask
[1];
264 r600_set_stencil_ref(ctx
, &ref
);
266 /* Update alphatest state. */
267 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
268 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
269 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
270 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
271 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
275 void r600_set_max_scissor(struct r600_context
*rctx
)
277 /* Set a scissor state such that it doesn't do anything. */
278 struct pipe_scissor_state scissor
;
284 r600_set_scissor_state(rctx
, &scissor
);
287 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
289 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
290 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
295 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
296 rctx
->two_side
= rs
->two_side
;
297 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
298 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
299 rctx
->multisample_enable
= rs
->multisample_enable
;
301 rctx
->rasterizer
= rs
;
303 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
304 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
306 if (rctx
->chip_class
>= EVERGREEN
) {
307 evergreen_polygon_offset_update(rctx
);
309 r600_polygon_offset_update(rctx
);
312 /* Workaround for a missing scissor enable on r600. */
313 if (rctx
->chip_class
== R600
) {
314 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
315 rctx
->scissor_enable
= rs
->scissor_enable
;
317 if (rs
->scissor_enable
) {
318 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
320 r600_set_max_scissor(rctx
);
326 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
328 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
329 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
331 if (rctx
->rasterizer
== rs
) {
332 rctx
->rasterizer
= NULL
;
334 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
335 rctx
->states
[rs
->rstate
.id
] = NULL
;
340 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
341 struct pipe_sampler_view
*state
)
343 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
345 pipe_resource_reference(&state
->texture
, NULL
);
349 void r600_sampler_states_dirty(struct r600_context
*rctx
,
350 struct r600_sampler_states
*state
)
352 if (state
->dirty_mask
) {
353 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
354 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
357 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
358 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
359 r600_atom_dirty(rctx
, &state
->atom
);
363 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
366 unsigned count
, void **states
)
368 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
369 struct r600_textures_info
*dst
;
370 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
371 int seamless_cube_map
= -1;
373 /* This sets 1-bit for states with index >= count. */
374 uint32_t disable_mask
= ~((1ull << count
) - 1);
375 /* These are the new states set by this function. */
376 uint32_t new_mask
= 0;
378 assert(start
== 0); /* XXX fix below */
381 case PIPE_SHADER_VERTEX
:
382 dst
= &rctx
->vs_samplers
;
384 case PIPE_SHADER_FRAGMENT
:
385 dst
= &rctx
->ps_samplers
;
388 debug_error("bad shader in r600_bind_samplers()");
392 for (i
= 0; i
< count
; i
++) {
393 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
395 if (rstate
== dst
->states
.states
[i
]) {
400 if (rstate
->border_color_use
) {
401 dst
->states
.has_bordercolor_mask
|= 1 << i
;
403 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
405 seamless_cube_map
= rstate
->seamless_cube_map
;
409 disable_mask
|= 1 << i
;
413 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
414 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
416 dst
->states
.enabled_mask
&= ~disable_mask
;
417 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
418 dst
->states
.enabled_mask
|= new_mask
;
419 dst
->states
.dirty_mask
|= new_mask
;
420 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
422 r600_sampler_states_dirty(rctx
, &dst
->states
);
424 /* Seamless cubemap state. */
425 if (rctx
->chip_class
<= R700
&&
426 seamless_cube_map
!= -1 &&
427 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
428 /* change in TA_CNTL_AUX need a pipeline flush */
429 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
430 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
431 r600_atom_dirty(rctx
, &rctx
->seamless_cube_map
.atom
);
435 static void r600_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
437 r600_bind_sampler_states(ctx
, PIPE_SHADER_VERTEX
, 0, count
, states
);
440 static void r600_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
442 r600_bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, states
);
445 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
450 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
452 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
453 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
455 if (rctx
->states
[rstate
->id
] == rstate
) {
456 rctx
->states
[rstate
->id
] = NULL
;
458 for (int i
= 0; i
< rstate
->nregs
; i
++) {
459 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
464 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
466 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
467 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
469 rctx
->vertex_elements
= v
;
471 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
472 r600_context_pipe_state_set(rctx
, &v
->rstate
);
476 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
478 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
479 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
481 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
482 rctx
->states
[v
->rstate
.id
] = NULL
;
484 if (rctx
->vertex_elements
== state
)
485 rctx
->vertex_elements
= NULL
;
487 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
491 static void r600_set_index_buffer(struct pipe_context
*ctx
,
492 const struct pipe_index_buffer
*ib
)
494 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
497 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
498 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
500 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
504 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
506 if (rctx
->vertex_buffer_state
.dirty_mask
) {
507 rctx
->flags
|= rctx
->has_vertex_cache
? R600_CONTEXT_VTX_FLUSH
: R600_CONTEXT_TEX_FLUSH
;
508 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 12 : 11) *
509 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
510 r600_atom_dirty(rctx
, &rctx
->vertex_buffer_state
.atom
);
514 static void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
515 const struct pipe_vertex_buffer
*input
)
517 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
518 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
519 struct pipe_vertex_buffer
*vb
= state
->vb
;
521 /* This sets 1-bit for buffers with index >= count. */
522 uint32_t disable_mask
= ~((1ull << count
) - 1);
523 /* These are the new buffers set by this function. */
524 uint32_t new_buffer_mask
= 0;
526 /* Set buffers with index >= count to NULL. */
527 uint32_t remaining_buffers_mask
=
528 rctx
->vertex_buffer_state
.enabled_mask
& disable_mask
;
530 while (remaining_buffers_mask
) {
531 i
= u_bit_scan(&remaining_buffers_mask
);
532 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
535 /* Set vertex buffers. */
536 for (i
= 0; i
< count
; i
++) {
537 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
538 if (input
[i
].buffer
) {
539 vb
[i
].stride
= input
[i
].stride
;
540 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
541 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
542 new_buffer_mask
|= 1 << i
;
544 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
545 disable_mask
|= 1 << i
;
550 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
551 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
552 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
553 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
555 r600_vertex_buffers_dirty(rctx
);
558 void r600_sampler_views_dirty(struct r600_context
*rctx
,
559 struct r600_samplerview_state
*state
)
561 if (state
->dirty_mask
) {
562 rctx
->flags
|= R600_CONTEXT_TEX_FLUSH
;
563 state
->atom
.num_dw
= (rctx
->chip_class
>= EVERGREEN
? 14 : 13) *
564 util_bitcount(state
->dirty_mask
);
565 r600_atom_dirty(rctx
, &state
->atom
);
569 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
570 unsigned start
, unsigned count
,
571 struct pipe_sampler_view
**views
)
573 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
574 struct r600_textures_info
*dst
;
575 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
576 uint32_t dirty_sampler_states_mask
= 0;
578 /* This sets 1-bit for textures with index >= count. */
579 uint32_t disable_mask
= ~((1ull << count
) - 1);
580 /* These are the new textures set by this function. */
581 uint32_t new_mask
= 0;
583 /* Set textures with index >= count to NULL. */
584 uint32_t remaining_mask
;
586 assert(start
== 0); /* XXX fix below */
589 case PIPE_SHADER_VERTEX
:
590 dst
= &rctx
->vs_samplers
;
592 case PIPE_SHADER_FRAGMENT
:
593 dst
= &rctx
->ps_samplers
;
596 debug_error("bad shader in r600_set_sampler_views()");
600 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
602 while (remaining_mask
) {
603 i
= u_bit_scan(&remaining_mask
);
604 assert(dst
->views
.views
[i
]);
606 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
609 for (i
= 0; i
< count
; i
++) {
610 if (rviews
[i
] == dst
->views
.views
[i
]) {
615 struct r600_texture
*rtex
=
616 (struct r600_texture
*)rviews
[i
]->base
.texture
;
618 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
619 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
621 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
624 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
625 if (rctx
->chip_class
!= CAYMAN
&& rtex
->cmask_size
&& rtex
->fmask_size
) {
626 dst
->views
.compressed_colortex_mask
|= 1 << i
;
628 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
631 /* Changing from array to non-arrays textures and vice versa requires
632 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
633 if (rctx
->chip_class
<= R700
&&
634 (dst
->states
.enabled_mask
& (1 << i
)) &&
635 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
636 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
637 dirty_sampler_states_mask
|= 1 << i
;
640 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
643 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
644 disable_mask
|= 1 << i
;
648 dst
->views
.enabled_mask
&= ~disable_mask
;
649 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
650 dst
->views
.enabled_mask
|= new_mask
;
651 dst
->views
.dirty_mask
|= new_mask
;
652 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
653 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
655 r600_sampler_views_dirty(rctx
, &dst
->views
);
657 if (dirty_sampler_states_mask
) {
658 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
659 r600_sampler_states_dirty(rctx
, &dst
->states
);
663 static void r600_set_vs_sampler_views(struct pipe_context
*ctx
, unsigned count
,
664 struct pipe_sampler_view
**views
)
666 r600_set_sampler_views(ctx
, PIPE_SHADER_VERTEX
, 0, count
, views
);
669 static void r600_set_ps_sampler_views(struct pipe_context
*ctx
, unsigned count
,
670 struct pipe_sampler_view
**views
)
672 r600_set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
, 0, count
, views
);
675 static void r600_set_viewport_state(struct pipe_context
*ctx
,
676 const struct pipe_viewport_state
*state
)
678 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
679 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
684 rctx
->viewport
= *state
;
685 rstate
->id
= R600_PIPE_STATE_VIEWPORT
;
686 r600_pipe_state_add_reg(rstate
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
687 r600_pipe_state_add_reg(rstate
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
688 r600_pipe_state_add_reg(rstate
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
689 r600_pipe_state_add_reg(rstate
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
690 r600_pipe_state_add_reg(rstate
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
691 r600_pipe_state_add_reg(rstate
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
693 free(rctx
->states
[R600_PIPE_STATE_VIEWPORT
]);
694 rctx
->states
[R600_PIPE_STATE_VIEWPORT
] = rstate
;
695 r600_context_pipe_state_set(rctx
, rstate
);
698 static void *r600_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
699 const struct pipe_vertex_element
*elements
)
701 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
702 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
709 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
711 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
719 /* Compute the key for the hw shader variant */
720 static INLINE
unsigned r600_shader_selector_key(struct pipe_context
* ctx
,
721 struct r600_pipe_shader_selector
* sel
)
723 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
726 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
727 key
= rctx
->two_side
|
728 ((rctx
->alpha_to_one
&& rctx
->multisample_enable
&& !rctx
->cb0_is_integer
) << 1) |
729 (MIN2(sel
->nr_ps_max_color_exports
, rctx
->nr_cbufs
+ rctx
->dual_src_blend
) << 2);
736 /* Select the hw shader variant depending on the current state.
737 * (*dirty) is set to 1 if current variant was changed */
738 static int r600_shader_select(struct pipe_context
*ctx
,
739 struct r600_pipe_shader_selector
* sel
,
743 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
744 struct r600_pipe_shader
* shader
= NULL
;
747 key
= r600_shader_selector_key(ctx
, sel
);
749 /* Check if we don't need to change anything.
750 * This path is also used for most shaders that don't need multiple
751 * variants, it will cost just a computation of the key and this
753 if (likely(sel
->current
&& sel
->current
->key
== key
)) {
757 /* lookup if we have other variants in the list */
758 if (sel
->num_shaders
> 1) {
759 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
761 while (c
&& c
->key
!= key
) {
767 p
->next_variant
= c
->next_variant
;
772 if (unlikely(!shader
)) {
773 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
774 shader
->selector
= sel
;
776 r
= r600_pipe_shader_create(ctx
, shader
);
778 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
784 /* We don't know the value of nr_ps_max_color_exports until we built
785 * at least one variant, so we may need to recompute the key after
786 * building first variant. */
787 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
788 sel
->num_shaders
== 0) {
789 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
790 key
= r600_shader_selector_key(ctx
, sel
);
800 shader
->next_variant
= sel
->current
;
801 sel
->current
= shader
;
803 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
804 r600_adjust_gprs(rctx
);
807 if (rctx
->ps_shader
&&
808 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
809 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
810 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
815 static void *r600_create_shader_state(struct pipe_context
*ctx
,
816 const struct pipe_shader_state
*state
,
817 unsigned pipe_shader_type
)
819 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
822 sel
->type
= pipe_shader_type
;
823 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
824 sel
->so
= state
->stream_output
;
826 r
= r600_shader_select(ctx
, sel
, NULL
);
833 static void *r600_create_ps_state(struct pipe_context
*ctx
,
834 const struct pipe_shader_state
*state
)
836 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
839 static void *r600_create_vs_state(struct pipe_context
*ctx
,
840 const struct pipe_shader_state
*state
)
842 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
845 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
847 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
850 state
= rctx
->dummy_pixel_shader
;
852 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
853 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
855 if (rctx
->chip_class
<= R700
) {
856 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
858 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
859 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
860 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
864 r600_adjust_gprs(rctx
);
867 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
868 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
869 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
873 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
875 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
877 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
879 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->current
->rstate
);
881 if (rctx
->chip_class
< EVERGREEN
&& rctx
->ps_shader
)
882 r600_adjust_gprs(rctx
);
886 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
887 struct r600_pipe_shader_selector
*sel
)
889 struct r600_pipe_shader
*p
= sel
->current
, *c
;
892 r600_pipe_shader_destroy(ctx
, p
);
902 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
904 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
905 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
907 if (rctx
->ps_shader
== sel
) {
908 rctx
->ps_shader
= NULL
;
911 r600_delete_shader_selector(ctx
, sel
);
914 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
916 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
917 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
919 if (rctx
->vs_shader
== sel
) {
920 rctx
->vs_shader
= NULL
;
923 r600_delete_shader_selector(ctx
, sel
);
926 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
928 if (state
->dirty_mask
) {
929 rctx
->flags
|= R600_CONTEXT_SHADERCONST_FLUSH
;
930 state
->atom
.num_dw
= rctx
->chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
931 : util_bitcount(state
->dirty_mask
)*19;
932 r600_atom_dirty(rctx
, &state
->atom
);
936 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
937 struct pipe_constant_buffer
*input
)
939 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
940 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
941 struct pipe_constant_buffer
*cb
;
944 /* Note that the state tracker can unbind constant buffers by
947 if (unlikely(!input
)) {
948 state
->enabled_mask
&= ~(1 << index
);
949 state
->dirty_mask
&= ~(1 << index
);
950 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
954 cb
= &state
->cb
[index
];
955 cb
->buffer_size
= input
->buffer_size
;
957 ptr
= input
->user_buffer
;
960 /* Upload the user buffer. */
961 if (R600_BIG_ENDIAN
) {
963 unsigned i
, size
= input
->buffer_size
;
965 if (!(tmpPtr
= malloc(size
))) {
966 R600_ERR("Failed to allocate BE swap buffer.\n");
970 for (i
= 0; i
< size
/ 4; ++i
) {
971 tmpPtr
[i
] = bswap_32(((uint32_t *)ptr
)[i
]);
974 u_upload_data(rctx
->uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
977 u_upload_data(rctx
->uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
980 /* Setup the hw buffer. */
981 cb
->buffer_offset
= input
->buffer_offset
;
982 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
985 state
->enabled_mask
|= 1 << index
;
986 state
->dirty_mask
|= 1 << index
;
987 r600_constant_buffers_dirty(rctx
, state
);
990 static struct pipe_stream_output_target
*
991 r600_create_so_target(struct pipe_context
*ctx
,
992 struct pipe_resource
*buffer
,
993 unsigned buffer_offset
,
994 unsigned buffer_size
)
996 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
997 struct r600_so_target
*t
;
1000 t
= CALLOC_STRUCT(r600_so_target
);
1005 t
->b
.reference
.count
= 1;
1007 pipe_resource_reference(&t
->b
.buffer
, buffer
);
1008 t
->b
.buffer_offset
= buffer_offset
;
1009 t
->b
.buffer_size
= buffer_size
;
1011 t
->filled_size
= (struct r600_resource
*)
1012 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
1013 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
1014 memset(ptr
, 0, t
->filled_size
->buf
->size
);
1015 rctx
->ws
->buffer_unmap(t
->filled_size
->cs_buf
);
1020 static void r600_so_target_destroy(struct pipe_context
*ctx
,
1021 struct pipe_stream_output_target
*target
)
1023 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
1024 pipe_resource_reference(&t
->b
.buffer
, NULL
);
1025 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
1029 static void r600_set_so_targets(struct pipe_context
*ctx
,
1030 unsigned num_targets
,
1031 struct pipe_stream_output_target
**targets
,
1032 unsigned append_bitmask
)
1034 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1037 /* Stop streamout. */
1038 if (rctx
->num_so_targets
&& !rctx
->streamout_start
) {
1039 r600_context_streamout_end(rctx
);
1042 /* Set the new targets. */
1043 for (i
= 0; i
< num_targets
; i
++) {
1044 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
1046 for (; i
< rctx
->num_so_targets
; i
++) {
1047 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
1050 rctx
->num_so_targets
= num_targets
;
1051 rctx
->streamout_start
= num_targets
!= 0;
1052 rctx
->streamout_append_bitmask
= append_bitmask
;
1055 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
1057 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
1059 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
1062 rctx
->sample_mask
.sample_mask
= sample_mask
;
1063 r600_atom_dirty(rctx
, &rctx
->sample_mask
.atom
);
1066 static void r600_update_derived_state(struct r600_context
*rctx
)
1068 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1069 unsigned ps_dirty
= 0, blend_override
;
1071 if (!rctx
->blitter
->running
) {
1072 /* Decompress textures if needed. */
1073 if (rctx
->vs_samplers
.views
.compressed_depthtex_mask
) {
1074 r600_decompress_depth_textures(rctx
, &rctx
->vs_samplers
.views
);
1076 if (rctx
->ps_samplers
.views
.compressed_depthtex_mask
) {
1077 r600_decompress_depth_textures(rctx
, &rctx
->ps_samplers
.views
);
1079 if (rctx
->vs_samplers
.views
.compressed_colortex_mask
) {
1080 r600_decompress_color_textures(rctx
, &rctx
->vs_samplers
.views
);
1082 if (rctx
->ps_samplers
.views
.compressed_colortex_mask
) {
1083 r600_decompress_color_textures(rctx
, &rctx
->ps_samplers
.views
);
1087 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1089 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
1090 (rctx
->ps_shader
->current
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
1091 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1093 if (rctx
->chip_class
>= EVERGREEN
)
1094 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1096 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
1102 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->current
->rstate
);
1104 blend_override
= (rctx
->dual_src_blend
&&
1105 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1107 if (blend_override
!= rctx
->blend_override
) {
1108 rctx
->blend_override
= blend_override
;
1109 r600_bind_blend_state_internal(rctx
,
1110 blend_override
? rctx
->no_blend
: rctx
->blend
);
1113 if (rctx
->chip_class
>= EVERGREEN
) {
1114 evergreen_update_dual_export_state(rctx
);
1116 r600_update_dual_export_state(rctx
);
1120 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1122 static const int prim_conv
[] = {
1123 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1124 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1125 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1126 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1127 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1128 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1129 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1130 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1131 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1132 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1133 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1134 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1135 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1136 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1137 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1139 assert(mode
< Elements(prim_conv
));
1141 return prim_conv
[mode
];
1144 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1146 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1147 struct pipe_draw_info info
= *dinfo
;
1148 struct pipe_index_buffer ib
= {};
1149 unsigned prim
, ls_mask
= 0, i
;
1150 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
1151 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1155 if ((!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) ||
1156 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
1161 if (!rctx
->vs_shader
) {
1166 r600_update_derived_state(rctx
);
1169 /* Initialize the index buffer struct. */
1170 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1171 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1172 ib
.index_size
= rctx
->index_buffer
.index_size
;
1173 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1175 /* Translate or upload, if needed. */
1176 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
1178 ptr
= (uint8_t*)ib
.user_buffer
;
1179 if (!ib
.buffer
&& ptr
) {
1180 u_upload_data(rctx
->uploader
, 0, info
.count
* ib
.index_size
,
1181 ptr
, &ib
.offset
, &ib
.buffer
);
1184 info
.index_bias
= info
.start
;
1187 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
1188 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
1189 rctx
->vgt
.nregs
= 0;
1190 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
1191 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0);
1192 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
);
1193 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
);
1194 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
);
1195 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1196 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A0C_PA_SC_LINE_STIPPLE
, 0);
1197 r600_pipe_state_add_reg(&rctx
->vgt
, R_02881C_PA_CL_VS_OUT_CNTL
, 0);
1198 r600_pipe_state_add_reg(&rctx
->vgt
, R_028810_PA_CL_CLIP_CNTL
, 0);
1201 rctx
->vgt
.nregs
= 0;
1202 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
1203 r600_pipe_state_mod_reg(&rctx
->vgt
, r600_conv_prim_to_gs_out(info
.mode
));
1204 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
1205 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
1206 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
1207 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
1209 if (prim
== V_008958_DI_PT_LINELIST
)
1211 else if (prim
== V_008958_DI_PT_LINESTRIP
||
1212 prim
== V_008958_DI_PT_LINELOOP
)
1214 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
1215 r600_pipe_state_mod_reg(&rctx
->vgt
,
1216 rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
|
1217 (rctx
->rasterizer
->clip_plane_enable
& rctx
->vs_shader
->current
->shader
.clip_dist_write
));
1218 r600_pipe_state_mod_reg(&rctx
->vgt
,
1219 rctx
->pa_cl_clip_cntl
|
1220 (rctx
->vs_shader
->current
->shader
.clip_dist_write
||
1221 rctx
->vs_shader
->current
->shader
.vs_prohibit_ucps
?
1222 0 : rctx
->rasterizer
->clip_plane_enable
& 0x3F));
1224 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
1226 /* Enable stream out if needed. */
1227 if (rctx
->streamout_start
) {
1228 r600_context_streamout_begin(rctx
);
1229 rctx
->streamout_start
= FALSE
;
1232 /* Emit states (the function expects that we emit at most 17 dwords here). */
1233 r600_need_cs_space(rctx
, 0, TRUE
);
1234 r600_flush_emit(rctx
);
1236 for (i
= 0; i
< R600_MAX_ATOM
; i
++) {
1237 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1240 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1242 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
1243 r600_context_block_emit_dirty(rctx
, dirty_block
, 0 /* pkt_flags */);
1245 rctx
->pm4_dirty_cdwords
= 0;
1248 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
1249 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1251 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
1252 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1253 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1254 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1256 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
1258 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
1259 cs
->buf
[cs
->cdw
++] = va
;
1260 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1261 cs
->buf
[cs
->cdw
++] = info
.count
;
1262 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1263 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
1264 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1266 if (info
.count_from_stream_output
) {
1267 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1268 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, (void*)t
->filled_size
);
1270 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1272 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1273 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1274 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1275 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1276 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1277 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1279 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1280 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, t
->filled_size
, RADEON_USAGE_READ
);
1283 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
1284 cs
->buf
[cs
->cdw
++] = info
.count
;
1285 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1286 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1289 /* Set the depth buffer as dirty. */
1290 if (rctx
->framebuffer
.zsbuf
) {
1291 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
1292 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1294 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1296 if (rctx
->compressed_cb_mask
) {
1297 struct pipe_surface
*surf
;
1298 struct r600_texture
*rtex
;
1299 unsigned mask
= rctx
->compressed_cb_mask
;
1302 unsigned i
= u_bit_scan(&mask
);
1303 surf
= rctx
->framebuffer
.cbufs
[i
];
1304 rtex
= (struct r600_texture
*)surf
->texture
;
1306 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1311 pipe_resource_reference(&ib
.buffer
, NULL
);
1314 void r600_draw_rectangle(struct blitter_context
*blitter
,
1315 unsigned x1
, unsigned y1
, unsigned x2
, unsigned y2
, float depth
,
1316 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1318 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1319 struct pipe_viewport_state viewport
;
1320 struct pipe_resource
*buf
= NULL
;
1321 unsigned offset
= 0;
1324 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1325 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1329 /* Some operations (like color resolve on r6xx) don't work
1330 * with the conventional primitive types.
1331 * One that works is PT_RECTLIST, which we use here. */
1333 /* setup viewport */
1334 viewport
.scale
[0] = 1.0f
;
1335 viewport
.scale
[1] = 1.0f
;
1336 viewport
.scale
[2] = 1.0f
;
1337 viewport
.scale
[3] = 1.0f
;
1338 viewport
.translate
[0] = 0.0f
;
1339 viewport
.translate
[1] = 0.0f
;
1340 viewport
.translate
[2] = 0.0f
;
1341 viewport
.translate
[3] = 0.0f
;
1342 rctx
->context
.set_viewport_state(&rctx
->context
, &viewport
);
1344 /* Upload vertices. The hw rectangle has only 3 vertices,
1345 * I guess the 4th one is derived from the first 3.
1346 * The vertex specification should match u_blitter's vertex element state. */
1347 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1364 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1365 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1366 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1370 util_draw_vertex_buffer(&rctx
->context
, NULL
, buf
, offset
,
1371 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1372 pipe_resource_reference(&buf
, NULL
);
1375 void _r600_pipe_state_add_reg_bo(struct r600_context
*ctx
,
1376 struct r600_pipe_state
*state
,
1377 uint32_t offset
, uint32_t value
,
1378 uint32_t range_id
, uint32_t block_id
,
1379 struct r600_resource
*bo
,
1380 enum radeon_bo_usage usage
)
1383 struct r600_range
*range
;
1384 struct r600_block
*block
;
1386 if (bo
) assert(usage
);
1388 range
= &ctx
->range
[range_id
];
1389 block
= range
->blocks
[block_id
];
1390 state
->regs
[state
->nregs
].block
= block
;
1391 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
1393 state
->regs
[state
->nregs
].value
= value
;
1394 state
->regs
[state
->nregs
].bo
= bo
;
1395 state
->regs
[state
->nregs
].bo_usage
= usage
;
1398 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1401 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
1402 struct r600_pipe_state
*state
,
1403 uint32_t offset
, uint32_t value
,
1404 uint32_t range_id
, uint32_t block_id
)
1406 _r600_pipe_state_add_reg_bo(ctx
, state
, offset
, value
,
1407 range_id
, block_id
, NULL
, 0);
1410 uint32_t r600_translate_stencil_op(int s_op
)
1413 case PIPE_STENCIL_OP_KEEP
:
1414 return V_028800_STENCIL_KEEP
;
1415 case PIPE_STENCIL_OP_ZERO
:
1416 return V_028800_STENCIL_ZERO
;
1417 case PIPE_STENCIL_OP_REPLACE
:
1418 return V_028800_STENCIL_REPLACE
;
1419 case PIPE_STENCIL_OP_INCR
:
1420 return V_028800_STENCIL_INCR
;
1421 case PIPE_STENCIL_OP_DECR
:
1422 return V_028800_STENCIL_DECR
;
1423 case PIPE_STENCIL_OP_INCR_WRAP
:
1424 return V_028800_STENCIL_INCR_WRAP
;
1425 case PIPE_STENCIL_OP_DECR_WRAP
:
1426 return V_028800_STENCIL_DECR_WRAP
;
1427 case PIPE_STENCIL_OP_INVERT
:
1428 return V_028800_STENCIL_INVERT
;
1430 R600_ERR("Unknown stencil op %d", s_op
);
1437 uint32_t r600_translate_fill(uint32_t func
)
1440 case PIPE_POLYGON_MODE_FILL
:
1442 case PIPE_POLYGON_MODE_LINE
:
1444 case PIPE_POLYGON_MODE_POINT
:
1452 unsigned r600_tex_wrap(unsigned wrap
)
1456 case PIPE_TEX_WRAP_REPEAT
:
1457 return V_03C000_SQ_TEX_WRAP
;
1458 case PIPE_TEX_WRAP_CLAMP
:
1459 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1460 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1461 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1462 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1463 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1464 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1465 return V_03C000_SQ_TEX_MIRROR
;
1466 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1467 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1468 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1469 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1470 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1471 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1475 unsigned r600_tex_filter(unsigned filter
)
1479 case PIPE_TEX_FILTER_NEAREST
:
1480 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1481 case PIPE_TEX_FILTER_LINEAR
:
1482 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1486 unsigned r600_tex_mipfilter(unsigned filter
)
1489 case PIPE_TEX_MIPFILTER_NEAREST
:
1490 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1491 case PIPE_TEX_MIPFILTER_LINEAR
:
1492 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1494 case PIPE_TEX_MIPFILTER_NONE
:
1495 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1499 unsigned r600_tex_compare(unsigned compare
)
1503 case PIPE_FUNC_NEVER
:
1504 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1505 case PIPE_FUNC_LESS
:
1506 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1507 case PIPE_FUNC_EQUAL
:
1508 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1509 case PIPE_FUNC_LEQUAL
:
1510 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1511 case PIPE_FUNC_GREATER
:
1512 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1513 case PIPE_FUNC_NOTEQUAL
:
1514 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1515 case PIPE_FUNC_GEQUAL
:
1516 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1517 case PIPE_FUNC_ALWAYS
:
1518 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1522 /* keep this at the end of this file, please */
1523 void r600_init_common_state_functions(struct r600_context
*rctx
)
1525 rctx
->context
.create_fs_state
= r600_create_ps_state
;
1526 rctx
->context
.create_vs_state
= r600_create_vs_state
;
1527 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
1528 rctx
->context
.bind_blend_state
= r600_bind_blend_state
;
1529 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
1530 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler_states
;
1531 rctx
->context
.bind_fs_state
= r600_bind_ps_state
;
1532 rctx
->context
.bind_rasterizer_state
= r600_bind_rs_state
;
1533 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
1534 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler_states
;
1535 rctx
->context
.bind_vs_state
= r600_bind_vs_state
;
1536 rctx
->context
.delete_blend_state
= r600_delete_state
;
1537 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
1538 rctx
->context
.delete_fs_state
= r600_delete_ps_state
;
1539 rctx
->context
.delete_rasterizer_state
= r600_delete_rs_state
;
1540 rctx
->context
.delete_sampler_state
= r600_delete_sampler_state
;
1541 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
1542 rctx
->context
.delete_vs_state
= r600_delete_vs_state
;
1543 rctx
->context
.set_blend_color
= r600_set_blend_color
;
1544 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
1545 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
1546 rctx
->context
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
1547 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
1548 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
1549 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
1550 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_views
;
1551 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_views
;
1552 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
1553 rctx
->context
.texture_barrier
= r600_texture_barrier
;
1554 rctx
->context
.create_stream_output_target
= r600_create_so_target
;
1555 rctx
->context
.stream_output_target_destroy
= r600_so_target_destroy
;
1556 rctx
->context
.set_stream_output_targets
= r600_set_so_targets
;
1557 rctx
->context
.draw_vbo
= r600_draw_vbo
;