2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "util/u_blitter.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
30 #include "pipebuffer/pb_buffer.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "r600_formats.h"
34 #include "r600_pipe.h"
36 #include "r600_hw_context_priv.h"
38 static void r600_emit_command_buffer(struct r600_context
*rctx
, struct r600_atom
*atom
)
40 struct radeon_winsys_cs
*cs
= rctx
->cs
;
41 struct r600_command_buffer
*cb
= (struct r600_command_buffer
*)atom
;
43 assert(cs
->cdw
+ cb
->atom
.num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
44 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->atom
.num_dw
);
45 cs
->cdw
+= cb
->atom
.num_dw
;
48 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
)
50 cb
->atom
.emit
= r600_emit_command_buffer
;
52 cb
->atom
.flags
= flags
;
53 cb
->buf
= CALLOC(1, 4 * num_dw
);
54 cb
->max_num_dw
= num_dw
;
57 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
62 static void r600_emit_surface_sync(struct r600_context
*rctx
, struct r600_atom
*atom
)
64 struct radeon_winsys_cs
*cs
= rctx
->cs
;
65 struct r600_atom_surface_sync
*a
= (struct r600_atom_surface_sync
*)atom
;
67 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SURFACE_SYNC
, 3, 0);
68 cs
->buf
[cs
->cdw
++] = a
->flush_flags
; /* CP_COHER_CNTL */
69 cs
->buf
[cs
->cdw
++] = 0xffffffff; /* CP_COHER_SIZE */
70 cs
->buf
[cs
->cdw
++] = 0; /* CP_COHER_BASE */
71 cs
->buf
[cs
->cdw
++] = 0x0000000A; /* POLL_INTERVAL */
76 static void r600_emit_r6xx_flush_and_inv(struct r600_context
*rctx
, struct r600_atom
*atom
)
78 struct radeon_winsys_cs
*cs
= rctx
->cs
;
79 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_EVENT_WRITE
, 0, 0);
80 cs
->buf
[cs
->cdw
++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0);
83 void r600_init_atom(struct r600_atom
*atom
,
84 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
85 unsigned num_dw
, enum r600_atom_flags flags
)
88 atom
->num_dw
= num_dw
;
92 void r600_init_common_atoms(struct r600_context
*rctx
)
94 r600_init_atom(&rctx
->atom_surface_sync
.atom
, r600_emit_surface_sync
, 5, EMIT_EARLY
);
95 r600_init_atom(&rctx
->atom_r6xx_flush_and_inv
, r600_emit_r6xx_flush_and_inv
, 2, EMIT_EARLY
);
98 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
)
102 if (rctx
->framebuffer
.nr_cbufs
) {
103 flags
|= S_0085F0_CB_ACTION_ENA(1) |
104 (((1 << rctx
->framebuffer
.nr_cbufs
) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT
);
107 /* Workaround for broken flushing on some R6xx chipsets. */
108 if (rctx
->family
== CHIP_RV670
||
109 rctx
->family
== CHIP_RS780
||
110 rctx
->family
== CHIP_RS880
) {
111 flags
|= S_0085F0_CB1_DEST_BASE_ENA(1) |
112 S_0085F0_DEST_BASE_0_ENA(1);
117 void r600_texture_barrier(struct pipe_context
*ctx
)
119 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
121 rctx
->atom_surface_sync
.flush_flags
|= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx
);
122 r600_atom_dirty(rctx
, &rctx
->atom_surface_sync
.atom
);
125 static bool r600_conv_pipe_prim(unsigned pprim
, unsigned *prim
)
127 static const int prim_conv
[] = {
128 V_008958_DI_PT_POINTLIST
,
129 V_008958_DI_PT_LINELIST
,
130 V_008958_DI_PT_LINELOOP
,
131 V_008958_DI_PT_LINESTRIP
,
132 V_008958_DI_PT_TRILIST
,
133 V_008958_DI_PT_TRISTRIP
,
134 V_008958_DI_PT_TRIFAN
,
135 V_008958_DI_PT_QUADLIST
,
136 V_008958_DI_PT_QUADSTRIP
,
137 V_008958_DI_PT_POLYGON
,
144 *prim
= prim_conv
[pprim
];
146 fprintf(stderr
, "%s:%d unsupported %d\n", __func__
, __LINE__
, pprim
);
152 /* common state between evergreen and r600 */
153 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
155 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
156 struct r600_pipe_blend
*blend
= (struct r600_pipe_blend
*)state
;
157 struct r600_pipe_state
*rstate
;
161 rstate
= &blend
->rstate
;
162 rctx
->states
[rstate
->id
] = rstate
;
163 rctx
->cb_target_mask
= blend
->cb_target_mask
;
165 /* Replace every bit except MULTIWRITE_ENABLE. */
166 rctx
->cb_color_control
&= ~C_028808_MULTIWRITE_ENABLE
;
167 rctx
->cb_color_control
|= blend
->cb_color_control
& C_028808_MULTIWRITE_ENABLE
;
169 r600_context_pipe_state_set(rctx
, rstate
);
172 void r600_set_blend_color(struct pipe_context
*ctx
,
173 const struct pipe_blend_color
*state
)
175 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
176 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
181 rstate
->id
= R600_PIPE_STATE_BLEND_COLOR
;
182 r600_pipe_state_add_reg(rstate
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]), NULL
, 0);
183 r600_pipe_state_add_reg(rstate
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]), NULL
, 0);
184 r600_pipe_state_add_reg(rstate
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]), NULL
, 0);
185 r600_pipe_state_add_reg(rstate
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]), NULL
, 0);
187 free(rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
]);
188 rctx
->states
[R600_PIPE_STATE_BLEND_COLOR
] = rstate
;
189 r600_context_pipe_state_set(rctx
, rstate
);
192 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
193 const struct r600_stencil_ref
*state
)
195 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
196 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
201 rstate
->id
= R600_PIPE_STATE_STENCIL_REF
;
202 r600_pipe_state_add_reg(rstate
,
203 R_028430_DB_STENCILREFMASK
,
204 S_028430_STENCILREF(state
->ref_value
[0]) |
205 S_028430_STENCILMASK(state
->valuemask
[0]) |
206 S_028430_STENCILWRITEMASK(state
->writemask
[0]),
208 r600_pipe_state_add_reg(rstate
,
209 R_028434_DB_STENCILREFMASK_BF
,
210 S_028434_STENCILREF_BF(state
->ref_value
[1]) |
211 S_028434_STENCILMASK_BF(state
->valuemask
[1]) |
212 S_028434_STENCILWRITEMASK_BF(state
->writemask
[1]),
215 free(rctx
->states
[R600_PIPE_STATE_STENCIL_REF
]);
216 rctx
->states
[R600_PIPE_STATE_STENCIL_REF
] = rstate
;
217 r600_context_pipe_state_set(rctx
, rstate
);
220 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
221 const struct pipe_stencil_ref
*state
)
223 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
224 struct r600_pipe_dsa
*dsa
= (struct r600_pipe_dsa
*)rctx
->states
[R600_PIPE_STATE_DSA
];
225 struct r600_stencil_ref ref
;
227 rctx
->stencil_ref
= *state
;
232 ref
.ref_value
[0] = state
->ref_value
[0];
233 ref
.ref_value
[1] = state
->ref_value
[1];
234 ref
.valuemask
[0] = dsa
->valuemask
[0];
235 ref
.valuemask
[1] = dsa
->valuemask
[1];
236 ref
.writemask
[0] = dsa
->writemask
[0];
237 ref
.writemask
[1] = dsa
->writemask
[1];
239 r600_set_stencil_ref(ctx
, &ref
);
242 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
244 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
245 struct r600_pipe_dsa
*dsa
= state
;
246 struct r600_pipe_state
*rstate
;
247 struct r600_stencil_ref ref
;
251 rstate
= &dsa
->rstate
;
252 rctx
->states
[rstate
->id
] = rstate
;
253 rctx
->alpha_ref
= dsa
->alpha_ref
;
254 rctx
->alpha_ref_dirty
= true;
255 r600_context_pipe_state_set(rctx
, rstate
);
257 ref
.ref_value
[0] = rctx
->stencil_ref
.ref_value
[0];
258 ref
.ref_value
[1] = rctx
->stencil_ref
.ref_value
[1];
259 ref
.valuemask
[0] = dsa
->valuemask
[0];
260 ref
.valuemask
[1] = dsa
->valuemask
[1];
261 ref
.writemask
[0] = dsa
->writemask
[0];
262 ref
.writemask
[1] = dsa
->writemask
[1];
264 r600_set_stencil_ref(ctx
, &ref
);
266 if (rctx
->atom_db_misc_state
.flush_depthstencil_enabled
!= dsa
->is_flush
) {
267 rctx
->atom_db_misc_state
.flush_depthstencil_enabled
= dsa
->is_flush
;
268 r600_atom_dirty(rctx
, &rctx
->atom_db_misc_state
.atom
);
272 void r600_set_max_scissor(struct r600_context
*rctx
)
274 /* Set a scissor state such that it doesn't do anything. */
275 struct pipe_scissor_state scissor
;
281 r600_set_scissor_state(rctx
, &scissor
);
284 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
286 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
287 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
292 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
293 rctx
->two_side
= rs
->two_side
;
294 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
295 rctx
->pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
297 rctx
->rasterizer
= rs
;
299 rctx
->states
[rs
->rstate
.id
] = &rs
->rstate
;
300 r600_context_pipe_state_set(rctx
, &rs
->rstate
);
302 if (rctx
->chip_class
>= EVERGREEN
) {
303 evergreen_polygon_offset_update(rctx
);
304 evergreen_set_rasterizer_discard(ctx
, rs
->rasterizer_discard
);
306 r600_polygon_offset_update(rctx
);
309 /* Workaround for a missing scissor enable on r600. */
310 if (rctx
->chip_class
== R600
) {
311 if (rs
->scissor_enable
!= rctx
->scissor_enable
) {
312 rctx
->scissor_enable
= rs
->scissor_enable
;
314 if (rs
->scissor_enable
) {
315 r600_set_scissor_state(rctx
, &rctx
->scissor_state
);
317 r600_set_max_scissor(rctx
);
323 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
325 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
326 struct r600_pipe_rasterizer
*rs
= (struct r600_pipe_rasterizer
*)state
;
328 if (rctx
->rasterizer
== rs
) {
329 rctx
->rasterizer
= NULL
;
331 if (rctx
->states
[rs
->rstate
.id
] == &rs
->rstate
) {
332 rctx
->states
[rs
->rstate
.id
] = NULL
;
337 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
338 struct pipe_sampler_view
*state
)
340 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
342 pipe_resource_reference(&state
->texture
, NULL
);
346 void r600_delete_state(struct pipe_context
*ctx
, void *state
)
348 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
349 struct r600_pipe_state
*rstate
= (struct r600_pipe_state
*)state
;
351 if (rctx
->states
[rstate
->id
] == rstate
) {
352 rctx
->states
[rstate
->id
] = NULL
;
354 for (int i
= 0; i
< rstate
->nregs
; i
++) {
355 pipe_resource_reference((struct pipe_resource
**)&rstate
->regs
[i
].bo
, NULL
);
360 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
362 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
363 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
365 rctx
->vertex_elements
= v
;
367 r600_inval_shader_cache(rctx
);
368 u_vbuf_bind_vertex_elements(rctx
->vbuf_mgr
, state
,
371 rctx
->states
[v
->rstate
.id
] = &v
->rstate
;
372 r600_context_pipe_state_set(rctx
, &v
->rstate
);
376 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
378 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
379 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
381 if (rctx
->states
[v
->rstate
.id
] == &v
->rstate
) {
382 rctx
->states
[v
->rstate
.id
] = NULL
;
384 if (rctx
->vertex_elements
== state
)
385 rctx
->vertex_elements
= NULL
;
387 pipe_resource_reference((struct pipe_resource
**)&v
->fetch_shader
, NULL
);
388 u_vbuf_destroy_vertex_elements(rctx
->vbuf_mgr
, v
->vmgr_elements
);
393 void r600_set_index_buffer(struct pipe_context
*ctx
,
394 const struct pipe_index_buffer
*ib
)
396 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
398 u_vbuf_set_index_buffer(rctx
->vbuf_mgr
, ib
);
401 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
402 const struct pipe_vertex_buffer
*buffers
)
404 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
408 for (i
= 0; i
< count
; i
++) {
409 if (!buffers
[i
].buffer
) {
410 r600_context_pipe_state_set_fs_resource(rctx
, NULL
, i
);
413 for (; i
< rctx
->vbuf_mgr
->nr_real_vertex_buffers
; i
++) {
414 r600_context_pipe_state_set_fs_resource(rctx
, NULL
, i
);
417 u_vbuf_set_vertex_buffers(rctx
->vbuf_mgr
, count
, buffers
);
420 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
422 const struct pipe_vertex_element
*elements
)
424 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
425 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
433 u_vbuf_create_vertex_elements(rctx
->vbuf_mgr
, count
,
434 elements
, v
->elements
);
436 if (r600_vertex_elements_build_fetch_shader(rctx
, v
)) {
444 void *r600_create_shader_state(struct pipe_context
*ctx
,
445 const struct pipe_shader_state
*state
)
447 struct r600_pipe_shader
*shader
= CALLOC_STRUCT(r600_pipe_shader
);
450 shader
->tokens
= tgsi_dup_tokens(state
->tokens
);
451 shader
->so
= state
->stream_output
;
453 r
= r600_pipe_shader_create(ctx
, shader
);
460 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
462 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
465 state
= rctx
->dummy_pixel_shader
;
468 rctx
->ps_shader
= (struct r600_pipe_shader
*)state
;
470 r600_inval_shader_cache(rctx
);
471 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->rstate
);
473 rctx
->cb_color_control
&= C_028808_MULTIWRITE_ENABLE
;
474 rctx
->cb_color_control
|= S_028808_MULTIWRITE_ENABLE(!!rctx
->ps_shader
->shader
.fs_write_all
);
476 if (rctx
->ps_shader
&& rctx
->vs_shader
) {
477 r600_adjust_gprs(rctx
);
481 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
483 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
485 rctx
->vs_shader
= (struct r600_pipe_shader
*)state
;
487 r600_inval_shader_cache(rctx
);
488 r600_context_pipe_state_set(rctx
, &rctx
->vs_shader
->rstate
);
490 if (rctx
->ps_shader
&& rctx
->vs_shader
) {
491 r600_adjust_gprs(rctx
);
495 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
497 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
498 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
500 if (rctx
->ps_shader
== shader
) {
501 rctx
->ps_shader
= NULL
;
504 free(shader
->tokens
);
505 r600_pipe_shader_destroy(ctx
, shader
);
509 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
511 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
512 struct r600_pipe_shader
*shader
= (struct r600_pipe_shader
*)state
;
514 if (rctx
->vs_shader
== shader
) {
515 rctx
->vs_shader
= NULL
;
518 free(shader
->tokens
);
519 r600_pipe_shader_destroy(ctx
, shader
);
523 static void r600_update_alpha_ref(struct r600_context
*rctx
)
526 struct r600_pipe_state rstate
;
528 alpha_ref
= rctx
->alpha_ref
;
530 if (rctx
->export_16bpc
)
531 alpha_ref
&= ~0x1FFF;
532 r600_pipe_state_add_reg(&rstate
, R_028438_SX_ALPHA_REF
, alpha_ref
, NULL
, 0);
534 r600_context_pipe_state_set(rctx
, &rstate
);
535 rctx
->alpha_ref_dirty
= false;
538 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
539 struct pipe_resource
*buffer
)
541 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
542 struct r600_resource
*rbuffer
= r600_resource(buffer
);
543 struct r600_pipe_resource_state
*rstate
;
547 /* Note that the state tracker can unbind constant buffers by
550 if (buffer
== NULL
) {
554 r600_inval_shader_cache(rctx
);
556 r600_upload_const_buffer(rctx
, &rbuffer
, &offset
);
557 va_offset
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
562 case PIPE_SHADER_VERTEX
:
563 rctx
->vs_const_buffer
.nregs
= 0;
564 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
565 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
+ index
* 4,
566 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
568 r600_pipe_state_add_reg(&rctx
->vs_const_buffer
,
569 R_028980_ALU_CONST_CACHE_VS_0
+ index
* 4,
570 va_offset
, rbuffer
, RADEON_USAGE_READ
);
571 r600_context_pipe_state_set(rctx
, &rctx
->vs_const_buffer
);
573 rstate
= &rctx
->vs_const_buffer_resource
[index
];
575 if (rctx
->chip_class
>= EVERGREEN
) {
576 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
578 r600_pipe_init_buffer_resource(rctx
, rstate
);
582 if (rctx
->chip_class
>= EVERGREEN
) {
583 evergreen_pipe_mod_buffer_resource(ctx
, rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
585 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
587 r600_context_pipe_state_set_vs_resource(rctx
, rstate
, index
);
589 case PIPE_SHADER_FRAGMENT
:
590 rctx
->ps_const_buffer
.nregs
= 0;
591 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
592 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
593 ALIGN_DIVUP(buffer
->width0
>> 4, 16),
595 r600_pipe_state_add_reg(&rctx
->ps_const_buffer
,
596 R_028940_ALU_CONST_CACHE_PS_0
,
597 va_offset
, rbuffer
, RADEON_USAGE_READ
);
598 r600_context_pipe_state_set(rctx
, &rctx
->ps_const_buffer
);
600 rstate
= &rctx
->ps_const_buffer_resource
[index
];
602 if (rctx
->chip_class
>= EVERGREEN
) {
603 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
605 r600_pipe_init_buffer_resource(rctx
, rstate
);
608 if (rctx
->chip_class
>= EVERGREEN
) {
609 evergreen_pipe_mod_buffer_resource(ctx
, rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
611 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, 16, RADEON_USAGE_READ
);
613 r600_context_pipe_state_set_ps_resource(rctx
, rstate
, index
);
616 R600_ERR("unsupported %d\n", shader
);
620 if (buffer
!= &rbuffer
->b
.b
.b
)
621 pipe_resource_reference((struct pipe_resource
**)&rbuffer
, NULL
);
624 struct pipe_stream_output_target
*
625 r600_create_so_target(struct pipe_context
*ctx
,
626 struct pipe_resource
*buffer
,
627 unsigned buffer_offset
,
628 unsigned buffer_size
)
630 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
631 struct r600_so_target
*t
;
634 t
= CALLOC_STRUCT(r600_so_target
);
639 t
->b
.reference
.count
= 1;
641 pipe_resource_reference(&t
->b
.buffer
, buffer
);
642 t
->b
.buffer_offset
= buffer_offset
;
643 t
->b
.buffer_size
= buffer_size
;
645 t
->filled_size
= (struct r600_resource
*)
646 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_STATIC
, 4);
647 ptr
= rctx
->ws
->buffer_map(t
->filled_size
->buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
648 memset(ptr
, 0, t
->filled_size
->buf
->size
);
649 rctx
->ws
->buffer_unmap(t
->filled_size
->buf
);
654 void r600_so_target_destroy(struct pipe_context
*ctx
,
655 struct pipe_stream_output_target
*target
)
657 struct r600_so_target
*t
= (struct r600_so_target
*)target
;
658 pipe_resource_reference(&t
->b
.buffer
, NULL
);
659 pipe_resource_reference((struct pipe_resource
**)&t
->filled_size
, NULL
);
663 void r600_set_so_targets(struct pipe_context
*ctx
,
664 unsigned num_targets
,
665 struct pipe_stream_output_target
**targets
,
666 unsigned append_bitmask
)
668 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
671 /* Stop streamout. */
672 if (rctx
->num_so_targets
) {
673 r600_context_streamout_end(rctx
);
676 /* Set the new targets. */
677 for (i
= 0; i
< num_targets
; i
++) {
678 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], targets
[i
]);
680 for (; i
< rctx
->num_so_targets
; i
++) {
681 pipe_so_target_reference((struct pipe_stream_output_target
**)&rctx
->so_targets
[i
], NULL
);
684 rctx
->num_so_targets
= num_targets
;
685 rctx
->streamout_start
= num_targets
!= 0;
686 rctx
->streamout_append_bitmask
= append_bitmask
;
689 static void r600_vertex_buffer_update(struct r600_context
*rctx
)
691 struct r600_pipe_resource_state
*rstate
;
692 struct r600_resource
*rbuffer
;
693 struct pipe_vertex_buffer
*vertex_buffer
;
694 unsigned i
, count
, offset
;
696 r600_inval_vertex_cache(rctx
);
698 if (rctx
->vertex_elements
->vbuffer_need_offset
) {
699 /* one resource per vertex elements */
700 count
= rctx
->vertex_elements
->count
;
702 /* bind vertex buffer once */
703 count
= rctx
->vbuf_mgr
->nr_real_vertex_buffers
;
706 for (i
= 0 ; i
< count
; i
++) {
707 rstate
= &rctx
->fs_resource
[i
];
709 if (rctx
->vertex_elements
->vbuffer_need_offset
) {
710 /* one resource per vertex elements */
711 unsigned vbuffer_index
;
712 vbuffer_index
= rctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
713 vertex_buffer
= &rctx
->vbuf_mgr
->real_vertex_buffer
[vbuffer_index
];
714 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
715 offset
= rctx
->vertex_elements
->vbuffer_offset
[i
];
717 /* bind vertex buffer once */
718 vertex_buffer
= &rctx
->vbuf_mgr
->real_vertex_buffer
[i
];
719 rbuffer
= (struct r600_resource
*)vertex_buffer
->buffer
;
722 if (vertex_buffer
== NULL
|| rbuffer
== NULL
)
724 offset
+= vertex_buffer
->buffer_offset
;
727 if (rctx
->chip_class
>= EVERGREEN
) {
728 evergreen_pipe_init_buffer_resource(rctx
, rstate
);
730 r600_pipe_init_buffer_resource(rctx
, rstate
);
734 if (rctx
->chip_class
>= EVERGREEN
) {
735 evergreen_pipe_mod_buffer_resource(&rctx
->context
, rstate
, rbuffer
, offset
, vertex_buffer
->stride
, RADEON_USAGE_READ
);
737 r600_pipe_mod_buffer_resource(rstate
, rbuffer
, offset
, vertex_buffer
->stride
, RADEON_USAGE_READ
);
739 r600_context_pipe_state_set_fs_resource(rctx
, rstate
, i
);
743 static int r600_shader_rebuild(struct pipe_context
* ctx
, struct r600_pipe_shader
* shader
)
745 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
748 r600_pipe_shader_destroy(ctx
, shader
);
749 r
= r600_pipe_shader_create(ctx
, shader
);
753 r600_context_pipe_state_set(rctx
, &shader
->rstate
);
758 static void r600_update_derived_state(struct r600_context
*rctx
)
760 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
761 struct r600_pipe_state rstate
;
766 r600_context_pipe_state_set(rctx
, &rstate
);
768 if (!rctx
->blitter
->running
) {
769 if (rctx
->have_depth_fb
|| rctx
->have_depth_texture
)
770 r600_flush_depth_textures(rctx
);
773 if (rctx
->chip_class
< EVERGREEN
) {
774 r600_update_sampler_states(rctx
);
777 if ((rctx
->ps_shader
->shader
.two_side
!= rctx
->two_side
) ||
778 ((rctx
->chip_class
>= EVERGREEN
) && rctx
->ps_shader
->shader
.fs_write_all
&&
779 (rctx
->ps_shader
->shader
.nr_cbufs
!= rctx
->nr_cbufs
))) {
780 r600_shader_rebuild(&rctx
->context
, rctx
->ps_shader
);
783 if (rctx
->alpha_ref_dirty
) {
784 r600_update_alpha_ref(rctx
);
787 if (rctx
->ps_shader
&& ((rctx
->sprite_coord_enable
&&
788 (rctx
->ps_shader
->sprite_coord_enable
!= rctx
->sprite_coord_enable
)) ||
789 (rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->flatshade
))) {
791 if (rctx
->chip_class
>= EVERGREEN
)
792 evergreen_pipe_shader_ps(ctx
, rctx
->ps_shader
);
794 r600_pipe_shader_ps(ctx
, rctx
->ps_shader
);
796 r600_context_pipe_state_set(rctx
, &rctx
->ps_shader
->rstate
);
801 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
803 static const int prim_conv
[] = {
804 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
805 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
806 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
807 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
808 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
809 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
810 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
811 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
812 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
813 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
814 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
815 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
816 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
817 V_028A6C_OUTPRIM_TYPE_TRISTRIP
819 assert(mode
< Elements(prim_conv
));
821 return prim_conv
[mode
];
824 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
826 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
827 struct pipe_draw_info info
= *dinfo
;
828 struct pipe_index_buffer ib
= {};
829 unsigned prim
, mask
, ls_mask
= 0;
830 struct r600_block
*dirty_block
= NULL
, *next_block
= NULL
;
831 struct r600_atom
*state
= NULL
, *next_state
= NULL
;
832 struct radeon_winsys_cs
*cs
= rctx
->cs
;
835 if ((!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) ||
836 (info
.indexed
&& !rctx
->vbuf_mgr
->index_buffer
.buffer
) ||
837 !r600_conv_pipe_prim(info
.mode
, &prim
)) {
842 if (!rctx
->vs_shader
) {
847 r600_update_derived_state(rctx
);
849 u_vbuf_draw_begin(rctx
->vbuf_mgr
, &info
);
850 r600_vertex_buffer_update(rctx
);
853 /* Initialize the index buffer struct. */
854 pipe_resource_reference(&ib
.buffer
, rctx
->vbuf_mgr
->index_buffer
.buffer
);
855 ib
.index_size
= rctx
->vbuf_mgr
->index_buffer
.index_size
;
856 ib
.offset
= rctx
->vbuf_mgr
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
858 /* Translate or upload, if needed. */
859 r600_translate_index_buffer(rctx
, &ib
, info
.count
);
861 if (u_vbuf_resource(ib
.buffer
)->user_ptr
) {
862 r600_upload_index_buffer(rctx
, &ib
, info
.count
);
865 info
.index_bias
= info
.start
;
866 if (info
.count_from_stream_output
) {
867 r600_context_draw_opaque_count(rctx
, (struct r600_so_target
*)info
.count_from_stream_output
);
871 mask
= (1ULL << ((unsigned)rctx
->framebuffer
.nr_cbufs
* 4)) - 1;
873 if (rctx
->vgt
.id
!= R600_PIPE_STATE_VGT
) {
874 rctx
->vgt
.id
= R600_PIPE_STATE_VGT
;
876 r600_pipe_state_add_reg(&rctx
->vgt
, R_008958_VGT_PRIMITIVE_TYPE
, prim
, NULL
, 0);
877 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, 0, NULL
, 0);
878 r600_pipe_state_add_reg(&rctx
->vgt
, R_028238_CB_TARGET_MASK
, rctx
->cb_target_mask
& mask
, NULL
, 0);
879 r600_pipe_state_add_reg(&rctx
->vgt
, R_028408_VGT_INDX_OFFSET
, info
.index_bias
, NULL
, 0);
880 r600_pipe_state_add_reg(&rctx
->vgt
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
.restart_index
, NULL
, 0);
881 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
.primitive_restart
, NULL
, 0);
882 r600_pipe_state_add_reg(&rctx
->vgt
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
, NULL
, 0);
883 r600_pipe_state_add_reg(&rctx
->vgt
, R_028A0C_PA_SC_LINE_STIPPLE
, 0, NULL
, 0);
884 if (rctx
->chip_class
<= R700
)
885 r600_pipe_state_add_reg(&rctx
->vgt
, R_028808_CB_COLOR_CONTROL
, rctx
->cb_color_control
, NULL
, 0);
886 r600_pipe_state_add_reg(&rctx
->vgt
, R_02881C_PA_CL_VS_OUT_CNTL
, 0, NULL
, 0);
887 r600_pipe_state_add_reg(&rctx
->vgt
, R_028810_PA_CL_CLIP_CNTL
, 0, NULL
, 0);
891 r600_pipe_state_mod_reg(&rctx
->vgt
, prim
);
892 r600_pipe_state_mod_reg(&rctx
->vgt
, r600_conv_prim_to_gs_out(info
.mode
));
893 r600_pipe_state_mod_reg(&rctx
->vgt
, rctx
->cb_target_mask
& mask
);
894 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.index_bias
);
895 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.restart_index
);
896 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.primitive_restart
);
897 r600_pipe_state_mod_reg(&rctx
->vgt
, info
.start_instance
);
899 if (prim
== V_008958_DI_PT_LINELIST
)
901 else if (prim
== V_008958_DI_PT_LINESTRIP
)
903 r600_pipe_state_mod_reg(&rctx
->vgt
, S_028A0C_AUTO_RESET_CNTL(ls_mask
) | rctx
->pa_sc_line_stipple
);
904 if (rctx
->chip_class
<= R700
)
905 r600_pipe_state_mod_reg(&rctx
->vgt
, rctx
->cb_color_control
);
906 r600_pipe_state_mod_reg(&rctx
->vgt
,
907 rctx
->vs_shader
->pa_cl_vs_out_cntl
|
908 (rctx
->rasterizer
->clip_plane_enable
& rctx
->vs_shader
->shader
.clip_dist_write
));
909 r600_pipe_state_mod_reg(&rctx
->vgt
,
910 rctx
->pa_cl_clip_cntl
|
911 (rctx
->vs_shader
->shader
.clip_dist_write
||
912 rctx
->vs_shader
->shader
.vs_prohibit_ucps
?
913 0 : rctx
->rasterizer
->clip_plane_enable
& 0x3F));
915 r600_context_pipe_state_set(rctx
, &rctx
->vgt
);
917 /* Emit states (the function expects that we emit at most 17 dwords here). */
918 r600_need_cs_space(rctx
, 0, TRUE
);
920 LIST_FOR_EACH_ENTRY_SAFE(state
, next_state
, &rctx
->dirty_states
, head
) {
921 r600_emit_atom(rctx
, state
);
923 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->dirty
,list
) {
924 r600_context_block_emit_dirty(rctx
, dirty_block
);
926 LIST_FOR_EACH_ENTRY_SAFE(dirty_block
, next_block
, &rctx
->resource_dirty
,list
) {
927 r600_context_block_resource_emit_dirty(rctx
, dirty_block
);
929 rctx
->pm4_dirty_cdwords
= 0;
931 /* Enable stream out if needed. */
932 if (rctx
->streamout_start
) {
933 r600_context_streamout_begin(rctx
);
934 rctx
->streamout_start
= FALSE
;
938 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->predicate_drawing
);
939 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
940 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
941 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
942 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->predicate_drawing
);
943 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
945 va
= r600_resource_va(ctx
->screen
, ib
.buffer
);
947 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->predicate_drawing
);
948 cs
->buf
[cs
->cdw
++] = va
;
949 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
950 cs
->buf
[cs
->cdw
++] = info
.count
;
951 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
952 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->predicate_drawing
);
953 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(rctx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
955 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->predicate_drawing
);
956 cs
->buf
[cs
->cdw
++] = info
.count
;
957 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
958 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
961 rctx
->flags
|= R600_CONTEXT_DST_CACHES_DIRTY
| R600_CONTEXT_DRAW_PENDING
;
963 if (rctx
->framebuffer
.zsbuf
)
965 struct pipe_resource
*tex
= rctx
->framebuffer
.zsbuf
->texture
;
966 ((struct r600_resource_texture
*)tex
)->dirty_db
= TRUE
;
969 pipe_resource_reference(&ib
.buffer
, NULL
);
970 u_vbuf_draw_end(rctx
->vbuf_mgr
);
973 void _r600_pipe_state_add_reg(struct r600_context
*ctx
,
974 struct r600_pipe_state
*state
,
975 uint32_t offset
, uint32_t value
,
976 uint32_t range_id
, uint32_t block_id
,
977 struct r600_resource
*bo
,
978 enum radeon_bo_usage usage
)
980 struct r600_range
*range
;
981 struct r600_block
*block
;
983 if (bo
) assert(usage
);
985 range
= &ctx
->range
[range_id
];
986 block
= range
->blocks
[block_id
];
987 state
->regs
[state
->nregs
].block
= block
;
988 state
->regs
[state
->nregs
].id
= (offset
- block
->start_offset
) >> 2;
990 state
->regs
[state
->nregs
].value
= value
;
991 state
->regs
[state
->nregs
].bo
= bo
;
992 state
->regs
[state
->nregs
].bo_usage
= usage
;
995 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
998 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state
*state
,
999 uint32_t offset
, uint32_t value
,
1000 struct r600_resource
*bo
,
1001 enum radeon_bo_usage usage
)
1003 if (bo
) assert(usage
);
1005 state
->regs
[state
->nregs
].id
= offset
;
1006 state
->regs
[state
->nregs
].block
= NULL
;
1007 state
->regs
[state
->nregs
].value
= value
;
1008 state
->regs
[state
->nregs
].bo
= bo
;
1009 state
->regs
[state
->nregs
].bo_usage
= usage
;
1012 assert(state
->nregs
< R600_BLOCK_MAX_REG
);
1015 uint32_t r600_translate_stencil_op(int s_op
)
1018 case PIPE_STENCIL_OP_KEEP
:
1019 return V_028800_STENCIL_KEEP
;
1020 case PIPE_STENCIL_OP_ZERO
:
1021 return V_028800_STENCIL_ZERO
;
1022 case PIPE_STENCIL_OP_REPLACE
:
1023 return V_028800_STENCIL_REPLACE
;
1024 case PIPE_STENCIL_OP_INCR
:
1025 return V_028800_STENCIL_INCR
;
1026 case PIPE_STENCIL_OP_DECR
:
1027 return V_028800_STENCIL_DECR
;
1028 case PIPE_STENCIL_OP_INCR_WRAP
:
1029 return V_028800_STENCIL_INCR_WRAP
;
1030 case PIPE_STENCIL_OP_DECR_WRAP
:
1031 return V_028800_STENCIL_DECR_WRAP
;
1032 case PIPE_STENCIL_OP_INVERT
:
1033 return V_028800_STENCIL_INVERT
;
1035 R600_ERR("Unknown stencil op %d", s_op
);
1042 uint32_t r600_translate_fill(uint32_t func
)
1045 case PIPE_POLYGON_MODE_FILL
:
1047 case PIPE_POLYGON_MODE_LINE
:
1049 case PIPE_POLYGON_MODE_POINT
:
1057 unsigned r600_tex_wrap(unsigned wrap
)
1061 case PIPE_TEX_WRAP_REPEAT
:
1062 return V_03C000_SQ_TEX_WRAP
;
1063 case PIPE_TEX_WRAP_CLAMP
:
1064 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1065 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1066 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1067 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1068 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1069 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1070 return V_03C000_SQ_TEX_MIRROR
;
1071 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1072 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1073 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1074 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1075 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1076 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1080 unsigned r600_tex_filter(unsigned filter
)
1084 case PIPE_TEX_FILTER_NEAREST
:
1085 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1086 case PIPE_TEX_FILTER_LINEAR
:
1087 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1091 unsigned r600_tex_mipfilter(unsigned filter
)
1094 case PIPE_TEX_MIPFILTER_NEAREST
:
1095 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1096 case PIPE_TEX_MIPFILTER_LINEAR
:
1097 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1099 case PIPE_TEX_MIPFILTER_NONE
:
1100 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1104 unsigned r600_tex_compare(unsigned compare
)
1108 case PIPE_FUNC_NEVER
:
1109 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1110 case PIPE_FUNC_LESS
:
1111 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1112 case PIPE_FUNC_EQUAL
:
1113 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1114 case PIPE_FUNC_LEQUAL
:
1115 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1116 case PIPE_FUNC_GREATER
:
1117 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1118 case PIPE_FUNC_NOTEQUAL
:
1119 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1120 case PIPE_FUNC_GEQUAL
:
1121 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1122 case PIPE_FUNC_ALWAYS
:
1123 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;