r600g: put user indices in the command stream for small index counts
[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600d.h"
29
30 #include "util/u_draw_quad.h"
31 #include "util/u_index_modify.h"
32 #include "util/u_upload_mgr.h"
33 #include "tgsi/tgsi_parse.h"
34 #include <byteswap.h>
35
36 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
39 {
40 cb->buf = CALLOC(1, 4 * num_dw);
41 cb->max_num_dw = num_dw;
42 }
43
44 void r600_release_command_buffer(struct r600_command_buffer *cb)
45 {
46 FREE(cb->buf);
47 }
48
49 void r600_init_atom(struct r600_context *rctx,
50 struct r600_atom *atom,
51 unsigned id,
52 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
53 unsigned num_dw)
54 {
55 assert(id < R600_NUM_ATOMS);
56 assert(rctx->atoms[id] == NULL);
57 rctx->atoms[id] = atom;
58 atom->id = id;
59 atom->emit = emit;
60 atom->num_dw = num_dw;
61 atom->dirty = false;
62 }
63
64 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
65 {
66 r600_emit_command_buffer(rctx->cs, ((struct r600_cso_state*)atom)->cb);
67 }
68
69 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
70 {
71 struct radeon_winsys_cs *cs = rctx->cs;
72 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
73 unsigned alpha_ref = a->sx_alpha_ref;
74
75 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
76 alpha_ref &= ~0x1FFF;
77 }
78
79 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
80 a->sx_alpha_test_control |
81 S_028410_ALPHA_TEST_BYPASS(a->bypass));
82 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
83 }
84
85 static void r600_texture_barrier(struct pipe_context *ctx)
86 {
87 struct r600_context *rctx = (struct r600_context *)ctx;
88
89 rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
90
91 /* R6xx errata */
92 if (rctx->chip_class == R600) {
93 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
94 }
95 }
96
97 static unsigned r600_conv_pipe_prim(unsigned prim)
98 {
99 static const unsigned prim_conv[] = {
100 V_008958_DI_PT_POINTLIST,
101 V_008958_DI_PT_LINELIST,
102 V_008958_DI_PT_LINELOOP,
103 V_008958_DI_PT_LINESTRIP,
104 V_008958_DI_PT_TRILIST,
105 V_008958_DI_PT_TRISTRIP,
106 V_008958_DI_PT_TRIFAN,
107 V_008958_DI_PT_QUADLIST,
108 V_008958_DI_PT_QUADSTRIP,
109 V_008958_DI_PT_POLYGON,
110 V_008958_DI_PT_LINELIST_ADJ,
111 V_008958_DI_PT_LINESTRIP_ADJ,
112 V_008958_DI_PT_TRILIST_ADJ,
113 V_008958_DI_PT_TRISTRIP_ADJ,
114 V_008958_DI_PT_RECTLIST
115 };
116 return prim_conv[prim];
117 }
118
119 /* common state between evergreen and r600 */
120
121 static void r600_bind_blend_state_internal(struct r600_context *rctx,
122 struct r600_blend_state *blend, bool blend_disable)
123 {
124 unsigned color_control;
125 bool update_cb = false;
126
127 rctx->alpha_to_one = blend->alpha_to_one;
128 rctx->dual_src_blend = blend->dual_src_blend;
129
130 if (!blend_disable) {
131 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
132 color_control = blend->cb_color_control;
133 } else {
134 /* Blending is disabled. */
135 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
136 color_control = blend->cb_color_control_no_blend;
137 }
138
139 /* Update derived states. */
140 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
141 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
142 update_cb = true;
143 }
144 if (rctx->chip_class <= R700 &&
145 rctx->cb_misc_state.cb_color_control != color_control) {
146 rctx->cb_misc_state.cb_color_control = color_control;
147 update_cb = true;
148 }
149 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
150 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
151 update_cb = true;
152 }
153 if (update_cb) {
154 rctx->cb_misc_state.atom.dirty = true;
155 }
156 }
157
158 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
159 {
160 struct r600_context *rctx = (struct r600_context *)ctx;
161 struct r600_blend_state *blend = (struct r600_blend_state *)state;
162
163 if (blend == NULL)
164 return;
165
166 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
167 }
168
169 static void r600_set_blend_color(struct pipe_context *ctx,
170 const struct pipe_blend_color *state)
171 {
172 struct r600_context *rctx = (struct r600_context *)ctx;
173
174 rctx->blend_color.state = *state;
175 rctx->blend_color.atom.dirty = true;
176 }
177
178 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
179 {
180 struct radeon_winsys_cs *cs = rctx->cs;
181 struct pipe_blend_color *state = &rctx->blend_color.state;
182
183 r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
184 r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
185 r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
186 r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
187 r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
188 }
189
190 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
191 {
192 struct radeon_winsys_cs *cs = rctx->cs;
193 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
194
195 r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
196 r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
197 }
198
199 void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
200 {
201 struct radeon_winsys_cs *cs = rctx->cs;
202 struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
203
204 r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
205 }
206
207 static void r600_set_clip_state(struct pipe_context *ctx,
208 const struct pipe_clip_state *state)
209 {
210 struct r600_context *rctx = (struct r600_context *)ctx;
211 struct pipe_constant_buffer cb;
212
213 rctx->clip_state.state = *state;
214 rctx->clip_state.atom.dirty = true;
215
216 cb.buffer = NULL;
217 cb.user_buffer = state->ucp;
218 cb.buffer_offset = 0;
219 cb.buffer_size = 4*4*8;
220 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
221 pipe_resource_reference(&cb.buffer, NULL);
222 }
223
224 static void r600_set_stencil_ref(struct pipe_context *ctx,
225 const struct r600_stencil_ref *state)
226 {
227 struct r600_context *rctx = (struct r600_context *)ctx;
228
229 rctx->stencil_ref.state = *state;
230 rctx->stencil_ref.atom.dirty = true;
231 }
232
233 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
234 {
235 struct radeon_winsys_cs *cs = rctx->cs;
236 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
237
238 r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
239 r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
240 S_028430_STENCILREF(a->state.ref_value[0]) |
241 S_028430_STENCILMASK(a->state.valuemask[0]) |
242 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
243 r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
244 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
245 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
246 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
247 }
248
249 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
250 const struct pipe_stencil_ref *state)
251 {
252 struct r600_context *rctx = (struct r600_context *)ctx;
253 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
254 struct r600_stencil_ref ref;
255
256 rctx->stencil_ref.pipe_state = *state;
257
258 if (!dsa)
259 return;
260
261 ref.ref_value[0] = state->ref_value[0];
262 ref.ref_value[1] = state->ref_value[1];
263 ref.valuemask[0] = dsa->valuemask[0];
264 ref.valuemask[1] = dsa->valuemask[1];
265 ref.writemask[0] = dsa->writemask[0];
266 ref.writemask[1] = dsa->writemask[1];
267
268 r600_set_stencil_ref(ctx, &ref);
269 }
270
271 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
272 {
273 struct r600_context *rctx = (struct r600_context *)ctx;
274 struct r600_dsa_state *dsa = state;
275 struct r600_stencil_ref ref;
276
277 if (state == NULL)
278 return;
279
280 r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
281
282 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
283 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
284 ref.valuemask[0] = dsa->valuemask[0];
285 ref.valuemask[1] = dsa->valuemask[1];
286 ref.writemask[0] = dsa->writemask[0];
287 ref.writemask[1] = dsa->writemask[1];
288
289 r600_set_stencil_ref(ctx, &ref);
290
291 /* Update alphatest state. */
292 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
293 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
294 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
295 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
296 rctx->alphatest_state.atom.dirty = true;
297 }
298 }
299
300 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
301 {
302 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
303 struct r600_context *rctx = (struct r600_context *)ctx;
304
305 if (state == NULL)
306 return;
307
308 rctx->rasterizer = rs;
309
310 r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
311
312 if (rs->offset_enable &&
313 (rs->offset_units != rctx->poly_offset_state.offset_units ||
314 rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
315 rctx->poly_offset_state.offset_units = rs->offset_units;
316 rctx->poly_offset_state.offset_scale = rs->offset_scale;
317 rctx->poly_offset_state.atom.dirty = true;
318 }
319
320 /* Update clip_misc_state. */
321 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
322 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
323 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
324 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
325 rctx->clip_misc_state.atom.dirty = true;
326 }
327
328 /* Workaround for a missing scissor enable on r600. */
329 if (rctx->chip_class == R600 &&
330 rs->scissor_enable != rctx->scissor.enable) {
331 rctx->scissor.enable = rs->scissor_enable;
332 rctx->scissor.atom.dirty = true;
333 }
334
335 /* Re-emit PA_SC_LINE_STIPPLE. */
336 rctx->last_primitive_type = -1;
337 }
338
339 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
340 {
341 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
342
343 r600_release_command_buffer(&rs->buffer);
344 FREE(rs);
345 }
346
347 static void r600_sampler_view_destroy(struct pipe_context *ctx,
348 struct pipe_sampler_view *state)
349 {
350 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
351
352 pipe_resource_reference(&state->texture, NULL);
353 FREE(resource);
354 }
355
356 void r600_sampler_states_dirty(struct r600_context *rctx,
357 struct r600_sampler_states *state)
358 {
359 if (state->dirty_mask) {
360 if (state->dirty_mask & state->has_bordercolor_mask) {
361 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
362 }
363 state->atom.num_dw =
364 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
365 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
366 state->atom.dirty = true;
367 }
368 }
369
370 static void r600_bind_sampler_states(struct pipe_context *pipe,
371 unsigned shader,
372 unsigned start,
373 unsigned count, void **states)
374 {
375 struct r600_context *rctx = (struct r600_context *)pipe;
376 struct r600_textures_info *dst = &rctx->samplers[shader];
377 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
378 int seamless_cube_map = -1;
379 unsigned i;
380 /* This sets 1-bit for states with index >= count. */
381 uint32_t disable_mask = ~((1ull << count) - 1);
382 /* These are the new states set by this function. */
383 uint32_t new_mask = 0;
384
385 assert(start == 0); /* XXX fix below */
386
387 for (i = 0; i < count; i++) {
388 struct r600_pipe_sampler_state *rstate = rstates[i];
389
390 if (rstate == dst->states.states[i]) {
391 continue;
392 }
393
394 if (rstate) {
395 if (rstate->border_color_use) {
396 dst->states.has_bordercolor_mask |= 1 << i;
397 } else {
398 dst->states.has_bordercolor_mask &= ~(1 << i);
399 }
400 seamless_cube_map = rstate->seamless_cube_map;
401
402 new_mask |= 1 << i;
403 } else {
404 disable_mask |= 1 << i;
405 }
406 }
407
408 memcpy(dst->states.states, rstates, sizeof(void*) * count);
409 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
410
411 dst->states.enabled_mask &= ~disable_mask;
412 dst->states.dirty_mask &= dst->states.enabled_mask;
413 dst->states.enabled_mask |= new_mask;
414 dst->states.dirty_mask |= new_mask;
415 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
416
417 r600_sampler_states_dirty(rctx, &dst->states);
418
419 /* Seamless cubemap state. */
420 if (rctx->chip_class <= R700 &&
421 seamless_cube_map != -1 &&
422 seamless_cube_map != rctx->seamless_cube_map.enabled) {
423 /* change in TA_CNTL_AUX need a pipeline flush */
424 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
425 rctx->seamless_cube_map.enabled = seamless_cube_map;
426 rctx->seamless_cube_map.atom.dirty = true;
427 }
428 }
429
430 static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
431 {
432 r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
433 }
434
435 static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
436 {
437 r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
438 }
439
440 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
441 {
442 free(state);
443 }
444
445 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
446 {
447 struct r600_blend_state *blend = (struct r600_blend_state*)state;
448
449 r600_release_command_buffer(&blend->buffer);
450 r600_release_command_buffer(&blend->buffer_no_blend);
451 FREE(blend);
452 }
453
454 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
455 {
456 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
457
458 r600_release_command_buffer(&dsa->buffer);
459 free(dsa);
460 }
461
462 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
463 {
464 struct r600_context *rctx = (struct r600_context *)ctx;
465
466 r600_set_cso_state(&rctx->vertex_fetch_shader, state);
467 }
468
469 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
470 {
471 pipe_resource_reference((struct pipe_resource**)&state, NULL);
472 }
473
474 static void r600_set_index_buffer(struct pipe_context *ctx,
475 const struct pipe_index_buffer *ib)
476 {
477 struct r600_context *rctx = (struct r600_context *)ctx;
478
479 if (ib) {
480 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
481 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
482 } else {
483 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
484 }
485 }
486
487 void r600_vertex_buffers_dirty(struct r600_context *rctx)
488 {
489 if (rctx->vertex_buffer_state.dirty_mask) {
490 rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
491 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
492 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
493 rctx->vertex_buffer_state.atom.dirty = true;
494 }
495 }
496
497 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
498 const struct pipe_vertex_buffer *input)
499 {
500 struct r600_context *rctx = (struct r600_context *)ctx;
501 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
502 struct pipe_vertex_buffer *vb = state->vb;
503 unsigned i;
504 /* This sets 1-bit for buffers with index >= count. */
505 uint32_t disable_mask = ~((1ull << count) - 1);
506 /* These are the new buffers set by this function. */
507 uint32_t new_buffer_mask = 0;
508
509 /* Set buffers with index >= count to NULL. */
510 uint32_t remaining_buffers_mask =
511 rctx->vertex_buffer_state.enabled_mask & disable_mask;
512
513 while (remaining_buffers_mask) {
514 i = u_bit_scan(&remaining_buffers_mask);
515 pipe_resource_reference(&vb[i].buffer, NULL);
516 }
517
518 /* Set vertex buffers. */
519 for (i = 0; i < count; i++) {
520 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
521 if (input[i].buffer) {
522 vb[i].stride = input[i].stride;
523 vb[i].buffer_offset = input[i].buffer_offset;
524 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
525 new_buffer_mask |= 1 << i;
526 } else {
527 pipe_resource_reference(&vb[i].buffer, NULL);
528 disable_mask |= 1 << i;
529 }
530 }
531 }
532
533 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
534 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
535 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
536 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
537
538 r600_vertex_buffers_dirty(rctx);
539 }
540
541 void r600_sampler_views_dirty(struct r600_context *rctx,
542 struct r600_samplerview_state *state)
543 {
544 if (state->dirty_mask) {
545 rctx->flags |= R600_CONTEXT_TEX_FLUSH;
546 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
547 util_bitcount(state->dirty_mask);
548 state->atom.dirty = true;
549 }
550 }
551
552 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
553 unsigned start, unsigned count,
554 struct pipe_sampler_view **views)
555 {
556 struct r600_context *rctx = (struct r600_context *) pipe;
557 struct r600_textures_info *dst = &rctx->samplers[shader];
558 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
559 uint32_t dirty_sampler_states_mask = 0;
560 unsigned i;
561 /* This sets 1-bit for textures with index >= count. */
562 uint32_t disable_mask = ~((1ull << count) - 1);
563 /* These are the new textures set by this function. */
564 uint32_t new_mask = 0;
565
566 /* Set textures with index >= count to NULL. */
567 uint32_t remaining_mask;
568
569 assert(start == 0); /* XXX fix below */
570
571 remaining_mask = dst->views.enabled_mask & disable_mask;
572
573 while (remaining_mask) {
574 i = u_bit_scan(&remaining_mask);
575 assert(dst->views.views[i]);
576
577 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
578 }
579
580 for (i = 0; i < count; i++) {
581 if (rviews[i] == dst->views.views[i]) {
582 continue;
583 }
584
585 if (rviews[i]) {
586 struct r600_texture *rtex =
587 (struct r600_texture*)rviews[i]->base.texture;
588
589 if (rtex->is_depth && !rtex->is_flushing_texture) {
590 dst->views.compressed_depthtex_mask |= 1 << i;
591 } else {
592 dst->views.compressed_depthtex_mask &= ~(1 << i);
593 }
594
595 /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
596 if (rctx->chip_class != CAYMAN && rtex->cmask_size && rtex->fmask_size) {
597 dst->views.compressed_colortex_mask |= 1 << i;
598 } else {
599 dst->views.compressed_colortex_mask &= ~(1 << i);
600 }
601
602 /* Changing from array to non-arrays textures and vice versa requires
603 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
604 if (rctx->chip_class <= R700 &&
605 (dst->states.enabled_mask & (1 << i)) &&
606 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
607 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
608 dirty_sampler_states_mask |= 1 << i;
609 }
610
611 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
612 new_mask |= 1 << i;
613 } else {
614 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
615 disable_mask |= 1 << i;
616 }
617 }
618
619 dst->views.enabled_mask &= ~disable_mask;
620 dst->views.dirty_mask &= dst->views.enabled_mask;
621 dst->views.enabled_mask |= new_mask;
622 dst->views.dirty_mask |= new_mask;
623 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
624 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
625
626 r600_sampler_views_dirty(rctx, &dst->views);
627
628 if (dirty_sampler_states_mask) {
629 dst->states.dirty_mask |= dirty_sampler_states_mask;
630 r600_sampler_states_dirty(rctx, &dst->states);
631 }
632 }
633
634 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
635 struct pipe_sampler_view **views)
636 {
637 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
638 }
639
640 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
641 struct pipe_sampler_view **views)
642 {
643 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
644 }
645
646 static void r600_set_viewport_state(struct pipe_context *ctx,
647 const struct pipe_viewport_state *state)
648 {
649 struct r600_context *rctx = (struct r600_context *)ctx;
650
651 rctx->viewport.state = *state;
652 rctx->viewport.atom.dirty = true;
653 }
654
655 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
656 {
657 struct radeon_winsys_cs *cs = rctx->cs;
658 struct pipe_viewport_state *state = &rctx->viewport.state;
659
660 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
661 r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
662 r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
663 r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
664 r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
665 r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
666 r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
667 }
668
669 /* Compute the key for the hw shader variant */
670 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
671 struct r600_pipe_shader_selector * sel)
672 {
673 struct r600_context *rctx = (struct r600_context *)ctx;
674 struct r600_shader_key key;
675 memset(&key, 0, sizeof(key));
676
677 if (sel->type == PIPE_SHADER_FRAGMENT) {
678 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
679 key.alpha_to_one = rctx->alpha_to_one &&
680 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
681 !rctx->framebuffer.cb0_is_integer;
682 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
683 /* Dual-source blending only makes sense with nr_cbufs == 1. */
684 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
685 key.nr_cbufs = 2;
686 }
687 return key;
688 }
689
690 /* Select the hw shader variant depending on the current state.
691 * (*dirty) is set to 1 if current variant was changed */
692 static int r600_shader_select(struct pipe_context *ctx,
693 struct r600_pipe_shader_selector* sel,
694 unsigned *dirty)
695 {
696 struct r600_shader_key key;
697 struct r600_context *rctx = (struct r600_context *)ctx;
698 struct r600_pipe_shader * shader = NULL;
699 int r;
700
701 key = r600_shader_selector_key(ctx, sel);
702
703 /* Check if we don't need to change anything.
704 * This path is also used for most shaders that don't need multiple
705 * variants, it will cost just a computation of the key and this
706 * test. */
707 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
708 return 0;
709 }
710
711 /* lookup if we have other variants in the list */
712 if (sel->num_shaders > 1) {
713 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
714
715 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
716 p = c;
717 c = c->next_variant;
718 }
719
720 if (c) {
721 p->next_variant = c->next_variant;
722 shader = c;
723 }
724 }
725
726 if (unlikely(!shader)) {
727 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
728 shader->selector = sel;
729
730 r = r600_pipe_shader_create(ctx, shader, key);
731 if (unlikely(r)) {
732 R600_ERR("Failed to build shader variant (type=%u) %d\n",
733 sel->type, r);
734 sel->current = NULL;
735 return r;
736 }
737
738 /* We don't know the value of nr_ps_max_color_exports until we built
739 * at least one variant, so we may need to recompute the key after
740 * building first variant. */
741 if (sel->type == PIPE_SHADER_FRAGMENT &&
742 sel->num_shaders == 0) {
743 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
744 key = r600_shader_selector_key(ctx, sel);
745 }
746
747 shader->key = key;
748 sel->num_shaders++;
749 }
750
751 if (dirty)
752 *dirty = 1;
753
754 shader->next_variant = sel->current;
755 sel->current = shader;
756
757 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
758 r600_adjust_gprs(rctx);
759 }
760
761 if (rctx->ps_shader &&
762 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
763 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
764 rctx->cb_misc_state.atom.dirty = true;
765 }
766 return 0;
767 }
768
769 static void *r600_create_shader_state(struct pipe_context *ctx,
770 const struct pipe_shader_state *state,
771 unsigned pipe_shader_type)
772 {
773 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
774 int r;
775
776 sel->type = pipe_shader_type;
777 sel->tokens = tgsi_dup_tokens(state->tokens);
778 sel->so = state->stream_output;
779
780 r = r600_shader_select(ctx, sel, NULL);
781 if (r)
782 return NULL;
783
784 return sel;
785 }
786
787 static void *r600_create_ps_state(struct pipe_context *ctx,
788 const struct pipe_shader_state *state)
789 {
790 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
791 }
792
793 static void *r600_create_vs_state(struct pipe_context *ctx,
794 const struct pipe_shader_state *state)
795 {
796 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
797 }
798
799 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
800 {
801 struct r600_context *rctx = (struct r600_context *)ctx;
802
803 if (!state)
804 state = rctx->dummy_pixel_shader;
805
806 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
807 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
808
809 if (rctx->chip_class <= R700) {
810 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
811
812 if (rctx->cb_misc_state.multiwrite != multiwrite) {
813 rctx->cb_misc_state.multiwrite = multiwrite;
814 rctx->cb_misc_state.atom.dirty = true;
815 }
816
817 if (rctx->vs_shader)
818 r600_adjust_gprs(rctx);
819 }
820
821 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
822 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
823 rctx->cb_misc_state.atom.dirty = true;
824 }
825
826 if (rctx->chip_class >= EVERGREEN) {
827 evergreen_update_db_shader_control(rctx);
828 } else {
829 r600_update_db_shader_control(rctx);
830 }
831 }
832
833 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
834 {
835 struct r600_context *rctx = (struct r600_context *)ctx;
836
837 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
838 if (state) {
839 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
840
841 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
842 r600_adjust_gprs(rctx);
843
844 /* Update clip misc state. */
845 if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
846 rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
847 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
848 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
849 rctx->clip_misc_state.atom.dirty = true;
850 }
851 }
852 }
853
854 static void r600_delete_shader_selector(struct pipe_context *ctx,
855 struct r600_pipe_shader_selector *sel)
856 {
857 struct r600_pipe_shader *p = sel->current, *c;
858 while (p) {
859 c = p->next_variant;
860 r600_pipe_shader_destroy(ctx, p);
861 free(p);
862 p = c;
863 }
864
865 free(sel->tokens);
866 free(sel);
867 }
868
869
870 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
871 {
872 struct r600_context *rctx = (struct r600_context *)ctx;
873 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
874
875 if (rctx->ps_shader == sel) {
876 rctx->ps_shader = NULL;
877 }
878
879 r600_delete_shader_selector(ctx, sel);
880 }
881
882 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
883 {
884 struct r600_context *rctx = (struct r600_context *)ctx;
885 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
886
887 if (rctx->vs_shader == sel) {
888 rctx->vs_shader = NULL;
889 }
890
891 r600_delete_shader_selector(ctx, sel);
892 }
893
894 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
895 {
896 if (state->dirty_mask) {
897 rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
898 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
899 : util_bitcount(state->dirty_mask)*19;
900 state->atom.dirty = true;
901 }
902 }
903
904 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
905 struct pipe_constant_buffer *input)
906 {
907 struct r600_context *rctx = (struct r600_context *)ctx;
908 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
909 struct pipe_constant_buffer *cb;
910 const uint8_t *ptr;
911
912 /* Note that the state tracker can unbind constant buffers by
913 * passing NULL here.
914 */
915 if (unlikely(!input)) {
916 state->enabled_mask &= ~(1 << index);
917 state->dirty_mask &= ~(1 << index);
918 pipe_resource_reference(&state->cb[index].buffer, NULL);
919 return;
920 }
921
922 cb = &state->cb[index];
923 cb->buffer_size = input->buffer_size;
924
925 ptr = input->user_buffer;
926
927 if (ptr) {
928 /* Upload the user buffer. */
929 if (R600_BIG_ENDIAN) {
930 uint32_t *tmpPtr;
931 unsigned i, size = input->buffer_size;
932
933 if (!(tmpPtr = malloc(size))) {
934 R600_ERR("Failed to allocate BE swap buffer.\n");
935 return;
936 }
937
938 for (i = 0; i < size / 4; ++i) {
939 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
940 }
941
942 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
943 free(tmpPtr);
944 } else {
945 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
946 }
947 } else {
948 /* Setup the hw buffer. */
949 cb->buffer_offset = input->buffer_offset;
950 pipe_resource_reference(&cb->buffer, input->buffer);
951 }
952
953 state->enabled_mask |= 1 << index;
954 state->dirty_mask |= 1 << index;
955 r600_constant_buffers_dirty(rctx, state);
956 }
957
958 static struct pipe_stream_output_target *
959 r600_create_so_target(struct pipe_context *ctx,
960 struct pipe_resource *buffer,
961 unsigned buffer_offset,
962 unsigned buffer_size)
963 {
964 struct r600_context *rctx = (struct r600_context *)ctx;
965 struct r600_so_target *t;
966 void *ptr;
967
968 t = CALLOC_STRUCT(r600_so_target);
969 if (!t) {
970 return NULL;
971 }
972
973 t->b.reference.count = 1;
974 t->b.context = ctx;
975 pipe_resource_reference(&t->b.buffer, buffer);
976 t->b.buffer_offset = buffer_offset;
977 t->b.buffer_size = buffer_size;
978
979 t->filled_size = (struct r600_resource*)
980 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
981 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
982 memset(ptr, 0, t->filled_size->buf->size);
983 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
984
985 return &t->b;
986 }
987
988 static void r600_so_target_destroy(struct pipe_context *ctx,
989 struct pipe_stream_output_target *target)
990 {
991 struct r600_so_target *t = (struct r600_so_target*)target;
992 pipe_resource_reference(&t->b.buffer, NULL);
993 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
994 FREE(t);
995 }
996
997 static void r600_set_so_targets(struct pipe_context *ctx,
998 unsigned num_targets,
999 struct pipe_stream_output_target **targets,
1000 unsigned append_bitmask)
1001 {
1002 struct r600_context *rctx = (struct r600_context *)ctx;
1003 unsigned i;
1004
1005 /* Stop streamout. */
1006 if (rctx->num_so_targets && !rctx->streamout_start) {
1007 r600_context_streamout_end(rctx);
1008 }
1009
1010 /* Set the new targets. */
1011 for (i = 0; i < num_targets; i++) {
1012 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
1013 }
1014 for (; i < rctx->num_so_targets; i++) {
1015 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
1016 }
1017
1018 rctx->num_so_targets = num_targets;
1019 rctx->streamout_start = num_targets != 0;
1020 rctx->streamout_append_bitmask = append_bitmask;
1021 }
1022
1023 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1024 {
1025 struct r600_context *rctx = (struct r600_context*)pipe;
1026
1027 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1028 return;
1029
1030 rctx->sample_mask.sample_mask = sample_mask;
1031 rctx->sample_mask.atom.dirty = true;
1032 }
1033
1034 static void r600_update_derived_state(struct r600_context *rctx)
1035 {
1036 struct pipe_context * ctx = (struct pipe_context*)rctx;
1037 unsigned ps_dirty = 0;
1038 bool blend_disable;
1039
1040 if (!rctx->blitter->running) {
1041 unsigned i;
1042
1043 /* Decompress textures if needed. */
1044 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1045 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1046 if (views->compressed_depthtex_mask) {
1047 r600_decompress_depth_textures(rctx, views);
1048 }
1049 if (views->compressed_colortex_mask) {
1050 r600_decompress_color_textures(rctx, views);
1051 }
1052 }
1053 }
1054
1055 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1056
1057 if (rctx->ps_shader && rctx->rasterizer &&
1058 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1059 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1060
1061 if (rctx->chip_class >= EVERGREEN)
1062 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
1063 else
1064 r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
1065
1066 ps_dirty = 1;
1067 }
1068
1069 if (ps_dirty)
1070 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
1071
1072 blend_disable = (rctx->dual_src_blend &&
1073 rctx->ps_shader->current->nr_ps_color_outputs < 2);
1074
1075 if (blend_disable != rctx->force_blend_disable) {
1076 rctx->force_blend_disable = blend_disable;
1077 r600_bind_blend_state_internal(rctx,
1078 rctx->blend_state.cso,
1079 blend_disable);
1080 }
1081 }
1082
1083 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1084 {
1085 static const int prim_conv[] = {
1086 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1087 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1088 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1089 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1090 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1091 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1092 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1093 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1094 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1095 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1096 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1097 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1098 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1099 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1100 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1101 };
1102 assert(mode < Elements(prim_conv));
1103
1104 return prim_conv[mode];
1105 }
1106
1107 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1108 {
1109 struct radeon_winsys_cs *cs = rctx->cs;
1110 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1111
1112 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1113 state->pa_cl_clip_cntl |
1114 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1115 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1116 state->pa_cl_vs_out_cntl |
1117 (state->clip_plane_enable & state->clip_dist_write));
1118 }
1119
1120 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1121 {
1122 struct r600_context *rctx = (struct r600_context *)ctx;
1123 struct pipe_draw_info info = *dinfo;
1124 struct pipe_index_buffer ib = {};
1125 unsigned i;
1126 struct r600_block *dirty_block = NULL, *next_block = NULL;
1127 struct radeon_winsys_cs *cs = rctx->cs;
1128
1129 if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1130 assert(0);
1131 return;
1132 }
1133
1134 if (!rctx->vs_shader) {
1135 assert(0);
1136 return;
1137 }
1138
1139 r600_update_derived_state(rctx);
1140
1141 if (info.indexed) {
1142 /* Initialize the index buffer struct. */
1143 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1144 ib.user_buffer = rctx->index_buffer.user_buffer;
1145 ib.index_size = rctx->index_buffer.index_size;
1146 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1147
1148 /* Translate 8-bit indices to 16-bit. */
1149 if (ib.index_size == 1) {
1150 struct pipe_resource *out_buffer = NULL;
1151 unsigned out_offset;
1152 void *ptr;
1153
1154 u_upload_alloc(rctx->uploader, 0, info.count * 2,
1155 &out_offset, &out_buffer, &ptr);
1156
1157 util_shorten_ubyte_elts_to_userptr(
1158 &rctx->context, &ib, 0, ib.offset, info.count, ptr);
1159
1160 pipe_resource_reference(&ib.buffer, NULL);
1161 ib.user_buffer = NULL;
1162 ib.buffer = out_buffer;
1163 ib.offset = out_offset;
1164 ib.index_size = 2;
1165 }
1166
1167 /* Upload the index buffer.
1168 * The upload is skipped for small index counts on little-endian machines
1169 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1170 * Note: Instanced rendering in combination with immediate indices hangs. */
1171 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1172 info.count*ib.index_size > 20)) {
1173 u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1174 ib.user_buffer, &ib.offset, &ib.buffer);
1175 ib.user_buffer = NULL;
1176 }
1177 } else {
1178 info.index_bias = info.start;
1179 }
1180
1181 /* Enable stream out if needed. */
1182 if (rctx->streamout_start) {
1183 r600_context_streamout_begin(rctx);
1184 rctx->streamout_start = FALSE;
1185 }
1186
1187 /* Set the index offset and multi primitive */
1188 if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
1189 rctx->vgt2_state.vgt_indx_offset = info.index_bias;
1190 rctx->vgt2_state.atom.dirty = true;
1191 }
1192 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1193 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
1194 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1195 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1196 rctx->vgt_state.atom.dirty = true;
1197 }
1198
1199 /* Emit states. */
1200 r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1201 r600_flush_emit(rctx);
1202
1203 for (i = 0; i < R600_NUM_ATOMS; i++) {
1204 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1205 continue;
1206 }
1207 r600_emit_atom(rctx, rctx->atoms[i]);
1208 }
1209 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1210 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1211 }
1212 rctx->pm4_dirty_cdwords = 0;
1213
1214 /* Update start instance. */
1215 if (rctx->last_start_instance != info.start_instance) {
1216 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1217 rctx->last_start_instance = info.start_instance;
1218 }
1219
1220 /* Update the primitive type. */
1221 if (rctx->last_primitive_type != info.mode) {
1222 unsigned ls_mask = 0;
1223
1224 if (info.mode == PIPE_PRIM_LINES)
1225 ls_mask = 1;
1226 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1227 info.mode == PIPE_PRIM_LINE_LOOP)
1228 ls_mask = 2;
1229
1230 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1231 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1232 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1233 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1234 r600_conv_prim_to_gs_out(info.mode));
1235 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1236 r600_conv_pipe_prim(info.mode));
1237
1238 rctx->last_primitive_type = info.mode;
1239 }
1240
1241 /* Draw packets. */
1242 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1243 cs->buf[cs->cdw++] = info.instance_count;
1244 if (info.indexed) {
1245 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1246 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1247 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1248 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1249
1250 if (ib.user_buffer) {
1251 unsigned size_bytes = info.count*ib.index_size;
1252 unsigned size_dw = align(size_bytes, 4) / 4;
1253 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1254 cs->buf[cs->cdw++] = info.count;
1255 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1256 memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1257 cs->cdw += size_dw;
1258 } else {
1259 uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1260 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1261 cs->buf[cs->cdw++] = va;
1262 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1263 cs->buf[cs->cdw++] = info.count;
1264 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1265 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1266 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1267 }
1268 } else {
1269 if (info.count_from_stream_output) {
1270 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1271 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
1272
1273 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1274
1275 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1276 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1277 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
1278 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1279 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1280 cs->buf[cs->cdw++] = 0; /* unused */
1281
1282 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1283 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
1284 }
1285
1286 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1287 cs->buf[cs->cdw++] = info.count;
1288 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1289 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1290 }
1291
1292 /* Set the depth buffer as dirty. */
1293 if (rctx->framebuffer.state.zsbuf) {
1294 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1295 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1296
1297 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1298 }
1299 if (rctx->framebuffer.compressed_cb_mask) {
1300 struct pipe_surface *surf;
1301 struct r600_texture *rtex;
1302 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1303
1304 do {
1305 unsigned i = u_bit_scan(&mask);
1306 surf = rctx->framebuffer.state.cbufs[i];
1307 rtex = (struct r600_texture*)surf->texture;
1308
1309 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1310
1311 } while (mask);
1312 }
1313
1314 pipe_resource_reference(&ib.buffer, NULL);
1315 }
1316
1317 void r600_draw_rectangle(struct blitter_context *blitter,
1318 int x1, int y1, int x2, int y2, float depth,
1319 enum blitter_attrib_type type, const union pipe_color_union *attrib)
1320 {
1321 struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1322 struct pipe_viewport_state viewport;
1323 struct pipe_resource *buf = NULL;
1324 unsigned offset = 0;
1325 float *vb;
1326
1327 if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1328 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1329 return;
1330 }
1331
1332 /* Some operations (like color resolve on r6xx) don't work
1333 * with the conventional primitive types.
1334 * One that works is PT_RECTLIST, which we use here. */
1335
1336 /* setup viewport */
1337 viewport.scale[0] = 1.0f;
1338 viewport.scale[1] = 1.0f;
1339 viewport.scale[2] = 1.0f;
1340 viewport.scale[3] = 1.0f;
1341 viewport.translate[0] = 0.0f;
1342 viewport.translate[1] = 0.0f;
1343 viewport.translate[2] = 0.0f;
1344 viewport.translate[3] = 0.0f;
1345 rctx->context.set_viewport_state(&rctx->context, &viewport);
1346
1347 /* Upload vertices. The hw rectangle has only 3 vertices,
1348 * I guess the 4th one is derived from the first 3.
1349 * The vertex specification should match u_blitter's vertex element state. */
1350 u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1351 vb[0] = x1;
1352 vb[1] = y1;
1353 vb[2] = depth;
1354 vb[3] = 1;
1355
1356 vb[8] = x1;
1357 vb[9] = y2;
1358 vb[10] = depth;
1359 vb[11] = 1;
1360
1361 vb[16] = x2;
1362 vb[17] = y1;
1363 vb[18] = depth;
1364 vb[19] = 1;
1365
1366 if (attrib) {
1367 memcpy(vb+4, attrib->f, sizeof(float)*4);
1368 memcpy(vb+12, attrib->f, sizeof(float)*4);
1369 memcpy(vb+20, attrib->f, sizeof(float)*4);
1370 }
1371
1372 /* draw */
1373 util_draw_vertex_buffer(&rctx->context, NULL, buf, offset,
1374 R600_PRIM_RECTANGLE_LIST, 3, 2);
1375 pipe_resource_reference(&buf, NULL);
1376 }
1377
1378 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1379 struct r600_pipe_state *state,
1380 uint32_t offset, uint32_t value,
1381 uint32_t range_id, uint32_t block_id,
1382 struct r600_resource *bo,
1383 enum radeon_bo_usage usage)
1384
1385 {
1386 struct r600_range *range;
1387 struct r600_block *block;
1388
1389 if (bo) assert(usage);
1390
1391 range = &ctx->range[range_id];
1392 block = range->blocks[block_id];
1393 state->regs[state->nregs].block = block;
1394 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1395
1396 state->regs[state->nregs].value = value;
1397 state->regs[state->nregs].bo = bo;
1398 state->regs[state->nregs].bo_usage = usage;
1399
1400 state->nregs++;
1401 assert(state->nregs < R600_BLOCK_MAX_REG);
1402 }
1403
1404 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1405 struct r600_pipe_state *state,
1406 uint32_t offset, uint32_t value,
1407 uint32_t range_id, uint32_t block_id)
1408 {
1409 _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1410 range_id, block_id, NULL, 0);
1411 }
1412
1413 uint32_t r600_translate_stencil_op(int s_op)
1414 {
1415 switch (s_op) {
1416 case PIPE_STENCIL_OP_KEEP:
1417 return V_028800_STENCIL_KEEP;
1418 case PIPE_STENCIL_OP_ZERO:
1419 return V_028800_STENCIL_ZERO;
1420 case PIPE_STENCIL_OP_REPLACE:
1421 return V_028800_STENCIL_REPLACE;
1422 case PIPE_STENCIL_OP_INCR:
1423 return V_028800_STENCIL_INCR;
1424 case PIPE_STENCIL_OP_DECR:
1425 return V_028800_STENCIL_DECR;
1426 case PIPE_STENCIL_OP_INCR_WRAP:
1427 return V_028800_STENCIL_INCR_WRAP;
1428 case PIPE_STENCIL_OP_DECR_WRAP:
1429 return V_028800_STENCIL_DECR_WRAP;
1430 case PIPE_STENCIL_OP_INVERT:
1431 return V_028800_STENCIL_INVERT;
1432 default:
1433 R600_ERR("Unknown stencil op %d", s_op);
1434 assert(0);
1435 break;
1436 }
1437 return 0;
1438 }
1439
1440 uint32_t r600_translate_fill(uint32_t func)
1441 {
1442 switch(func) {
1443 case PIPE_POLYGON_MODE_FILL:
1444 return 2;
1445 case PIPE_POLYGON_MODE_LINE:
1446 return 1;
1447 case PIPE_POLYGON_MODE_POINT:
1448 return 0;
1449 default:
1450 assert(0);
1451 return 0;
1452 }
1453 }
1454
1455 unsigned r600_tex_wrap(unsigned wrap)
1456 {
1457 switch (wrap) {
1458 default:
1459 case PIPE_TEX_WRAP_REPEAT:
1460 return V_03C000_SQ_TEX_WRAP;
1461 case PIPE_TEX_WRAP_CLAMP:
1462 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1463 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1464 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1465 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1466 return V_03C000_SQ_TEX_CLAMP_BORDER;
1467 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1468 return V_03C000_SQ_TEX_MIRROR;
1469 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1470 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1471 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1472 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1473 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1474 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1475 }
1476 }
1477
1478 unsigned r600_tex_filter(unsigned filter)
1479 {
1480 switch (filter) {
1481 default:
1482 case PIPE_TEX_FILTER_NEAREST:
1483 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1484 case PIPE_TEX_FILTER_LINEAR:
1485 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1486 }
1487 }
1488
1489 unsigned r600_tex_mipfilter(unsigned filter)
1490 {
1491 switch (filter) {
1492 case PIPE_TEX_MIPFILTER_NEAREST:
1493 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1494 case PIPE_TEX_MIPFILTER_LINEAR:
1495 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1496 default:
1497 case PIPE_TEX_MIPFILTER_NONE:
1498 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1499 }
1500 }
1501
1502 unsigned r600_tex_compare(unsigned compare)
1503 {
1504 switch (compare) {
1505 default:
1506 case PIPE_FUNC_NEVER:
1507 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1508 case PIPE_FUNC_LESS:
1509 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1510 case PIPE_FUNC_EQUAL:
1511 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1512 case PIPE_FUNC_LEQUAL:
1513 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1514 case PIPE_FUNC_GREATER:
1515 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1516 case PIPE_FUNC_NOTEQUAL:
1517 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1518 case PIPE_FUNC_GEQUAL:
1519 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1520 case PIPE_FUNC_ALWAYS:
1521 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1522 }
1523 }
1524
1525 /* keep this at the end of this file, please */
1526 void r600_init_common_state_functions(struct r600_context *rctx)
1527 {
1528 rctx->context.create_fs_state = r600_create_ps_state;
1529 rctx->context.create_vs_state = r600_create_vs_state;
1530 rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
1531 rctx->context.bind_blend_state = r600_bind_blend_state;
1532 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1533 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
1534 rctx->context.bind_fs_state = r600_bind_ps_state;
1535 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1536 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1537 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
1538 rctx->context.bind_vs_state = r600_bind_vs_state;
1539 rctx->context.delete_blend_state = r600_delete_blend_state;
1540 rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
1541 rctx->context.delete_fs_state = r600_delete_ps_state;
1542 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1543 rctx->context.delete_sampler_state = r600_delete_sampler_state;
1544 rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
1545 rctx->context.delete_vs_state = r600_delete_vs_state;
1546 rctx->context.set_blend_color = r600_set_blend_color;
1547 rctx->context.set_clip_state = r600_set_clip_state;
1548 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1549 rctx->context.set_sample_mask = r600_set_sample_mask;
1550 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1551 rctx->context.set_viewport_state = r600_set_viewport_state;
1552 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1553 rctx->context.set_index_buffer = r600_set_index_buffer;
1554 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1555 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1556 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1557 rctx->context.texture_barrier = r600_texture_barrier;
1558 rctx->context.create_stream_output_target = r600_create_so_target;
1559 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1560 rctx->context.set_stream_output_targets = r600_set_so_targets;
1561 rctx->context.draw_vbo = r600_draw_vbo;
1562 }