2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_math.h"
37 #include "tgsi/tgsi_parse.h"
39 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
41 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
44 cb
->buf
= CALLOC(1, 4 * num_dw
);
45 cb
->max_num_dw
= num_dw
;
48 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
53 void r600_init_atom(struct r600_context
*rctx
,
54 struct r600_atom
*atom
,
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
59 assert(id
< R600_NUM_ATOMS
);
60 assert(rctx
->atoms
[id
] == NULL
);
61 rctx
->atoms
[id
] = atom
;
62 atom
->emit
= (void*)emit
;
63 atom
->num_dw
= num_dw
;
67 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
69 r600_emit_command_buffer(rctx
->b
.rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
72 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
74 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
75 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
76 unsigned alpha_ref
= a
->sx_alpha_ref
;
78 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
82 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
83 a
->sx_alpha_test_control
|
84 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
85 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
88 static void r600_texture_barrier(struct pipe_context
*ctx
)
90 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
92 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
93 R600_CONTEXT_FLUSH_AND_INV_CB
|
94 R600_CONTEXT_FLUSH_AND_INV
|
95 R600_CONTEXT_WAIT_3D_IDLE
;
98 static unsigned r600_conv_pipe_prim(unsigned prim
)
100 static const unsigned prim_conv
[] = {
101 V_008958_DI_PT_POINTLIST
,
102 V_008958_DI_PT_LINELIST
,
103 V_008958_DI_PT_LINELOOP
,
104 V_008958_DI_PT_LINESTRIP
,
105 V_008958_DI_PT_TRILIST
,
106 V_008958_DI_PT_TRISTRIP
,
107 V_008958_DI_PT_TRIFAN
,
108 V_008958_DI_PT_QUADLIST
,
109 V_008958_DI_PT_QUADSTRIP
,
110 V_008958_DI_PT_POLYGON
,
111 V_008958_DI_PT_LINELIST_ADJ
,
112 V_008958_DI_PT_LINESTRIP_ADJ
,
113 V_008958_DI_PT_TRILIST_ADJ
,
114 V_008958_DI_PT_TRISTRIP_ADJ
,
115 V_008958_DI_PT_RECTLIST
117 return prim_conv
[prim
];
120 /* common state between evergreen and r600 */
122 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
123 struct r600_blend_state
*blend
, bool blend_disable
)
125 unsigned color_control
;
126 bool update_cb
= false;
128 rctx
->alpha_to_one
= blend
->alpha_to_one
;
129 rctx
->dual_src_blend
= blend
->dual_src_blend
;
131 if (!blend_disable
) {
132 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
133 color_control
= blend
->cb_color_control
;
135 /* Blending is disabled. */
136 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
137 color_control
= blend
->cb_color_control_no_blend
;
140 /* Update derived states. */
141 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
142 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
145 if (rctx
->b
.chip_class
<= R700
&&
146 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
147 rctx
->cb_misc_state
.cb_color_control
= color_control
;
150 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
151 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
155 rctx
->cb_misc_state
.atom
.dirty
= true;
159 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
161 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
162 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
167 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
170 static void r600_set_blend_color(struct pipe_context
*ctx
,
171 const struct pipe_blend_color
*state
)
173 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
175 rctx
->blend_color
.state
= *state
;
176 rctx
->blend_color
.atom
.dirty
= true;
179 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
181 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
182 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
184 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
185 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
186 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
187 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
188 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
191 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
193 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
194 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
196 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
197 r600_write_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
198 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
199 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
202 static void r600_set_clip_state(struct pipe_context
*ctx
,
203 const struct pipe_clip_state
*state
)
205 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
206 struct pipe_constant_buffer cb
;
208 rctx
->clip_state
.state
= *state
;
209 rctx
->clip_state
.atom
.dirty
= true;
212 cb
.user_buffer
= state
->ucp
;
213 cb
.buffer_offset
= 0;
214 cb
.buffer_size
= 4*4*8;
215 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
216 pipe_resource_reference(&cb
.buffer
, NULL
);
219 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
220 const struct r600_stencil_ref
*state
)
222 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
224 rctx
->stencil_ref
.state
= *state
;
225 rctx
->stencil_ref
.atom
.dirty
= true;
228 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
230 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
231 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
233 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
234 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
235 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
236 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
237 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
238 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
239 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
240 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
241 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
244 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
245 const struct pipe_stencil_ref
*state
)
247 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
248 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
249 struct r600_stencil_ref ref
;
251 rctx
->stencil_ref
.pipe_state
= *state
;
256 ref
.ref_value
[0] = state
->ref_value
[0];
257 ref
.ref_value
[1] = state
->ref_value
[1];
258 ref
.valuemask
[0] = dsa
->valuemask
[0];
259 ref
.valuemask
[1] = dsa
->valuemask
[1];
260 ref
.writemask
[0] = dsa
->writemask
[0];
261 ref
.writemask
[1] = dsa
->writemask
[1];
263 r600_set_stencil_ref(ctx
, &ref
);
266 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
268 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
269 struct r600_dsa_state
*dsa
= state
;
270 struct r600_stencil_ref ref
;
273 r600_set_cso_state_with_cb(&rctx
->dsa_state
, NULL
, NULL
);
277 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
279 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
280 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
281 ref
.valuemask
[0] = dsa
->valuemask
[0];
282 ref
.valuemask
[1] = dsa
->valuemask
[1];
283 ref
.writemask
[0] = dsa
->writemask
[0];
284 ref
.writemask
[1] = dsa
->writemask
[1];
285 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
286 rctx
->zwritemask
= dsa
->zwritemask
;
287 if (rctx
->b
.chip_class
>= EVERGREEN
) {
288 /* work around some issue when not writting to zbuffer
289 * we are having lockup on evergreen so do not enable
290 * hyperz when not writting zbuffer
292 rctx
->db_misc_state
.atom
.dirty
= true;
296 r600_set_stencil_ref(ctx
, &ref
);
298 /* Update alphatest state. */
299 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
300 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
301 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
302 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
303 rctx
->alphatest_state
.atom
.dirty
= true;
304 if (rctx
->b
.chip_class
>= EVERGREEN
) {
305 evergreen_update_db_shader_control(rctx
);
307 r600_update_db_shader_control(rctx
);
312 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
314 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
315 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
320 rctx
->rasterizer
= rs
;
322 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
324 if (rs
->offset_enable
&&
325 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
326 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
327 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
328 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
329 rctx
->poly_offset_state
.atom
.dirty
= true;
332 /* Update clip_misc_state. */
333 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
334 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
335 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
336 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
337 rctx
->clip_misc_state
.atom
.dirty
= true;
340 /* Workaround for a missing scissor enable on r600. */
341 if (rctx
->b
.chip_class
== R600
&&
342 rs
->scissor_enable
!= rctx
->scissor
.enable
) {
343 rctx
->scissor
.enable
= rs
->scissor_enable
;
344 rctx
->scissor
.atom
.dirty
= true;
347 /* Re-emit PA_SC_LINE_STIPPLE. */
348 rctx
->last_primitive_type
= -1;
351 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
353 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
355 r600_release_command_buffer(&rs
->buffer
);
359 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
360 struct pipe_sampler_view
*state
)
362 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
364 pipe_resource_reference(&state
->texture
, NULL
);
368 void r600_sampler_states_dirty(struct r600_context
*rctx
,
369 struct r600_sampler_states
*state
)
371 if (state
->dirty_mask
) {
372 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
373 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
376 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
377 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
378 state
->atom
.dirty
= true;
382 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
385 unsigned count
, void **states
)
387 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
388 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
389 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
390 int seamless_cube_map
= -1;
392 /* This sets 1-bit for states with index >= count. */
393 uint32_t disable_mask
= ~((1ull << count
) - 1);
394 /* These are the new states set by this function. */
395 uint32_t new_mask
= 0;
397 assert(start
== 0); /* XXX fix below */
399 if (shader
!= PIPE_SHADER_VERTEX
&&
400 shader
!= PIPE_SHADER_FRAGMENT
) {
404 for (i
= 0; i
< count
; i
++) {
405 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
407 if (rstate
== dst
->states
.states
[i
]) {
412 if (rstate
->border_color_use
) {
413 dst
->states
.has_bordercolor_mask
|= 1 << i
;
415 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
417 seamless_cube_map
= rstate
->seamless_cube_map
;
421 disable_mask
|= 1 << i
;
425 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
426 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
428 dst
->states
.enabled_mask
&= ~disable_mask
;
429 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
430 dst
->states
.enabled_mask
|= new_mask
;
431 dst
->states
.dirty_mask
|= new_mask
;
432 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
434 r600_sampler_states_dirty(rctx
, &dst
->states
);
436 /* Seamless cubemap state. */
437 if (rctx
->b
.chip_class
<= R700
&&
438 seamless_cube_map
!= -1 &&
439 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
440 /* change in TA_CNTL_AUX need a pipeline flush */
441 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
442 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
443 rctx
->seamless_cube_map
.atom
.dirty
= true;
447 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
452 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
454 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
456 r600_release_command_buffer(&blend
->buffer
);
457 r600_release_command_buffer(&blend
->buffer_no_blend
);
461 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
463 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
464 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
466 if (rctx
->dsa_state
.cso
== state
) {
467 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
470 r600_release_command_buffer(&dsa
->buffer
);
474 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
476 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
478 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
481 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
483 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
484 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
488 static void r600_set_index_buffer(struct pipe_context
*ctx
,
489 const struct pipe_index_buffer
*ib
)
491 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
494 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
495 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
496 r600_context_add_resource_size(ctx
, ib
->buffer
);
498 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
502 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
504 if (rctx
->vertex_buffer_state
.dirty_mask
) {
505 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
;
506 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
507 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
508 rctx
->vertex_buffer_state
.atom
.dirty
= true;
512 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
513 unsigned start_slot
, unsigned count
,
514 const struct pipe_vertex_buffer
*input
)
516 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
517 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
518 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
520 uint32_t disable_mask
= 0;
521 /* These are the new buffers set by this function. */
522 uint32_t new_buffer_mask
= 0;
524 /* Set vertex buffers. */
526 for (i
= 0; i
< count
; i
++) {
527 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
528 if (input
[i
].buffer
) {
529 vb
[i
].stride
= input
[i
].stride
;
530 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
531 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
532 new_buffer_mask
|= 1 << i
;
533 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
535 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
536 disable_mask
|= 1 << i
;
541 for (i
= 0; i
< count
; i
++) {
542 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
544 disable_mask
= ((1ull << count
) - 1);
547 disable_mask
<<= start_slot
;
548 new_buffer_mask
<<= start_slot
;
550 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
551 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
552 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
553 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
555 r600_vertex_buffers_dirty(rctx
);
558 void r600_sampler_views_dirty(struct r600_context
*rctx
,
559 struct r600_samplerview_state
*state
)
561 if (state
->dirty_mask
) {
562 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
563 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
564 util_bitcount(state
->dirty_mask
);
565 state
->atom
.dirty
= true;
569 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
570 unsigned start
, unsigned count
,
571 struct pipe_sampler_view
**views
)
573 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
574 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
575 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
576 uint32_t dirty_sampler_states_mask
= 0;
578 /* This sets 1-bit for textures with index >= count. */
579 uint32_t disable_mask
= ~((1ull << count
) - 1);
580 /* These are the new textures set by this function. */
581 uint32_t new_mask
= 0;
583 /* Set textures with index >= count to NULL. */
584 uint32_t remaining_mask
;
586 assert(start
== 0); /* XXX fix below */
588 if (shader
== PIPE_SHADER_COMPUTE
) {
589 evergreen_set_cs_sampler_view(pipe
, start
, count
, views
);
593 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
595 while (remaining_mask
) {
596 i
= u_bit_scan(&remaining_mask
);
597 assert(dst
->views
.views
[i
]);
599 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
602 for (i
= 0; i
< count
; i
++) {
603 if (rviews
[i
] == dst
->views
.views
[i
]) {
608 struct r600_texture
*rtex
=
609 (struct r600_texture
*)rviews
[i
]->base
.texture
;
611 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
612 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
613 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
615 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
618 /* Track compressed colorbuffers. */
619 if (rtex
->cmask
.size
) {
620 dst
->views
.compressed_colortex_mask
|= 1 << i
;
622 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
625 /* Changing from array to non-arrays textures and vice versa requires
626 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
627 if (rctx
->b
.chip_class
<= R700
&&
628 (dst
->states
.enabled_mask
& (1 << i
)) &&
629 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
630 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
631 dirty_sampler_states_mask
|= 1 << i
;
634 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
636 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
638 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
639 disable_mask
|= 1 << i
;
643 dst
->views
.enabled_mask
&= ~disable_mask
;
644 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
645 dst
->views
.enabled_mask
|= new_mask
;
646 dst
->views
.dirty_mask
|= new_mask
;
647 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
648 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
649 dst
->views
.dirty_txq_constants
= TRUE
;
650 dst
->views
.dirty_buffer_constants
= TRUE
;
651 r600_sampler_views_dirty(rctx
, &dst
->views
);
653 if (dirty_sampler_states_mask
) {
654 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
655 r600_sampler_states_dirty(rctx
, &dst
->states
);
659 static void r600_set_viewport_states(struct pipe_context
*ctx
,
661 unsigned num_viewports
,
662 const struct pipe_viewport_state
*state
)
664 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
666 rctx
->viewport
.state
= *state
;
667 rctx
->viewport
.atom
.dirty
= true;
670 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
672 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
673 struct pipe_viewport_state
*state
= &rctx
->viewport
.state
;
675 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
, 6);
676 radeon_emit(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
677 radeon_emit(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
678 radeon_emit(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
679 radeon_emit(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
680 radeon_emit(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
681 radeon_emit(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
684 /* Compute the key for the hw shader variant */
685 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
686 struct r600_pipe_shader_selector
* sel
)
688 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
689 struct r600_shader_key key
;
690 memset(&key
, 0, sizeof(key
));
692 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
693 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
694 key
.alpha_to_one
= rctx
->alpha_to_one
&&
695 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
696 !rctx
->framebuffer
.cb0_is_integer
;
697 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
698 /* Dual-source blending only makes sense with nr_cbufs == 1. */
699 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
705 /* Select the hw shader variant depending on the current state.
706 * (*dirty) is set to 1 if current variant was changed */
707 static int r600_shader_select(struct pipe_context
*ctx
,
708 struct r600_pipe_shader_selector
* sel
,
711 struct r600_shader_key key
;
712 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
713 struct r600_pipe_shader
* shader
= NULL
;
716 memset(&key
, 0, sizeof(key
));
717 key
= r600_shader_selector_key(ctx
, sel
);
719 /* Check if we don't need to change anything.
720 * This path is also used for most shaders that don't need multiple
721 * variants, it will cost just a computation of the key and this
723 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
727 /* lookup if we have other variants in the list */
728 if (sel
->num_shaders
> 1) {
729 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
731 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
737 p
->next_variant
= c
->next_variant
;
742 if (unlikely(!shader
)) {
743 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
744 shader
->selector
= sel
;
746 r
= r600_pipe_shader_create(ctx
, shader
, key
);
748 R600_ERR("Failed to build shader variant (type=%u) %d\n",
755 /* We don't know the value of nr_ps_max_color_exports until we built
756 * at least one variant, so we may need to recompute the key after
757 * building first variant. */
758 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
759 sel
->num_shaders
== 0) {
760 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
761 key
= r600_shader_selector_key(ctx
, sel
);
764 memcpy(&shader
->key
, &key
, sizeof(key
));
771 shader
->next_variant
= sel
->current
;
772 sel
->current
= shader
;
774 if (rctx
->ps_shader
&&
775 rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
776 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
777 rctx
->cb_misc_state
.atom
.dirty
= true;
782 static void *r600_create_shader_state(struct pipe_context
*ctx
,
783 const struct pipe_shader_state
*state
,
784 unsigned pipe_shader_type
)
786 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
789 sel
->type
= pipe_shader_type
;
790 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
791 sel
->so
= state
->stream_output
;
793 r
= r600_shader_select(ctx
, sel
, NULL
);
800 static void *r600_create_ps_state(struct pipe_context
*ctx
,
801 const struct pipe_shader_state
*state
)
803 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
806 static void *r600_create_vs_state(struct pipe_context
*ctx
,
807 const struct pipe_shader_state
*state
)
809 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
812 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
814 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
817 state
= rctx
->dummy_pixel_shader
;
819 rctx
->pixel_shader
.shader
= rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
820 rctx
->pixel_shader
.atom
.num_dw
= rctx
->ps_shader
->current
->command_buffer
.num_dw
;
821 rctx
->pixel_shader
.atom
.dirty
= true;
823 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)rctx
->ps_shader
->current
->bo
);
825 if (rctx
->b
.chip_class
<= R700
) {
826 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
828 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
829 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
830 rctx
->cb_misc_state
.atom
.dirty
= true;
834 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
835 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
836 rctx
->cb_misc_state
.atom
.dirty
= true;
839 if (rctx
->b
.chip_class
>= EVERGREEN
) {
840 evergreen_update_db_shader_control(rctx
);
842 r600_update_db_shader_control(rctx
);
846 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
848 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
853 rctx
->vertex_shader
.shader
= rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
854 rctx
->vertex_shader
.atom
.dirty
= true;
855 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
857 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)rctx
->vs_shader
->current
->bo
);
859 /* Update clip misc state. */
860 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
861 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
) {
862 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
863 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
864 rctx
->clip_misc_state
.atom
.dirty
= true;
868 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
869 struct r600_pipe_shader_selector
*sel
)
871 struct r600_pipe_shader
*p
= sel
->current
, *c
;
874 r600_pipe_shader_destroy(ctx
, p
);
884 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
886 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
887 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
889 if (rctx
->ps_shader
== sel
) {
890 rctx
->ps_shader
= NULL
;
893 r600_delete_shader_selector(ctx
, sel
);
896 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
898 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
899 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
901 if (rctx
->vs_shader
== sel
) {
902 rctx
->vs_shader
= NULL
;
905 r600_delete_shader_selector(ctx
, sel
);
908 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
910 if (state
->dirty_mask
) {
911 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
912 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
913 : util_bitcount(state
->dirty_mask
)*19;
914 state
->atom
.dirty
= true;
918 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
919 struct pipe_constant_buffer
*input
)
921 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
922 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
923 struct pipe_constant_buffer
*cb
;
926 /* Note that the state tracker can unbind constant buffers by
929 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
930 state
->enabled_mask
&= ~(1 << index
);
931 state
->dirty_mask
&= ~(1 << index
);
932 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
936 cb
= &state
->cb
[index
];
937 cb
->buffer_size
= input
->buffer_size
;
939 ptr
= input
->user_buffer
;
942 /* Upload the user buffer. */
943 if (R600_BIG_ENDIAN
) {
945 unsigned i
, size
= input
->buffer_size
;
947 if (!(tmpPtr
= malloc(size
))) {
948 R600_ERR("Failed to allocate BE swap buffer.\n");
952 for (i
= 0; i
< size
/ 4; ++i
) {
953 tmpPtr
[i
] = util_bswap32(((uint32_t *)ptr
)[i
]);
956 u_upload_data(rctx
->b
.uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
959 u_upload_data(rctx
->b
.uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
961 /* account it in gtt */
962 rctx
->b
.gtt
+= input
->buffer_size
;
964 /* Setup the hw buffer. */
965 cb
->buffer_offset
= input
->buffer_offset
;
966 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
967 r600_context_add_resource_size(ctx
, input
->buffer
);
970 state
->enabled_mask
|= 1 << index
;
971 state
->dirty_mask
|= 1 << index
;
972 r600_constant_buffers_dirty(rctx
, state
);
975 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
977 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
979 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
982 rctx
->sample_mask
.sample_mask
= sample_mask
;
983 rctx
->sample_mask
.atom
.dirty
= true;
987 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
988 * doesn't require full swizzles it does need masking and setting alpha
989 * to one, so we setup a set of 5 constants with the masks + alpha value
990 * then in the shader, we AND the 4 components with 0xffffffff or 0,
991 * then OR the alpha with the value given here.
992 * We use a 6th constant to store the txq buffer size in
994 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
996 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
999 struct pipe_constant_buffer cb
;
1002 if (!samplers
->views
.dirty_buffer_constants
)
1005 samplers
->views
.dirty_buffer_constants
= FALSE
;
1007 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1008 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1009 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1010 memset(samplers
->buffer_constants
, 0, array_size
);
1011 for (i
= 0; i
< bits
; i
++) {
1012 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1014 const struct util_format_description
*desc
;
1015 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1017 for (j
= 0; j
< 4; j
++)
1018 if (j
< desc
->nr_channels
)
1019 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1021 samplers
->buffer_constants
[offset
+j
] = 0x0;
1022 if (desc
->nr_channels
< 4) {
1023 if (desc
->channel
[0].pure_integer
)
1024 samplers
->buffer_constants
[offset
+4] = 1;
1026 samplers
->buffer_constants
[offset
+4] = 0x3f800000;
1028 samplers
->buffer_constants
[offset
+ 4] = 0;
1030 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1035 cb
.user_buffer
= samplers
->buffer_constants
;
1036 cb
.buffer_offset
= 0;
1037 cb
.buffer_size
= array_size
;
1038 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1039 pipe_resource_reference(&cb
.buffer
, NULL
);
1042 /* On evergreen we only need to store the buffer size for TXQ */
1043 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1045 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1047 uint32_t array_size
;
1048 struct pipe_constant_buffer cb
;
1051 if (!samplers
->views
.dirty_buffer_constants
)
1054 samplers
->views
.dirty_buffer_constants
= FALSE
;
1056 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1057 array_size
= bits
* sizeof(uint32_t) * 4;
1058 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1059 memset(samplers
->buffer_constants
, 0, array_size
);
1060 for (i
= 0; i
< bits
; i
++)
1061 if (samplers
->views
.enabled_mask
& (1 << i
))
1062 samplers
->buffer_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1065 cb
.user_buffer
= samplers
->buffer_constants
;
1066 cb
.buffer_offset
= 0;
1067 cb
.buffer_size
= array_size
;
1068 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1069 pipe_resource_reference(&cb
.buffer
, NULL
);
1072 static void r600_setup_txq_cube_array_constants(struct r600_context
*rctx
, int shader_type
)
1074 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1076 uint32_t array_size
;
1077 struct pipe_constant_buffer cb
;
1080 if (!samplers
->views
.dirty_txq_constants
)
1083 samplers
->views
.dirty_txq_constants
= FALSE
;
1085 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1086 array_size
= bits
* sizeof(uint32_t) * 4;
1087 samplers
->txq_constants
= realloc(samplers
->txq_constants
, array_size
);
1088 memset(samplers
->txq_constants
, 0, array_size
);
1089 for (i
= 0; i
< bits
; i
++)
1090 if (samplers
->views
.enabled_mask
& (1 << i
))
1091 samplers
->txq_constants
[i
] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1094 cb
.user_buffer
= samplers
->txq_constants
;
1095 cb
.buffer_offset
= 0;
1096 cb
.buffer_size
= array_size
;
1097 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_TXQ_CONST_BUFFER
, &cb
);
1098 pipe_resource_reference(&cb
.buffer
, NULL
);
1101 static bool r600_update_derived_state(struct r600_context
*rctx
)
1103 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1104 bool ps_dirty
= false;
1107 if (!rctx
->blitter
->running
) {
1110 /* Decompress textures if needed. */
1111 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1112 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1113 if (views
->compressed_depthtex_mask
) {
1114 r600_decompress_depth_textures(rctx
, views
);
1116 if (views
->compressed_colortex_mask
) {
1117 r600_decompress_color_textures(rctx
, views
);
1122 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1124 if (rctx
->ps_shader
&& rctx
->rasterizer
&&
1125 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1126 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
))) {
1128 if (rctx
->b
.chip_class
>= EVERGREEN
)
1129 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1131 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1137 rctx
->pixel_shader
.atom
.num_dw
= rctx
->ps_shader
->current
->command_buffer
.num_dw
;
1138 rctx
->pixel_shader
.atom
.dirty
= true;
1141 /* on R600 we stuff masks + txq info into one constant buffer */
1142 /* on evergreen we only need a txq info one */
1143 if (rctx
->b
.chip_class
< EVERGREEN
) {
1144 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1145 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1146 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1147 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1149 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.uses_tex_buffers
)
1150 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1151 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.uses_tex_buffers
)
1152 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1156 if (rctx
->ps_shader
&& rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1157 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1158 if (rctx
->vs_shader
&& rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
)
1159 r600_setup_txq_cube_array_constants(rctx
, PIPE_SHADER_VERTEX
);
1161 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1162 if (!r600_adjust_gprs(rctx
)) {
1163 /* discard rendering */
1168 blend_disable
= (rctx
->dual_src_blend
&&
1169 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1171 if (blend_disable
!= rctx
->force_blend_disable
) {
1172 rctx
->force_blend_disable
= blend_disable
;
1173 r600_bind_blend_state_internal(rctx
,
1174 rctx
->blend_state
.cso
,
1180 static unsigned r600_conv_prim_to_gs_out(unsigned mode
)
1182 static const int prim_conv
[] = {
1183 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
1184 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1185 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1186 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1187 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1188 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1189 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1190 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1191 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1192 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1193 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1194 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
1195 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1196 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
1197 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1199 assert(mode
< Elements(prim_conv
));
1201 return prim_conv
[mode
];
1204 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1206 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1207 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1209 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1210 state
->pa_cl_clip_cntl
|
1211 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F));
1212 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1213 state
->pa_cl_vs_out_cntl
|
1214 (state
->clip_plane_enable
& state
->clip_dist_write
));
1217 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1219 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1220 struct pipe_draw_info info
= *dinfo
;
1221 struct pipe_index_buffer ib
= {};
1223 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1225 if (!info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1230 if (!rctx
->vs_shader
) {
1235 /* make sure that the gfx ring is only one active */
1236 if (rctx
->b
.rings
.dma
.cs
) {
1237 rctx
->b
.rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
);
1240 if (!r600_update_derived_state(rctx
)) {
1241 /* useless to render because current rendering command
1248 /* Initialize the index buffer struct. */
1249 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1250 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1251 ib
.index_size
= rctx
->index_buffer
.index_size
;
1252 ib
.offset
= rctx
->index_buffer
.offset
+ info
.start
* ib
.index_size
;
1254 /* Translate 8-bit indices to 16-bit. */
1255 if (ib
.index_size
== 1) {
1256 struct pipe_resource
*out_buffer
= NULL
;
1257 unsigned out_offset
;
1260 u_upload_alloc(rctx
->b
.uploader
, 0, info
.count
* 2,
1261 &out_offset
, &out_buffer
, &ptr
);
1263 util_shorten_ubyte_elts_to_userptr(
1264 &rctx
->b
.b
, &ib
, 0, ib
.offset
, info
.count
, ptr
);
1266 pipe_resource_reference(&ib
.buffer
, NULL
);
1267 ib
.user_buffer
= NULL
;
1268 ib
.buffer
= out_buffer
;
1269 ib
.offset
= out_offset
;
1273 /* Upload the index buffer.
1274 * The upload is skipped for small index counts on little-endian machines
1275 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1276 * Note: Instanced rendering in combination with immediate indices hangs. */
1277 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.instance_count
> 1 ||
1278 info
.count
*ib
.index_size
> 20)) {
1279 u_upload_data(rctx
->b
.uploader
, 0, info
.count
* ib
.index_size
,
1280 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1281 ib
.user_buffer
= NULL
;
1284 info
.index_bias
= info
.start
;
1287 /* Set the index offset and primitive restart. */
1288 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1289 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1290 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
) {
1291 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1292 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1293 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1294 rctx
->vgt_state
.atom
.dirty
= true;
1297 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1298 if (rctx
->b
.chip_class
== R600
) {
1299 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1300 rctx
->cb_misc_state
.atom
.dirty
= true;
1304 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1305 r600_flush_emit(rctx
);
1307 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1308 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1311 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1314 /* Update start instance. */
1315 if (rctx
->last_start_instance
!= info
.start_instance
) {
1316 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1317 rctx
->last_start_instance
= info
.start_instance
;
1320 /* Update the primitive type. */
1321 if (rctx
->last_primitive_type
!= info
.mode
) {
1322 unsigned ls_mask
= 0;
1324 if (info
.mode
== PIPE_PRIM_LINES
)
1326 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1327 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1330 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1331 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1332 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1333 r600_write_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
1334 r600_conv_prim_to_gs_out(info
.mode
));
1335 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1336 r600_conv_pipe_prim(info
.mode
));
1338 rctx
->last_primitive_type
= info
.mode
;
1342 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->b
.predicate_drawing
);
1343 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1345 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->b
.predicate_drawing
);
1346 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1347 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1348 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1350 if (ib
.user_buffer
) {
1351 unsigned size_bytes
= info
.count
*ib
.index_size
;
1352 unsigned size_dw
= align(size_bytes
, 4) / 4;
1353 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->b
.predicate_drawing
);
1354 cs
->buf
[cs
->cdw
++] = info
.count
;
1355 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1356 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1359 uint64_t va
= r600_resource_va(ctx
->screen
, ib
.buffer
) + ib
.offset
;
1360 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->b
.predicate_drawing
);
1361 cs
->buf
[cs
->cdw
++] = va
;
1362 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1363 cs
->buf
[cs
->cdw
++] = info
.count
;
1364 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1365 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1366 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, (struct r600_resource
*)ib
.buffer
, RADEON_USAGE_READ
);
1369 if (info
.count_from_stream_output
) {
1370 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1371 uint64_t va
= r600_resource_va(&rctx
->screen
->b
.b
, (void*)t
->buf_filled_size
) + t
->buf_filled_size_offset
;
1373 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1375 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1376 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1377 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1378 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1379 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1380 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1382 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1383 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, t
->buf_filled_size
, RADEON_USAGE_READ
);
1386 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->b
.predicate_drawing
);
1387 cs
->buf
[cs
->cdw
++] = info
.count
;
1388 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1389 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1392 if (rctx
->screen
->trace_bo
) {
1393 r600_trace_emit(rctx
);
1396 /* Set the depth buffer as dirty. */
1397 if (rctx
->framebuffer
.state
.zsbuf
) {
1398 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1399 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1401 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1403 if (rctx
->framebuffer
.compressed_cb_mask
) {
1404 struct pipe_surface
*surf
;
1405 struct r600_texture
*rtex
;
1406 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1409 unsigned i
= u_bit_scan(&mask
);
1410 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1411 rtex
= (struct r600_texture
*)surf
->texture
;
1413 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1418 pipe_resource_reference(&ib
.buffer
, NULL
);
1419 rctx
->b
.num_draw_calls
++;
1422 void r600_draw_rectangle(struct blitter_context
*blitter
,
1423 int x1
, int y1
, int x2
, int y2
, float depth
,
1424 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
)
1426 struct r600_context
*rctx
= (struct r600_context
*)util_blitter_get_pipe(blitter
);
1427 struct pipe_viewport_state viewport
;
1428 struct pipe_resource
*buf
= NULL
;
1429 unsigned offset
= 0;
1432 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
1433 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
1437 /* Some operations (like color resolve on r6xx) don't work
1438 * with the conventional primitive types.
1439 * One that works is PT_RECTLIST, which we use here. */
1441 /* setup viewport */
1442 viewport
.scale
[0] = 1.0f
;
1443 viewport
.scale
[1] = 1.0f
;
1444 viewport
.scale
[2] = 1.0f
;
1445 viewport
.scale
[3] = 1.0f
;
1446 viewport
.translate
[0] = 0.0f
;
1447 viewport
.translate
[1] = 0.0f
;
1448 viewport
.translate
[2] = 0.0f
;
1449 viewport
.translate
[3] = 0.0f
;
1450 rctx
->b
.b
.set_viewport_states(&rctx
->b
.b
, 0, 1, &viewport
);
1452 /* Upload vertices. The hw rectangle has only 3 vertices,
1453 * I guess the 4th one is derived from the first 3.
1454 * The vertex specification should match u_blitter's vertex element state. */
1455 u_upload_alloc(rctx
->b
.uploader
, 0, sizeof(float) * 24, &offset
, &buf
, (void**)&vb
);
1472 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
1473 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
1474 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
1478 util_draw_vertex_buffer(&rctx
->b
.b
, NULL
, buf
, rctx
->blitter
->vb_slot
, offset
,
1479 R600_PRIM_RECTANGLE_LIST
, 3, 2);
1480 pipe_resource_reference(&buf
, NULL
);
1483 uint32_t r600_translate_stencil_op(int s_op
)
1486 case PIPE_STENCIL_OP_KEEP
:
1487 return V_028800_STENCIL_KEEP
;
1488 case PIPE_STENCIL_OP_ZERO
:
1489 return V_028800_STENCIL_ZERO
;
1490 case PIPE_STENCIL_OP_REPLACE
:
1491 return V_028800_STENCIL_REPLACE
;
1492 case PIPE_STENCIL_OP_INCR
:
1493 return V_028800_STENCIL_INCR
;
1494 case PIPE_STENCIL_OP_DECR
:
1495 return V_028800_STENCIL_DECR
;
1496 case PIPE_STENCIL_OP_INCR_WRAP
:
1497 return V_028800_STENCIL_INCR_WRAP
;
1498 case PIPE_STENCIL_OP_DECR_WRAP
:
1499 return V_028800_STENCIL_DECR_WRAP
;
1500 case PIPE_STENCIL_OP_INVERT
:
1501 return V_028800_STENCIL_INVERT
;
1503 R600_ERR("Unknown stencil op %d", s_op
);
1510 uint32_t r600_translate_fill(uint32_t func
)
1513 case PIPE_POLYGON_MODE_FILL
:
1515 case PIPE_POLYGON_MODE_LINE
:
1517 case PIPE_POLYGON_MODE_POINT
:
1525 unsigned r600_tex_wrap(unsigned wrap
)
1529 case PIPE_TEX_WRAP_REPEAT
:
1530 return V_03C000_SQ_TEX_WRAP
;
1531 case PIPE_TEX_WRAP_CLAMP
:
1532 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1533 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1534 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1535 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1536 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1537 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1538 return V_03C000_SQ_TEX_MIRROR
;
1539 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1540 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1541 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1542 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1543 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1544 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1548 unsigned r600_tex_filter(unsigned filter
)
1552 case PIPE_TEX_FILTER_NEAREST
:
1553 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1554 case PIPE_TEX_FILTER_LINEAR
:
1555 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1559 unsigned r600_tex_mipfilter(unsigned filter
)
1562 case PIPE_TEX_MIPFILTER_NEAREST
:
1563 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1564 case PIPE_TEX_MIPFILTER_LINEAR
:
1565 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1567 case PIPE_TEX_MIPFILTER_NONE
:
1568 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1572 unsigned r600_tex_compare(unsigned compare
)
1576 case PIPE_FUNC_NEVER
:
1577 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1578 case PIPE_FUNC_LESS
:
1579 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1580 case PIPE_FUNC_EQUAL
:
1581 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1582 case PIPE_FUNC_LEQUAL
:
1583 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1584 case PIPE_FUNC_GREATER
:
1585 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1586 case PIPE_FUNC_NOTEQUAL
:
1587 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1588 case PIPE_FUNC_GEQUAL
:
1589 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1590 case PIPE_FUNC_ALWAYS
:
1591 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1595 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1597 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1598 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1600 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1601 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1604 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1606 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1607 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1609 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1610 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1611 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1612 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1613 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1616 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1618 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1619 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
->current
;
1621 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
1623 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1624 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->bo
, RADEON_USAGE_READ
));
1627 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1628 struct pipe_resource
*texture
,
1629 const struct pipe_surface
*templ
,
1630 unsigned width
, unsigned height
)
1632 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1634 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1635 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1636 assert(templ
->u
.tex
.first_layer
== templ
->u
.tex
.last_layer
);
1637 if (surface
== NULL
)
1639 pipe_reference_init(&surface
->base
.reference
, 1);
1640 pipe_resource_reference(&surface
->base
.texture
, texture
);
1641 surface
->base
.context
= pipe
;
1642 surface
->base
.format
= templ
->format
;
1643 surface
->base
.width
= width
;
1644 surface
->base
.height
= height
;
1645 surface
->base
.u
= templ
->u
;
1646 return &surface
->base
;
1649 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1650 struct pipe_resource
*tex
,
1651 const struct pipe_surface
*templ
)
1653 unsigned level
= templ
->u
.tex
.level
;
1655 return r600_create_surface_custom(pipe
, tex
, templ
,
1656 u_minify(tex
->width0
, level
),
1657 u_minify(tex
->height0
, level
));
1660 static void r600_surface_destroy(struct pipe_context
*pipe
,
1661 struct pipe_surface
*surface
)
1663 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1664 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
1665 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
1666 pipe_resource_reference(&surface
->texture
, NULL
);
1670 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
1671 const unsigned char *swizzle_view
,
1675 unsigned char swizzle
[4];
1676 unsigned result
= 0;
1677 const uint32_t tex_swizzle_shift
[4] = {
1680 const uint32_t vtx_swizzle_shift
[4] = {
1683 const uint32_t swizzle_bit
[4] = {
1686 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
1689 swizzle_shift
= vtx_swizzle_shift
;
1692 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1694 memcpy(swizzle
, swizzle_format
, 4);
1698 for (i
= 0; i
< 4; i
++) {
1699 switch (swizzle
[i
]) {
1700 case UTIL_FORMAT_SWIZZLE_Y
:
1701 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1703 case UTIL_FORMAT_SWIZZLE_Z
:
1704 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1706 case UTIL_FORMAT_SWIZZLE_W
:
1707 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1709 case UTIL_FORMAT_SWIZZLE_0
:
1710 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1712 case UTIL_FORMAT_SWIZZLE_1
:
1713 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1715 default: /* UTIL_FORMAT_SWIZZLE_X */
1716 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1722 /* texture format translate */
1723 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1724 enum pipe_format format
,
1725 const unsigned char *swizzle_view
,
1726 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1728 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1729 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1730 const struct util_format_description
*desc
;
1731 boolean uniform
= TRUE
;
1732 bool enable_s3tc
= rscreen
->b
.info
.drm_minor
>= 9;
1733 bool is_srgb_valid
= FALSE
;
1734 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
1735 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
1738 const uint32_t sign_bit
[4] = {
1739 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1740 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1741 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1742 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1744 desc
= util_format_description(format
);
1746 /* Depth and stencil swizzling is handled separately. */
1747 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
1748 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
1751 /* Colorspace (return non-RGB formats directly). */
1752 switch (desc
->colorspace
) {
1753 /* Depth stencil formats */
1754 case UTIL_FORMAT_COLORSPACE_ZS
:
1756 /* Depth sampler formats. */
1757 case PIPE_FORMAT_Z16_UNORM
:
1758 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1761 case PIPE_FORMAT_Z24X8_UNORM
:
1762 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1763 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1766 case PIPE_FORMAT_X8Z24_UNORM
:
1767 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1768 if (rscreen
->b
.chip_class
< EVERGREEN
)
1770 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1773 case PIPE_FORMAT_Z32_FLOAT
:
1774 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1775 result
= FMT_32_FLOAT
;
1777 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1778 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1779 result
= FMT_X24_8_32_FLOAT
;
1781 /* Stencil sampler formats. */
1782 case PIPE_FORMAT_S8_UINT
:
1783 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1784 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1787 case PIPE_FORMAT_X24S8_UINT
:
1788 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1789 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1792 case PIPE_FORMAT_S8X24_UINT
:
1793 if (rscreen
->b
.chip_class
< EVERGREEN
)
1795 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1796 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1799 case PIPE_FORMAT_X32_S8X24_UINT
:
1800 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1801 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1802 result
= FMT_X24_8_32_FLOAT
;
1808 case UTIL_FORMAT_COLORSPACE_YUV
:
1809 yuv_format
|= (1 << 30);
1811 case PIPE_FORMAT_UYVY
:
1812 case PIPE_FORMAT_YUYV
:
1816 goto out_unknown
; /* XXX */
1818 case UTIL_FORMAT_COLORSPACE_SRGB
:
1819 word4
|= S_038010_FORCE_DEGAMMA(1);
1826 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1831 case PIPE_FORMAT_RGTC1_SNORM
:
1832 case PIPE_FORMAT_LATC1_SNORM
:
1833 word4
|= sign_bit
[0];
1834 case PIPE_FORMAT_RGTC1_UNORM
:
1835 case PIPE_FORMAT_LATC1_UNORM
:
1838 case PIPE_FORMAT_RGTC2_SNORM
:
1839 case PIPE_FORMAT_LATC2_SNORM
:
1840 word4
|= sign_bit
[0] | sign_bit
[1];
1841 case PIPE_FORMAT_RGTC2_UNORM
:
1842 case PIPE_FORMAT_LATC2_UNORM
:
1850 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1855 if (!util_format_s3tc_enabled
) {
1860 case PIPE_FORMAT_DXT1_RGB
:
1861 case PIPE_FORMAT_DXT1_RGBA
:
1862 case PIPE_FORMAT_DXT1_SRGB
:
1863 case PIPE_FORMAT_DXT1_SRGBA
:
1865 is_srgb_valid
= TRUE
;
1867 case PIPE_FORMAT_DXT3_RGBA
:
1868 case PIPE_FORMAT_DXT3_SRGBA
:
1870 is_srgb_valid
= TRUE
;
1872 case PIPE_FORMAT_DXT5_RGBA
:
1873 case PIPE_FORMAT_DXT5_SRGBA
:
1875 is_srgb_valid
= TRUE
;
1882 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1884 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1885 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1888 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1889 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1897 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1898 result
= FMT_5_9_9_9_SHAREDEXP
;
1900 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1901 result
= FMT_10_11_11_FLOAT
;
1906 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1907 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1908 word4
|= sign_bit
[i
];
1912 /* R8G8Bx_SNORM - XXX CxV8U8 */
1914 /* See whether the components are of the same size. */
1915 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1916 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1919 /* Non-uniform formats. */
1921 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1922 desc
->channel
[0].pure_integer
)
1923 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1924 switch(desc
->nr_channels
) {
1926 if (desc
->channel
[0].size
== 5 &&
1927 desc
->channel
[1].size
== 6 &&
1928 desc
->channel
[2].size
== 5) {
1934 if (desc
->channel
[0].size
== 5 &&
1935 desc
->channel
[1].size
== 5 &&
1936 desc
->channel
[2].size
== 5 &&
1937 desc
->channel
[3].size
== 1) {
1938 result
= FMT_1_5_5_5
;
1941 if (desc
->channel
[0].size
== 10 &&
1942 desc
->channel
[1].size
== 10 &&
1943 desc
->channel
[2].size
== 10 &&
1944 desc
->channel
[3].size
== 2) {
1945 result
= FMT_2_10_10_10
;
1953 /* Find the first non-VOID channel. */
1954 for (i
= 0; i
< 4; i
++) {
1955 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1963 /* uniform formats */
1964 switch (desc
->channel
[i
].type
) {
1965 case UTIL_FORMAT_TYPE_UNSIGNED
:
1966 case UTIL_FORMAT_TYPE_SIGNED
:
1968 if (!desc
->channel
[i
].normalized
&&
1969 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
1973 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
1974 desc
->channel
[i
].pure_integer
)
1975 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1977 switch (desc
->channel
[i
].size
) {
1979 switch (desc
->nr_channels
) {
1984 result
= FMT_4_4_4_4
;
1989 switch (desc
->nr_channels
) {
1997 result
= FMT_8_8_8_8
;
1998 is_srgb_valid
= TRUE
;
2003 switch (desc
->nr_channels
) {
2011 result
= FMT_16_16_16_16
;
2016 switch (desc
->nr_channels
) {
2024 result
= FMT_32_32_32_32
;
2030 case UTIL_FORMAT_TYPE_FLOAT
:
2031 switch (desc
->channel
[i
].size
) {
2033 switch (desc
->nr_channels
) {
2035 result
= FMT_16_FLOAT
;
2038 result
= FMT_16_16_FLOAT
;
2041 result
= FMT_16_16_16_16_FLOAT
;
2046 switch (desc
->nr_channels
) {
2048 result
= FMT_32_FLOAT
;
2051 result
= FMT_32_32_FLOAT
;
2054 result
= FMT_32_32_32_32_FLOAT
;
2063 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2068 *yuv_format_p
= yuv_format
;
2071 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2075 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2077 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2078 struct r600_resource
*rbuffer
= r600_resource(buf
);
2079 unsigned i
, shader
, mask
, alignment
= rbuffer
->buf
->alignment
;
2081 /* Discard the buffer. */
2082 pb_reference(&rbuffer
->buf
, NULL
);
2084 /* Create a new one in the same pipe_resource. */
2085 r600_init_resource(&rctx
->screen
->b
, rbuffer
, rbuffer
->b
.b
.width0
, alignment
,
2086 TRUE
, rbuffer
->b
.b
.usage
);
2088 /* We changed the buffer, now we need to bind it where the old one was bound. */
2089 /* Vertex buffers. */
2090 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2092 i
= u_bit_scan(&mask
);
2093 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2094 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2095 r600_vertex_buffers_dirty(rctx
);
2098 /* Streamout buffers. */
2099 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2100 if (rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2101 if (rctx
->b
.streamout
.begin_emitted
) {
2102 r600_emit_streamout_end(&rctx
->b
);
2104 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2105 r600_streamout_buffers_dirty(&rctx
->b
);
2109 /* Constant buffers. */
2110 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2111 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2113 uint32_t mask
= state
->enabled_mask
;
2116 unsigned i
= u_bit_scan(&mask
);
2117 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2119 state
->dirty_mask
|= 1 << i
;
2123 r600_constant_buffers_dirty(rctx
, state
);
2127 /* XXX TODO: texture buffer objects */
2130 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2132 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2134 if (rctx
->db_misc_state
.occlusion_query_enabled
!= enable
) {
2135 rctx
->db_misc_state
.occlusion_query_enabled
= enable
;
2136 rctx
->db_misc_state
.atom
.dirty
= true;
2140 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2141 bool include_draw_vbo
)
2143 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2146 /* keep this at the end of this file, please */
2147 void r600_init_common_state_functions(struct r600_context
*rctx
)
2149 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2150 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2151 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2152 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2153 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2154 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2155 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2156 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2157 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2158 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2159 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2160 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2161 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2162 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2163 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2164 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2165 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2166 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2167 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2168 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2169 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2170 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2171 rctx
->b
.b
.set_viewport_states
= r600_set_viewport_states
;
2172 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2173 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2174 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2175 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2176 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2177 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2178 rctx
->b
.b
.create_surface
= r600_create_surface
;
2179 rctx
->b
.b
.surface_destroy
= r600_surface_destroy
;
2180 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2181 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2182 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2183 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;
2186 void r600_trace_emit(struct r600_context
*rctx
)
2188 struct r600_screen
*rscreen
= rctx
->screen
;
2189 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2193 va
= r600_resource_va(&rscreen
->b
.b
, (void*)rscreen
->trace_bo
);
2194 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rscreen
->trace_bo
, RADEON_USAGE_READWRITE
);
2195 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
2196 radeon_emit(cs
, va
& 0xFFFFFFFFUL
);
2197 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
);
2198 radeon_emit(cs
, cs
->cdw
);
2199 radeon_emit(cs
, rscreen
->cs_count
);
2200 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2201 radeon_emit(cs
, reloc
);